From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 3 Oct 2019 00:48:55 +0000 (-0700)
Subject: Add test
X-Git-Tag: working-ls180~1000^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e730a595eeee1d9936a892c2477c99593d64bcfe;p=yosys.git

Add test
---

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 6bca62e2b..dc0acf3ca 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -173,3 +173,34 @@ select -assert-count 1 t:$dff r:WIDTH=2 %i
 select -assert-count 2 t:$mux
 select -assert-count 2 t:$mux r:WIDTH=2 %i
 select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_signed_rst_init(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
+    initial o <= 4'b0010;
+    always @(posedge clk) begin
+        if (ce) o <= i;
+        if (!rstn) o <= 4'b1111;
+    end
+endmodule
+EOT
+
+proc
+#equiv_opt -assert peepopt
+
+design -save gold
+peepopt
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -seq 1 -verify -prove-asserts -show-ports miter
+
+design -load postopt
+wreduce
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 2 t:$mux
+select -assert-count 2 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D