From: Tobias Platen <tplaten@posteo.de>
Date: Sat, 16 Jan 2021 16:43:46 +0000 (+0100)
Subject: move microwatt_mmu bool variable to pspec
X-Git-Tag: 24jan2021_ls180~25
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e74b2863ec00f0f4aab13b20017a34f11b0439c7;p=soc.git

move microwatt_mmu bool variable to pspec
---

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index 4129d368..d2a0e546 100644
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -238,9 +238,11 @@ class AllFunctionUnits(Elaboratable):
 
     """
 
-    def __init__(self, pspec, pilist=None, div_fsm=True,microwatt_mmu = False):
+    def __init__(self, pspec, pilist=None, div_fsm=True):
         addrwid = pspec.addr_wid
         units = pspec.units
+        microwatt_mmu = hasattr(pspec, "mmu") and pspec.mmu == True
+        print("AllFunctionUnits.microwatt_mmu="+str(microwatt_mmu))
         if not isinstance(units, dict):
             units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1,
                      'spr': 1,
diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
index 60011e3b..f2e12b99 100644
--- a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
+++ b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
@@ -28,7 +28,7 @@ class MMUDataPathTestCase(TestAccumulatorBase):
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    suite.addTest(TestRunner(MMUDataPathTestCase().test_data))
+    suite.addTest(TestRunner(MMUDataPathTestCase().test_data,microwatt_mmu=True))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 04d3604e..9d115a3d 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -68,7 +68,7 @@ def sort_fuspecs(fuspecs):
 
 
 class NonProductionCore(Elaboratable):
-    def __init__(self, pspec, microwatt_mmu = False):
+    def __init__(self, pspec):
         self.pspec = pspec
 
         # single LD/ST funnel for memory access
@@ -76,8 +76,8 @@ class NonProductionCore(Elaboratable):
         pi = self.l0.l0.dports[0]
 
         # function units (only one each)
-        self.microwatt_mmu = microwatt_mmu
-        self.fus = AllFunctionUnits(pspec, pilist=[pi], microwatt_mmu = self.microwatt_mmu)
+        # only include mmu if enabled in pspec
+        self.fus = AllFunctionUnits(pspec, pilist=[pi])
 
         # register files (yes plural)
         self.regs = RegFiles()
diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 708eb1ff..ea5a5c27 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -132,9 +132,10 @@ def get_dmi(dmi, addr):
 
 
 class TestRunner(FHDLTestCase):
-    def __init__(self, tst_data):
+    def __init__(self, tst_data, microwatt_mmu=False):
         super().__init__("run_all")
         self.test_data = tst_data
+        self.microwatt_mmu = microwatt_mmu
 
     def run_all(self):
         m = Module()
@@ -151,6 +152,7 @@ class TestRunner(FHDLTestCase):
                              nocore=False,
                              xics=False,
                              gpio=False,
+                             mmu=self.microwatt_mmu,
                              reg_wid=64)
         m.submodules.issuer = issuer = TestIssuerInternal(pspec)
         imem = issuer.imem._get_memory()
@@ -306,7 +308,7 @@ class TestRunner(FHDLTestCase):
                                 (test.name, int_reg, value))
 
         sim.add_sync_process(process)
-        with sim.write_vcd("issuer_simulator.vcd",
+        with sim.write_vcd("issuer_simulator.vcd","issuer_simulator.gtkw",
                            traces=[]):
             sim.run()