From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 23 Apr 2021 12:45:59 +0000 (+0100)
Subject: add exceptions
X-Git-Tag: 0.0.1~45
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e754cdbf7d35811f177612b4b43261b2e0310c2d;p=openpower-isa.git

add exceptions
---

diff --git a/src/openpower/exceptions.py b/src/openpower/exceptions.py
new file mode 100644
index 00000000..a0fc9a7f
--- /dev/null
+++ b/src/openpower/exceptions.py
@@ -0,0 +1,14 @@
+"""exceptions
+"""
+from nmutil.iocontrol import RecordObject
+from nmigen import Signal
+
+# https://bugs.libre-soc.org/show_bug.cgi?id=465
+class LDSTException(RecordObject):
+    _exc_types = ['happened', 'alignment', 'instr_fault', 'invalid', 'badtree',
+                 'perm_error', 'rc_error', 'segment_fault',]
+    def __init__(self, name=None):
+        RecordObject.__init__(self, name=name)
+        for f in self._exc_types:
+            setattr(self, f, Signal())
+
diff --git a/src/openpower/state.py b/src/openpower/state.py
new file mode 100644
index 00000000..a3972ef1
--- /dev/null
+++ b/src/openpower/state.py
@@ -0,0 +1,20 @@
+from nmutil.iocontrol import RecordObject
+from nmigen import Signal
+from soc.sv.svstate import SVSTATERec
+
+
+class CoreState(RecordObject):
+    """contains "Core State Information" which says exactly where things are
+
+    example: eint says to PowerDecoder that it should fire an exception
+    rather than let the current decoded instruction proceed.  likewise
+    if dec goes negative.  MSR contains LE/BE and Priv state.  PC contains
+    the Program Counter, and SVSTATE is the Sub-Program-Counter.
+    """
+    def __init__(self, name):
+        super().__init__(name=name)
+        self.pc = Signal(64)      # Program Counter (CIA, NIA)
+        self.msr = Signal(64)     # Machine Status Register (MSR)
+        self.eint = Signal()      # External Interrupt
+        self.dec = Signal(64)     # DEC SPR (again, for interrupt generation)
+        self.svstate = SVSTATERec(name) # Simple-V SVSTATE