From: Gabe Black <gabeblack@google.com>
Date: Tue, 26 Nov 2019 00:38:22 +0000 (-0800)
Subject: x86: Use the m5 op range in the system.
X-Git-Tag: v19.0.0.0~35
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e758cd09d8163c2352aca8a7336c8d84d4cd0975;p=gem5.git

x86: Use the m5 op range in the system.

Don't hard code a range into the TLB.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I0ead4353672ccf6e3e51ddbb4676be3a09f1136a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23182
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
---

diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 2e61d027f..b3200ec0b 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -55,5 +55,6 @@ class X86TLB(BaseTLB):
     cxx_class = 'X86ISA::TLB'
     cxx_header = 'arch/x86/tlb.hh'
     size = Param.Unsigned(64, "TLB size")
+    system = Param.System(Parent.any, "system object")
     walker = Param.X86PagetableWalker(\
             X86PagetableWalker(), "page table walker")
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 2985a8bcb..65ed9c01d 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -61,7 +61,7 @@ namespace X86ISA {
 
 TLB::TLB(const Params *p)
     : BaseTLB(p), configAddress(0), size(p->size),
-      tlb(size), lruSeq(0)
+      tlb(size), lruSeq(0), m5opRange(p->system->m5opRange())
 {
     if (!size)
         fatal("TLBs must have a non-zero size.\n");
@@ -229,8 +229,6 @@ TLB::finalizePhysical(const RequestPtr &req,
 {
     Addr paddr = req->getPaddr();
 
-    AddrRange m5opRange(0xFFFF0000, 0x100000000);
-
     if (m5opRange.contains(paddr)) {
         req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
                       Request::STRICT_ORDER);
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index b969bca9d..21bd6401c 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -100,6 +100,8 @@ namespace X86ISA
         TlbEntryTrie trie;
         uint64_t lruSeq;
 
+        AddrRange m5opRange;
+
         // Statistics
         Stats::Scalar rdAccesses;
         Stats::Scalar wrAccesses;