From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 25 Sep 2021 19:16:23 +0000 (+0100)
Subject: Revert "move coresync clock synchronisation into HDLRunner"
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e78c4f5d7b8c1c03d1b20ceb021eb5fd99c19dd2;p=soc.git

Revert "move coresync clock synchronisation into HDLRunner"

This reverts commit 8a51f6944fa6c5185285b0139f5b419fb68aa145.
---

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 09481697..e4e109ec 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -201,10 +201,6 @@ class HDLRunner(StateRunner):
         comb += self.issuer.pc_i.data.eq(self.pc_i)
         comb += self.issuer.svstate_i.data.eq(self.svstate_i)
 
-        # run core clock at same rate as test clock
-        intclk = ClockSignal("coresync")
-        comb += intclk.eq(ClockSignal())
-
     def prepare_for_test(self, test):
         self.test = test
 
@@ -384,6 +380,10 @@ class TestRunner(FHDLTestCase):
         if self.run_sim:
             simrun = SimRunner(self, m, pspec)
 
+        # run core clock at same rate as test clock
+        intclk = ClockSignal("coresync")
+        comb += intclk.eq(ClockSignal())
+
         # nmigen Simulation - everything runs around this, so it
         # still has to be created.
         sim = Simulator(m)