From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 18 Oct 2018 22:38:06 +0000 (+0100)
Subject: jalr, mul, rem
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7957dbd98ffcf21e764cc008b6e3ca951a1d13f;p=riscv-isa-sim.git

jalr, mul, rem
---

diff --git a/riscv/insns/jalr.h b/riscv/insns/jalr.h
index 386e8db..a4df628 100644
--- a/riscv/insns/jalr.h
+++ b/riscv/insns/jalr.h
@@ -1,3 +1,3 @@
 reg_t tmp = npc;
-set_pc((RS1 + insn.i_imm()) & ~reg_t(1));
+set_pc(rv_and(rv_add(RS1, insn.i_imm()), ~reg_t(1)));
 WRITE_RD(tmp);
diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index 737b9cb..d7a95e9 100644
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -2,4 +2,5 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulh(RS1, RS2));
 else
-  WRITE_RD(sext32((rv_mul(sext32(RS1), sext32(RS2))) >> 32));
+  WRITE_RD(sext32(rv_sr(rv_mul(sext32(RS1), sext32(RS2)),
+                        sv_reg_t(32U))));
diff --git a/riscv/insns/mulhsu.h b/riscv/insns/mulhsu.h
index 6890799..724e661 100644
--- a/riscv/insns/mulhsu.h
+++ b/riscv/insns/mulhsu.h
@@ -2,4 +2,5 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhsu(RS1, RS2));
 else
-  WRITE_RD(sext32((rv_mul(sext32(RS1), reg_t((uint32_t)RS2))) >> 32));
+  WRITE_RD(sext32(rv_sr((rv_mul(sext32(RS1), sv_reg_uint32(RS2))),
+                  sv_reg_t(32U))));
diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index a9527b2..dee66b0 100644
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -2,5 +2,6 @@ require_extension('M');
 if (xlen == 64)
   WRITE_RD(mulhu(RS1, RS2));
 else
-  WRITE_RD(sext32((rv_mul((uint64_t)(uint32_t)RS1,
-                          (uint64_t)(uint32_t)RS2)) >> 32));
+  WRITE_RD(sext32(rv_sr(rv_mul(sv_reg_uint32(RS1),
+                          sv_reg_uint32(RS2)),
+                        sv_reg_t(32U))));
diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index 5464915..eae3d80 100644
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,9 +1,9 @@
 require_extension('M');
-sreg_t lhs = sext_xlen(RS1);
-sreg_t rhs = sext_xlen(RS2);
-if(rhs == 0)
+sv_sreg_t lhs = sext_xlen(RS1);
+sv_sreg_t rhs = sext_xlen(RS2);
+if(rv_eq(rhs, sv_reg_t(0)))
   WRITE_RD(lhs);
-else if(lhs == INT64_MIN && rhs == -1)
+else if(rv_eq(lhs, sv_reg_t(INT64_MIN)) && rv_eq(rhs, sv_reg_t(-1L)))
   WRITE_RD(0);
 else
   WRITE_RD(sext_xlen(rv_rem(lhs, rhs)));
diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index 8c59de6..cbd03fe 100644
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,7 +1,7 @@
 require_extension('M');
-reg_t lhs = zext_xlen(RS1);
-reg_t rhs = zext_xlen(RS2);
-if(rhs == 0)
+sv_reg_t lhs = zext_xlen(RS1);
+sv_reg_t rhs = zext_xlen(RS2);
+if(rv_eq(rhs, sv_reg_t(0)))
   WRITE_RD(sext_xlen(RS1));
 else
   WRITE_RD(sext_xlen(rv_rem(lhs, rhs)));
diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index 7f30d0e..d2a3264 100644
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,8 +1,8 @@
 require_extension('M');
 require_rv64;
-reg_t lhs = zext32(RS1);
-reg_t rhs = zext32(RS2);
-if(rhs == 0)
+sv_reg_t lhs = zext32(RS1);
+sv_reg_t rhs = zext32(RS2);
+if(rv_eq(rhs, sv_reg_t(0)))
   WRITE_RD(sext32(lhs));
 else
   WRITE_RD(sext32(rv_rem(lhs, rhs)));
diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index cf4bd4f..fe326f0 100644
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,8 +1,8 @@
 require_extension('M');
 require_rv64;
-sreg_t lhs = sext32(RS1);
-sreg_t rhs = sext32(RS2);
-if(rhs == 0)
+sv_sreg_t lhs = sext32(RS1);
+sv_sreg_t rhs = sext32(RS2);
+if(rv_eq(rhs, sv_reg_t(0)))
   WRITE_RD(lhs);
 else
   WRITE_RD(sext32(rv_rem(lhs, rhs)));