From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Mar 2020 17:05:20 +0000 (+0000)
Subject: sort out imports to get minerva generate working
X-Git-Tag: div_pipeline~1710
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7986942fe53eabf1cc9cb808a8377827bc373b2;p=soc.git

sort out imports to get minerva generate working
---

diff --git a/src/soc/minerva/core.py b/src/soc/minerva/core.py
index d8f1a17d..c73d5fd0 100644
--- a/src/soc/minerva/core.py
+++ b/src/soc/minerva/core.py
@@ -2,21 +2,22 @@ from functools import reduce
 from operator import or_
 from itertools import tee
 
-from nmigen import Elaboratable, Module, Record, Mux, Const, Signal
+from nmigen import Elaboratable, Module, Record, Mux, Const, Signal, Memory
 from nmigen.lib.coding import PriorityEncoder
 
 from soc.minerva.stage import Stage
 from soc.minerva.csr import CSRFile
 from soc.minerva.units.adder import Adder
 from soc.minerva.units.compare import CompareUnit
-from soc.minerva.units.debug import DebugUnit,
+from soc.minerva.units.debug import DebugUnit
 from soc.minerva.units.decoder import InstructionDecoder
 from soc.minerva.units.divider import Divider, DummyDivider
 from soc.minerva.units.exception import ExceptionUnit
-from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit
+from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit, PCSelector
 from soc.minerva.units.rvficon import RVFIController
-from soc.minerva.units.loadstore import BareLoadStoreUnit, CachedLoadStoreUnit
-from soc.minerva.units.logic import LogicUnit,
+from soc.minerva.units.loadstore import (BareLoadStoreUnit, CachedLoadStoreUnit,
+                                         DataSelector)
+from soc.minerva.units.logic import LogicUnit
 from soc.minerva.units.multiplier import DummyMultiplier, Multiplier
 from soc.minerva.units.predict import BranchPredictor
 from soc.minerva.units.shifter import Shifter