From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 7 Dec 2021 00:03:10 +0000 (+0000)
Subject: debug print
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e79c2bfb70fa322644f9775c1190bb61dcaae509;p=soc.git

debug print
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 3460e976..25ccac59 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -160,6 +160,7 @@ TAG_RAM_WIDTH = TAG_WIDTH * NUM_WAYS
 print ("TAG_RAM_WIDTH", TAG_RAM_WIDTH)
 print ("    TAG_WIDTH", TAG_WIDTH)
 print ("     NUM_WAYS", NUM_WAYS)
+print ("    NUM_LINES", NUM_LINES)
 
 def CacheTagArray():
     tag_layout = [('valid', NUM_WAYS),