From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 23:37:47 +0000 (-0700)
Subject: CIs before PIs; also sort each cell's connections before iterating
X-Git-Tag: working-ls180~1237^2~224
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7a8955818b8b0fee02673607b429f1de0f7164e;p=yosys.git

CIs before PIs; also sort each cell's connections before iterating
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 66ab3878e..ce93ffb28 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -215,6 +215,7 @@ struct XAigerWriter
 			RTLIL::Module* box_module = module->design->module(cell->type);
 			bool abc_box = box_module && box_module->attributes.count("\\abc_box_id");
 
+			cell->connections_.sort(RTLIL::sort_by_id_str());
 			for (const auto &c : cell->connections()) {
 				/*if (c.second.is_fully_const()) continue;*/
 				for (auto b : c.second.bits()) {
@@ -313,15 +314,15 @@ struct XAigerWriter
 		aig_map[State::S0] = 0;
 		aig_map[State::S1] = 1;
 
-		for (auto &c : ci_bits) {
+		for (auto bit : input_bits) {
 			aig_m++, aig_i++;
-			c.second = 2*aig_m;
-			aig_map[c.first] = c.second;
+			aig_map[bit] = 2*aig_m;
 		}
 
-		for (auto bit : input_bits) {
+		for (auto &c : ci_bits) {
 			aig_m++, aig_i++;
-			aig_map[bit] = 2*aig_m;
+			c.second = 2*aig_m;
+			aig_map[c.first] = c.second;
 		}
 
 		if (imode && input_bits.empty()) {
@@ -585,6 +586,7 @@ struct XAigerWriter
 					holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type);
 				RTLIL::Wire *holes_wire;
 				int num_inputs = 0;
+				// NB: cell->connections_ already sorted from before
 				for (const auto &c : cell->connections()) {
 					if (cell->input(c.first)) {
 						box_inputs += c.second.size();