From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 15:34:06 +0000 (-0700)
Subject: Add shregmap -tech xilinx test
X-Git-Tag: working-ls180~1085^2~55
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7a8cdbccfa6f619f2e25c540b5af6d8e34ff431;p=yosys.git

Add shregmap -tech xilinx test
---

diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
index 0e5fe882b..a717c54f1 100644
--- a/tests/various/shregmap.ys
+++ b/tests/various/shregmap.ys
@@ -64,3 +64,4 @@ sat -verify -prove-asserts -show-ports -seq 5 miter
 
 # design -load gate
 # stat
+