From: Richard Sandiford Date: Fri, 12 Jul 2019 08:14:34 +0000 (+0000) Subject: [arch64] Fix ambiguous .md attribute uses X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7ba492a04d0bfef9752cbb16fcce3ffc31bf99f;p=gcc.git [arch64] Fix ambiguous .md attribute uses This patch is part of a series that fixes ambiguous attribute uses in .md files, i.e. cases in which attributes didn't use to specify an iterator, and in which could have different values depending on the iterator chosen. No behavioural change except for dropping the unused SVE divide permutations. 2019-07-12 Richard Sandiford gcc/ * config/aarch64/aarch64.md (*compare_condjump) (loadwb_pair_, loadwb_pair_) (storewb_pair_, storewb_pair_) (*ands_compare0): Fix ambiguous uses of .md attributes. * config/aarch64/aarch64-simd.md (*aarch64_get_lane_extend): Likewise. (*aarch64_get_lane_zero_extend): Likewise. * config/aarch64/aarch64-sve.md (while_ult): Likewise. (*cond__any): Fix SVE_I/SVE_SDI typo. From-SVN: r273433 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0894db7f0d3..66e715f42e9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2019-07-12 Richard Sandiford + + * config/aarch64/aarch64.md (*compare_condjump) + (loadwb_pair_, loadwb_pair_) + (storewb_pair_, storewb_pair_) + (*ands_compare0): Fix ambiguous uses of .md attributes. + * config/aarch64/aarch64-simd.md + (*aarch64_get_lane_extend): Likewise. + (*aarch64_get_lane_zero_extend): Likewise. + * config/aarch64/aarch64-sve.md + (while_ult): Likewise. + (*cond__any): Fix SVE_I/SVE_SDI typo. + 2019-07-12 Richard Sandiford * doc/md.texi: Document that @ patterns can have different diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 0c2600f1fc6..d480e430f25 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3135,30 +3135,31 @@ (define_insn "*aarch64_get_lane_extend" [(set (match_operand:GPI 0 "register_operand" "=r") (sign_extend:GPI - (vec_select: + (vec_select: (match_operand:VDQQH 1 "register_operand" "w") (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] "TARGET_SIMD" { - operands[2] = aarch64_endian_lane_rtx (mode, INTVAL (operands[2])); + operands[2] = aarch64_endian_lane_rtx (mode, + INTVAL (operands[2])); return "smov\\t%0, %1.[%2]"; } - [(set_attr "type" "neon_to_gp")] -) - -(define_insn "*aarch64_get_lane_zero_extend" - [(set (match_operand:GPI 0 "register_operand" "=r") - (zero_extend:GPI - (vec_select: - (match_operand:VDQQH 1 "register_operand" "w") - (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] - "TARGET_SIMD" - { - operands[2] = aarch64_endian_lane_rtx (mode, - INTVAL (operands[2])); - return "umov\\t%w0, %1.[%2]"; - } - [(set_attr "type" "neon_to_gp")] + [(set_attr "type" "neon_to_gp")] +) + +(define_insn "*aarch64_get_lane_zero_extend" + [(set (match_operand:GPI 0 "register_operand" "=r") + (zero_extend:GPI + (vec_select: + (match_operand:VDQQH 1 "register_operand" "w") + (parallel [(match_operand:SI 2 "immediate_operand" "i")]))))] + "TARGET_SIMD" + { + operands[2] = aarch64_endian_lane_rtx (mode, + INTVAL (operands[2])); + return "umov\\t%w0, %1.[%2]"; + } + [(set_attr "type" "neon_to_gp")] ) ;; Lane extraction of a value, neither sign nor zero extension diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index c4670b6080b..e489afbdde9 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -1363,7 +1363,7 @@ ;; don't have an unnecessary PTRUE. "&& !CONSTANT_P (operands[1])" { - operands[1] = CONSTM1_RTX (mode); + operands[1] = CONSTM1_RTX (mode); } ) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 4d559c4c928..d1b2c20104d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -567,14 +567,14 @@ ;; sub x0, x1, #(CST & 0xfff000) ;; subs x0, x0, #(CST & 0x000fff) ;; b .Label -(define_insn_and_split "*compare_condjump" +(define_insn_and_split "*compare_condjump" [(set (pc) (if_then_else (EQL (match_operand:GPI 0 "register_operand" "r") (match_operand:GPI 1 "aarch64_imm24" "n")) (label_ref:P (match_operand 2 "" "")) (pc)))] - "!aarch64_move_imm (INTVAL (operands[1]), mode) - && !aarch64_plus_operand (operands[1], mode) + "!aarch64_move_imm (INTVAL (operands[1]), mode) + && !aarch64_plus_operand (operands[1], mode) && !reload_completed" "#" "&& true" @@ -582,11 +582,12 @@ { HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff; HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000; - rtx tmp = gen_reg_rtx (mode); - emit_insn (gen_add3 (tmp, operands[0], GEN_INT (-hi_imm))); - emit_insn (gen_add3_compare0 (tmp, tmp, GEN_INT (-lo_imm))); + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_add3 (tmp, operands[0], GEN_INT (-hi_imm))); + emit_insn (gen_add3_compare0 (tmp, tmp, GEN_INT (-lo_imm))); rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM); - rtx cmp_rtx = gen_rtx_fmt_ee (, mode, cc_reg, const0_rtx); + rtx cmp_rtx = gen_rtx_fmt_ee (, mode, + cc_reg, const0_rtx); emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2])); DONE; } @@ -1505,8 +1506,8 @@ (mem:GPI (plus:P (match_dup 1) (match_operand:P 5 "const_int_operand" "n"))))])] "INTVAL (operands[5]) == GET_MODE_SIZE (mode)" - "ldp\\t%2, %3, [%1], %4" - [(set_attr "type" "load_")] + "ldp\\t%2, %3, [%1], %4" + [(set_attr "type" "load_")] ) (define_insn "loadwb_pair_" @@ -1520,7 +1521,7 @@ (mem:GPF (plus:P (match_dup 1) (match_operand:P 5 "const_int_operand" "n"))))])] "INTVAL (operands[5]) == GET_MODE_SIZE (mode)" - "ldp\\t%2, %3, [%1], %4" + "ldp\\t%2, %3, [%1], %4" [(set_attr "type" "neon_load1_2reg")] ) @@ -1553,8 +1554,8 @@ (match_operand:P 5 "const_int_operand" "n"))) (match_operand:GPI 3 "register_operand" "r"))])] "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (mode)" - "stp\\t%2, %3, [%0, %4]!" - [(set_attr "type" "store_")] + "stp\\t%2, %3, [%0, %4]!" + [(set_attr "type" "store_")] ) (define_insn "storewb_pair_" @@ -1569,7 +1570,7 @@ (match_operand:P 5 "const_int_operand" "n"))) (match_operand:GPF 3 "register_operand" "w"))])] "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (mode)" - "stp\\t%2, %3, [%0, %4]!" + "stp\\t%2, %3, [%0, %4]!" [(set_attr "type" "neon_store1_2reg")] ) @@ -4782,7 +4783,7 @@ [(set_attr "type" "alus_imm")] ) -(define_insn "*ands_compare0" +(define_insn "*ands_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ (zero_extend:GPI (match_operand:SHORT 1 "register_operand" "r"))