From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 12 Sep 2015 14:01:20 +0000 (+0200)
Subject: Fixed sharing of $memrd cells
X-Git-Tag: yosys-0.6~166
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7c018e5d14c3c609669ab514a7e9111ff006022;p=yosys.git

Fixed sharing of $memrd cells
---

diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 2c39708bb..9dd0dc0a3 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -708,6 +708,10 @@ struct ShareWorker
 		if (c1->type == "$memrd")
 		{
 			RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
+			RTLIL::SigSpec addr1 = c1->getPort("\\ADDR");
+			RTLIL::SigSpec addr2 = c2->getPort("\\ADDR");
+			if (addr1 != addr2)
+				supercell->setPort("\\ADDR", module->Mux(NEW_ID, addr2, addr1, act));
 			supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort("\\DATA"), c2->getPort("\\DATA")));
 			supercell_aux.insert(supercell);
 			return supercell;