From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 2 Sep 2019 10:26:15 +0000 (+0100)
Subject: dev-arm: State update when setting MISCREG_ICC_IGRPENx register
X-Git-Tag: v19.0.0.0~571
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7c75d2c114836203fb5c4d0a7d842c4f4ebaa0e;p=gem5.git

dev-arm: State update when setting MISCREG_ICC_IGRPENx register

This is because by enabling ainterrupt group at the cpu interface, we
need to check if a previously pending interrupt needs to be forwarded to
the PE.
We are doing the same when globally enabling irqs in the distributor
(GICD_CTLR).

Change-Id: I80aeb87b2a58a108de899006d5a2f12eadbe6c2e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20629
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index b793f7c28..0cb036798 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -1321,7 +1321,9 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
               return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
           }
 
-          break;
+          isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val);
+          updateDistributor();
+          return;
       }
 
       // Virtual Interrupt Group 0 Enable register
@@ -1360,6 +1362,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
           }
 
           setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
+          updateDistributor();
           return;
       }