From: Luke Kenneth Casson Leighton Date: Thu, 9 Jul 2020 18:57:34 +0000 (+0100) Subject: check result first then CR second X-Git-Tag: div_pipeline~134 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7ce4abfb14fb7c2e9849b4799cdbf0af8bfdeb3;p=soc.git check result first then CR second --- diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index 2fe7ac08..9041aa6d 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -220,9 +220,9 @@ class TestRunner(FHDLTestCase): yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2) yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2) + ALUHelpers.check_int_o(self, res, sim_o, code) ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) ALUHelpers.check_xer_ov(self, res, sim_o, code) - ALUHelpers.check_int_o(self, res, sim_o, code) ALUHelpers.check_xer_so(self, res, sim_o, code)