From: Benedikt Tutzer <e1225461@student.tuwien.ac.at>
Date: Tue, 10 Jul 2018 06:52:36 +0000 (+0200)
Subject: added destructors for wires and cells
X-Git-Tag: yosys-0.9~179^2~50
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7d3f3cd464fe323872285bed40e6f347683147b;p=yosys.git

added destructors for wires and cells
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 5cef90206..6e8b51682 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2223,6 +2223,13 @@ RTLIL::Wire::Wire()
 #endif
 }
 
+RTLIL::Wire::~Wire()
+{
+#ifdef WITH_PYTHON
+	RTLIL::Wire::get_all_wires()->erase(hashidx_);
+#endif
+}
+
 #ifdef WITH_PYTHON
 static std::map<unsigned int, RTLIL::Wire*> *all_wires = new std::map<unsigned int, RTLIL::Wire*>();
 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
@@ -2256,6 +2263,13 @@ RTLIL::Cell::Cell() : module(nullptr)
 #endif
 }
 
+RTLIL::Cell::~Cell()
+{
+#ifdef WITH_PYTHON
+	RTLIL::Cell::get_all_cells()->erase(hashidx_);
+#endif
+}
+
 #ifdef WITH_PYTHON
 static std::map<unsigned int, RTLIL::Cell*> *all_cells = new std::map<unsigned int, RTLIL::Cell*>();
 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 232a8c13a..e71a5fceb 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1149,7 +1149,7 @@ protected:
 	// use module->addWire() and module->remove() to create or destroy wires
 	friend struct RTLIL::Module;
 	Wire();
-	~Wire() { };
+	~Wire();
 
 public:
 	// do not simply copy wires
@@ -1186,6 +1186,7 @@ protected:
 	// use module->addCell() and module->remove() to create or destroy cells
 	friend struct RTLIL::Module;
 	Cell();
+	~Cell();
 
 public:
 	// do not simply copy cells