From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 23 Jan 2022 11:05:23 +0000 (+0000)
Subject: looked in soc.vhdl in microwatt and the parameters are 64 cache
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7de0b277f0c88990eafcdfac9292037120a94fa;p=soc.git

looked in soc.vhdl in microwatt and the parameters are 64 cache
lines.  this would not be important if it was not explicitly in
the linux-5.7 device-tree file
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 910d123a..f12a736e 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -68,8 +68,8 @@ from nmutil.util import wrap
 
 # TODO: make these parameters of DCache at some point
 LINE_SIZE = 64    # Line size in bytes
-NUM_LINES = 32    # Number of lines in a set
-NUM_WAYS = 4      # Number of ways
+NUM_LINES = 64    # Number of lines in a set
+NUM_WAYS = 2      # Number of ways
 TLB_SET_SIZE = 64 # L1 DTLB entries per set
 TLB_NUM_WAYS = 2  # L1 DTLB number of sets
 TLB_LG_PGSZ = 12  # L1 DTLB log_2(page_size)
diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 8010bf2e..3f37b5bf 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -72,9 +72,9 @@ LINE_SIZE      = 64
 # ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
 ROW_SIZE       = WB_DATA_BITS // 8
 # Number of lines in a set
-NUM_LINES      = 32
+NUM_LINES      = 64
 # Number of ways
-NUM_WAYS       = 4
+NUM_WAYS       = 2
 # L1 ITLB number of entries (direct mapped)
 TLB_SIZE       = 64
 # L1 ITLB log_2(page_size)