From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 16 Apr 2018 18:23:13 +0000 (+0100)
Subject: add SIMD comparison section
X-Git-Tag: convert-csv-opcode-to-binary~5652
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7ebc07288f758c0440fc31e5cb5f6a3b5114fa7;p=libreriscv.git

add SIMD comparison section
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index c19db7a05..d1b6dd20a 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1119,7 +1119,7 @@ instruction decode) with minimum disruption and effort.
 RVV is extremely well-designed and has some amazing features, including
 2D reorganisation of memory through LOAD/STORE "strides".
 
-* plus: regular predictable workload means that implmentations may
+* plus: regular predictable workload means that implementations may
   streamline effects on L1/L2 Cache.
 * plus: regular and clear parallel workload also means that lanes
   (similar to Alt-RVP) may be used as an implementation detail,