From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Thu, 16 Feb 2012 03:44:24 +0000 (-0800)
Subject: reimplement div[u][w]/rem[u][w]
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e819f852c5eafb457401396d9c3de85cd5870549;p=riscv-isa-sim.git

reimplement div[u][w]/rem[u][w]

fixes bugs for inputs not properly sign-extended
---

diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 82a4066..8412f61 100644
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,6 +1,8 @@
-if(RS2 == 0)
+sreg_t lhs = sext_xprlen(RS1);
+sreg_t rhs = sext_xprlen(RS2);
+if(rhs == 0)
   RD = UINT64_MAX;
-else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
-  RD = RS1;
+else if(lhs == INT64_MIN && rhs == -1)
+  RD = lhs;
 else
-  RD = sext_xprlen(sext_xprlen(RS1) / sext_xprlen(RS2));
+  RD = sext_xprlen(lhs / rhs);
diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 681afd2..4346349 100644
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,4 +1,6 @@
-if(RS2 == 0)
+reg_t lhs = zext_xprlen(RS1);
+reg_t rhs = zext_xprlen(RS2);
+if(rhs == 0)
   RD = UINT64_MAX;
 else
-  RD = sext_xprlen(zext_xprlen(RS1) / zext_xprlen(RS2));
+  RD = sext_xprlen(lhs / rhs);
diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index 2cf0511..7f6e321 100644
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,5 +1,7 @@
 require_xpr64;
-if(zext32(RS2) == 0)
+reg_t lhs = zext32(RS1);
+reg_t rhs = zext32(RS2);
+if(rhs == 0)
   RD = UINT64_MAX;
 else
-  RD = sext32(zext32(RS1) / zext32(RS2));
+  RD = sext32(lhs / rhs);
diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index 84f42a9..b51d9b7 100644
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,7 +1,7 @@
 require_xpr64;
-if(int32_t(RS2) == 0)
+sreg_t lhs = sext32(RS1);
+sreg_t rhs = sext32(RS2);
+if(rhs == 0)
   RD = UINT64_MAX;
-else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
-  RD = RS1;
 else
-  RD = sext32(int32_t(RS1) / int32_t(RS2));
+  RD = sext32(lhs / rhs);
diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index ac82a56..8094b5b 100644
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,6 +1,8 @@
-if(RS2 == 0)
-  RD = RS1;
-else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
+sreg_t lhs = sext_xprlen(RS1);
+sreg_t rhs = sext_xprlen(RS2);
+if(rhs == 0)
+  RD = lhs;
+else if(lhs == INT64_MIN && rhs == -1)
   RD = 0;
 else
-  RD = sext_xprlen(sext_xprlen(RS1) % sext_xprlen(RS2));
+  RD = sext_xprlen(lhs % rhs);
diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index c698aca..ca66318 100644
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,4 +1,6 @@
-if(RS2 == 0)
-  RD = RS1;
+reg_t lhs = zext_xprlen(RS1);
+reg_t rhs = zext_xprlen(RS2);
+if(rhs == 0)
+  RD = lhs;
 else
-  RD = sext_xprlen(zext_xprlen(RS1) % zext_xprlen(RS2));
+  RD = sext_xprlen(lhs % rhs);
diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index 1cc015d..aac13fb 100644
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,5 +1,7 @@
 require_xpr64;
-if(zext_xprlen(RS2) == 0)
-  RD = RS1;
+reg_t lhs = zext32(RS1);
+reg_t rhs = zext32(RS2);
+if(rhs == 0)
+  RD = lhs;
 else
-  RD = sext32(zext_xprlen(RS1) % zext_xprlen(RS2));
+  RD = sext32(lhs % rhs);
diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index 1093533..cc89fa7 100644
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,7 +1,7 @@
 require_xpr64;
-if(int32_t(RS2) == 0)
-  RD = RS1;
-else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
-  RD = 0;
+sreg_t lhs = sext32(RS1);
+sreg_t rhs = sext32(RS2);
+if(rhs == 0)
+  RD = lhs;
 else
-  RD = sext32(int32_t(RS1) % int32_t(RS2));
+  RD = sext32(lhs % rhs);