From: lkcl <lkcl@web>
Date: Mon, 16 Aug 2021 15:51:22 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~423
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e81b0060b849373bd2afe04896bde505bfbd4425;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 5ded5ded2..47556095e 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -81,7 +81,8 @@ behaviour*)
 In Vertical-First Mode, the `ALL` bit still applies, but to the elements
 that are executed up to the Hint length, in parallel batches. Contrast
 this with Horizontal-First Mode which tests elements from
-`0..VL-1`, Vertical-First tests elements `srcstep..MIN(srcstep+VFHint,VL-1)` See
+`0..VL-1`, Vertical-First tests elements
+`srcstep..MIN(srcstep+VFHint-1,VL-1)`. See
 [[sv/setvl]] for the definition of Vertical-First Hint.
 
 Predication in both INT and CR modes may be applied to `sv.bc` and other