From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 23 May 2020 15:21:21 +0000 (+0100)
Subject: add stub DataMerger class
X-Git-Tag: div_pipeline~912
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e81df6a0efb1e66eca096e1950a8ebb6f2ad3571;p=soc.git

add stub DataMerger class
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 5dc6daae..ae26656b 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -127,6 +127,22 @@ class DualPortSplitter(Elaboratable):
     pass
 
 
+# TODO:
+class DataMerger(Elaboratable):
+    """DataMerger
+
+    Merges data based on an address-match matrix
+
+    """
+    def __init__(self, array_size):
+        """
+        :addr_array_i: an NxN Array of Signals with bits set indicating address match
+        :data_i: an Nx Array of Records {data: 128 bit, byte_enable: 16 bit}
+        :data_o: an Output Record of same type {data: 128 bit, byte_enable: 16 bit}
+        """
+        pass
+
+
 class LDSTPort(Elaboratable):
     def __init__(self, idx, regwid=64, addrwid=48):
         self.pi = PortInterface("ldst_port%d" % idx, regwid, addrwid)