From: Luke Leighton <lkcl@lkcl.net>
Date: Tue, 27 Feb 2018 00:21:20 +0000 (+0000)
Subject: add more interfaces
X-Git-Tag: convert-csv-opcode-to-binary~5861
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e82512b53f95fb126ad5f06b7b97833d66858e77;p=libreriscv.git

add more interfaces
---

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 4c69326e6..6c4980498 100644
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -220,6 +220,12 @@ List of Interfaces:
 * [[SPI]]
 * SD/MMC and eMMC [[sdmmc]]
 * Pin Multiplexing [[pinmux]]
+* Gigabit Ethernet [[RGMII]]
+
+List of Internal Interfaces:
+
+* [[AXI]]
+* [[wishbone]]
 
 # Items requiring clarification, or proposals TBD
 
diff --git a/shakti/m_class/AXI.mdwn b/shakti/m_class/AXI.mdwn
new file mode 100644
index 000000000..534538bda
--- /dev/null
+++ b/shakti/m_class/AXI.mdwn
@@ -0,0 +1,6 @@
+# AXI Bridge
+
+See also [[wishbone]] Bus
+
+*
+* <https://github.com/alexforencich/verilog-axis>
diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
new file mode 100644
index 000000000..8606bac42
--- /dev/null
+++ b/shakti/m_class/wishbone.mdwn
@@ -0,0 +1,6 @@
+# Wishbone Bridge
+
+See also [[AXI]] Bus
+
+*
+* <https://github.com/alexforencich/verilog-wishbone>