From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 2 Dec 2015 13:18:09 +0000 (+0100)
Subject: build: pass build_name to get_verilog (same name for top module and top level file)
X-Git-Tag: 24jan2021_ls180~2027
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8262ed44792eb46fb1164e62446f289a9613159;p=litex.git

build: pass build_name to get_verilog (same name for top module and top level file)
---

diff --git a/litex/build/altera/quartus.py b/litex/build/altera/quartus.py
index cdab36be..e7a27622 100644
--- a/litex/build/altera/quartus.py
+++ b/litex/build/altera/quartus.py
@@ -113,7 +113,7 @@ quartus_sta {build_name} -c {build_name}
 
 class AlteraQuartusToolchain:
     def build(self, platform, fragment, build_dir="build", build_name="top",
-              toolchain_path="/opt/Altera", run=True):
+              toolchain_path="/opt/Altera", run=True, **kwargs):
         cwd = os.getcwd()
         tools.mkdir_noerror(build_dir)
         os.chdir(build_dir)
@@ -122,7 +122,7 @@ class AlteraQuartusToolchain:
             fragment = fragment.get_fragment()
         platform.finalize(fragment)
 
-        v_output = platform.get_verilog(fragment)
+        v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
diff --git a/litex/build/lattice/diamond.py b/litex/build/lattice/diamond.py
index 857fef02..68d1db44 100644
--- a/litex/build/lattice/diamond.py
+++ b/litex/build/lattice/diamond.py
@@ -76,7 +76,7 @@ def _run_diamond(build_name, source, ver=None):
 
 class LatticeDiamondToolchain:
     def build(self, platform, fragment, build_dir="build", build_name="top",
-              toolchain_path="/opt/Diamond", run=True):
+              toolchain_path="/opt/Diamond", run=True, **kwargs):
         tools.mkdir_noerror(build_dir)
         cwd = os.getcwd()
         os.chdir(build_dir)
@@ -85,7 +85,7 @@ class LatticeDiamondToolchain:
             fragment = fragment.get_fragment()
         platform.finalize(fragment)
 
-        v_output = platform.get_verilog(fragment)
+        v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py
index e2d29ac3..374bffc0 100644
--- a/litex/build/xilinx/ise.py
+++ b/litex/build/xilinx/ise.py
@@ -133,7 +133,7 @@ class XilinxISEToolchain:
         self.ise_commands = ""
 
     def build(self, platform, fragment, build_dir="build", build_name="top",
-            toolchain_path=None, source=None, run=True, mode="xst"):
+            toolchain_path=None, source=None, run=True, mode="xst", **kwargs):
         if not isinstance(fragment, _Fragment):
             fragment = fragment.get_fragment()
         if toolchain_path is None:
@@ -155,7 +155,7 @@ class XilinxISEToolchain:
         os.chdir(build_dir)
         try:
             if mode == "xst" or mode == "yosys":
-                v_output = platform.get_verilog(fragment)
+                v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
                 vns = v_output.ns
                 named_sc, named_pc = platform.resolve_signals(vns)
                 v_file = build_name + ".v"
diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 557016e7..032b78bb 100644
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -112,7 +112,7 @@ class XilinxVivadoToolchain:
         tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
 
     def build(self, platform, fragment, build_dir="build", build_name="top",
-            toolchain_path="/opt/Xilinx/Vivado", source=True, run=True):
+            toolchain_path="/opt/Xilinx/Vivado", source=True, run=True, **kwargs):
         tools.mkdir_noerror(build_dir)
         cwd = os.getcwd()
         os.chdir(build_dir)
@@ -120,7 +120,7 @@ class XilinxVivadoToolchain:
         if not isinstance(fragment, _Fragment):
             fragment = fragment.get_fragment()
         platform.finalize(fragment)
-        v_output = platform.get_verilog(fragment)
+        v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)