From: Luke Kenneth Casson Leighton Date: Thu, 15 Nov 2018 15:36:27 +0000 (+0000) Subject: add remap a tag X-Git-Tag: convert-csv-opcode-to-binary~4839 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e833215000d6d21fa9bc3b396d6cdca37938c9af;p=libreriscv.git add remap a tag --- diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 12bf0446c..572f87f81 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -671,7 +671,7 @@ for the storage of comparisions: in these specific circumstances the requirement for there to be an active CSR *register* entry is removed. -## REMAP CSR +## REMAP CSR (Note: both the REMAP and SHAPE sections are best read after the rest of the document has been read) @@ -963,8 +963,8 @@ Where vectorisation is present on either or both src registers, the branch may stil go ahead if any only if *all* tests succeed (i.e. excluding those tests that are predicated out). -Note that when either src1 or src2 have zero-predication enabled, -a cleared bit in the respective predicate indicates that the result +Note that when zero-predication is enabled (from source rs1), +a cleared bit in the predicate indicates that the result of the compare is set to "false", i.e. that the corresponding destination bit (or result)) be set to zero. Contrast this with when zeroing is not set: bits in the destination predicate are