From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 8 Sep 2020 08:06:11 +0000 (+0100)
Subject: add cxxsim option
X-Git-Tag: semi_working_ecp5~130
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8382995b860b6949c075ceb063f2a1bd942bd9b;p=soc.git

add cxxsim option
---

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 91e68a71..6426d05b 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -5,7 +5,10 @@ related bugs:
  * https://bugs.libre-soc.org/show_bug.cgi?id=363
 """
 from nmigen import Module, Signal, Cat
-from nmigen.back.pysim import Simulator, Delay, Settle
+if True:
+    from nmigen.back.pysim import Simulator, Delay, Settle
+else:
+    from nmigen.sim.cxxsim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest