From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 22:47:40 +0000 (-0700)
Subject: Cleanup
X-Git-Tag: working-ls180~1039^2~249
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e83f231927c41e1771da2e8d1a2153361afc30b0;p=yosys.git

Cleanup
---

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 41f34b4bd..a1b0b5004 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -21,8 +21,8 @@ code sigH
 endcode
 
 match ffA
+	if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
 	select ffA->type.in($dff)
-	filter mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
 	filter !port(mul, \A).remove_const().empty()
 	filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
 	optional
@@ -44,8 +44,8 @@ code sigA clock clock_pol
 endcode
 
 match ffB
+	if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
 	select ffB->type.in($dff)
-	filter mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
 	filter !port(mul, \B).remove_const().empty()
 	filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
 	optional
@@ -73,11 +73,11 @@ code sigB clock clock_pol
 endcode
 
 match ffH
+	if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
 	select ffH->type.in($dff)
 	select nusers(port(ffH, \D)) == 2
 	index <SigSpec> port(ffH, \D) === sigH
 	// Ensure pipeline register is not already used
-	filter mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
 	optional
 endmatch
 
@@ -154,7 +154,7 @@ endcode
 
 match muxA
 	select muxA->type.in($mux)
-	select nusers(port(muxA, \A)) == 2
+	index <int> nusers(port(muxA, \A)) === 2
 	index <SigSpec> port(muxA, \A) === sigO
 	optional
 endmatch
@@ -162,7 +162,7 @@ endmatch
 match muxB
 	if !muxA
 	select muxB->type.in($mux)
-	select nusers(port(muxB, \B)) == 2
+	index <int> nusers(port(muxB, \B)) === 2
 	index <SigSpec> port(muxB, \B) === sigO
 	optional
 endmatch
@@ -185,16 +185,16 @@ code sigOused
 endcode
 
 match ffO_lo
+	if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2
 	select ffO_lo->type.in($dff)
-	filter nusers(sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()))) == 2
 	filter includes(port(ffO_lo, \D).to_sigbit_set(), sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int())).remove_const().to_sigbit_set())
 	optional
 endmatch
 
 match ffO_hi
+	if GetSize(sigOused) > 16
+	if nusers(sigOused.extract_end(16)) == 2
 	select ffO_hi->type.in($dff)
-	filter GetSize(sigOused) > 16
-	filter nusers(sigOused.extract_end(16)) == 2
 	filter includes(port(ffO_hi, \D).to_sigbit_set(), sigOused.extract_end(16).remove_const().to_sigbit_set())
 	optional
 endmatch
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 4f5fae8df..f982a10cf 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -9,11 +9,11 @@ match dsp
 endmatch
 
 match ffA
+	if param(dsp, \AREG).as_int() == 0
+	if !port(dsp, \A).remove_const().empty()
 	select ffA->type.in($dff)
 	// DSP48E1 does not support clock inversion
 	select param(ffA, \CLK_POLARITY).as_bool()
-	filter param(dsp, \AREG).as_int() == 0
-	filter !port(dsp, \A).remove_const().empty()
 	filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set())
 	optional
 endmatch
@@ -24,11 +24,11 @@ code clock
 endcode
 
 match ffB
+	if param(dsp, \BREG).as_int() == 0
+	if !port(dsp, \B).remove_const().empty()
 	select ffB->type.in($dff)
 	// DSP48E1 does not support clock inversion
 	select param(ffB, \CLK_POLARITY).as_bool()
-	filter param(dsp, \BREG).as_int() == 0
-	filter !port(dsp, \B).remove_const().empty()
 	filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set())
 	optional
 endmatch
@@ -51,9 +51,9 @@ endcode
 match addA
 	select addA->type.in($add)
 	select param(addA, \A_SIGNED).as_bool() && param(addA, \B_SIGNED).as_bool()
-	select nusers(port(addA, \A)) == 2
+	index <int> nusers(port(addA, \A)) === 2
 	//index <SigSpec> port(addA, \A) === sigP.extract(0, param(addA, \A_WIDTH).as_int())
-	filter GetSize(sigP) >= param(addA, \A_WIDTH).as_int()
+	filter param(addA, \A_WIDTH).as_int() <= GetSize(sigP)
 	filter port(addA, \A) == sigP.extract(0, param(addA, \A_WIDTH).as_int())
 	optional
 endmatch
@@ -62,9 +62,9 @@ match addB
 	if !addA
 	select addB->type.in($add, $sub)
 	select param(addB, \A_SIGNED).as_bool() && param(addB, \B_SIGNED).as_bool()
-	select nusers(port(addB, \B)) == 2
+	index <int> nusers(port(addB, \B)) === 2
 	//index <SigSpec> port(addB, \B) === sigP.extract(0, param(addB, \B_WIDTH).as_int())
-	filter GetSize(sigP) >= param(addB, \B_WIDTH).as_int()
+	filter param(addB, \B_WIDTH).as_int() <= GetSize(sigP)
 	filter port(addB, \B) ==  sigP.extract(0, param(addB, \B_WIDTH).as_int())
 	optional
 endmatch
@@ -110,12 +110,12 @@ code sigPused
 endcode
 
 match ffP
+	if param(dsp, \PREG).as_int() == 0
 	if !sigPused.empty()
 	select ffP->type.in($dff)
-	select nusers(port(ffP, \D)) == 2
+	index <int> nusers(port(ffP, \D)) === 2
 	// DSP48E1 does not support clock inversion
 	select param(ffP, \CLK_POLARITY).as_bool()
-	filter param(dsp, \PREG).as_int() == 0
 	filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
 	filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
 	optional