From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 11 May 2021 11:27:00 +0000 (+0100)
Subject: add setting of MSR "PR" bit for when running MMU test
X-Git-Tag: 0.0.3~56
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e84bed4b66dcd68856aeb6aed028ccda31cbf5b5;p=openpower-isa.git

add setting of MSR "PR" bit for when running MMU test
---

diff --git a/src/openpower/test/mmu/mmu_rom_cases.py b/src/openpower/test/mmu/mmu_rom_cases.py
index 75ba5617..746d8a10 100644
--- a/src/openpower/test/mmu/mmu_rom_cases.py
+++ b/src/openpower/test/mmu/mmu_rom_cases.py
@@ -1,6 +1,8 @@
 from openpower.simulator.program import Program
 from openpower.endian import bigendian
 from openpower.test.common import (TestAccumulatorBase, skip_case)
+from openpower.consts import MSR
+
 
 def b(x):
     return int.from_bytes(x.to_bytes(8, byteorder='little'),
@@ -45,9 +47,11 @@ class MMUTestCaseROM(TestAccumulatorBase):
         prtbl = 0x1000000
         initial_regs[1] = prtbl
         
+        initial_msr = 1 << MSR.PR # must set "problem" state for virtual memory
         initial_sprs = {'DSISR': 0, 'DAR': 0,
                          720: 0}
         self.add_case(Program(lst, bigendian),
-                      initial_regs, initial_sprs)
+                      initial_regs, initial_sprs,
+                      initial_msr=initial_msr)