From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 22:41:31 +0000 (+0100)
Subject: rename FPADDBaseData to FPBaseData and move to separate module
X-Git-Tag: ls180-24jan2020~592
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8507974125bb8d80371e2f08521292c849b44e5;p=ieee754fpu.git

rename FPADDBaseData to FPBaseData and move to separate module
---

diff --git a/src/ieee754/fclass/fclass.py b/src/ieee754/fclass/fclass.py
index 09b5d478..8d5de09e 100644
--- a/src/ieee754/fclass/fclass.py
+++ b/src/ieee754/fclass/fclass.py
@@ -4,7 +4,7 @@
 from nmigen import Module, Signal, Cat
 
 from nmutil.pipemodbase import PipeModBase
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
@@ -18,7 +18,7 @@ class FPClassMod(PipeModBase):
         super().__init__(in_pspec, "fclass")
 
     def ispec(self):
-        return FPADDBaseData(self.in_pspec)
+        return FPBaseData(self.in_pspec)
 
     def ospec(self):
         return FPPackData(self.out_pspec)
diff --git a/src/ieee754/fclass/pipeline.py b/src/ieee754/fclass/pipeline.py
index af032310..dbb4460a 100644
--- a/src/ieee754/fclass/pipeline.py
+++ b/src/ieee754/fclass/pipeline.py
@@ -8,7 +8,7 @@ from nmigen.cli import main, verilog
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.pack import FPPackData
 
 
@@ -49,7 +49,7 @@ class FPClassBasePipe(ControlBase):
 class FPClassMuxInOutBase(ReservationStations):
     """ Reservation-Station version of FPClass pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
         * 2-stage multiplier pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
@@ -68,7 +68,7 @@ class FPClassMuxInOutBase(ReservationStations):
         ReservationStations.__init__(self, num_rows)
 
     def i_specfn(self):
-        return FPADDBaseData(self.in_pspec)
+        return FPBaseData(self.in_pspec)
 
     def o_specfn(self):
         return FPPackData(self.out_pspec)
@@ -77,7 +77,7 @@ class FPClassMuxInOutBase(ReservationStations):
 class FPClassMuxInOut(FPClassMuxInOutBase):
     """ Reservation-Station version of FPClass pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
         * 2-stage multiplier pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
diff --git a/src/ieee754/fcvt/downsize.py b/src/ieee754/fcvt/downsize.py
index 1628c3f9..bcc92525 100644
--- a/src/ieee754/fcvt/downsize.py
+++ b/src/ieee754/fcvt/downsize.py
@@ -5,7 +5,7 @@ from nmigen import Module, Signal, Const
 from nmigen.cli import main, verilog
 
 from nmutil.pipemodbase import PipeModBase
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.postcalc import FPPostCalcData
 from ieee754.fpcommon.msbhigh import FPMSBHigh
 from ieee754.fpcommon.exphigh import FPEXPHigh
@@ -22,7 +22,7 @@ class FPCVTDownConvertMod(PipeModBase):
         super().__init__(in_pspec, "downconvert")
 
     def ispec(self):
-        return FPADDBaseData(self.in_pspec)
+        return FPBaseData(self.in_pspec)
 
     def ospec(self):
         return FPPostCalcData(self.out_pspec, e_extra=True)
diff --git a/src/ieee754/fcvt/float2int.py b/src/ieee754/fcvt/float2int.py
index 845a4e00..d28ab19d 100644
--- a/src/ieee754/fcvt/float2int.py
+++ b/src/ieee754/fcvt/float2int.py
@@ -5,7 +5,7 @@ from nmigen import Module, Signal, Cat, Const, Mux, Elaboratable
 from nmigen.cli import main, verilog
 
 from ieee754.fpcommon.fpbase import Overflow
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.postcalc import FPPostCalcData
 from ieee754.fpcommon.exphigh import FPEXPHigh
 
@@ -27,7 +27,7 @@ class FPCVTFloatToIntMod(Elaboratable):
         self.o = self.ospec()
 
     def ispec(self):
-        return FPADDBaseData(self.in_pspec)
+        return FPBaseData(self.in_pspec)
 
     def ospec(self):
         return FPPackData(self.out_pspec)
diff --git a/src/ieee754/fcvt/int2float.py b/src/ieee754/fcvt/int2float.py
index 8c25cdb8..2004abc2 100644
--- a/src/ieee754/fcvt/int2float.py
+++ b/src/ieee754/fcvt/int2float.py
@@ -5,7 +5,7 @@ from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
 from nmutil.pipemodbase import PipeModBase
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.postcalc import FPPostCalcData
 from ieee754.fpcommon.msbhigh import FPMSBHigh
 
@@ -24,7 +24,7 @@ class FPCVTIntToFloatMod(PipeModBase):
         super().__init__(in_pspec, "intconvert")
 
     def ispec(self):
-        return FPADDBaseData(self.in_pspec)
+        return FPBaseData(self.in_pspec)
 
     def ospec(self):
         return FPPostCalcData(self.out_pspec, e_extra=True)
diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index 605bb16a..2eb83c5a 100644
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -14,7 +14,7 @@ from nmigen.cli import main, verilog
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
 
@@ -88,7 +88,7 @@ class FPCVTBasePipe(ControlBase):
 class FPCVTMuxInOutBase(ReservationStations):
     """ Reservation-Station version of FPCVT pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
         * 2-stage multiplier pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
@@ -107,7 +107,7 @@ class FPCVTMuxInOutBase(ReservationStations):
         ReservationStations.__init__(self, num_rows)
 
     def i_specfn(self):
-        return FPADDBaseData(self.in_pspec)
+        return FPBaseData(self.in_pspec)
 
     def o_specfn(self):
         return FPPackData(self.out_pspec)
@@ -116,7 +116,7 @@ class FPCVTMuxInOutBase(ReservationStations):
 class FPCVTF2IntMuxInOut(FPCVTMuxInOutBase):
     """ Reservation-Station version of FPCVT pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
         * 2-stage multiplier pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
diff --git a/src/ieee754/fcvt/upsize.py b/src/ieee754/fcvt/upsize.py
index 9aefa328..ec281350 100644
--- a/src/ieee754/fcvt/upsize.py
+++ b/src/ieee754/fcvt/upsize.py
@@ -9,7 +9,7 @@ from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
 from nmutil.pipemodbase import PipeModBase
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.postcalc import FPPostCalcData
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
@@ -23,7 +23,7 @@ class FPCVTUpConvertMod(PipeModBase):
         super().__init__(in_pspec, "upconvert")
 
     def ispec(self):
-        return FPADDBaseData(self.in_pspec)
+        return FPBaseData(self.in_pspec)
 
     def ospec(self):
         return FPPostCalcData(self.out_pspec, e_extra=False)
diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index 943533c6..bbeff3d1 100644
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -8,7 +8,7 @@ Stack looks like this:
 * addalign  - FPAddAlignSingleAdd
 * normpack  - FPNormToPack
 
-scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
+scnorm   - FPDIVSpecialCasesDeNorm ispec FPBaseData
 ------                             ospec FPSCData
 
                 StageChain: FPMULSpecialCasesMod,
@@ -46,7 +46,7 @@ from nmutil.multipipe import CombMuxOutPipe
 from nmutil.multipipe import PriorityCombMuxInPipe
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
@@ -76,7 +76,7 @@ class FPADDBasePipe(ControlBase):
 class FPADDMuxInOut(ReservationStations):
     """ Reservation-Station version of FPADD pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
         * 3-stage adder pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
@@ -91,7 +91,7 @@ class FPADDMuxInOut(ReservationStations):
         ReservationStations.__init__(self, num_rows)
 
     def i_specfn(self):
-        return FPADDBaseData(self.pspec)
+        return FPBaseData(self.pspec)
 
     def o_specfn(self):
         return FPPackData(self.pspec)
diff --git a/src/ieee754/fpadd/specialcases.py b/src/ieee754/fpadd/specialcases.py
index 68cad890..e87212d1 100644
--- a/src/ieee754/fpadd/specialcases.py
+++ b/src/ieee754/fpadd/specialcases.py
@@ -10,7 +10,7 @@ from nmutil.pipemodbase import PipeModBase, PipeModBaseChain
 from ieee754.fpcommon.fpbase import FPNumDecode
 
 from ieee754.fpcommon.fpbase import FPNumBaseRecord
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNormMod)
 
 
@@ -24,7 +24,7 @@ class FPAddSpecialCasesMod(PipeModBase):
         super().__init__(pspec, "specialcases")
 
     def ispec(self):
-        return FPADDBaseData(self.pspec)
+        return FPBaseData(self.pspec)
 
     def ospec(self):
         return FPSCData(self.pspec, True)
diff --git a/src/ieee754/fpadd/statemachine.py b/src/ieee754/fpadd/statemachine.py
index 1f59cacb..efc2ebc6 100644
--- a/src/ieee754/fpadd/statemachine.py
+++ b/src/ieee754/fpadd/statemachine.py
@@ -11,7 +11,7 @@ from ieee754.fpcommon.fpbase import Trigger
 from nmutil.singlepipe import StageChain
 
 from ieee754.fpcommon.fpbase import FPState, FPID
-from ieee754.fpcommon.getop import (FPGetOp, FPADDBaseData, FPGet2Op)
+from ieee754.fpcommon.getop import (FPGetOp, FPBaseData, FPGet2Op)
 from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNorm)
 from ieee754.fpcommon.postcalc import FPPostCalcData
 from ieee754.fpcommon.postnormalise import (FPNorm1Data,
@@ -68,7 +68,7 @@ class FPADDBaseMod(Elaboratable):
         self.states = []
 
     def ispec(self):
-        return FPADDBaseData(self.width, self.id_wid)
+        return FPBaseData(self.width, self.id_wid)
 
     def ospec(self):
         return FPOpData(self.width, self.id_wid)
diff --git a/src/ieee754/fpcommon/basedata.py b/src/ieee754/fpcommon/basedata.py
new file mode 100644
index 00000000..056ad44c
--- /dev/null
+++ b/src/ieee754/fpcommon/basedata.py
@@ -0,0 +1,37 @@
+# IEEE Floating Point Adder (Single Precision)
+# Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
+from nmigen import Signal
+from ieee754.fpcommon.getop import FPPipeContext
+
+
+class FPBaseData:
+
+    def __init__(self, pspec, n_ops=2):
+        width = pspec.width
+        self.ctx = FPPipeContext(pspec)
+        ops = []
+        for i in range(n_ops):
+            name = chr(ord("a")+i)
+            operand = Signal(width, name=name)
+            setattr(self, name, operand)
+            ops.append(operand)
+        self.muxid = self.ctx.muxid # make muxid available here: complicated
+        self.ops = ops
+
+    def eq(self, i):
+        ret = []
+        for op1, op2 in zip(self.ops, i.ops):
+            ret.append(op1.eq(op2))
+        ret.append(self.ctx.eq(i.ctx))
+        return ret
+
+    def __iter__(self):
+        if self.ops:
+            yield from self.ops
+        yield from self.ctx
+
+    def ports(self):
+        return list(self)
+
+
diff --git a/src/ieee754/fpcommon/getop.py b/src/ieee754/fpcommon/getop.py
index bc60a55a..117d2922 100644
--- a/src/ieee754/fpcommon/getop.py
+++ b/src/ieee754/fpcommon/getop.py
@@ -77,36 +77,6 @@ class FPPipeContext:
         return list(self)
 
 
-class FPADDBaseData:
-
-    def __init__(self, pspec, n_ops=2):
-        width = pspec.width
-        self.ctx = FPPipeContext(pspec)
-        ops = []
-        for i in range(n_ops):
-            name = chr(ord("a")+i)
-            operand = Signal(width, name=name)
-            setattr(self, name, operand)
-            ops.append(operand)
-        self.muxid = self.ctx.muxid # make muxid available here: complicated
-        self.ops = ops
-
-    def eq(self, i):
-        ret = []
-        for op1, op2 in zip(self.ops, i.ops):
-            ret.append(op1.eq(op2))
-        ret.append(self.ctx.eq(i.ctx))
-        return ret
-
-    def __iter__(self):
-        if self.ops:
-            yield from self.ops
-        yield from self.ctx
-
-    def ports(self):
-        return list(self)
-
-
 class FPGet2OpMod(PrevControl):
     def __init__(self, width, id_wid, op_wid=None):
         PrevControl.__init__(self)
@@ -117,10 +87,10 @@ class FPGet2OpMod(PrevControl):
         self.o = self.ospec()
 
     def ispec(self):
-        return FPADDBaseData(self.width, self.id_wid, self.op_wid)
+        return FPBaseData(self.width, self.id_wid, self.op_wid)
 
     def ospec(self):
-        return FPADDBaseData(self.width, self.id_wid, self.op_wid)
+        return FPBaseData(self.width, self.id_wid, self.op_wid)
 
     def process(self, i):
         return self.o
diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index b13fff34..3bbf3123 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -10,7 +10,7 @@ Relevant bugreports:
 
 Stack looks like this:
 
-scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
+scnorm   - FPDIVSpecialCasesDeNorm ispec FPBaseData
 ------                             ospec FPSCData
 
                 StageChain: FPDIVSpecialCasesMod,
@@ -66,7 +66,7 @@ even 8 is starting to get alarmingly high.
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.fpbase import FPFormat
 from ieee754.fpcommon.pack import FPPackData
@@ -149,7 +149,7 @@ def roundup(x, mod):
 class FPDIVMuxInOut(ReservationStations):
     """ Reservation-Station version of FPDIV pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
         * N-stage divider pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
@@ -190,7 +190,7 @@ class FPDIVMuxInOut(ReservationStations):
         ReservationStations.__init__(self, num_rows)
 
     def i_specfn(self):
-        return FPADDBaseData(self.pspec)
+        return FPBaseData(self.pspec)
 
     def o_specfn(self):
         return FPPackData(self.pspec)
diff --git a/src/ieee754/fpdiv/specialcases.py b/src/ieee754/fpdiv/specialcases.py
index 20f67028..701bb998 100644
--- a/src/ieee754/fpdiv/specialcases.py
+++ b/src/ieee754/fpdiv/specialcases.py
@@ -15,7 +15,7 @@ from math import log
 
 from nmutil.pipemodbase import PipeModBase, PipeModBaseChain
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNormMod)
 from ieee754.fpmul.align import FPAlignModSingle
 from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation as DP
@@ -31,7 +31,7 @@ class FPDIVSpecialCasesMod(PipeModBase):
         super().__init__(pspec, "specialcases")
 
     def ispec(self):
-        return FPADDBaseData(self.pspec)
+        return FPBaseData(self.pspec)
 
     def ospec(self):
         return FPSCData(self.pspec, False)
diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py
index c20fa625..dae5fbb4 100644
--- a/src/ieee754/fpmul/pipeline.py
+++ b/src/ieee754/fpmul/pipeline.py
@@ -8,7 +8,7 @@ Stack looks like this:
 * mulstages - FPMulstages
 * normpack  - FPNormToPack
 
-scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
+scnorm   - FPDIVSpecialCasesDeNorm ispec FPBaseData
 ------                             ospec FPSCData
 
                 StageChain: FPMULSpecialCasesMod,
@@ -43,7 +43,7 @@ from nmigen.cli import main, verilog
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
@@ -73,7 +73,7 @@ class FPMULBasePipe(ControlBase):
 class FPMULMuxInOut(ReservationStations):
     """ Reservation-Station version of FPMUL pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
         * 2-stage multiplier pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
@@ -88,7 +88,7 @@ class FPMULMuxInOut(ReservationStations):
         ReservationStations.__init__(self, num_rows)
 
     def i_specfn(self):
-        return FPADDBaseData(self.pspec)
+        return FPBaseData(self.pspec)
 
     def o_specfn(self):
         return FPPackData(self.pspec)
diff --git a/src/ieee754/fpmul/specialcases.py b/src/ieee754/fpmul/specialcases.py
index fa834400..efab2e32 100644
--- a/src/ieee754/fpmul/specialcases.py
+++ b/src/ieee754/fpmul/specialcases.py
@@ -7,7 +7,7 @@ from math import log
 from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 
 from nmutil.pipemodbase import PipeModBase, PipeModBaseChain
-from ieee754.fpcommon.getop import FPADDBaseData
+from ieee754.fpcommon.basedata import FPBaseData
 from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNormMod)
 from ieee754.fpmul.align import FPAlignModSingle
 
@@ -22,7 +22,7 @@ class FPMulSpecialCasesMod(PipeModBase):
         super().__init__(pspec, "specialcases")
 
     def ispec(self):
-        return FPADDBaseData(self.pspec)
+        return FPBaseData(self.pspec)
 
     def ospec(self):
         return FPSCData(self.pspec, False)