From: lkcl <lkcl@web>
Date: Sat, 10 Sep 2022 01:05:37 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~539
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e85647cb6f148b3bf23bb23ba30b7fab83dd8118;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index bb13521aa..cb2279c4b 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -309,9 +309,8 @@ Scheme.
   (caveat: see bits 8-31)
 * **old-suffix** - the EXT000 to EXT063 32-bit Major opcodes of Power ISA 3.0
 * **new-suffix** - two **new** Major Opcode areas **exclusively**
-  for Scalar-only instructions that shall **never** be Prefixed by SVP64:
-  RESERVED1 EXT200-EXT263 and
-  RESERVED2 EXT300-EXT363
+  for Scalar-only instructions that shall **never** be Prefixed by SVP64
+  (RESERVED2 EXT300-EXT363) and one that may (RESERVED1 EXT200-EXT263)
 * **0000** - all 24 bits bits 8-31 are zero (0x000000)
 * **!zero** - bits 8-31 may be any value *other* than zero (0x000001-0xffffff)
 * **nnnn** - bits 8-31 may be any value in the range 0x000000 to 0xffffff