From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Thu, 9 Jun 2016 22:52:52 +0000 (-0700)
Subject: i965: Remove fake W-tiled render target support
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8580b8f981a48dd481c62292c7d618a4860dfad;p=mesa.git

i965: Remove fake W-tiled render target support

This hasn't been used since 1cfb4bc890b8 where we deleted the meta stencil
blit path.

Reviewed-by: Chad Versace <chad.versace@intel.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index be7f6ce28b1..b29412e37f7 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -264,12 +264,6 @@ void gen4_init_vtable_surface_functions(struct brw_context *brw);
 uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
 uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
 
-void brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
-                           bool is_render_target,
-                           unsigned *width, unsigned *height,
-                           unsigned *pitch, uint32_t *tiling,
-                           unsigned *format);
-
 uint32_t brw_format_for_mesa_format(mesa_format mesa_format);
 
 GLuint translate_tex_target(GLenum target);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 83c4c810af2..7b2953c0323 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -105,31 +105,6 @@ brw_get_surface_num_multisamples(unsigned num_samples)
       return BRW_SURFACE_MULTISAMPLECOUNT_1;
 }
 
-void
-brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
-                      bool is_render_target,
-                      unsigned *width, unsigned *height,
-                      unsigned *pitch, uint32_t *tiling, unsigned *format)
-{
-   static const unsigned halign_stencil = 8;
-
-   /* In Y-tiling row is twice as wide as in W-tiling, and subsequently
-    * there are half as many rows.
-    * In addition, mip-levels are accessed manually by the program and
-    * therefore the surface is setup to cover all the mip-levels for one slice.
-    * (Hardware is still used to access individual slices).
-    */
-   *tiling = I915_TILING_Y;
-   *pitch = mt->pitch * 2;
-   *width = ALIGN(mt->total_width, halign_stencil) * 2;
-   *height = (mt->total_height / mt->physical_depth0) / 2;
-
-   if (is_render_target) {
-      *format = BRW_SURFACEFORMAT_R8_UINT;
-   }
-}
-
-
 /**
  * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
  * swizzling.
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 6a98d76a08f..abd60168458 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -490,22 +490,15 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
    }
 
    /* _NEW_BUFFERS */
-   /* Render targets can't use IMS layout. Stencil in turn gets configured as
-    * single sampled and indexed manually by the program.
-    */
-   if (mt->format == MESA_FORMAT_S_UINT8) {
-      brw_configure_w_tiled(mt, true, &width, &height, &pitch,
-                            &tiling, &format);
-   } else {
-      assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
-      assert(brw_render_target_supported(brw, rb));
-      mesa_format rb_format = _mesa_get_render_format(ctx,
-                                                      intel_rb_format(irb));
-      format = brw->render_target_format[rb_format];
-      if (unlikely(!brw->format_supported_as_render_target[rb_format]))
-         _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
-                       __func__, _mesa_get_format_name(rb_format));
-   }
+   /* Render targets can't use IMS layout. */
+   assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
+   assert(brw_render_target_supported(brw, rb));
+   mesa_format rb_format = _mesa_get_render_format(ctx,
+                                                   intel_rb_format(irb));
+   format = brw->render_target_format[rb_format];
+   if (unlikely(!brw->format_supported_as_render_target[rb_format]))
+      _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
+                    __func__, _mesa_get_format_name(rb_format));
 
    struct intel_mipmap_tree *aux_mt = mt->mcs_mt;
    const uint32_t aux_mode = gen8_get_aux_mode(brw, mt);