From: Tom Stellard <thomas.stellard@amd.com>
Date: Thu, 13 Sep 2012 15:19:48 +0000 (+0000)
Subject: radeon/llvm: Add support for i8 reads on R600
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e866dbd1b538ce086ef0a8b7e5ae7ae8e81a72e7;p=mesa.git

radeon/llvm: Add support for i8 reads on R600
---

diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td
index 01948731fbb..9dbdc615e2d 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstructions.td
+++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td
@@ -74,6 +74,14 @@ def COND_LE : PatLeaf <
                      case ISD::SETLE: return true;}}}]
 >;
 
+//===----------------------------------------------------------------------===//
+// Load/Store Pattern Fragments
+//===----------------------------------------------------------------------===//
+
+def zextloadi8_global : PatFrag<(ops node:$ptr), (zextloadi8 node:$ptr), [{
+    return isGlobalLoad(dyn_cast<LoadSDNode>(N));
+}]>;
+
 class Constants {
 int TWO_PI = 0x40c90fdb;
 int PI = 0x40490fdb;
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
index dcf833876ce..65fd22f8cf5 100644
--- a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -167,6 +167,7 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
       }
     case AMDGPU::VTX_READ_PARAM_i32_eg:
     case AMDGPU::VTX_READ_PARAM_f32_eg:
+    case AMDGPU::VTX_READ_GLOBAL_i8_eg:
     case AMDGPU::VTX_READ_GLOBAL_i32_eg:
     case AMDGPU::VTX_READ_GLOBAL_f32_eg:
     case AMDGPU::VTX_READ_GLOBAL_v4i32_eg:
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index c9c9f611ed6..0f4bbb3a04b 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -1059,6 +1059,17 @@ class VTX_READ_eg <bits<8> buffer_id, dag outs, list<dag> pattern>
   // Inst{127-96} = 0;
 }
 
+class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern>
+    : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
+
+  let MEGA_FETCH_COUNT = 1;
+  let DST_SEL_X = 0;
+  let DST_SEL_Y = 7;   // Masked
+  let DST_SEL_Z = 7;   // Masked
+  let DST_SEL_W = 7;   // Masked
+  let DATA_FORMAT = 1; // FMT_8
+}
+
 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern>
     : VTX_READ_eg <buffer_id, (outs R600_TReg32_X:$dst), pattern> {
 
@@ -1111,6 +1122,11 @@ def VTX_READ_PARAM_f32_eg : VTX_READ_PARAM_32_eg<f32>;
 // VTX Read from global memory space
 //===----------------------------------------------------------------------===//
 
+// 8-bit reads
+def VTX_READ_GLOBAL_i8_eg : VTX_READ_8_eg <1,
+  [(set (i32 R600_TReg32_X:$dst), (zextloadi8_global ADDRVTX_READ:$ptr))]
+>;
+
 // 32-bit reads
 
 class VTX_READ_GLOBAL_eg <ValueType vt> : VTX_READ_32_eg <1,