From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Sat, 18 Jul 2020 13:25:26 +0000 (+0100)
Subject: dev-arm: Check for security attribute when writing to ICFGR registers
X-Git-Tag: v20.1.0.0~412
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e877f715cad29745cf0257c3f73315c2f1a1402d;p=gem5.git

dev-arm: Check for security attribute when writing to ICFGR registers

This is matching the GICD_ICFGR read; a non secure access to a secure
interrupt should be treated as RAZ/WI

Change-Id: I9e92e03c13fe0474ed139b0ed22cebd5847b9109
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31615
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc
index 485ba7284..f8605da27 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -743,6 +743,11 @@ Gicv3Distributor::write(Addr addr, uint64_t data, size_t size,
 
         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
              i = i + 2, int_id++) {
+
+            if (nsAccessToSecInt(int_id, is_secure_access)) {
+                continue;
+            }
+
             irqConfig[int_id] = data & (0x2 << i) ?
                                 Gicv3::INT_EDGE_TRIGGERED :
                                 Gicv3::INT_LEVEL_SENSITIVE;