From: lkcl Date: Thu, 17 Dec 2020 14:19:07 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1233 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e87c1a411cec3aecbb83e29a70a2122d34de3015;p=libreriscv.git --- diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 72bd69908..203b41465 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -20,6 +20,27 @@ and for immediate variants: Thus in the first example, the source registers may each be independently marked as scalar or vector, and likewise the destination; in the second example only the one source and one dest may be marked as scalar or vector. -Thus we can see that Vector Indexed may be covered, but there is not a convenient way to provide both fixed and element strided. This is a known limitation of retro-fitting an existing scalar ISA with Vectorisation. +Thus we can see that Vector Indexed may be covered, but there is not a convenient way to provide both fixed and element strided. This is a known limitation of retro-fitting an existing scalar ISA with Vectorisation. The solution requires an operation that has both RA, RB and an immediate. + +At the minimum however it is possible to provide unit stride and vector mode, as follows: + + function op_ld(rd, rs, immed) # LD not VLD! +  rdv = map_dest_extra(rd); +  rsv = map_src_extra(rs); +  ps = get_pred_val(FALSE, rs); # predication on src +  pd = get_pred_val(FALSE, rd); # ... AND on dest +  for (int i = 0, int j = 0; i < VL && j < VL;): + if (rs.isvec) while (!(ps & 1<