From: Richard Sandiford Date: Thu, 30 Mar 2023 10:09:13 +0000 (+0100) Subject: aarch64: Add the SME2 ADD and SUB instructions X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e87ff6724fe32ecff11fc36a19a09ab8fbc66c13;p=binutils-gdb.git aarch64: Add the SME2 ADD and SUB instructions Add support for the SME2 ADD. SUB, FADD and FSUB instructions. SUB and FSUB have the same form as ADD and FADD, except that ADD also has a 2-operand accumulating form. The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the 64-bit FADD/FSUB instructions require FEAT_SME_F64F64. These are the first instructions to have tied register list operands, as opposed to tied single registers. The parse_operands change prevents unsuffixed Z registers (width==-1) from being treated as though they had an Advanced SIMD-style suffix (.4s etc.). It means that: Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}' becomes: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}' --- diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 652fd4e6ff3..5e023152c17 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6659,6 +6659,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zm_16: case AARCH64_OPND_SVE_Zn: case AARCH64_OPND_SVE_Zt: + case AARCH64_OPND_SME_Zm: reg_type = REG_TYPE_Z; goto vector_reg; @@ -6811,7 +6812,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto failure; } - if (vectype.width != 0 && *str != ',') + if ((int) vectype.width > 0 && *str != ',') { set_fatal_syntax_error (_("expected element type rather than vector type")); diff --git a/gas/testsuite/gas/aarch64/sme2-9-invalid.d b/gas/testsuite/gas/aarch64/sme2-9-invalid.d new file mode 100644 index 00000000000..78b3fa2875b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-9-invalid.s +#error_output: sme2-9-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-9-invalid.l b/gas/testsuite/gas/aarch64/sme2-9-invalid.l new file mode 100644 index 00000000000..e181f0b7378 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-invalid.l @@ -0,0 +1,179 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `add 0,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `add za\.s\[w8,0\],0' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z2\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z1\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z4\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z2\.s-z5\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z3\.s-z6\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `add 0,{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `add za\.s\[w8,0\],0,z0\.s' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},0' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w0,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `add za\.s\[w31,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,1<<63\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},z31\.s' +[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `add za\.s\[w8,0:0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `add za\.s\[w8,0:-1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `add za\.s\[w8,0:1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `add za\.s\[w8,0:100\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},z16\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},z16\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `add za\.s\[w8,0\],{z0\.s,z1\.s,z5\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1},z0\.s' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.s\[w8,0\],{z0\.s-z1\.s},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z2\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z15\.s-z16\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z31\.s,z0\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z4\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z2\.s-z5\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z3\.s-z6\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},{z15\.s-z18\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},{z29\.s,z30\.s,z31\.s,z0\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z2\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z4\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z1\.b},{z0\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z1\.b},{z0\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `add {z0\.b-z2\.b},{z0\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z1\.b},{z2\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z1\.b-z2\.b},{z1\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z31\.b,z0\.b},{z31\.b,z0\.b},z0\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z1\.b},{z0\.b-z1\.b},z16\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z1\.b},{z0\.b-z1\.b},z31\.b' +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z1\.b},{z0\.h-z1\.h},z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z1\.b},{z0\.b-z1\.b},z0\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.q-z1\.q},{z0\.q-z1\.q},z0\.q' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z3\.b},{z0\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z3\.b},{z0\.b-z1\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z3\.b},{z2\.b-z5\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z1\.b-z4\.b},{z1\.b-z4\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z2\.b-z5\.b},{z2\.b-z5\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z3\.b-z6\.b},{z3\.b-z6\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z31\.b,z0\.b,z1\.b,z2\.b},{z31\.b,z0\.b,z1\.b,z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z3\.b},{z0\.b-z3\.b},z16\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z3\.b},{z0\.b-z3\.b},z31\.b' +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z3\.b},{z0\.h-z3\.h},z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z3\.b},{z0\.b-z3\.b},z0\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.q-z3\.q},{z0\.q-z3\.q},z0\.q' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.b-z1\.b},{z0\.b-z1\.b},z0\.b' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.h-z1\.h},{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.s-z1\.s},{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.d-z1\.d},{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.b-z3\.b},{z0\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.h-z3\.h},{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.s-z3\.s},{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.d-z3\.d},{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.b\[w8,0\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.h\[w8,0\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-9-invalid.s b/gas/testsuite/gas/aarch64/sme2-9-invalid.s new file mode 100644 index 00000000000..d5bfc095e21 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-invalid.s @@ -0,0 +1,128 @@ + add 0, { z0.s - z1.s } + add za.s[w8, 0], 0 + + add za.s[w7, 0], { z0.s - z1.s } + add za.s[w12, 0], { z0.s - z1.s } + add za.s[w8, -1], { z0.s - z1.s } + add za.s[w8, 8], { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z2.s } + add za.s[w8, 0], { z1.s - z2.s } + + add za.s[w7, 0], { z0.s - z3.s } + add za.s[w12, 0], { z0.s - z3.s } + add za.s[w8, -1], { z0.s - z3.s } + add za.s[w8, 8], { z1.s - z3.s } + add za.s[w8, 0], { z1.s - z4.s } + add za.s[w8, 0], { z2.s - z5.s } + add za.s[w8, 0], { z3.s - z6.s } + + add za.s[w8, 0, vgx4], { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z3.s } + add za[w8, 0], { z0.s - z1.s } + add za.s[w8, 0], { z0 - z1 } + + add 0, { z0.s - z1.s }, z0.s + add za.s[w8, 0], 0, z0.s + add za.s[w8, 0], { z0.s - z1.s }, 0 + + add za.s[w0, 0], { z0.s - z1.s }, z0.s + add za.s[w31, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 1<<63], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z31.s + add za.s[w8, 0:0], { z0.s - z1.s }, z0.s + add za.s[w8, 0:-1], { z0.s - z1.s }, z0.s + add za.s[w8, 0:1], { z0.s - z1.s }, z0.s + add za.s[w8, 0:100], { z0.s - z1.s }, z0.s + + add za.s[w7, 0], { z0.s - z1.s }, z0.s + add za.s[w12, 0], { z0.s - z1.s }, z0.s + add za.s[w8, -1], { z0.s - z1.s }, z0.s + add za.s[w8, 8], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z16.s + + add za.s[w7, 0], { z0.s - z3.s }, z0.s + add za.s[w12, 0], { z0.s - z3.s }, z0.s + add za.s[w8, -1], { z0.s - z3.s }, z0.s + add za.s[w8, 8], { z0.s - z3.s }, z0.s + add za.s[w8, 0], { z0.s - z3.s }, z16.s + + add za.s[w8, 0], { z0.s - z2.s }, z0.s + add za.s[w8, 0], { z0.s - z4.s }, z0.s + add za.s[w8, 0], { z0.s, z1.s, z2.s }, z0.s + add za.s[w8, 0], { z0.s, z1.s, z5.s }, z0.s + + add za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s + add za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s + add za[w8, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z0 - z1 }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z0 + add za[w8, 0], { z0.s - z1.s }, z0 + + add za.s[w7, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w12, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, -1], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 8], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 0], { z1.s - z2.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z1.s }, { z15.s - z16.s } + add za.s[w8, 0], { z0.s - z1.s }, { z31.s, z0.s } + + add za.s[w7, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w12, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, -1], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 8], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 0], { z1.s - z4.s }, { z0.s - z3.s } + add za.s[w8, 0], { z2.s - z5.s }, { z0.s - z3.s } + add za.s[w8, 0], { z3.s - z6.s }, { z0.s - z3.s } + add za.s[w8, 0], { z0.s - z3.s }, { z15.s - z18.s } + add za.s[w8, 0], { z0.s - z3.s }, { z29.s, z30.s, z31.s, z0.s } + + add za.s[w8, 0], { z0.s - z2.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z3.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z2.s } + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z3.s } + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z4.s } + + add za.s[w8, 0, vgx4], { z0.s - z1.s }, { z0.s - z3.s } + add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z3.s } + add za.s[w8, 0, vgx2], { z0.s - z3.s }, { z0.s - z1.s } + add za[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } + + add { z0.b - z1.b }, { z0.b - z2.b }, z0.b + add { z0.b - z1.b }, { z0.b - z3.b }, z0.b + add { z0.b - z2.b }, { z0.b - z2.b }, z0.b + add { z0.b - z1.b }, { z2.b - z3.b }, z0.b + add { z1.b - z2.b }, { z1.b - z2.b }, z0.b + add { z31.b, z0.b }, { z31.b, z0.b }, z0.b + add { z0.b - z1.b }, { z0.b - z1.b }, z16.b + add { z0.b - z1.b }, { z0.b - z1.b }, z31.b + add { z0.b - z1.b }, { z0.h - z1.h }, z0.b + add { z0.b - z1.b }, { z0.b - z1.b }, z0.h + add { z0.q - z1.q }, { z0.q - z1.q }, z0.q + + add { z0.b - z3.b }, { z0.b - z2.b }, z0.b + add { z0.b - z3.b }, { z0.b - z1.b }, z0.b + add { z0.b - z3.b }, { z2.b - z5.b }, z0.b + add { z1.b - z4.b }, { z1.b - z4.b }, z0.b + add { z2.b - z5.b }, { z2.b - z5.b }, z0.b + add { z3.b - z6.b }, { z3.b - z6.b }, z0.b + add { z31.b, z0.b, z1.b, z2.b }, { z31.b, z0.b, z1.b, z2.b }, z0.b + add { z0.b - z3.b }, { z0.b - z3.b }, z16.b + add { z0.b - z3.b }, { z0.b - z3.b }, z31.b + add { z0.b - z3.b }, { z0.h - z3.h }, z0.b + add { z0.b - z3.b }, { z0.b - z3.b }, z0.h + add { z0.q - z3.q }, { z0.q - z3.q }, z0.q + + sub { z0.b - z1.b }, { z0.b - z1.b }, z0.b + sub { z0.h - z1.h }, { z0.h - z1.h }, z0.h + sub { z0.s - z1.s }, { z0.s - z1.s }, z0.s + sub { z0.d - z1.d }, { z0.d - z1.d }, z0.d + + sub { z0.b - z3.b }, { z0.b - z3.b }, z0.b + sub { z0.h - z3.h }, { z0.h - z3.h }, z0.h + sub { z0.s - z3.s }, { z0.s - z3.s }, z0.s + sub { z0.d - z3.d }, { z0.d - z3.d }, z0.d + + fadd za.b[w8, 0], { z0.b - z1.b } + fadd za.h[w8, 0], { z0.h - z1.h } diff --git a/gas/testsuite/gas/aarch64/sme2-9-noarch.d b/gas/testsuite/gas/aarch64/sme2-9-noarch.d new file mode 100644 index 00000000000..076b3dabf58 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-9.s +#error_output: sme2-9-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-9-noarch.l b/gas/testsuite/gas/aarch64/sme2-9-noarch.l new file mode 100644 index 00000000000..1a2ad07a209 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-noarch.l @@ -0,0 +1,177 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w10,3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,1\],{z12\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z1\.b},{z0\.b-z1\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.b-z31\.b},{z30\.b-z31\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z1\.b},{z0\.b-z1\.b},z15\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z14\.b-z15\.b},{z14\.b-z15\.b},z5\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z1\.h},{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.h-z31\.h},{z30\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z1\.h},{z0\.h-z1\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z20\.h-z21\.h},{z20\.h-z21\.h},z11\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z1\.s},{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.s-z31\.s},{z30\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z1\.s},{z0\.s-z1\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z2\.s-z3\.s},{z2\.s-z3\.s},z9\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z1\.d},{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.d-z31\.d},{z30\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z1\.d},{z0\.d-z1\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.d-z29\.d},{z28\.d-z29\.d},z1\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z3\.b},{z0\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.b-z31\.b},{z28\.b-z31\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z3\.b},{z0\.b-z3\.b},z15\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z24\.b-z27\.b},{z24\.b-z27\.b},z5\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z3\.h},{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.h-z31\.h},{z28\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z3\.h},{z0\.h-z3\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z20\.h-z23\.h},{z20\.h-z23\.h},z11\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z3\.s},{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.s-z31\.s},{z28\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z3\.s},{z0\.s-z3\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z4\.s-z7\.s},{z4\.s-z7\.s},z9\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z3\.d},{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.d-z31\.d},{z28\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z3\.d},{z0\.d-z3\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z16\.d-z19\.d},{z16\.d-z19\.d},z3\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w10,3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,1\],{z12\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,7\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w10,3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,7\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11,1\],{z12\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,7\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w10,3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,7\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11,1\],{z12\.s-z15\.s}' diff --git a/gas/testsuite/gas/aarch64/sme2-9.d b/gas/testsuite/gas/aarch64/sme2-9.d new file mode 100644 index 00000000000..ece09550d66 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9.d @@ -0,0 +1,185 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c10 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c17 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d53 add za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c10 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c17 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d91 add za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1207810 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201817 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201bd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s +[^:]+: c1201bf0 add za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c1201bf0 add za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c12f1810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s +[^:]+: c1263935 add za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1307810 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301817 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301b90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s +[^:]+: c1301bf0 add za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c1301bf0 add za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c13f1810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s +[^:]+: c13d7af2 add za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a07810 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01817 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01bd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s} +[^:]+: c1be1810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s} +[^:]+: c1b25ad1 add za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a17810 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11817 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11b90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s} +[^:]+: c1bd1810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s} +[^:]+: c1b97a13 add za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s} +[^:]+: c120a300 add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^:]+: c120a31e add {z30\.b-z31\.b}, {z30\.b-z31\.b}, z0\.b +[^:]+: c12fa300 add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z15\.b +[^:]+: c125a30e add {z14\.b-z15\.b}, {z14\.b-z15\.b}, z5\.b +[^:]+: c160a300 add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^:]+: c160a31e add {z30\.h-z31\.h}, {z30\.h-z31\.h}, z0\.h +[^:]+: c16fa300 add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z15\.h +[^:]+: c16ba314 add {z20\.h-z21\.h}, {z20\.h-z21\.h}, z11\.h +[^:]+: c1a0a300 add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^:]+: c1a0a31e add {z30\.s-z31\.s}, {z30\.s-z31\.s}, z0\.s +[^:]+: c1afa300 add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z15\.s +[^:]+: c1a9a302 add {z2\.s-z3\.s}, {z2\.s-z3\.s}, z9\.s +[^:]+: c1e0a300 add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^:]+: c1e0a31e add {z30\.d-z31\.d}, {z30\.d-z31\.d}, z0\.d +[^:]+: c1efa300 add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z15\.d +[^:]+: c1e1a31c add {z28\.d-z29\.d}, {z28\.d-z29\.d}, z1\.d +[^:]+: c120ab00 add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^:]+: c120ab1c add {z28\.b-z31\.b}, {z28\.b-z31\.b}, z0\.b +[^:]+: c12fab00 add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z15\.b +[^:]+: c125ab18 add {z24\.b-z27\.b}, {z24\.b-z27\.b}, z5\.b +[^:]+: c160ab00 add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^:]+: c160ab1c add {z28\.h-z31\.h}, {z28\.h-z31\.h}, z0\.h +[^:]+: c16fab00 add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z15\.h +[^:]+: c16bab14 add {z20\.h-z23\.h}, {z20\.h-z23\.h}, z11\.h +[^:]+: c1a0ab00 add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^:]+: c1a0ab1c add {z28\.s-z31\.s}, {z28\.s-z31\.s}, z0\.s +[^:]+: c1afab00 add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z15\.s +[^:]+: c1a9ab04 add {z4\.s-z7\.s}, {z4\.s-z7\.s}, z9\.s +[^:]+: c1e0ab00 add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^:]+: c1e0ab1c add {z28\.d-z31\.d}, {z28\.d-z31\.d}, z0\.d +[^:]+: c1efab00 add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z15\.d +[^:]+: c1e3ab10 add {z16\.d-z19\.d}, {z16\.d-z19\.d}, z3\.d +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c18 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c1f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d5b sub za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c18 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c1f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d99 sub za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1207818 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c120181f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201bd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s +[^:]+: c1201bf8 sub za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c1201bf8 sub za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c12f1818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s +[^:]+: c126393d sub za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1307818 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c130181f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301b98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s +[^:]+: c1301bf8 sub za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c1301bf8 sub za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c13f1818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s +[^:]+: c13d7afa sub za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a07818 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a0181f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01bd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s} +[^:]+: c1be1818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s} +[^:]+: c1b25ad9 sub za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a17818 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a1181f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11b98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s} +[^:]+: c1bd1818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s} +[^:]+: c1b97a1b sub za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c00 fadd za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c07 fadd za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fc0 fadd za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d43 fadd za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c00 fadd za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c07 fadd za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f80 fadd za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d81 fadd za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c08 fsub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c0f fsub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fc8 fsub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d4b fsub za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c08 fsub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c0f fsub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f88 fsub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d89 fsub za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} diff --git a/gas/testsuite/gas/aarch64/sme2-9.s b/gas/testsuite/gas/aarch64/sme2-9.s new file mode 100644 index 00000000000..838e75b684e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9.s @@ -0,0 +1,199 @@ + add za.s[w8, 0], { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z1.s } + ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + add za.s[w11, 0], { z0.s - z1.s } + add za.s[w8, 7], { z0.s - z1.s } + add za.s[w8, 0], { z30.s - z31.s } + add za.s[w10, 3], { z10.s - z11.s } + + add za.s[w8, 0], { z0.s - z3.s } + add za.s[w8, 0, vgx4], { z0.s - z3.s } + ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + add za.s[w11, 0], { z0.s - z3.s } + add za.s[w8, 7], { z0.s - z3.s } + add za.s[w8, 0], { z28.s - z31.s } + add za.s[w11, 1], { z12.s - z15.s } + + add za.s[w8, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s + ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s + ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S + add za.s[w11, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 7], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z30.s - z31.s }, z0.s + add za.s[w8, 0], { z31.s, z0.s }, z0.s + add za.s[w8, 0], { z31.s - z0.s }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z15.s + add za.s[w9, 5], { z9.s - z10.s }, z6.s + + add za.s[w8, 0], { z0.s - z3.s }, z0.s + add za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s + ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s + ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S + add za.s[w11, 0], { z0.s - z3.s }, z0.s + add za.s[w8, 7], { z0.s - z3.s }, z0.s + add za.s[w8, 0], { z28.s - z31.s }, z0.s + add za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s + add za.s[w8, 0], { z31.s - z2.s }, z0.s + add za.s[w8, 0], { z0.s - z3.s }, z15.s + add za.s[w11, 2], { z23.s - z26.s }, z13.s + + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s } + ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s } + ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S } + add za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s } + add za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s } + + add za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s } + ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s } + ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S } + add za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s } + add za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s } + add za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s } + + add { z0.b - z1.b }, { z0.b - z1.b }, z0.b + add { z30.b - z31.b }, { z30.b - z31.b }, z0.b + add { z0.b - z1.b }, { z0.b - z1.b }, z15.b + add { z14.b - z15.b }, { z14.b - z15.b }, z5.b + + add { z0.h - z1.h }, { z0.h - z1.h }, z0.h + add { z30.h - z31.h }, { z30.h - z31.h }, z0.h + add { z0.h - z1.h }, { z0.h - z1.h }, z15.h + add { z20.h - z21.h }, { z20.h - z21.h }, z11.h + + add { z0.s - z1.s }, { z0.s - z1.s }, z0.s + add { z30.s - z31.s }, { z30.s - z31.s }, z0.s + add { z0.s - z1.s }, { z0.s - z1.s }, z15.s + add { z2.s - z3.s }, { z2.s - z3.s }, z9.s + + add { z0.d - z1.d }, { z0.d - z1.d }, z0.d + add { z30.d - z31.d }, { z30.d - z31.d }, z0.d + add { z0.d - z1.d }, { z0.d - z1.d }, z15.d + add { z28.d - z29.d }, { z28.d - z29.d }, z1.d + + add { z0.b - z3.b }, { z0.b - z3.b }, z0.b + add { z28.b - z31.b }, { z28.b - z31.b }, z0.b + add { z0.b - z3.b }, { z0.b - z3.b }, z15.b + add { z24.b - z27.b }, { z24.b - z27.b }, z5.b + + add { z0.h - z3.h }, { z0.h - z3.h }, z0.h + add { z28.h - z31.h }, { z28.h - z31.h }, z0.h + add { z0.h - z3.h }, { z0.h - z3.h }, z15.h + add { z20.h - z23.h }, { z20.h - z23.h }, z11.h + + add { z0.s - z3.s }, { z0.s - z3.s }, z0.s + add { z28.s - z31.s }, { z28.s - z31.s }, z0.s + add { z0.s - z3.s }, { z0.s - z3.s }, z15.s + add { z4.s - z7.s }, { z4.s - z7.s }, z9.s + + add { z0.d - z3.d }, { z0.d - z3.d }, z0.d + add { z28.d - z31.d }, { z28.d - z31.d }, z0.d + add { z0.d - z3.d }, { z0.d - z3.d }, z15.d + add { z16.d - z19.d }, { z16.d - z19.d }, z3.d + + sub za.s[w8, 0], { z0.s - z1.s } + sub za.s[w8, 0, vgx2], { z0.s - z1.s } + SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + sub za.s[w11, 0], { z0.s - z1.s } + sub za.s[w8, 7], { z0.s - z1.s } + sub za.s[w8, 0], { z30.s - z31.s } + sub za.s[w10, 3], { z10.s - z11.s } + + sub za.s[w8, 0], { z0.s - z3.s } + sub za.s[w8, 0, vgx4], { z0.s - z3.s } + SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + sub za.s[w11, 0], { z0.s - z3.s } + sub za.s[w8, 7], { z0.s - z3.s } + sub za.s[w8, 0], { z28.s - z31.s } + sub za.s[w11, 1], { z12.s - z15.s } + + sub za.s[w8, 0], { z0.s - z1.s }, z0.s + sub za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s + SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s + SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S + sub za.s[w11, 0], { z0.s - z1.s }, z0.s + sub za.s[w8, 7], { z0.s - z1.s }, z0.s + sub za.s[w8, 0], { z30.s - z31.s }, z0.s + sub za.s[w8, 0], { z31.s, z0.s }, z0.s + sub za.s[w8, 0], { z31.s - z0.s }, z0.s + sub za.s[w8, 0], { z0.s - z1.s }, z15.s + sub za.s[w9, 5], { z9.s - z10.s }, z6.s + + sub za.s[w8, 0], { z0.s - z3.s }, z0.s + sub za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s + SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s + SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S + sub za.s[w11, 0], { z0.s - z3.s }, z0.s + sub za.s[w8, 7], { z0.s - z3.s }, z0.s + sub za.s[w8, 0], { z28.s - z31.s }, z0.s + sub za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s + sub za.s[w8, 0], { z31.s - z2.s }, z0.s + sub za.s[w8, 0], { z0.s - z3.s }, z15.s + sub za.s[w11, 2], { z23.s - z26.s }, z13.s + + sub za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + sub za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s } + SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s } + SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S } + sub za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s } + sub za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s } + sub za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s } + sub za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s } + sub za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s } + + sub za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } + sub za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s } + SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s } + SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S } + sub za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s } + sub za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s } + sub za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s } + sub za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s } + sub za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s } + + fadd za.s[w8, 0], { z0.s - z1.s } + fadd za.s[w8, 0, vgx2], { z0.s - z1.s } + FADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + FADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + fadd za.s[w11, 0], { z0.s - z1.s } + fadd za.s[w8, 7], { z0.s - z1.s } + fadd za.s[w8, 0], { z30.s - z31.s } + fadd za.s[w10, 3], { z10.s - z11.s } + + fadd za.s[w8, 0], { z0.s - z3.s } + fadd za.s[w8, 0, vgx4], { z0.s - z3.s } + FADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + FADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + fadd za.s[w11, 0], { z0.s - z3.s } + fadd za.s[w8, 7], { z0.s - z3.s } + fadd za.s[w8, 0], { z28.s - z31.s } + fadd za.s[w11, 1], { z12.s - z15.s } + + fsub za.s[w8, 0], { z0.s - z1.s } + fsub za.s[w8, 0, vgx2], { z0.s - z1.s } + FSUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + FSUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + fsub za.s[w11, 0], { z0.s - z1.s } + fsub za.s[w8, 7], { z0.s - z1.s } + fsub za.s[w8, 0], { z30.s - z31.s } + fsub za.s[w10, 3], { z10.s - z11.s } + + fsub za.s[w8, 0], { z0.s - z3.s } + fsub za.s[w8, 0, vgx4], { z0.s - z3.s } + FSUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + FSUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + fsub za.s[w11, 0], { z0.s - z3.s } + fsub za.s[w8, 7], { z0.s - z3.s } + fsub za.s[w8, 0], { z28.s - z31.s } + fsub za.s[w11, 1], { z12.s - z15.s } diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.d b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.d new file mode 100644 index 00000000000..f3a623dd9e8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-f64f64-1-invalid.s +#error_output: sme2-f64f64-1-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.l b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.l new file mode 100644 index 00000000000..60ee8bd0f8e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.l @@ -0,0 +1,27 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w7,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w12,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,-1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,8\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fadd za\.d\[w8,0\],{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z1\.d-z2\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w7,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w12,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,-1\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,8\],{z1\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z1\.d-z4\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z3\.d-z6\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fadd za\.d\[w8,0,vgx4\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fadd za\.d\[w8,0,vgx2\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fadd za\.d\[w8,0\],{z0-z1}' +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.d\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.s b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.s new file mode 100644 index 00000000000..e045dcd984a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.s @@ -0,0 +1,20 @@ + fadd za.d[w7, 0], { z0.d - z1.d } + fadd za.d[w12, 0], { z0.d - z1.d } + fadd za.d[w8, -1], { z0.d - z1.d } + fadd za.d[w8, 8], { z0.d - z1.d } + fadd za.d[w8, 0], { z0.d - z2.d } + fadd za.d[w8, 0], { z1.d - z2.d } + + fadd za.d[w7, 0], { z0.d - z3.d } + fadd za.d[w12, 0], { z0.d - z3.d } + fadd za.d[w8, -1], { z0.d - z3.d } + fadd za.d[w8, 8], { z1.d - z3.d } + fadd za.d[w8, 0], { z1.d - z4.d } + fadd za.d[w8, 0], { z2.d - z5.d } + fadd za.d[w8, 0], { z3.d - z6.d } + + fadd za.d[w8, 0, vgx4], { z0.d - z1.d } + fadd za.d[w8, 0, vgx2], { z0.d - z3.d } + fadd za[w8, 0], { z0.d - z1.d } + fadd za.d[w8, 0], { z0 - z1 } + fadd za.d[w8, 0], { z0.s - z1.s } diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.d b/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.d new file mode 100644 index 00000000000..fe14d018a2f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme2 +#source: sme2-f64f64-1.s +#error_output: sme2-f64f64-1-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.l b/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.l new file mode 100644 index 00000000000..f3750f5b171 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.l @@ -0,0 +1,33 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0,vgx2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,7\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w10,3\],{z10\.d-z11\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0,vgx4\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,7\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11,1\],{z12\.d-z15\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0,vgx2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,7\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w10,3\],{z10\.d-z11\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0,vgx4\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,7\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11,1\],{z12\.d-z15\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1.d b/gas/testsuite/gas/aarch64/sme2-f64f64-1.d new file mode 100644 index 00000000000..3f3d167a4e8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1.d @@ -0,0 +1,41 @@ +#as: -march=armv8-a+sme2+sme-f64f64 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e07c00 fadd za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c07 fadd za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01fc0 fadd za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d} +[^:]+: c1e05d43 fadd za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e17c00 fadd za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c07 fadd za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11f80 fadd za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d} +[^:]+: c1e17d81 fadd za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e07c08 fsub za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c0f fsub za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01fc8 fsub za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d} +[^:]+: c1e05d4b fsub za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e17c08 fsub za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c0f fsub za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11f88 fsub za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d} +[^:]+: c1e17d89 fsub za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1.s b/gas/testsuite/gas/aarch64/sme2-f64f64-1.s new file mode 100644 index 00000000000..546f20dd44d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1.s @@ -0,0 +1,35 @@ + fadd za.d[w8, 0], { z0.d - z1.d } + fadd za.d[w8, 0, vgx2], { z0.d - z1.d } + FADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d } + FADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D } + fadd za.d[w11, 0], { z0.d - z1.d } + fadd za.d[w8, 7], { z0.d - z1.d } + fadd za.d[w8, 0], { z30.d - z31.d } + fadd za.d[w10, 3], { z10.d - z11.d } + + fadd za.d[w8, 0], { z0.d - z3.d } + fadd za.d[w8, 0, vgx4], { z0.d - z3.d } + FADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d } + FADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D } + fadd za.d[w11, 0], { z0.d - z3.d } + fadd za.d[w8, 7], { z0.d - z3.d } + fadd za.d[w8, 0], { z28.d - z31.d } + fadd za.d[w11, 1], { z12.d - z15.d } + + fsub za.d[w8, 0], { z0.d - z1.d } + fsub za.d[w8, 0, vgx2], { z0.d - z1.d } + FSUB ZA.d[W8, 0, VGx2], { Z0.d - Z1.d } + FSUB ZA.D[W8, 0, VGX2], { Z0.D - Z1.D } + fsub za.d[w11, 0], { z0.d - z1.d } + fsub za.d[w8, 7], { z0.d - z1.d } + fsub za.d[w8, 0], { z30.d - z31.d } + fsub za.d[w10, 3], { z10.d - z11.d } + + fsub za.d[w8, 0], { z0.d - z3.d } + fsub za.d[w8, 0, vgx4], { z0.d - z3.d } + FSUB ZA.d[W8, 0, VGx4], { Z0.d - Z3.d } + FSUB ZA.D[W8, 0, VGX4], { Z0.D - Z3.D } + fsub za.d[w11, 0], { z0.d - z3.d } + fsub za.d[w8, 7], { z0.d - z3.d } + fsub za.d[w8, 0], { z28.d - z31.d } + fsub za.d[w11, 1], { z12.d - z15.d } diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.d b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.d new file mode 100644 index 00000000000..01172951481 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-i16i64-1-invalid.s +#error_output: sme2-i16i64-1-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.l b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.l new file mode 100644 index 00000000000..d9d537a63d4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.l @@ -0,0 +1,111 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z1\.d-z2\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z1\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z1\.d-z4\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z3\.d-z6\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.d\[w8,0\],{z0-z1}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w0,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `add za\.d\[w31,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,1<<63\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},z31\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},z16\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},z16\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d,z1\.d,z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `add za\.d\[w8,0\],{z0\.d,z1\.d,z5\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.d\[w8,0\],{z0-z1},z0\.d' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.d-z1\.d},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.s\[w8,0\],{z0\.d-z1\.d},z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.s-z1\.s},z0\.d' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w0,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `add za\.d\[w31,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,1<<63\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z1\.d-z2\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z15\.d-z16\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z31\.d,z0\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z1\.d-z4\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z2\.d-z5\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z3\.d-z6\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},{z15\.d-z18\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},{z29\.d,z30\.d,z31\.d,z0\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z2\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z4\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s} diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.s b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.s new file mode 100644 index 00000000000..ef2e48d2477 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.s @@ -0,0 +1,86 @@ + add za.d[w7, 0], { z0.d - z1.d } + add za.d[w12, 0], { z0.d - z1.d } + add za.d[w8, -1], { z0.d - z1.d } + add za.d[w8, 8], { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z2.d } + add za.d[w8, 0], { z1.d - z2.d } + + add za.d[w7, 0], { z0.d - z3.d } + add za.d[w12, 0], { z0.d - z3.d } + add za.d[w8, -1], { z0.d - z3.d } + add za.d[w8, 8], { z1.d - z3.d } + add za.d[w8, 0], { z1.d - z4.d } + add za.d[w8, 0], { z2.d - z5.d } + add za.d[w8, 0], { z3.d - z6.d } + + add za.d[w8, 0, vgx4], { z0.d - z1.d } + add za.d[w8, 0, vgx2], { z0.d - z3.d } + add za[w8, 0], { z0.d - z1.d } + add za.d[w8, 0], { z0 - z1 } + add za.d[w8, 0], { z0.s - z1.s } + + add za.d[w0, 0], { z0.d - z1.d }, z0.d + add za.d[w31, 0], { z0.d - z1.d }, z0.d + add za.d[w8, 1<<63], { z0.d - z1.d }, z0.d + add za.d[w8, 0], { z0.d - z1.d }, z31.d + + add za.d[w7, 0], { z0.d - z1.d }, z0.d + add za.d[w12, 0], { z0.d - z1.d }, z0.d + add za.d[w8, -1], { z0.d - z1.d }, z0.d + add za.d[w8, 8], { z0.d - z1.d }, z0.d + add za.d[w8, 0], { z0.d - z1.d }, z16.d + + add za.d[w7, 0], { z0.d - z3.d }, z0.d + add za.d[w12, 0], { z0.d - z3.d }, z0.d + add za.d[w8, -1], { z0.d - z3.d }, z0.d + add za.d[w8, 8], { z0.d - z3.d }, z0.d + add za.d[w8, 0], { z0.d - z3.d }, z16.d + + add za.d[w8, 0], { z0.d - z2.d }, z0.d + add za.d[w8, 0], { z0.d - z4.d }, z0.d + add za.d[w8, 0], { z0.d, z1.d, z2.d }, z0.d + add za.d[w8, 0], { z0.d, z1.d, z5.d }, z0.d + + add za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d + add za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d + add za[w8, 0], { z0.d - z1.d }, z0.d + add za.d[w8, 0], { z0 - z1 }, z0.d + add za.d[w8, 0], { z0.d - z1.d }, z0 + add za[w8, 0], { z0.d - z1.d }, z0 + add za.s[w8, 0], { z0.d - z1.d }, z0.s + add za.d[w8, 0], { z0.s - z1.s }, z0.d + + add za.d[w0, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w31, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 1<<63], { z0.d - z1.d }, { z0.d - z1.d } + + add za.d[w7, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w12, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, -1], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 8], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 8], { z1.d - z2.d }, { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z1.d }, { z15.d - z16.d } + add za.d[w8, 0], { z0.d - z1.d }, { z31.d, z0.d } + + add za.d[w7, 0], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w12, 0], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, -1], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 8], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 0], { z1.d - z4.d }, { z0.d - z3.d } + add za.d[w8, 0], { z2.d - z5.d }, { z0.d - z3.d } + add za.d[w8, 0], { z3.d - z6.d }, { z0.d - z3.d } + add za.d[w8, 0], { z0.d - z3.d }, { z15.d - z18.d } + add za.d[w8, 0], { z0.d - z3.d }, { z29.d, z30.d, z31.d, z0.d } + + add za.d[w8, 0], { z0.d - z2.d }, { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z3.d }, { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z2.d } + add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z3.d } + add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z4.d } + + add za.d[w8, 0, vgx4], { z0.d - z1.d }, { z0.d - z3.d } + add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z1.d } + add za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z3.d } + add za.d[w8, 0, vgx2], { z0.d - z3.d }, { z0.d - z1.d } + add za[w8, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za[w8, 0], { z0.d - z3.d }, { z0.d - z3.d } diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.d b/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.d new file mode 100644 index 00000000000..fe924efd561 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme2 +#source: sme2-i16i64-1.s +#error_output: sme2-i16i64-1-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.l b/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.l new file mode 100644 index 00000000000..bbdccc7ac63 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.l @@ -0,0 +1,57 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w10,3\],{z10\.d-z11\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,1\],{z12\.d-z15\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},Z0\.D' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d,z0\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d-z0\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w9,5\],{z9\.d-z10\.d},z6\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},Z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d-z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,2\],{z23\.d-z26\.d},z13\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z30\.d-z31\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w10,1\],{z22\.d-z23\.d},{z18\.d-z19\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z28\.d-z31\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,3\],{z16\.d-z19\.d},{z24\.d-z27\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1.d b/gas/testsuite/gas/aarch64/sme2-i16i64-1.d new file mode 100644 index 00000000000..8b95f5d3974 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1.d @@ -0,0 +1,65 @@ +#as: -march=armv8-a+sme2+sme-i16i64 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e07c10 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c17 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01fd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d} +[^:]+: c1e05d53 add za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e17c10 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c17 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11f90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d} +[^:]+: c1e17d91 add za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d} +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1607810 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601817 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601bd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d +[^:]+: c1601bf0 add za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d +[^:]+: c1601bf0 add za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d +[^:]+: c16f1810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d +[^:]+: c1663935 add za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1707810 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701817 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701b90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d +[^:]+: c1701bf0 add za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d +[^:]+: c1701bf0 add za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d +[^:]+: c17f1810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d +[^:]+: c17d7af2 add za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e07810 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01817 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01bd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d} +[^:]+: c1fe1810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d} +[^:]+: c1f25ad1 add za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e17810 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11817 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11b90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d} +[^:]+: c1fd1810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d} +[^:]+: c1f97a13 add za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1.s b/gas/testsuite/gas/aarch64/sme2-i16i64-1.s new file mode 100644 index 00000000000..537669a1b93 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1.s @@ -0,0 +1,61 @@ + add za.d[w8, 0], { z0.d - z1.d } + add za.d[w8, 0, vgx2], { z0.d - z1.d } + ADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d } + ADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D } + add za.d[w11, 0], { z0.d - z1.d } + add za.d[w8, 7], { z0.d - z1.d } + add za.d[w8, 0], { z30.d - z31.d } + add za.d[w10, 3], { z10.d - z11.d } + + add za.d[w8, 0], { z0.d - z3.d } + add za.d[w8, 0, vgx4], { z0.d - z3.d } + ADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d } + ADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D } + add za.d[w11, 0], { z0.d - z3.d } + add za.d[w8, 7], { z0.d - z3.d } + add za.d[w8, 0], { z28.d - z31.d } + add za.d[w11, 1], { z12.d - z15.d } + + add za.d[w8, 0], { z0.d - z1.d }, z0.d + add za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d + ADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d + ADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D + add za.d[w11, 0], { z0.d - z1.d }, z0.d + add za.d[w8, 7], { z0.d - z1.d }, z0.d + add za.d[w8, 0], { z30.d - z31.d }, z0.d + add za.d[w8, 0], { z31.d, z0.d }, z0.d + add za.d[w8, 0], { z31.d - z0.d }, z0.d + add za.d[w8, 0], { z0.d - z1.d }, z15.d + add za.d[w9, 5], { z9.d - z10.d }, z6.d + + add za.d[w8, 0], { z0.d - z3.d }, z0.d + add za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d + ADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d + ADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D + add za.d[w11, 0], { z0.d - z3.d }, z0.d + add za.d[w8, 7], { z0.d - z3.d }, z0.d + add za.d[w8, 0], { z28.d - z31.d }, z0.d + add za.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d + add za.d[w8, 0], { z31.d - z2.d }, z0.d + add za.d[w8, 0], { z0.d - z3.d }, z15.d + add za.d[w11, 2], { z23.d - z26.d }, z13.d + + add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d } + ADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d } + ADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D } + add za.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d } + add za.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d } + + add za.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d } + ADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d } + ADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D } + add za.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d } + add za.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d } + add za.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d } diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 69e0f833170..3689fff81f1 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -487,6 +487,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ + AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */ AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */ AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */ AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ @@ -695,6 +696,8 @@ enum aarch64_insn_class movewide, pcreladdr, ic_system, + sme_fp_sd, + sme_int_sd, sme_misc, sme_mov, sme_ldr, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index cdc9e465d13..5dba041483c 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -667,12 +667,13 @@ aarch64_insert_operand (const aarch64_operand *self, case 203: case 209: case 212: - case 222: + case 216: case 223: - case 230: + case 224: case 231: case 232: case 233: + case 234: return aarch64_ins_regno (self, info, code, inst, errors); case 15: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -684,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 256: + case 257: return aarch64_ins_reglane (self, info, code, inst, errors); case 36: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -729,13 +730,13 @@ aarch64_insert_operand (const aarch64_operand *self, case 192: case 193: case 194: - case 236: - case 250: + case 237: case 251: - case 253: - case 255: - case 260: + case 252: + case 254: + case 256: case 261: + case 262: return aarch64_ins_imm (self, info, code, inst, errors); case 44: case 45: @@ -804,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 107: return aarch64_ins_prfop (self, info, code, inst, errors); case 108: - case 252: - case 254: + case 253: + case 255: return aarch64_ins_none (self, info, code, inst, errors); case 109: return aarch64_ins_hint (self, info, code, inst, errors); @@ -896,48 +897,48 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sve_index (self, info, code, inst, errors); case 211: case 213: - case 229: + case 230: return aarch64_ins_sve_reglist (self, info, code, inst, errors); case 214: case 215: - case 216: case 217: case 218: case 219: - case 228: - return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 220: + case 229: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 221: + case 222: return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); - case 224: - case 226: - case 237: - return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); case 225: case 227: + case 238: + return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); + case 226: + case 228: return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 234: case 235: - case 244: + case 236: case 245: case 246: case 247: case 248: case 249: + case 250: return aarch64_ins_simple_index (self, info, code, inst, errors); - case 238: case 239: case 240: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 241: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); + return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 242: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 243: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + case 244: return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); - case 257: case 258: case 259: + case 260: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index bd03f4116cc..ae699ec2cd5 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -2008,6 +2008,8 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) % 3 + 1, 0); break; + case sme_fp_sd: + case sme_int_sd: case sve_size_bh: case sve_size_sd: insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index f69f30f8884..c38880201e1 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -166,7 +166,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x100xxxxxxxxxxxxxxxxx zero. */ - return 2596; + return 2614; } } } @@ -190,7 +190,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x101xx0xxxxxxxxxxxxxx luti4. */ - return 2499; + return 2511; } else { @@ -198,7 +198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x101xx1xxxxxxxxxxxxxx luti4. */ - return 2498; + return 2510; } } else @@ -207,7 +207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x101xxxxxxxxxxxxxxxxx luti4. */ - return 2497; + return 2509; } } } @@ -226,7 +226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0x010xxxxx00xxxxxxxxxx mov. */ - return 2506; + return 2518; } else { @@ -234,7 +234,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0x011xxxxx00xxxxxxxxxx mov. */ - return 2502; + return 2514; } } else @@ -247,7 +247,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x11xxx0xx00xxxxxxxxxx luti2. */ - return 2496; + return 2508; } else { @@ -255,7 +255,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x11xxx1xx00xxxxxxxxxx luti2. */ - return 2495; + return 2507; } } else @@ -268,7 +268,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x110xxxxx00xxxxxxxxxx movt. */ - return 2517; + return 2529; } else { @@ -276,7 +276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x111xxxxx00xxxxxxxxxx movt. */ - return 2516; + return 2528; } } else @@ -285,7 +285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000110x11xxxxxx00xxxxxxxxxx luti2. */ - return 2494; + return 2506; } } } @@ -298,7 +298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx10xxxxxxxxxx mov. */ - return 2504; + return 2516; } else { @@ -306,7 +306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx10xxxxxxxxxx mov. */ - return 2500; + return 2512; } } } @@ -320,7 +320,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx01xxxxxxxxxx mov. */ - return 2507; + return 2519; } else { @@ -328,7 +328,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx01xxxxxxxxxx mov. */ - return 2503; + return 2515; } } else @@ -339,7 +339,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx11xxxxxxxxxx mov. */ - return 2505; + return 2517; } else { @@ -347,7 +347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx11xxxxxxxxxx mov. */ - return 2501; + return 2513; } } } @@ -374,7 +374,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx000xxxxxxxxxxxx0 ld1b. */ - return 2433; + return 2445; } else { @@ -382,7 +382,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx100xxxxxxxxxxxx0 ld1b. */ - return 2434; + return 2446; } } else @@ -393,7 +393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx010xxxxxxxxxxxx0 ld1w. */ - return 2457; + return 2469; } else { @@ -401,7 +401,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx110xxxxxxxxxxxx0 ld1w. */ - return 2458; + return 2470; } } } @@ -415,7 +415,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx001xxxxxxxxxxxx0 ld1h. */ - return 2449; + return 2461; } else { @@ -423,7 +423,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx101xxxxxxxxxxxx0 ld1h. */ - return 2450; + return 2462; } } else @@ -434,7 +434,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx011xxxxxxxxxxxx0 ld1d. */ - return 2441; + return 2453; } else { @@ -442,7 +442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx111xxxxxxxxxxxx0 ld1d. */ - return 2442; + return 2454; } } } @@ -459,7 +459,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx000xxxxxxxxxxxx1 ldnt1b. */ - return 2465; + return 2477; } else { @@ -467,7 +467,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx100xxxxxxxxxxxx1 ldnt1b. */ - return 2466; + return 2478; } } else @@ -478,7 +478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx010xxxxxxxxxxxx1 ldnt1w. */ - return 2489; + return 2501; } else { @@ -486,7 +486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx110xxxxxxxxxxxx1 ldnt1w. */ - return 2490; + return 2502; } } } @@ -500,7 +500,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx001xxxxxxxxxxxx1 ldnt1h. */ - return 2481; + return 2493; } else { @@ -508,7 +508,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx101xxxxxxxxxxxx1 ldnt1h. */ - return 2482; + return 2494; } } else @@ -519,7 +519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx011xxxxxxxxxxxx1 ldnt1d. */ - return 2473; + return 2485; } else { @@ -527,7 +527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx111xxxxxxxxxxxx1 ldnt1d. */ - return 2474; + return 2486; } } } @@ -591,7 +591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx000xxxxxxxxxxxx0 ld1b. */ - return 2429; + return 2441; } else { @@ -599,7 +599,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx100xxxxxxxxxxxx0 ld1b. */ - return 2430; + return 2442; } } else @@ -610,7 +610,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx010xxxxxxxxxxxx0 ld1w. */ - return 2453; + return 2465; } else { @@ -618,7 +618,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx110xxxxxxxxxxxx0 ld1w. */ - return 2454; + return 2466; } } } @@ -632,7 +632,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx001xxxxxxxxxxxx0 ld1h. */ - return 2445; + return 2457; } else { @@ -640,7 +640,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx101xxxxxxxxxxxx0 ld1h. */ - return 2446; + return 2458; } } else @@ -651,7 +651,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx011xxxxxxxxxxxx0 ld1d. */ - return 2437; + return 2449; } else { @@ -659,7 +659,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx111xxxxxxxxxxxx0 ld1d. */ - return 2438; + return 2450; } } } @@ -676,7 +676,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx000xxxxxxxxxxxx1 ldnt1b. */ - return 2461; + return 2473; } else { @@ -684,7 +684,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx100xxxxxxxxxxxx1 ldnt1b. */ - return 2462; + return 2474; } } else @@ -695,7 +695,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx010xxxxxxxxxxxx1 ldnt1w. */ - return 2485; + return 2497; } else { @@ -703,7 +703,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx110xxxxxxxxxxxx1 ldnt1w. */ - return 2486; + return 2498; } } } @@ -717,7 +717,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx001xxxxxxxxxxxx1 ldnt1h. */ - return 2477; + return 2489; } else { @@ -725,7 +725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx101xxxxxxxxxxxx1 ldnt1h. */ - return 2478; + return 2490; } } else @@ -736,7 +736,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx011xxxxxxxxxxxx1 ldnt1d. */ - return 2469; + return 2481; } else { @@ -744,7 +744,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx111xxxxxxxxxxxx1 ldnt1d. */ - return 2470; + return 2482; } } } @@ -812,7 +812,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2527; + return 2539; } else { @@ -820,7 +820,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2528; + return 2540; } } else @@ -831,7 +831,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2551; + return 2563; } else { @@ -839,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2552; + return 2564; } } } @@ -853,7 +853,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2543; + return 2555; } else { @@ -861,7 +861,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2544; + return 2556; } } else @@ -872,7 +872,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2535; + return 2547; } else { @@ -880,7 +880,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2536; + return 2548; } } } @@ -897,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2559; + return 2571; } else { @@ -905,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2560; + return 2572; } } else @@ -916,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2583; + return 2595; } else { @@ -924,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2584; + return 2596; } } } @@ -938,7 +938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2575; + return 2587; } else { @@ -946,7 +946,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2576; + return 2588; } } else @@ -957,7 +957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2567; + return 2579; } else { @@ -965,7 +965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2568; + return 2580; } } } @@ -1029,7 +1029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2523; + return 2535; } else { @@ -1037,7 +1037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2524; + return 2536; } } else @@ -1048,7 +1048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2547; + return 2559; } else { @@ -1056,7 +1056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2548; + return 2560; } } } @@ -1070,7 +1070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2539; + return 2551; } else { @@ -1078,7 +1078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2540; + return 2552; } } else @@ -1089,7 +1089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2531; + return 2543; } else { @@ -1097,7 +1097,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2532; + return 2544; } } } @@ -1114,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2555; + return 2567; } else { @@ -1122,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2556; + return 2568; } } else @@ -1133,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2579; + return 2591; } else { @@ -1141,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2580; + return 2592; } } } @@ -1155,7 +1155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2571; + return 2583; } else { @@ -1163,7 +1163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2572; + return 2584; } } else @@ -1174,7 +1174,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2563; + return 2575; } else { @@ -1182,7 +1182,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2564; + return 2576; } } } @@ -1274,7 +1274,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx000xxxxxxxxx0xxx ld1b. */ - return 2435; + return 2447; } else { @@ -1282,7 +1282,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx010xxxxxxxxx0xxx ld1w. */ - return 2459; + return 2471; } } else @@ -1293,7 +1293,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx001xxxxxxxxx0xxx ld1h. */ - return 2451; + return 2463; } else { @@ -1301,7 +1301,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx011xxxxxxxxx0xxx ld1d. */ - return 2443; + return 2455; } } } @@ -1315,7 +1315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx000xxxxxxxxx1xxx ldnt1b. */ - return 2467; + return 2479; } else { @@ -1323,7 +1323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx010xxxxxxxxx1xxx ldnt1w. */ - return 2491; + return 2503; } } else @@ -1334,7 +1334,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx001xxxxxxxxx1xxx ldnt1h. */ - return 2483; + return 2495; } else { @@ -1342,7 +1342,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx011xxxxxxxxx1xxx ldnt1d. */ - return 2475; + return 2487; } } } @@ -1370,7 +1370,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx100xxxxxxxxx0xxx ld1b. */ - return 2436; + return 2448; } else { @@ -1378,7 +1378,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x00001000xxxxx100xxxxxxxxx0xxx ldr. */ - return 2493; + return 2505; } } else @@ -1387,7 +1387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx110xxxxxxxxx0xxx ld1w. */ - return 2460; + return 2472; } } else @@ -1398,7 +1398,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx101xxxxxxxxx0xxx ld1h. */ - return 2452; + return 2464; } else { @@ -1406,7 +1406,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx111xxxxxxxxx0xxx ld1d. */ - return 2444; + return 2456; } } } @@ -1420,7 +1420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx100xxxxxxxxx1xxx ldnt1b. */ - return 2468; + return 2480; } else { @@ -1428,7 +1428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx110xxxxxxxxx1xxx ldnt1w. */ - return 2492; + return 2504; } } else @@ -1439,7 +1439,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx101xxxxxxxxx1xxx ldnt1h. */ - return 2484; + return 2496; } else { @@ -1447,7 +1447,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx111xxxxxxxxx1xxx ldnt1d. */ - return 2476; + return 2488; } } } @@ -1511,7 +1511,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx000xxxxxxxxx0xxx ld1b. */ - return 2431; + return 2443; } else { @@ -1519,7 +1519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx100xxxxxxxxx0xxx ld1b. */ - return 2432; + return 2444; } } else @@ -1530,7 +1530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx010xxxxxxxxx0xxx ld1w. */ - return 2455; + return 2467; } else { @@ -1538,7 +1538,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx110xxxxxxxxx0xxx ld1w. */ - return 2456; + return 2468; } } } @@ -1552,7 +1552,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx001xxxxxxxxx0xxx ld1h. */ - return 2447; + return 2459; } else { @@ -1560,7 +1560,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx101xxxxxxxxx0xxx ld1h. */ - return 2448; + return 2460; } } else @@ -1571,7 +1571,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx011xxxxxxxxx0xxx ld1d. */ - return 2439; + return 2451; } else { @@ -1579,7 +1579,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx111xxxxxxxxx0xxx ld1d. */ - return 2440; + return 2452; } } } @@ -1596,7 +1596,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx000xxxxxxxxx1xxx ldnt1b. */ - return 2463; + return 2475; } else { @@ -1604,7 +1604,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx100xxxxxxxxx1xxx ldnt1b. */ - return 2464; + return 2476; } } else @@ -1615,7 +1615,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx010xxxxxxxxx1xxx ldnt1w. */ - return 2487; + return 2499; } else { @@ -1623,7 +1623,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx110xxxxxxxxx1xxx ldnt1w. */ - return 2488; + return 2500; } } } @@ -1637,7 +1637,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx001xxxxxxxxx1xxx ldnt1h. */ - return 2479; + return 2491; } else { @@ -1645,7 +1645,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx101xxxxxxxxx1xxx ldnt1h. */ - return 2480; + return 2492; } } else @@ -1656,7 +1656,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx011xxxxxxxxx1xxx ldnt1d. */ - return 2471; + return 2483; } else { @@ -1664,7 +1664,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx111xxxxxxxxx1xxx ldnt1d. */ - return 2472; + return 2484; } } } @@ -1727,21 +1727,219 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx0xxxxxxxxxxxxxxxx - sel. */ - return 2521; + if (((word >> 3) & 0x1) == 0) + { + if (((word >> 4) & 0x1) == 0) + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx00xxxxxxxxxx00xxx + fadd. */ + return 2437; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx10xxxxxxxxxx00xxx + fadd. */ + return 2438; + } + } + else + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xxxx0xxxxx10xxx + add. */ + return 2430; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xxxx0xxxxx10xxx + add. */ + return 2431; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xxxx0xxxxx10xxx + add. */ + return 2432; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xxxx0xxxxx10xxx + add. */ + return 2433; + } + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx00xxxx1xxxxx10xxx + add. */ + return 2428; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx10xxxx1xxxxx10xxx + add. */ + return 2429; + } + } + } + } + else + { + if (((word >> 4) & 0x1) == 0) + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx00xxxxxxxxxx01xxx + fsub. */ + return 2439; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx10xxxxxxxxxx01xxx + fsub. */ + return 2440; + } + } + else + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xxxx0xxxxx11xxx + sub. */ + return 2602; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xxxx0xxxxx11xxx + sub. */ + return 2603; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xxxx0xxxxx11xxx + sub. */ + return 2604; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xxxx0xxxxx11xxx + sub. */ + return 2605; + } + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx00xxxx1xxxxx11xxx + sub. */ + return 2600; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx10xxxx1xxxxx11xxx + sub. */ + return 2601; + } + } + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx1xxxxxxxxxxxxxxxx - sel. */ - return 2522; + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx01x0xxxxxxxxxxxxx + sel. */ + return 2533; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx11x0xxxxxxxxxxxxx + sel. */ + return 2534; + } + } + else + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x1x0xxxxxxxxxxx + add. */ + return 2434; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x1x1xxxxxxxxxxx + add. */ + return 2435; + } + } } } } @@ -1765,7 +1963,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx0xxx st1b. */ - return 2529; + return 2541; } else { @@ -1773,7 +1971,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx0xxx st1w. */ - return 2553; + return 2565; } } else @@ -1784,7 +1982,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx0xxx st1h. */ - return 2545; + return 2557; } else { @@ -1792,7 +1990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx0xxx st1d. */ - return 2537; + return 2549; } } } @@ -1806,7 +2004,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2561; + return 2573; } else { @@ -1814,7 +2012,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2585; + return 2597; } } else @@ -1825,7 +2023,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2577; + return 2589; } else { @@ -1833,7 +2031,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2569; + return 2581; } } } @@ -1861,7 +2059,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx100xxxxxxxxx0xxx st1b. */ - return 2530; + return 2542; } else { @@ -1869,7 +2067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1100001001xxxxx100xxxxxxxxx0xxx str. */ - return 2587; + return 2599; } } else @@ -1878,7 +2076,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx0xxx st1w. */ - return 2554; + return 2566; } } else @@ -1889,7 +2087,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx0xxx st1h. */ - return 2546; + return 2558; } else { @@ -1897,7 +2095,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx0xxx st1d. */ - return 2538; + return 2550; } } } @@ -1911,7 +2109,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2562; + return 2574; } else { @@ -1919,7 +2117,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2586; + return 2598; } } else @@ -1930,7 +2128,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2578; + return 2590; } else { @@ -1938,7 +2136,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2570; + return 2582; } } } @@ -1980,7 +2178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx0xxx st1b. */ - return 2525; + return 2537; } else { @@ -1988,7 +2186,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx0xxx st1b. */ - return 2526; + return 2538; } } else @@ -1999,7 +2197,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx0xxx st1w. */ - return 2549; + return 2561; } else { @@ -2007,7 +2205,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx0xxx st1w. */ - return 2550; + return 2562; } } } @@ -2021,7 +2219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx0xxx st1h. */ - return 2541; + return 2553; } else { @@ -2029,7 +2227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx0xxx st1h. */ - return 2542; + return 2554; } } else @@ -2040,7 +2238,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx0xxx st1d. */ - return 2533; + return 2545; } else { @@ -2048,7 +2246,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx0xxx st1d. */ - return 2534; + return 2546; } } } @@ -2065,7 +2263,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2557; + return 2569; } else { @@ -2073,7 +2271,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2558; + return 2570; } } else @@ -2084,7 +2282,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2581; + return 2593; } else { @@ -2092,7 +2290,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2582; + return 2594; } } } @@ -2106,7 +2304,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2573; + return 2585; } else { @@ -2114,7 +2312,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2574; + return 2586; } } else @@ -2125,7 +2323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2565; + return 2577; } else { @@ -2133,7 +2331,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2566; + return 2578; } } } @@ -4535,7 +4733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2637; + return 2655; } else { @@ -4543,7 +4741,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2645; + return 2663; } } else @@ -4554,7 +4752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2641; + return 2659; } else { @@ -4562,7 +4760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2648; + return 2666; } } } @@ -4600,7 +4798,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 2697; + return 2715; } else { @@ -4608,7 +4806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 2703; + return 2721; } } else @@ -4619,7 +4817,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 2700; + return 2718; } else { @@ -4627,7 +4825,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 2706; + return 2724; } } } @@ -4641,7 +4839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 2721; + return 2739; } else { @@ -4649,7 +4847,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 2727; + return 2745; } } else @@ -4660,7 +4858,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 2724; + return 2742; } else { @@ -4668,7 +4866,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 2730; + return 2748; } } } @@ -4685,7 +4883,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 2709; + return 2727; } else { @@ -4693,7 +4891,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 2715; + return 2733; } } else @@ -4704,7 +4902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 2712; + return 2730; } else { @@ -4712,7 +4910,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 2718; + return 2736; } } } @@ -4726,7 +4924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 2733; + return 2751; } else { @@ -4734,7 +4932,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 2739; + return 2757; } } else @@ -4745,7 +4943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 2736; + return 2754; } else { @@ -4753,7 +4951,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 2742; + return 2760; } } } @@ -4818,7 +5016,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2638; + return 2656; } else { @@ -4826,7 +5024,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2646; + return 2664; } } else @@ -4837,7 +5035,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2642; + return 2660; } else { @@ -4845,7 +5043,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2649; + return 2667; } } } @@ -4883,7 +5081,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 2698; + return 2716; } else { @@ -4891,7 +5089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 2704; + return 2722; } } else @@ -4902,7 +5100,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 2701; + return 2719; } else { @@ -4910,7 +5108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 2707; + return 2725; } } } @@ -4924,7 +5122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 2722; + return 2740; } else { @@ -4932,7 +5130,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 2728; + return 2746; } } else @@ -4943,7 +5141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 2725; + return 2743; } else { @@ -4951,7 +5149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 2731; + return 2749; } } } @@ -4968,7 +5166,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 2710; + return 2728; } else { @@ -4976,7 +5174,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 2716; + return 2734; } } else @@ -4987,7 +5185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 2713; + return 2731; } else { @@ -4995,7 +5193,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 2719; + return 2737; } } } @@ -5009,7 +5207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 2734; + return 2752; } else { @@ -5017,7 +5215,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 2740; + return 2758; } } else @@ -5028,7 +5226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 2737; + return 2755; } else { @@ -5036,7 +5234,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 2743; + return 2761; } } } @@ -5104,7 +5302,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2640; + return 2658; } else { @@ -5112,7 +5310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2647; + return 2665; } } else @@ -5121,7 +5319,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2644; + return 2662; } } else @@ -5132,7 +5330,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2639; + return 2657; } else { @@ -5140,7 +5338,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2643; + return 2661; } } } @@ -5202,7 +5400,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 2699; + return 2717; } else { @@ -5210,7 +5408,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 2793; + return 2811; } } else @@ -5221,7 +5419,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 2705; + return 2723; } else { @@ -5229,7 +5427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 2795; + return 2813; } } } @@ -5243,7 +5441,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 2702; + return 2720; } else { @@ -5251,7 +5449,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 2794; + return 2812; } } else @@ -5260,7 +5458,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 2708; + return 2726; } } } @@ -5276,7 +5474,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 2723; + return 2741; } else { @@ -5284,7 +5482,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 2799; + return 2817; } } else @@ -5295,7 +5493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 2729; + return 2747; } else { @@ -5303,7 +5501,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 2801; + return 2819; } } } @@ -5317,7 +5515,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 2726; + return 2744; } else { @@ -5325,7 +5523,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 2800; + return 2818; } } else @@ -5334,7 +5532,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 2732; + return 2750; } } } @@ -5353,7 +5551,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 2711; + return 2729; } else { @@ -5361,7 +5559,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 2796; + return 2814; } } else @@ -5372,7 +5570,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 2717; + return 2735; } else { @@ -5380,7 +5578,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 2798; + return 2816; } } } @@ -5394,7 +5592,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 2714; + return 2732; } else { @@ -5402,7 +5600,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 2797; + return 2815; } } else @@ -5411,7 +5609,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 2720; + return 2738; } } } @@ -5427,7 +5625,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 2735; + return 2753; } else { @@ -5435,7 +5633,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 2802; + return 2820; } } else @@ -5446,7 +5644,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 2741; + return 2759; } else { @@ -5454,7 +5652,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 2804; + return 2822; } } } @@ -5468,7 +5666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 2738; + return 2756; } else { @@ -5476,7 +5674,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 2803; + return 2821; } } else @@ -5485,7 +5683,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 2744; + return 2762; } } } @@ -5858,7 +6056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 2822; + return 2840; } else { @@ -5876,7 +6074,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 2825; + return 2843; } } } @@ -5956,7 +6154,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2635; + return 2653; } else { @@ -5964,7 +6162,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2636; + return 2654; } } else @@ -6071,7 +6269,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 2827; + return 2845; } } } @@ -6087,7 +6285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 2824; + return 2842; } else { @@ -6132,7 +6330,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2634; + return 2652; } else { @@ -6226,7 +6424,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 2826; + return 2844; } } } @@ -6356,7 +6554,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 2828; + return 2846; } } } @@ -6372,7 +6570,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 2823; + return 2841; } else { @@ -7214,7 +7412,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2654; + return 2672; } } } @@ -7288,7 +7486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2655; + return 2673; } } } @@ -9962,7 +10160,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2653; + return 2671; } } } @@ -11666,7 +11864,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2682; + return 2700; } } else @@ -11909,7 +12107,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2658; + return 2676; } else { @@ -11917,7 +12115,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2659; + return 2677; } } else @@ -12149,7 +12347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2679; + return 2697; } else { @@ -12170,7 +12368,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2686; + return 2704; } else { @@ -12178,7 +12376,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2685; + return 2703; } } else @@ -12233,7 +12431,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2678; + return 2696; } else { @@ -12245,7 +12443,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2684; + return 2702; } else { @@ -12253,7 +12451,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2683; + return 2701; } } else @@ -12304,7 +12502,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2662; + return 2680; } else { @@ -12312,7 +12510,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2663; + return 2681; } } else @@ -12671,7 +12869,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2656; + return 2674; } else { @@ -12704,7 +12902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2680; + return 2698; } else { @@ -12734,7 +12932,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2657; + return 2675; } else { @@ -12863,7 +13061,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2666; + return 2684; } else { @@ -12873,7 +13071,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2668; + return 2686; } else { @@ -12881,7 +13079,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2670; + return 2688; } } } @@ -12893,7 +13091,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2667; + return 2685; } else { @@ -12903,7 +13101,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2669; + return 2687; } else { @@ -12911,7 +13109,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2671; + return 2689; } } } @@ -13970,7 +14168,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2650; + return 2668; } else { @@ -13978,7 +14176,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2652; + return 2670; } } else @@ -13987,7 +14185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2651; + return 2669; } } } @@ -15483,7 +15681,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2660; + return 2678; } else { @@ -15491,7 +15689,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2661; + return 2679; } } } @@ -15865,7 +16063,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2664; + return 2682; } else { @@ -15873,7 +16071,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2665; + return 2683; } } } @@ -16234,7 +16432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx10xxx whilege. */ - return 2588; + return 2606; } else { @@ -16242,7 +16440,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx11xxx whilegt. */ - return 2589; + return 2607; } } else @@ -16272,7 +16470,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011100xxxxx1xxxx pext. */ - return 2518; + return 2530; } } } @@ -16286,7 +16484,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx10xxx whilehs. */ - return 2591; + return 2609; } else { @@ -16294,7 +16492,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx11xxx whilehi. */ - return 2590; + return 2608; } } else @@ -16324,7 +16522,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011110xxxxx1xxxx ptrue. */ - return 2520; + return 2532; } } } @@ -16341,7 +16539,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx10xxx whilelt. */ - return 2595; + return 2613; } else { @@ -16349,7 +16547,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx11xxx whilele. */ - return 2592; + return 2610; } } else @@ -16379,7 +16577,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011101xxxxx1xxxx pext. */ - return 2519; + return 2531; } } } @@ -16393,7 +16591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx10xxx whilelo. */ - return 2593; + return 2611; } else { @@ -16401,7 +16599,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx11xxx whilels. */ - return 2594; + return 2612; } } else @@ -17527,7 +17725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2681; + return 2699; } } else @@ -18186,7 +18384,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx10xxxx10xxxx1xxxxxxxxx cntp. */ - return 2428; + return 2436; } } else @@ -18888,7 +19086,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 2817; + return 2835; } else { @@ -19468,7 +19666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 2745; + return 2763; } else { @@ -19476,7 +19674,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 2747; + return 2765; } } else @@ -19487,7 +19685,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 2751; + return 2769; } else { @@ -19495,7 +19693,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 2753; + return 2771; } } } @@ -19509,7 +19707,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 2748; + return 2766; } else { @@ -19517,7 +19715,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 2750; + return 2768; } } else @@ -19528,7 +19726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 2754; + return 2772; } else { @@ -19536,7 +19734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 2756; + return 2774; } } } @@ -19553,7 +19751,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 2769; + return 2787; } else { @@ -19561,7 +19759,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 2771; + return 2789; } } else @@ -19572,7 +19770,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 2775; + return 2793; } else { @@ -19580,7 +19778,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 2777; + return 2795; } } } @@ -19594,7 +19792,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 2772; + return 2790; } else { @@ -19602,7 +19800,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 2774; + return 2792; } } else @@ -19613,7 +19811,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 2778; + return 2796; } else { @@ -19621,7 +19819,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 2780; + return 2798; } } } @@ -19641,7 +19839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 2757; + return 2775; } else { @@ -19649,7 +19847,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 2759; + return 2777; } } else @@ -19660,7 +19858,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 2763; + return 2781; } else { @@ -19668,7 +19866,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 2765; + return 2783; } } } @@ -19682,7 +19880,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 2760; + return 2778; } else { @@ -19690,7 +19888,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 2762; + return 2780; } } else @@ -19701,7 +19899,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 2766; + return 2784; } else { @@ -19709,7 +19907,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 2768; + return 2786; } } } @@ -19726,7 +19924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 2781; + return 2799; } else { @@ -19734,7 +19932,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 2783; + return 2801; } } else @@ -19745,7 +19943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 2787; + return 2805; } else { @@ -19753,7 +19951,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 2789; + return 2807; } } } @@ -19767,7 +19965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 2784; + return 2802; } else { @@ -19775,7 +19973,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 2786; + return 2804; } } else @@ -19786,7 +19984,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 2790; + return 2808; } else { @@ -19794,7 +19992,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 2792; + return 2810; } } } @@ -19828,7 +20026,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 2746; + return 2764; } else { @@ -19836,7 +20034,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 2805; + return 2823; } } else @@ -19847,7 +20045,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 2752; + return 2770; } else { @@ -19855,7 +20053,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 2807; + return 2825; } } } @@ -19869,7 +20067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 2749; + return 2767; } else { @@ -19877,7 +20075,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 2806; + return 2824; } } else @@ -19886,7 +20084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 2755; + return 2773; } } } @@ -19902,7 +20100,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 2770; + return 2788; } else { @@ -19910,7 +20108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 2811; + return 2829; } } else @@ -19921,7 +20119,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 2776; + return 2794; } else { @@ -19929,7 +20127,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 2813; + return 2831; } } } @@ -19943,7 +20141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 2773; + return 2791; } else { @@ -19951,7 +20149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 2812; + return 2830; } } else @@ -19960,7 +20158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 2779; + return 2797; } } } @@ -19979,7 +20177,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 2758; + return 2776; } else { @@ -19987,7 +20185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 2808; + return 2826; } } else @@ -19998,7 +20196,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 2764; + return 2782; } else { @@ -20006,7 +20204,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 2810; + return 2828; } } } @@ -20020,7 +20218,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 2761; + return 2779; } else { @@ -20028,7 +20226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 2809; + return 2827; } } else @@ -20037,7 +20235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 2767; + return 2785; } } } @@ -20053,7 +20251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 2782; + return 2800; } else { @@ -20061,7 +20259,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 2814; + return 2832; } } else @@ -20072,7 +20270,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 2788; + return 2806; } else { @@ -20080,7 +20278,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 2816; + return 2834; } } } @@ -20094,7 +20292,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 2785; + return 2803; } else { @@ -20102,7 +20300,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 2815; + return 2833; } } else @@ -20111,7 +20309,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 2791; + return 2809; } } } @@ -20278,7 +20476,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2672; + return 2690; } } } @@ -20311,7 +20509,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2598; + return 2616; } } else @@ -20385,7 +20583,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2674; + return 2692; } } } @@ -20418,7 +20616,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2675; + return 2693; } } else @@ -20465,7 +20663,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2605; + return 2623; } else { @@ -20473,7 +20671,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2607; + return 2625; } } else @@ -20484,7 +20682,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2609; + return 2627; } else { @@ -20498,7 +20696,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2610; + return 2628; } else { @@ -20506,7 +20704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2603; + return 2621; } } else @@ -20515,7 +20713,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2612; + return 2630; } } else @@ -20528,7 +20726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2611; + return 2629; } else { @@ -20536,7 +20734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2616; + return 2634; } } else @@ -20545,7 +20743,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2613; + return 2631; } } } @@ -20726,7 +20924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2597; + return 2615; } } else @@ -20757,7 +20955,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2673; + return 2691; } else { @@ -20776,7 +20974,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2689; + return 2707; } else { @@ -20786,7 +20984,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2687; + return 2705; } else { @@ -20796,7 +20994,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 2694; + return 2712; } else { @@ -20804,7 +21002,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 2693; + return 2711; } } } @@ -21388,7 +21586,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2690; + return 2708; } else { @@ -21396,7 +21594,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 2691; + return 2709; } } } @@ -21714,7 +21912,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2608; + return 2626; } } else @@ -22325,7 +22523,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2601; + return 2619; } } } @@ -22377,7 +22575,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2614; + return 2632; } } } @@ -22620,7 +22818,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2604; + return 2622; } } else @@ -22696,7 +22894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2617; + return 2635; } } else @@ -23522,7 +23720,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2602; + return 2620; } } else @@ -23554,7 +23752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2615; + return 2633; } } else @@ -23794,7 +23992,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2606; + return 2624; } } else @@ -23826,7 +24024,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2620; + return 2638; } else { @@ -23834,7 +24032,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2624; + return 2642; } } } @@ -23856,7 +24054,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2621; + return 2639; } else { @@ -23864,7 +24062,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2625; + return 2643; } } } @@ -23903,7 +24101,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2618; + return 2636; } else { @@ -23911,7 +24109,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2622; + return 2640; } } else @@ -23933,7 +24131,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2619; + return 2637; } else { @@ -23941,7 +24139,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2623; + return 2641; } } else @@ -25749,7 +25947,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2626; + return 2644; } else { @@ -25757,7 +25955,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2630; + return 2648; } } else @@ -25779,7 +25977,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2627; + return 2645; } else { @@ -25787,7 +25985,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2631; + return 2649; } } else @@ -26293,7 +26491,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2628; + return 2646; } else { @@ -26301,7 +26499,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2632; + return 2650; } } } @@ -26323,7 +26521,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2629; + return 2647; } else { @@ -26331,7 +26529,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2633; + return 2651; } } } @@ -26387,7 +26585,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2600; + return 2618; } else { @@ -26395,7 +26593,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2599; + return 2617; } } } @@ -26498,7 +26696,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2677; + return 2695; } else { @@ -26506,7 +26704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2676; + return 2694; } } else @@ -26517,7 +26715,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2688; + return 2706; } else { @@ -26527,7 +26725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 2696; + return 2714; } else { @@ -26535,7 +26733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 2695; + return 2713; } } } @@ -27026,22 +27224,22 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2391: return NULL; /* mova --> NULL. */ case 2388: value = 2390; break; /* mov --> mova. */ case 2390: return NULL; /* mova --> NULL. */ - case 2506: value = 2514; break; /* mov --> mova. */ - case 2514: return NULL; /* mova --> NULL. */ - case 2502: value = 2510; break; /* mov --> mova. */ - case 2510: return NULL; /* mova --> NULL. */ - case 2504: value = 2512; break; /* mov --> mova. */ - case 2512: return NULL; /* mova --> NULL. */ - case 2500: value = 2508; break; /* mov --> mova. */ - case 2508: return NULL; /* mova --> NULL. */ - case 2507: value = 2515; break; /* mov --> mova. */ - case 2515: return NULL; /* mova --> NULL. */ - case 2503: value = 2511; break; /* mov --> mova. */ - case 2511: return NULL; /* mova --> NULL. */ - case 2505: value = 2513; break; /* mov --> mova. */ - case 2513: return NULL; /* mova --> NULL. */ - case 2501: value = 2509; break; /* mov --> mova. */ - case 2509: return NULL; /* mova --> NULL. */ + case 2518: value = 2526; break; /* mov --> mova. */ + case 2526: return NULL; /* mova --> NULL. */ + case 2514: value = 2522; break; /* mov --> mova. */ + case 2522: return NULL; /* mova --> NULL. */ + case 2516: value = 2524; break; /* mov --> mova. */ + case 2524: return NULL; /* mova --> NULL. */ + case 2512: value = 2520; break; /* mov --> mova. */ + case 2520: return NULL; /* mova --> NULL. */ + case 2519: value = 2527; break; /* mov --> mova. */ + case 2527: return NULL; /* mova --> NULL. */ + case 2515: value = 2523; break; /* mov --> mova. */ + case 2523: return NULL; /* mova --> NULL. */ + case 2517: value = 2525; break; /* mov --> mova. */ + case 2525: return NULL; /* mova --> NULL. */ + case 2513: value = 2521; break; /* mov --> mova. */ + case 2521: return NULL; /* mova --> NULL. */ case 2393: value = 2398; break; /* ld1b --> ld1b. */ case 2398: return NULL; /* ld1b --> NULL. */ case 2395: value = 2400; break; /* ld1w --> ld1w. */ @@ -27063,11 +27261,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 2818; break; /* addg --> smax. */ - case 2818: value = 2819; break; /* smax --> umax. */ - case 2819: value = 2820; break; /* umax --> smin. */ - case 2820: value = 2821; break; /* smin --> umin. */ - case 2821: return NULL; /* umin --> NULL. */ + case 19: value = 2836; break; /* addg --> smax. */ + case 2836: value = 2837; break; /* smax --> umax. */ + case 2837: value = 2838; break; /* umax --> smin. */ + case 2838: value = 2839; break; /* smin --> umin. */ + case 2839: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -27225,8 +27423,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 2692; break; /* fcvt --> bfcvt. */ - case 2692: return NULL; /* bfcvt --> NULL. */ + case 825: value = 2710; break; /* fcvt --> bfcvt. */ + case 2710: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ @@ -27733,12 +27931,13 @@ aarch64_extract_operand (const aarch64_operand *self, case 203: case 209: case 212: - case 222: + case 216: case 223: - case 230: + case 224: case 231: case 232: case 233: + case 234: return aarch64_ext_regno (self, info, code, inst, errors); case 10: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -27754,7 +27953,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 256: + case 257: return aarch64_ext_reglane (self, info, code, inst, errors); case 36: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -27800,13 +27999,13 @@ aarch64_extract_operand (const aarch64_operand *self, case 192: case 193: case 194: - case 236: - case 250: + case 237: case 251: - case 253: - case 255: - case 260: + case 252: + case 254: + case 256: case 261: + case 262: return aarch64_ext_imm (self, info, code, inst, errors); case 44: case 45: @@ -27877,8 +28076,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 107: return aarch64_ext_prfop (self, info, code, inst, errors); case 108: - case 252: - case 254: + case 253: + case 255: return aarch64_ext_none (self, info, code, inst, errors); case 109: return aarch64_ext_hint (self, info, code, inst, errors); @@ -27969,48 +28168,48 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sve_index (self, info, code, inst, errors); case 211: case 213: - case 229: + case 230: return aarch64_ext_sve_reglist (self, info, code, inst, errors); case 214: case 215: - case 216: case 217: case 218: case 219: - case 228: - return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 220: + case 229: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 221: + case 222: return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); - case 224: - case 226: - case 237: - return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); case 225: case 227: + case 238: + return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); + case 226: + case 228: return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 234: case 235: - case 244: + case 236: case 245: case 246: case 247: case 248: case 249: + case 250: return aarch64_ext_simple_index (self, info, code, inst, errors); - case 238: case 239: case 240: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 241: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); + return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 242: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 243: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + case 244: return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); - case 257: case 258: case 259: + case 260: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 0475adbc31d..1148f2e952a 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -3169,6 +3169,8 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) variant = i - 1; break; + case sme_fp_sd: + case sme_int_sd: case sve_size_bh: case sve_size_sd: variant = extract_field (FLD_SVE_sz, inst->value, 0); diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 21e06e6114f..8658d07bf39 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -240,6 +240,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index cd185b8af29..d9cc0544e82 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -241,6 +241,7 @@ const aarch64_field fields[] = { 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */ { 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */ { 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */ + { 16, 4 }, /* SME_Zm: Z0-Z15, bits [19:16]. */ { 17, 4 }, /* SME_Zm2: Z0-Z31, multiple of 2, bits [20:17]. */ { 18, 3 }, /* SME_Zm4: Z0-Z31, multiple of 4, bits [20:18]. */ { 6, 4 }, /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */ @@ -1764,6 +1765,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SME_Zm: + if (opnd->reg.regno > 15) + { + set_invalid_regno_error (mismatch_detail, idx, "z", 0, 15); + return 0; + } + break; + case AARCH64_OPND_SME_PnT_Wm_imm: size = aarch64_get_qualifier_esize (opnd->qualifier); max_value = 16 / size - 1; @@ -3101,23 +3110,38 @@ aarch64_match_operands_constraint (aarch64_inst *inst, break; default: - /* Check for cases where a source register needs to be the same as the - destination register. Do this before matching qualifiers since if - an instruction has both invalid tying and invalid qualifiers, - the error about qualifiers would suggest several alternative - instructions that also have invalid tying. */ - if (inst->operands[0].reg.regno - != inst->operands[i].reg.regno) - { - if (mismatch_detail) - { - mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND; - mismatch_detail->index = i; - mismatch_detail->error = NULL; - } - return 0; - } - break; + { + /* Check for cases where a source register needs to be the + same as the destination register. Do this before + matching qualifiers since if an instruction has both + invalid tying and invalid qualifiers, the error about + qualifiers would suggest several alternative instructions + that also have invalid tying. */ + enum aarch64_operand_class op_class1 + = aarch64_get_operand_class (inst->operands[0].type); + enum aarch64_operand_class op_class2 + = aarch64_get_operand_class (inst->operands[i].type); + assert (op_class1 == op_class2); + if (op_class1 == AARCH64_OPND_CLASS_SVE_REGLIST + ? ((inst->operands[0].reglist.first_regno + != inst->operands[i].reglist.first_regno) + || (inst->operands[0].reglist.num_regs + != inst->operands[i].reglist.num_regs) + || (inst->operands[0].reglist.stride + != inst->operands[i].reglist.stride)) + : (inst->operands[0].reg.regno + != inst->operands[i].reg.regno)) + { + if (mismatch_detail) + { + mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND; + mismatch_detail->index = i; + mismatch_detail->error = NULL; + } + return 0; + } + break; + } } } @@ -3874,6 +3898,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm_16: case AARCH64_OPND_SVE_Zn: case AARCH64_OPND_SVE_Zt: + case AARCH64_OPND_SME_Zm: if (opnd->qualifier == AARCH64_OPND_QLF_NIL) snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno)); else @@ -6501,6 +6526,18 @@ aarch64_cpu_supports_inst_p (uint64_t cpu_variant, aarch64_inst *inst) || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *inst->opcode->avariant)) return false; + if (inst->opcode->iclass == sme_fp_sd + && inst->operands[0].qualifier == AARCH64_OPND_QLF_S_D + && !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, + AARCH64_FEATURE_SME_F64F64)) + return false; + + if (inst->opcode->iclass == sme_int_sd + && inst->operands[0].qualifier == AARCH64_OPND_QLF_S_D + && !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, + AARCH64_FEATURE_SME_I16I64)) + return false; + return true; } diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 8422be4c9db..1284dd47d4d 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -62,6 +62,7 @@ enum aarch64_field_kind FLD_SME_ZAda_3b, FLD_SME_Zdn2, FLD_SME_Zdn4, + FLD_SME_Zm, FLD_SME_Zm2, FLD_SME_Zm4, FLD_SME_Zn2, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 0f881681aab..b97e375c1f0 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5325,7 +5325,19 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("whilelt", 0x25205410, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), /* SME2 extensions to SME. */ + SME2_INSN ("add", 0xc1a01c10, 0xffbf9c38, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("add", 0xc1a11c10, 0xffbf9c78, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("add", 0xc1201810, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("add", 0xc1301810, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("add", 0xc1a01810, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("add", 0xc1a11810, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("add", 0xc120a300, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), + SME2_INSN ("add", 0xc120ab00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0), + SME2_INSN ("fadd", 0xc1a01c00, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("fadd", 0xc1a11c00, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("fsub", 0xc1a01c08, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("fsub", 0xc1a11c08, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), SME2_INSN ("ld1b", 0xa0408000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0), SME2_INSN ("ld1b", 0xa1400000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), @@ -5485,6 +5497,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), SME2_INSN ("str", 0xe13f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0), + SME2_INSN ("sub", 0xc1a01c18, 0xffbf9c38, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("sub", 0xc1a11c18, 0xffbf9c78, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("sub", 0xc1201818, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("sub", 0xc1301818, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("sub", 0xc1a01818, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("sub", 0xc1a11818, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), @@ -6138,6 +6156,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = F(FLD_SME_Zdn2), "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \ F(FLD_SME_Zdn4), "a list of SVE vector registers") \ + Y(SVE_REG, regno, "SME_Zm", 0, F(FLD_SME_Zm), \ + "an SVE vector register") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \ F(FLD_SME_Zm2), "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \