From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 31 Jan 2012 05:07:57 +0000 (-0800)
Subject: Merge with main repository.
X-Git-Tag: stable_2012_06_28~265
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e88165a431a90cf7e33e205794caed898ca6fcb1;p=gem5.git

Merge with main repository.
---

e88165a431a90cf7e33e205794caed898ca6fcb1
diff --cc src/arch/mips/vtophys.hh
index 37a7378a8,741ac36bc..a3fbdd457
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@@ -38,9 -38,26 +38,8 @@@
  #include "arch/mips/utility.hh"
  
  class ThreadContext;
- class FunctionalPort;
  
  namespace MipsISA {
 -    inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
 -
 -    // User Virtual
 -    inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
 -
 -    inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
 -
 -    inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
 -
 -    inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
 -
 -    inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
 -
 -    inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
 -
 -    inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
 -
 -
      Addr vtophys(Addr vaddr);
      Addr vtophys(ThreadContext *tc, Addr vaddr);
  
diff --cc src/kern/solaris/solaris.hh
index da6ce84f7,c6fb93f04..9cd5af16f
--- a/src/kern/solaris/solaris.hh
+++ b/src/kern/solaris/solaris.hh
@@@ -32,10 -32,16 +32,8 @@@
  #define __SOLARIS_HH__
  
  #include "base/types.hh"
 -#include "config/full_system.hh"
 -
 -#if FULL_SYSTEM
 -
 -class Solaris {};
 -
 -#else //!FULL_SYSTEM
 -
  #include "kern/operatingsystem.hh"
  
- class TranslatingPort;
- 
  ///
  /// This class encapsulates the types, structures, constants,
  /// functions, and syscall-number mappings specific to the Solaris
diff --cc tests/configs/o3-timing-ruby.py
index b967a5080,3b6d58b3b..14b0ff1ab
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@@ -43,4 -43,7 +43,7 @@@ system = System(cpu = cpu
  system.physmem.port = system.membus.port
  cpu.connectAllPorts(system.membus)
  
+ # Connect the system port for loading of binaries etc
+ system.system_port = system.membus.port
+ 
 -root = Root(system = system)
 +root = Root(full_system = False, system = system)
diff --cc tests/configs/simple-timing-ruby.py
index 46436d18c,1d67f6f97..4f812f209
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@@ -79,11 -82,9 +79,8 @@@ assert(len(system.ruby._cpu_ruby_ports
  # Tie the cpu cache ports to the ruby cpu ports and
  # physmem, respectively
  #
 -cpu.icache_port = system.ruby._cpu_ruby_ports[0].port
 -cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port
 +cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
  
- # Connect the system port for loading of binaries etc
- system.system_port = system.ruby._sys_port_proxy.port
- 
  # -----------------------
  # run simulation
  # -----------------------