From: Jonathan Marek Date: Sat, 11 Jul 2020 16:29:38 +0000 (-0400) Subject: freedreno/regs: update a6xx RB regs X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e883aa2585251c8ea9256132ba45877bf58464c4;p=mesa.git freedreno/regs: update a6xx RB regs Update some registers in the 0x8c00-0x8dff range. Signed-off-by: Jonathan Marek Part-of: --- diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml index b9a92cdc325..ab830373072 100644 --- a/src/freedreno/registers/a6xx.xml +++ b/src/freedreno/registers/a6xx.xml @@ -1592,27 +1592,6 @@ to upconvert to 32b float internally? - - - - - - - - - - - - - - - - - - - - - @@ -1788,19 +1767,9 @@ to upconvert to 32b float internally? - - - - - - - @@ -2182,18 +2151,24 @@ to upconvert to 32b float internally? (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords) --> - + - - + + + + + + + + @@ -2201,6 +2176,8 @@ to upconvert to 32b float internally? + + @@ -2210,7 +2187,7 @@ to upconvert to 32b float internally? - + + @@ -2235,18 +2213,22 @@ to upconvert to 32b float internally? + + + + @@ -2286,17 +2268,18 @@ to upconvert to 32b float internally? - - + + - + + - + @@ -2316,14 +2299,15 @@ to upconvert to 32b float internally? + - - + + + - + @@ -2356,6 +2341,7 @@ to upconvert to 32b float internally? + @@ -2375,22 +2361,18 @@ to upconvert to 32b float internally? + - - - stride of depth/stencil buffer - - - size of layer - + + - - + + - + @@ -2412,17 +2394,14 @@ to upconvert to 32b float internally? + - - stride of stencil buffer - - - size of layer - + + - - + + @@ -2435,47 +2414,58 @@ to upconvert to 32b float internally? - + + + - + - + - - - - - + + + + + + + + + + + + + - + - + + - + - + - - + + - + @@ -2498,32 +2488,48 @@ to upconvert to 32b float internally? then probably a component mask, I always see 0xf + + - + - - + + + + + + + + + - + - - + + + + - + - + + + + + + - + @@ -2539,33 +2545,40 @@ to upconvert to 32b float internally? + + - - - - + + + + + + - - - - - + + + + + + + - + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c index 2bc30bcf993..486dc7db284 100644 --- a/src/freedreno/vulkan/tu_clear_blit.c +++ b/src/freedreno/vulkan/tu_clear_blit.c @@ -240,7 +240,7 @@ r2d_dst_buffer(struct tu_cs *cs, VkFormat vk_format, uint64_t va, uint32_t pitch .srgb = vk_format_is_srgb(vk_format)), A6XX_RB_2D_DST_LO((uint32_t) va), A6XX_RB_2D_DST_HI(va >> 32), - A6XX_RB_2D_DST_SIZE(.pitch = pitch)); + A6XX_RB_2D_DST_PITCH(pitch)); } static void @@ -266,7 +266,7 @@ r2d_setup_common(struct tu_cmd_buffer *cmd, unknown_8c01 = 0x00084001; } - tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_8C01, 1); + tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_UNKNOWN_8C01, 1); tu_cs_emit(cs, unknown_8c01); uint32_t blit_cntl = A6XX_RB_2D_BLIT_CNTL( diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c index 2c50b9f06fa..b31d9d7722c 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c @@ -282,7 +282,7 @@ emit_blit_setup(struct fd_ringbuffer *ring, COND(is_srgb, A6XX_SP_2D_DST_FORMAT_SRGB) | A6XX_SP_2D_DST_FORMAT_MASK(0xf)); - OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1); + OUT_PKT4(ring, REG_A6XX_RB_2D_UNKNOWN_8C01, 1); OUT_RING(ring, 0); } @@ -384,7 +384,7 @@ emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring, A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) | A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX)); OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */ - OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(p)); + OUT_RING(ring, A6XX_RB_2D_DST_PITCH(p)); OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); @@ -442,7 +442,7 @@ emit_blit_dst(struct fd_ringbuffer *ring, struct pipe_resource *prsc, enum pipe_ COND(util_format_is_srgb(pfmt), A6XX_RB_2D_DST_INFO_SRGB) | COND(ubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS)); OUT_RELOC(ring, dst->bo, off, 0, 0); /* RB_2D_DST_LO/HI */ - OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(pitch)); + OUT_RING(ring, A6XX_RB_2D_DST_PITCH(pitch)); OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c index 507b1e51bd9..dd9c75051c9 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c @@ -375,7 +375,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); emit_marker6(ring, 7); - OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1); + OUT_PKT4(ring, REG_A6XX_RB_2D_UNKNOWN_8C01, 1); OUT_RING(ring, 0x0); OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13); @@ -418,7 +418,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) | A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX)); OUT_RELOC(ring, zsbuf->lrz, 0, 0, 0); - OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(zsbuf->lrz_pitch * 2)); + OUT_RING(ring, A6XX_RB_2D_DST_PITCH(zsbuf->lrz_pitch * 2).value); OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000); OUT_RING(ring, 0x00000000);