From: Kajol Jain Date: Wed, 12 Jun 2019 08:41:04 +0000 (+0530) Subject: arch-power: Added support for Trap instructons X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e895d59cfd67b348d49240425100a9a4c707b66d;p=gem5.git arch-power: Added support for Trap instructons * Added trap instructons. * Added trap interrupt handler. * Raise trap interrupt whenever condition satisfied for corresponding trap instruction. * Added bit need to set for that type of interrupt. Change-Id: I46de00558139e0726c056fd71f819d63cb8045df Signed-off-by: Kajol Jain --- diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh index cdaf1c8b4..28eac707b 100644 --- a/src/arch/power/faults.hh +++ b/src/arch/power/faults.hh @@ -36,6 +36,7 @@ #include "cpu/thread_context.hh" #include "sim/faults.hh" +#define SRR1_TRAP_BIT 16 #define SRR1_PRI_BIT 17 #define SRR1_ILLEGAL_INSTR_BIT 18 @@ -206,6 +207,19 @@ class ProgramIllegalInterrupt : public ProgramInterrupt } }; +class ProgramTrapInterrupt : public ProgramInterrupt +{ + public: + ProgramTrapInterrupt() + { + } + virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst = + StaticInst::nullStaticInstPtr) + { + ProgramInterrupt::invoke(tc, inst ,setBitMask(SRR1_TRAP_BIT)); + } +}; + class ProgramPriInterrupt : public ProgramInterrupt { public: diff --git a/src/arch/power/isa/bitfields.isa b/src/arch/power/isa/bitfields.isa index 2f828a674..2a1974bfc 100644 --- a/src/arch/power/isa/bitfields.isa +++ b/src/arch/power/isa/bitfields.isa @@ -100,3 +100,6 @@ def bitfield BHRB <20:11>; //L field for mtmsr and SLB move from entry VSID,ESID instructions. def bitfield L <16>; + +//TO field for trap instructions +def bitfield TO <25:21>; diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 285487d5a..59af89cff 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -175,7 +175,6 @@ decode PO default Unknown::unknown() { } }}, [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]); - 2: tdi({{ }}); } format LoadDispOp { @@ -282,6 +281,38 @@ decode PO default Unknown::unknown() { } } + + format IntImmArithOp { + + 3: twi({{ + if(FullSystem) { + int32_t val = Ra_sw; + if(((TO & 0x10) && (val < simm)) || + ((TO & 0x08) && (val > simm)) || + ((TO & 0x04) && (val == simm)) || + ((TO & 0x02) && ((uint32_t)val < (uint32_t)simm)) || + ((TO & 0x01) && ((uint32_t)val > (uint32_t)simm))) { + fault= std::make_shared(); + } + } + }}); + + 2: tdi({{ + if(FullSystem) { + int64_t val1 = Ra_sd; + int64_t val2 = simm; + //printf("Val 1 : 0x%016lx val2: 0x%016lx\n", val,val2); + if(((TO & 0x10) && (val1 < val2)) || + ((TO & 0x08) && (val1 > val2)) || + ((TO & 0x04) && (val1 == val2)) || + ((TO & 0x02) && ((uint64_t)val1 < (uint64_t)val2)) || + ((TO & 0x01) && ((uint64_t)val1 > (uint64_t)val2))) { + fault= std::make_shared(); + } + } + }}); + } + format IntImmCompOp { 11: cmpi({{ if (length) { @@ -406,7 +437,37 @@ decode PO default Unknown::unknown() { } format IntArithOp { - 779: modsw({{ + + 4: tw({{ + if(FullSystem) { + int32_t val1 = Ra_sw; + int32_t val2 = Rb_sw; + if(((TO & 0x10) && (val1 < val2)) || + ((TO & 0x08) && (val1 > val2)) || + ((TO & 0x04) && (val1 == val2)) || + ((TO & 0x02) && ((uint32_t)val1 < (uint32_t)val2)) || + ((TO & 0x01) && ((uint32_t)val1 > (uint32_t)val2))) { + fault= std::make_shared(); + } + } + + }}); + + 68: td ({{ + if(FullSystem) { + int64_t val1 = Ra_sd; + int64_t val2 = Rb_sd; + if(((TO & 0x10) && (val1 < val2)) || + ((TO & 0x08) && (val1 > val2)) || + ((TO & 0x04) && (val1 == val2)) || + ((TO & 0x02) && ((uint64_t)val1 < (uint64_t)val2)) || + ((TO & 0x01) && ((uint64_t)val1 > (uint64_t)val2))) { + fault= std::make_shared(); + } + } + }}); + + 779: modsw({{ int64_t src1 = Ra_sw; int64_t src2 = Rb_sw; if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {