From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 15 May 2021 11:29:46 +0000 (+0100)
Subject: add load/store FP indexed instructions to minor_31.csv
X-Git-Tag: 0.0.3~36
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e89771fc4c865fd8d6a26ca54b577dbc17397126;p=openpower-isa.git

add load/store FP indexed instructions to minor_31.csv
---

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index 88e1aed8..df2774cb 100644
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -92,7 +92,12 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b1101110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,cix,0,0,0,NONE,0,0,ldcix,X
 0b0000110101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,ldux,X
 0b0000010101,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,ldx,X
-0b1000010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lfsx,X
+0b1001010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,lfdx,X
+0b1001110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,0,lfdux,X
+0b1101010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,1,0,0,0,0,NONE,0,0,lfiwax,X
+0b1101110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,lfiwzx,X
+0b1000010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,0,lfsx,X
+0b1000110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,FRT,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,0,lfsux,X
 0b0001110100,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,1,0,0,NONE,0,1,lharx,X
 0b0101110111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhaux,X
 0b0101010111,LDST,OP_LOAD,RA_OR_ZERO,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lhax,X
@@ -163,6 +168,11 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b0011010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is8B,0,0,0,1,0,0,ONE,0,1,stdcx,X
 0b0010110101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,1,stdux,X
 0b0010010101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,1,stdx,X
+0b1011010111,LDST,OP_STORE,RA_OR_ZERO,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,stfdx,X
+0b1011110111,LDST,OP_STORE,RA_OR_ZERO,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is8B,0,0,1,0,0,0,NONE,0,0,stfdux,X
+0b1111010111,LDST,OP_STORE,RA_OR_ZERO,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,stfiwx,X
+0b1010010111,LDST,OP_STORE,RA_OR_ZERO,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,1,0,NONE,0,0,stfsx,X
+0b1010110111,LDST,OP_STORE,RA_OR_ZERO,RB,FRS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,1,0,1,0,NONE,0,0,stfsux,X
 0b1110010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,1,0,0,0,0,0,NONE,0,1,sthbrx,X
 0b1110110101,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,cix,0,0,0,NONE,0,1,sthcix,X
 0b1011010110,LDST,OP_STORE,RA_OR_ZERO,RB,RS,NONE,NONE,CR0,0,0,ZERO,0,is2B,0,0,0,1,0,0,ONE,0,1,sthcx,X