From: Ali Saidi Date: Thu, 20 Jul 2006 23:00:40 +0000 (-0400) Subject: Enforce the timing cpu ticking at it's clock rate X-Git-Tag: m5_2.0_beta1~68 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8a329507566a6de71d5b60250f48d1ce6fa44fe;p=gem5.git Enforce the timing cpu ticking at it's clock rate Add a max time option in seconds and a single system root clock be 1THz configs/test/fs.py: Add a max time option in seconds and a single system root clock be 1THz src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: Enforce the timing cpu ticking at it's clock rate --HG-- extra : convert_revision : a1b0de27abde867f9c3da5bec11639e3d82a95f5 --- diff --git a/configs/test/fs.py b/configs/test/fs.py index f4c50fc23..7e89b7dd4 100644 --- a/configs/test/fs.py +++ b/configs/test/fs.py @@ -10,6 +10,7 @@ parser = optparse.OptionParser() parser.add_option("-d", "--detailed", action="store_true") parser.add_option("-t", "--timing", action="store_true") parser.add_option("-m", "--maxtick", type="int") +parser.add_option("--maxtime", type="float") parser.add_option("--dual", help="Run full system using dual systems", action="store_true") @@ -102,7 +103,7 @@ if options.dual: MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')), MyLinuxAlphaSystem(readfile=script('netperf-server.rcS'))) else: - root = TsunamiRoot(clock = '2GHz', system = MyLinuxAlphaSystem()) + root = TsunamiRoot(clock = '1THz', system = MyLinuxAlphaSystem()) m5.instantiate(root) @@ -116,6 +117,10 @@ m5.instantiate(root) if options.maxtick: exit_event = m5.simulate(options.maxtick) +elif options.maxtime: + simtime = int(options.maxtime * root.clock.value) + print "simulating for: ", simtime + exit_event = m5.simulate(simtime) else: exit_event = m5.simulate() diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 246bcec05..5c1654f7e 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -85,8 +85,16 @@ TimingSimpleCPU::CpuPort::recvStatusChange(Status status) panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); } + +void +TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t) +{ + pkt = _pkt; + Event::schedule(t); +} + TimingSimpleCPU::TimingSimpleCPU(Params *p) - : BaseSimpleCPU(p), icachePort(this), dcachePort(this) + : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) { _status = Idle; ifetch_pkt = dcache_pkt = NULL; @@ -462,11 +470,26 @@ TimingSimpleCPU::completeIfetch(Packet *pkt) } } +void +TimingSimpleCPU::IcachePort::ITickEvent::process() +{ + cpu->completeIfetch(pkt); +} bool TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) { - cpu->completeIfetch(pkt); + // These next few lines could be replaced with something faster + // who knows what though + Tick time = pkt->req->getTime(); + while (time < curTick) + time += lat; + + if (time == curTick) + cpu->completeIfetch(pkt); + else + tickEvent.schedule(pkt, time); + return true; } @@ -523,10 +546,24 @@ TimingSimpleCPU::completeDrain() bool TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) { - cpu->completeDataAccess(pkt); + Tick time = pkt->req->getTime(); + while (time < curTick) + time += lat; + + if (time == curTick) + cpu->completeDataAccess(pkt); + else + tickEvent.schedule(pkt, time); + return true; } +void +TimingSimpleCPU::DcachePort::DTickEvent::process() +{ + cpu->completeDataAccess(pkt); +} + void TimingSimpleCPU::DcachePort::recvRetry() { diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index ac36e5c99..d03fa4bc0 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -74,11 +74,12 @@ class TimingSimpleCPU : public BaseSimpleCPU { protected: TimingSimpleCPU *cpu; + Tick lat; public: - CpuPort(const std::string &_name, TimingSimpleCPU *_cpu) - : Port(_name), cpu(_cpu) + CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) + : Port(_name), cpu(_cpu), lat(_lat) { } protected: @@ -92,14 +93,26 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) { resp.clear(); snoop.clear(); } + + struct TickEvent : public Event + { + Packet *pkt; + TimingSimpleCPU *cpu; + + TickEvent(TimingSimpleCPU *_cpu) + :Event(&mainEventQueue), cpu(_cpu) {} + const char *description() { return "Timing CPU clock event"; } + void schedule(Packet *_pkt, Tick t); + }; + }; class IcachePort : public CpuPort { public: - IcachePort(TimingSimpleCPU *_cpu) - : CpuPort(_cpu->name() + "-iport", _cpu) + IcachePort(TimingSimpleCPU *_cpu, Tick _lat) + : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) { } protected: @@ -107,14 +120,26 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual bool recvTiming(Packet *pkt); virtual void recvRetry(); + + struct ITickEvent : public TickEvent + { + + ITickEvent(TimingSimpleCPU *_cpu) + : TickEvent(_cpu) {} + void process(); + const char *description() { return "Timing CPU clock event"; } + }; + + ITickEvent tickEvent; + }; class DcachePort : public CpuPort { public: - DcachePort(TimingSimpleCPU *_cpu) - : CpuPort(_cpu->name() + "-dport", _cpu) + DcachePort(TimingSimpleCPU *_cpu, Tick _lat) + : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) { } protected: @@ -122,6 +147,17 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual bool recvTiming(Packet *pkt); virtual void recvRetry(); + + struct DTickEvent : public TickEvent + { + DTickEvent(TimingSimpleCPU *_cpu) + : TickEvent(_cpu) {} + void process(); + const char *description() { return "Timing CPU clock event"; } + }; + + DTickEvent tickEvent; + }; IcachePort icachePort;