From: Florent Kermarrec Date: Sat, 2 May 2015 12:26:19 +0000 (+0200) Subject: do more test with last changes fix small issues X-Git-Tag: 24jan2021_ls180~2270 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8c01ff4aa9fc44417f0a458d5d42a54c808fdc9;p=litex.git do more test with last changes fix small issues --- diff --git a/misoclib/com/liteusb/frontend/wishbone.py b/misoclib/com/liteusb/frontend/wishbone.py index fceb54f5..8b4d4dc1 100644 --- a/misoclib/com/liteusb/frontend/wishbone.py +++ b/misoclib/com/liteusb/frontend/wishbone.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from misoclib.com.liteusb.common import * -from misoclib.tools.litescope.bridge.wishbone import LiteScopeWishboneBridge +from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge class LiteUSBWishboneBridge(LiteScopeWishboneBridge): def __init__(self, port, clk_freq): diff --git a/misoclib/com/liteusb/software/wishbone.py b/misoclib/com/liteusb/software/wishbone.py index 971bb97e..a1a1a637 100644 --- a/misoclib/com/liteusb/software/wishbone.py +++ b/misoclib/com/liteusb/software/wishbone.py @@ -5,7 +5,7 @@ class LiteUSBWishboneDriverFTDI: "write": 0x01, "read": 0x02 } - def __init__(self, interface, mode, tag, addrmap=None, debug=False): + def __init__(self, interface, mode, tag, addrmap=None, busword=8, debug=False): self.interface = interface self.mode = mode self.tag = tag diff --git a/software/common.mak b/software/common.mak index 493ec2e8..b2aaf71b 100644 --- a/software/common.mak +++ b/software/common.mak @@ -19,7 +19,7 @@ LD_quiet = @echo " LD " $@ && $(TARGET_PREFIX)ld OBJCOPY_quiet = @echo " OBJCOPY " $@ && $(TARGET_PREFIX)objcopy RANLIB_quiet = @echo " RANLIB " $@ && $(TARGET_PREFIX)ranlib -MSC_GIT_ID := $(shell cd $(MSCDIR) && python3 -c "from misoclib.cpu.peripherals.identifier.git import get_id; print(hex(get_id()), end='')") +MSC_GIT_ID := $(shell cd $(MSCDIR) && python3 -c "from misoclib.cpu.git import get_id; print(hex(get_id()), end='')") ifeq ($(V),1) CC = $(CC_normal)