From: Ciro Santilli <ciro.santilli@arm.com>
Date: Thu, 19 Nov 2020 12:19:49 +0000 (+0000)
Subject: arch-arm: add official names to all PMU events
X-Git-Tag: develop-gem5-snapshot~409
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8c641602a435cdc05d8ad29983c41f8e6641bea;p=gem5.git

arch-arm: add official names to all PMU events

Change-Id: I1d44ffa540b0cf175f279c6509839ad2dd69017a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37976
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index c712a97b6..18390107e 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -117,14 +117,20 @@ class ArmPMU(SimObject):
         if bpred is not None and isNullPointer(bpred):
             bpred = None
 
+        # 0x00: SW_INCR
         self.addEvent(SoftwareIncrement(self,0x00))
         # 0x01: L1I_CACHE_REFILL
+        # 0x02: L1I_TLB_REFILL,
         self.addEvent(ProbeEvent(self,0x02, itb, "Refills"))
         # 0x03: L1D_CACHE_REFILL
         # 0x04: L1D_CACHE
+        # 0x05: L1D_TLB_REFILL
         self.addEvent(ProbeEvent(self,0x05, dtb, "Refills"))
+        # 0x06: LD_RETIRED
         self.addEvent(ProbeEvent(self,0x06, cpu, "RetiredLoads"))
+        # 0x07: ST_RETIRED
         self.addEvent(ProbeEvent(self,0x07, cpu, "RetiredStores"))
+        # 0x08: INST_RETIRED
         self.addEvent(ProbeEvent(self,0x08, cpu, "RetiredInsts"))
         # 0x09: EXC_TAKEN
         # 0x0A: EXC_RETURN
@@ -133,10 +139,14 @@ class ArmPMU(SimObject):
         # 0x0D: BR_IMMED_RETIRED
         # 0x0E: BR_RETURN_RETIRED
         # 0x0F: UNALIGEND_LDST_RETIRED
+        # 0x10: BR_MIS_PRED
         self.addEvent(ProbeEvent(self,0x10, bpred, "Misses"))
+        # 0x11: CPU_CYCLES
         self.addEvent(ProbeEvent(self, ARCH_EVENT_CORE_CYCLES, cpu,
                                  "ActiveCycles"))
+        # 0x12: BR_PRED
         self.addEvent(ProbeEvent(self,0x12, bpred, "Branches"))
+        # 0x13: MEM_ACCESS
         self.addEvent(ProbeEvent(self,0x13, cpu, "RetiredLoads",
                                  "RetiredStores"))
         # 0x14: L1I_CACHE
@@ -152,6 +162,7 @@ class ArmPMU(SimObject):
         # 0x1E: CHAIN
         # 0x1F: L1D_CACHE_ALLOCATE
         # 0x20: L2D_CACHE_ALLOCATE
+        # 0x21: BR_RETIRED
         self.addEvent(ProbeEvent(self,0x21, cpu, "RetiredBranches"))
         # 0x22: BR_MIS_PRED_RETIRED
         # 0x23: STALL_FRONTEND