From: lkcl <lkcl@web>
Date: Sat, 13 Feb 2021 22:23:38 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~183
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8d000d207e411767681b07ba8b03deacdcef638;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 6ef96a6cf..3cced7dd8 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -72,7 +72,7 @@ An autogenerator containing CSV files is available so that the task of creating
 
 * ISACaller: part done.  svp64 detected, PowerDecoder2 in use
 * power-gem5: TODO
-* TestIssuer: TODO
+* TestIssuer: part done.  svp64 detected, PowerDecoder2 in use.
 * Microwatt: TODO
 * python-based assembler-translator: 40% done (lkcl)
 * c++ macros: underway (jacob)
@@ -132,7 +132,7 @@ Due to the need for exceptions to occur in the middle, the loop should *not* be
 
 * ISACaller: DONE, first revision <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71>
 * power-gem5: TODO
-* TestIssuer: TODO
+* TestIssuer: part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
 * Microwatt: TODO
 
 ## Increasing register file sizes