From: lkcl Date: Wed, 17 May 2023 15:38:26 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8d66619cfbdf2270c8c5dbba01c997bcee28e9b;p=libreriscv.git --- diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index 747d2dbca..e104522da 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -47,14 +47,14 @@ The Mode table for Arithmetic and Logical operations, being bits 19-23 of SVP64 `RM`, is laid out as follows: -| 0-1 | 2 | 3 4 | description | -| ------ | --- |---------|-------------------------- | +| 0-1 | 2 | 3 4 | description | +| ------ | --- |---------|----------------------------------| | 0 0 | 0 | dz sz | simple mode | -| 0 0 | 1 | RG 0 | scalar reduce mode (mapreduce) | -| 0 0 | 1 | / 1 | reserved | -| 1 0 | N | dz sz | sat mode: N=0/1 u/s | +| 0 0 | 1 | RG 0 | scalar reduce mode (mapreduce) | +| 0 0 | 1 | / 1 | reserved | +| 1 0 | N | dz sz | sat mode: N=0/1 u/s | | VLi 1 | inv | CR-bit | Rc=1: ffirst CR sel | -| VLi 1 | inv | zz RC1 | Rc=0: ffirst z/nonz | +| VLi 1 | inv | zz RC1 | Rc=0: ffirst z/nonz | Fields: