From: M R Swami Reddy <MR.Swami.Reddy@nsc.com>
Date: Mon, 5 May 2008 10:25:20 +0000 (+0000)
Subject: Added 3 miscellaneous testcases like read32.ms uread16.ms hw-trap.ms.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8db345894127db4220b2b97275034e71bcbac37;p=binutils-gdb.git

Added 3 miscellaneous testcases like read32.ms uread16.ms hw-trap.ms.
---

diff --git a/sim/testsuite/sim/cr16/hw-trap.ms b/sim/testsuite/sim/cr16/hw-trap.ms
new file mode 100644
index 00000000000..8c8c185829c
--- /dev/null
+++ b/sim/testsuite/sim/cr16/hw-trap.ms
@@ -0,0 +1,10 @@
+# mach(): cr16
+
+	.include "testutils.inc"
+
+	start
+
+# perform trap
+	movw $0,r2
+	movw $0x410,r0
+	pass # the pass macro use the trap 8
diff --git a/sim/testsuite/sim/cr16/uread16.ms b/sim/testsuite/sim/cr16/uread16.ms
new file mode 100644
index 00000000000..54253b462e9
--- /dev/null
+++ b/sim/testsuite/sim/cr16/uread16.ms
@@ -0,0 +1,17 @@
+# mach: cr16
+
+	.include "testutils.inc"
+
+	start
+
+	.global read16
+read16:
+	loadw foo,r1
+	cmpw $42, r1
+	beq ok
+	fail
+ok:
+	pass
+
+foo:
+	.word 42
diff --git a/sim/testsuite/sim/cr16/uread32.ms b/sim/testsuite/sim/cr16/uread32.ms
new file mode 100644
index 00000000000..c2181e5c2ae
--- /dev/null
+++ b/sim/testsuite/sim/cr16/uread32.ms
@@ -0,0 +1,17 @@
+# mach: cr16
+
+	.include "testutils.inc"
+
+	start
+
+	.global read32
+read32:
+	loadd foo, (r1,r0)
+	cmpd $0x12345678, (r1,r0)
+	beq ok
+	fail
+ok:
+	pass
+
+foo:
+	.long 0x12345678