From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 8 Aug 2014 11:14:15 +0000 (+0800)
Subject: s6ddrphy: fix DFI interface data width computation
X-Git-Tag: 24jan2021_ls180~2682
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8db842538e5533d946015fdb7cd3e4cc360911d;p=litex.git

s6ddrphy: fix DFI interface data width computation
---

diff --git a/misoclib/sdramphy/s6ddrphy.py b/misoclib/sdramphy/s6ddrphy.py
index bdd9d6be..d4f9aa2f 100644
--- a/misoclib/sdramphy/s6ddrphy.py
+++ b/misoclib/sdramphy/s6ddrphy.py
@@ -42,7 +42,7 @@ class S6DDRPHY(Module):
 			write_latency=0
 		)
 
-		self.dfi = Interface(a, ba, nphases*d, nphases)
+		self.dfi = Interface(a, ba, self.phy_settings.dfi_d, nphases)
 		self.clk4x_wr_strb = Signal()
 		self.clk4x_rd_strb = Signal()