From: lkcl <lkcl@web>
Date: Wed, 22 Nov 2023 14:15:10 +0000 (+0000)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8dc1e324d78d17f03023bcd7c2a54b7f1c58c2d;p=libreriscv.git

---

diff --git a/nlnet_2023_svp64_riscv.mdwn b/nlnet_2023_svp64_riscv.mdwn
index eab1a50a2..537a47679 100644
--- a/nlnet_2023_svp64_riscv.mdwn
+++ b/nlnet_2023_svp64_riscv.mdwn
@@ -47,6 +47,19 @@ EUR $50,000.
 
 # Explain what the requested budget will be used for? 
 
+* Research and assessment of ARM7 and i486 (both on opencores.org)
+  as to their feasibility for applying Simple-V Prefixing
+* Assessment of the missing RISC-V instructions (only 96 where
+  Power ISA SFFS is 214) which are present in Power ISA 3.0
+* Implementation of the missing RISC-V instructions that bring
+  it up to par with Power ISA
+* Assessment of application of Simple-V Prefixing to SVP64,
+  modernising the work already done four years ago under
+  NLnet Grant 2019-10-012
+* Upgrading sv-spike which was completed four years ago with
+  an early prototype Simple-V Specification
+  https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv
+
 
 # Does the project have other funding sources, both past and present?