From: Chen Liqin Date: Mon, 1 Dec 2008 08:47:26 +0000 (+0000) Subject: score.h (IRA_COVER_CLASSES): Define. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8ddcbf9c9ccb37a62a542e07c92540180d6d7c6;p=gcc.git score.h (IRA_COVER_CLASSES): Define. 2008-12-01 Chen Liqin * config/score/score.h (IRA_COVER_CLASSES): Define. From-SVN: r142307 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5602b5a74d9..feb2d26d79b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2008-12-01 Chen Liqin + + * config/score/score.h (IRA_COVER_CLASSES): Define. + 2008-11-30 Eric Botcazou PR target/38287 diff --git a/gcc/config/score/score.h b/gcc/config/score/score.h index d9900a50214..7f09feb3894 100644 --- a/gcc/config/score/score.h +++ b/gcc/config/score/score.h @@ -438,6 +438,18 @@ enum reg_class also contains the register. */ #define REGNO_REG_CLASS(REGNO) score_reg_class (REGNO) +/* The following macro defines cover classes for Integrated Register + Allocator. Cover classes is a set of non-intersected register + classes covering all hard registers used for register allocation + purpose. Any move between two registers of a cover class should be + cheaper than load or store of the registers. The macro value is + array of register classes with LIM_REG_CLASSES used as the end + marker. */ +#define IRA_COVER_CLASSES \ +{ \ + G32_REGS, CE_REGS, SP_REGS, LIM_REG_CLASSES \ +} + /* A macro whose definition is the name of the class to which a valid base register must belong. A base register is one used in an address which is the register value plus a displacement. */