From: Jean-Paul Chaput Date: Mon, 30 Nov 2020 11:13:07 +0000 (+0100) Subject: Added experiments11, base for full chip with FlexLib & LibreSOCIO. X-Git-Tag: partial-core-ls180-gdsii~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e8f57087ee794b2565862e93f0176b6d25025dd0;p=soclayout.git Added experiments11, base for full chip with FlexLib & LibreSOCIO. --- diff --git a/experiments11/Makefile b/experiments11/Makefile new file mode 100755 index 0000000..b519e0a --- /dev/null +++ b/experiments11/Makefile @@ -0,0 +1,31 @@ + + LOGICAL_SYNTHESIS = Yosys + PHYSICAL_SYNTHESIS = Coriolis + DESIGN_KIT = FlexLib018 + YOSYS_FLATTEN = No + YOSYS_SET_TOP = Yes + CHIP = chip + CORE = ls180 + USE_CLOCKTREE = Yes + USE_DEBUG = No + USE_KITE = No + RM_CHIP = Yes +# VST_FLAGS = --vst-use-concat + + NETLISTS = ls180 +# NETLISTS = $(shell cat cells.lst) +# YOSYS_FLATTEN = $(shell cat flatten.lst) + + + + include ./mk/design-flow.mk + +chip_r.vst: ls180.vst + -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign)) + +chip_r.ap: chip_r.vst + +blif: ls180.blif +vst: ls180.vst +view: cgt-chip_r +layout: chip_r.ap diff --git a/experiments11/coriolis2/__init__.py b/experiments11/coriolis2/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/experiments11/coriolis2/katana.py b/experiments11/coriolis2/katana.py new file mode 100644 index 0000000..31b176f --- /dev/null +++ b/experiments11/coriolis2/katana.py @@ -0,0 +1,5 @@ +from Hurricane import DebugSession + +#DebugSession.addToTrace( katana.getCell().getNet( 'cu_issue_i' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'cu_wr_rel_o(2)' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'xer_so_ok' ) ) diff --git a/experiments11/coriolis2/settings.py b/experiments11/coriolis2/settings.py new file mode 100644 index 0000000..7a0737b --- /dev/null +++ b/experiments11/coriolis2/settings.py @@ -0,0 +1,46 @@ +# -*- Mode:Python -*- + +import os +import socket +import helpers + +NdaDirectory = None +if os.environ.has_key('NDA_TOP'): + NdaDirectory = os.environ['NDA_TOP'] +if not NdaDirectory: + hostname = socket.gethostname() + if hostname.startswith('lepka'): + NdaDirectory = '/dsk/l1/jpc/crypted/soc/techno' + if not os.path.isdir(NdaDirectory): + print '[ERROR] You forgot to mount the NDA encrypted directory, stupid!' + else: + NdaDirectory = '/users/soft/techno/techno' +helpers.setNdaTopDir( NdaDirectory ) + +import Cfg +from CRL import AllianceFramework +from helpers import overlay, l, u, n +from NDA.node180.tsmc_c018 import techno, FlexLib, LibreSOCIO + +techno.setup() +FlexLib.setup() +LibreSOCIO.setup() + +with overlay.CfgCache('', priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.etesian.graphics = 3 + cfg.conductor.stopLevel = 0 + cfg.conductor.maxPlaceIterations = 2 + cfg.conductor.useFixedAbHeight = False + env = AllianceFramework.get().getEnvironment() + env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' ) + env.setPOWER ('vdd') + env.setGROUND('vss') + +print( ' o Successfully run "<>/coriolis2/settings.py".' ) diff --git a/experiments11/doDesign.py b/experiments11/doDesign.py new file mode 100644 index 0000000..da1f5a2 --- /dev/null +++ b/experiments11/doDesign.py @@ -0,0 +1,75 @@ + +from __future__ import print_function + +import os +import json +import sys +import traceback +import CRL +import helpers +from helpers.io import ErrorMessage, WarningMessage +from helpers import trace, l, u, n +import plugins +from Hurricane import DbU +from plugins.alpha.block.configuration import IoPin, GaugeConf +from plugins.alpha.block.iospecs import IoSpecs +from plugins.alpha.block.block import Block +from plugins.alpha.core2chip.libresocio import CoreToChip +from plugins.alpha.chip.configuration import ChipConf +from plugins.alpha.chip.chip import Chip + + +af = CRL.AllianceFramework.get() + +def scriptMain (**kw): + """The mandatory function to be called by Coriolis CGT/Unicorn.""" + global af + rvalue = True + coreSize = 5200.0 + chipBorder = 2*214.0 + 10*13.0 + ioSpecs = IoSpecs() + ioSpecs.loadFromPinmux( './non_generated/litex_pinpads.json' ) + try: + #helpers.setTraceLevel( 550 ) + cell, editor = plugins.kwParseMain( **kw ) + cell = af.getCell( 'ls180', CRL.Catalog.State.Logical ) + if cell is None: + print( ErrorMessage( 2, 'doDesign.scriptMain(): Unable to load cell "{}".' \ + .format('ls180') )) + sys.exit(1) + if editor: editor.setCell( cell ) + ls180Conf = ChipConf( cell, ioPads=ioSpecs.ioPadsSpec ) + ls180Conf.cfg.etesian.bloat = 'nsxlib' + ls180Conf.cfg.etesian.uniformDensity = True + ls180Conf.cfg.etesian.aspectRatio = 1.0 + ls180Conf.cfg.etesian.spaceMargin = 0.05 + ls180Conf.cfg.anabatic.searchHalo = 2 + ls180Conf.cfg.anabatic.globalIterations = 20 + ls180Conf.cfg.anabatic.topRoutingLayer = 'METAL5' + ls180Conf.cfg.katana.hTracksReservedLocal = 6 + ls180Conf.cfg.katana.vTracksReservedLocal = 3 + ls180Conf.cfg.katana.hTracksReservedMin = 3 + ls180Conf.cfg.katana.vTracksReservedMin = 1 + ls180Conf.cfg.block.spareSide = u(200) + ls180Conf.editor = editor + ls180Conf.useSpares = True + ls180Conf.useClockTree = True + ls180Conf.useHFNS = False + ls180Conf.bColumns = 2 + ls180Conf.bRows = 2 + ls180Conf.chipConf.name = 'chip' + ls180Conf.chipConf.ioPadGauge = 'LibreSOCIO' + ls180Conf.coreSize = (u(coreSize), u(coreSize)) + ls180Conf.chipSize = (u(coreSize + chipBorder), u(coreSize + chipBorder)) + ls180ToChip = CoreToChip( ls180Conf ) + ls180ToChip.buildChip() + chipBuilder = Chip( ls180Conf ) + rvalue = chipBuilder.doPnR() + chipBuilder.save() + CRL.Gds.save( ls180Conf.chip ) + except Exception, e: + helpers.io.catch(e) + rvalue = False + sys.stdout.flush() + sys.stderr.flush() + return rvalue diff --git a/experiments11/non_generated/litex_pinpads.json b/experiments11/non_generated/litex_pinpads.json new file mode 100644 index 0000000..d08a8e9 --- /dev/null +++ b/experiments11/non_generated/litex_pinpads.json @@ -0,0 +1,1329 @@ +{ + "chip.clocks": { + "JTAG": "p_jtag_tck", + "MSPI": "p_spimaster_clk", + "MTWI": "p_i2c_scl", + "SD": "p_sdcard_clk", + "SDR": "p_sdram_clock" + }, + "chip.domains": { + "EINT": [ + "p_eint_0", + "p_eint_1", + "p_eint_2" + ], + "GPIO": [ + "p_gpio_8", + "p_gpio_9", + "p_gpio_10", + "p_gpio_11", + "p_gpio_12", + "p_gpio_13", + "p_gpio_14", + "p_gpio_15", + "p_gpio_0", + "p_gpio_1", + "p_gpio_2", + "p_gpio_3", + "p_gpio_4", + "p_gpio_5", + "p_gpio_6", + "p_gpio_7" + ], + "JTAG": [ + "p_jtag_tms", + "p_jtag_tdi", + "p_jtag_tdo", + "p_jtag_tck" + ], + "MSPI": [ + "p_spisdcard_clk", + "p_spisdcard_cs_n", + "p_spisdcard_mosi", + "p_spisdcard_miso", + "p_spimaster_clk", + "p_spimaster_cs_n", + "p_spimaster_mosi", + "p_spimaster_miso" + ], + "MTWI": [ + "p_i2c_sda", + "p_i2c_scl" + ], + "PWM": [ + "p_pwm0", + "p_pwm1" + ], + "SD": [ + "p_sdcard_cmd", + "p_sdcard_clk", + "p_sdcard_data0", + "p_sdcard_data1", + "p_sdcard_data2", + "p_sdcard_data3" + ], + "SDR": [ + "p_sdram_dm_0", + "p_sdram_dq_0", + "p_sdram_dq_1", + "p_sdram_dq_2", + "p_sdram_dq_3", + "p_sdram_dq_4", + "p_sdram_dq_5", + "p_sdram_dq_6", + "p_sdram_dq_7", + "p_sdram_a_0", + "p_sdram_a_1", + "p_sdram_a_2", + "p_sdram_a_3", + "p_sdram_a_4", + "p_sdram_a_5", + "p_sdram_a_6", + "p_sdram_a_7", + "p_sdram_a_8", + "p_sdram_a_9", + "p_sdram_ba_0", + "p_sdram_ba_1", + "p_sdram_clock", + "p_sdram_cke", + "p_sdram_ras_n", + "p_sdram_cas_n", + "p_sdram_we_n", + "p_sdram_cs_n", + "p_sdram_a_10", + "p_sdram_a_11", + "p_sdram_a_12", + "p_sdram_dm_1", + "p_sdram_dq_8", + "p_sdram_dq_9", + "p_sdram_dq_10", + "p_sdram_dq_11", + "p_sdram_dq_12", + "p_sdram_dq_13", + "p_sdram_dq_14", + "p_sdram_dq_15" + ], + "UART": [ + "p_uart_tx", + "p_uart_rx" + ] + }, + "chip.n_extpower": 3, + "chip.n_intpower": 5, + "pads.east": [ + "p_sdram_a_10", + "iopower_1", + "ioground_1", + "p_sdram_a_11", + "p_sdram_a_12", + "p_sdram_dm_1", + "p_sdram_dq_8", + "p_sdram_dq_9", + "p_sdram_dq_10", + "p_sdram_dq_11", + "p_sdram_dq_12", + "p_sdram_dq_13", + "p_sdram_dq_14", + "p_sdram_dq_15", + "power_1", + "ground_1", + "p_gpio_8", + "p_gpio_9", + "p_gpio_10", + "p_gpio_11", + "p_gpio_12", + "p_gpio_13", + "p_gpio_14", + "p_gpio_15", + "nc_0", + "p_jtag_tms", + "p_jtag_tdi", + "p_jtag_tdo", + "p_jtag_tck", + "nc_1", + "nc_2", + "nc_3" + ], + "pads.instances": [ + [ + "iopower_0", + "iovdd" + ], + [ + "ioground_0", + "iovss" + ], + [ + "p_sdram_dm_0", + "sdram_dm(0)", + "sdram_dm(0)", + "+" + ], + [ + "p_sdram_dq_0", + "sdram_dq_0", + "sdram_dq_o(0)", + "sdram_dq_i(0)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_1", + "sdram_dq_1", + "sdram_dq_o(1)", + "sdram_dq_i(1)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_2", + "sdram_dq_2", + "sdram_dq_o(2)", + "sdram_dq_i(2)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_3", + "sdram_dq_3", + "sdram_dq_o(3)", + "sdram_dq_i(3)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_4", + "sdram_dq_4", + "sdram_dq_o(4)", + "sdram_dq_i(4)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_5", + "sdram_dq_5", + "sdram_dq_o(5)", + "sdram_dq_i(5)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_6", + "sdram_dq_6", + "sdram_dq_o(6)", + "sdram_dq_i(6)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_7", + "sdram_dq_7", + "sdram_dq_o(7)", + "sdram_dq_i(7)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_a_0", + "sdram_a(0)", + "sdram_a(0)", + "+" + ], + [ + "p_sdram_a_1", + "sdram_a(1)", + "sdram_a(1)", + "+" + ], + [ + "p_sdram_a_2", + "sdram_a(2)", + "sdram_a(2)", + "+" + ], + [ + "p_sdram_a_3", + "sdram_a(3)", + "sdram_a(3)", + "+" + ], + [ + "p_sdram_a_4", + "sdram_a(4)", + "sdram_a(4)", + "+" + ], + [ + "p_sdram_a_5", + "sdram_a(5)", + "sdram_a(5)", + "+" + ], + [ + "p_sdram_a_6", + "sdram_a(6)", + "sdram_a(6)", + "+" + ], + [ + "p_sdram_a_7", + "sdram_a(7)", + "sdram_a(7)", + "+" + ], + [ + "p_sdram_a_8", + "sdram_a(8)", + "sdram_a(8)", + "+" + ], + [ + "p_sdram_a_9", + "sdram_a(9)", + "sdram_a(9)", + "+" + ], + [ + "p_sdram_ba_0", + "sdram_ba(0)", + "sdram_ba(0)", + "+" + ], + [ + "p_sdram_ba_1", + "sdram_ba(1)", + "sdram_ba(1)", + "+" + ], + [ + "p_sdram_clock", + "sdram_clock", + "sdram_clock", + "+" + ], + [ + "p_sdram_cke", + "sdram_cke", + "sdram_cke", + "+" + ], + [ + "p_sdram_ras_n", + "sdram_ras_n", + "sdram_ras_n", + "+" + ], + [ + "p_sdram_cas_n", + "sdram_cas_n", + "sdram_cas_n", + "+" + ], + [ + "p_sdram_we_n", + "sdram_we_n", + "sdram_we_n", + "+" + ], + [ + "p_sdram_cs_n", + "sdram_cs_n", + "sdram_cs_n", + "+" + ], + [ + "power_0", + "vdd" + ], + [ + "ground_0", + "vss" + ], + [ + "iopower_1", + "iovdd" + ], + [ + "ioground_1", + "iovdd" + ], + [ + "p_sdram_a_10", + "sdram_a(10)", + "sdram_a(10)", + "+" + ], + [ + "p_sdram_a_11", + "sdram_a(11)", + "sdram_a(11)", + "+" + ], + [ + "p_sdram_a_12", + "sdram_a(12)", + "sdram_a(12)", + "+" + ], + [ + "p_sdram_dm_1", + "sdram_dm(1)", + "sdram_dm(1)", + "*" + ], + [ + "p_sdram_dq_8", + "sdram_dq_8", + "sdram_dq_o(8)", + "sdram_dq_i(8)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_9", + "sdram_dq_9", + "sdram_dq_o(9)", + "sdram_dq_i(9)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_10", + "sdram_dq_10", + "sdram_dq_o(10)", + "sdram_dq_i(10)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_11", + "sdram_dq_11", + "sdram_dq_o(11)", + "sdram_dq_i(11)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_12", + "sdram_dq_12", + "sdram_dq_o(12)", + "sdram_dq_i(12)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_13", + "sdram_dq_13", + "sdram_dq_o(13)", + "sdram_dq_i(13)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_14", + "sdram_dq_14", + "sdram_dq_o(14)", + "sdram_dq_i(14)", + "sdram_dq_oe", + "*" + ], + [ + "p_sdram_dq_15", + "sdram_dq_15", + "sdram_dq_o(15)", + "sdram_dq_i(15)", + "sdram_dq_oe", + "*" + ], + [ + "power_1", + "vdd" + ], + [ + "ground_1", + "vss" + ], + [ + "p_gpio_8", + "gpio_8", + "gpio_o(8)", + "gpio_i(8)", + "gpio_oe(8)", + "*" + ], + [ + "p_gpio_9", + "gpio_9", + "gpio_o(9)", + "gpio_i(9)", + "gpio_oe(9)", + "*" + ], + [ + "p_gpio_10", + "gpio_10", + "gpio_o(10)", + "gpio_i(10)", + "gpio_oe(10)", + "*" + ], + [ + "p_gpio_11", + "gpio_11", + "gpio_o(11)", + "gpio_i(11)", + "gpio_oe(11)", + "*" + ], + [ + "p_gpio_12", + "gpio_12", + "gpio_o(12)", + "gpio_i(12)", + "gpio_oe(12)", + "*" + ], + [ + "p_gpio_13", + "gpio_13", + "gpio_o(13)", + "gpio_i(13)", + "gpio_oe(13)", + "*" + ], + [ + "p_gpio_14", + "gpio_14", + "gpio_o(14)", + "gpio_i(14)", + "gpio_oe(14)", + "*" + ], + [ + "p_gpio_15", + "gpio_15", + "gpio_o(15)", + "gpio_i(15)", + "gpio_oe(15)", + "*" + ], + [ + "p_jtag_tms", + "jtag_tms", + "jtag_tms", + "-" + ], + [ + "p_jtag_tdi", + "jtag_tdi", + "jtag_tdi", + "-" + ], + [ + "p_jtag_tdo", + "jtag_tdo", + "jtag_tdo", + "+" + ], + [ + "p_jtag_tck", + "jtag_tck", + "jtag_tck", + "+" + ], + [ + "power_2", + "vdd" + ], + [ + "ground_2", + "vss" + ], + [ + "p_i2c_sda", + "i2c_sda", + "i2c_sda_o", + "i2c_sda_i", + "i2c_sda_oe", + "*" + ], + [ + "p_i2c_scl", + "i2c_scl", + "i2c_scl", + "+" + ], + [ + "p_spisdcard_clk", + "spisdcard_clk", + "spisdcard_clk", + "+" + ], + [ + "p_spisdcard_cs_n", + "spisdcard_cs_n", + "spisdcard_cs_n", + "+" + ], + [ + "p_spisdcard_mosi", + "spisdcard_mosi", + "spisdcard_mosi", + "+" + ], + [ + "p_spisdcard_miso", + "spisdcard_miso", + "spisdcard_miso", + "-" + ], + [ + "p_uart_tx", + "uart_tx", + "uart_tx", + "+" + ], + [ + "p_uart_rx", + "uart_rx", + "uart_rx", + "-" + ], + [ + "p_gpio_0", + "gpio_0", + "gpio_o(0)", + "gpio_i(0)", + "gpio_oe(0)", + "*" + ], + [ + "p_gpio_1", + "gpio_1", + "gpio_o(1)", + "gpio_i(1)", + "gpio_oe(1)", + "*" + ], + [ + "p_gpio_2", + "gpio_2", + "gpio_o(2)", + "gpio_i(2)", + "gpio_oe(2)", + "*" + ], + [ + "p_gpio_3", + "gpio_3", + "gpio_o(3)", + "gpio_i(3)", + "gpio_oe(3)", + "*" + ], + [ + "p_gpio_4", + "gpio_4", + "gpio_o(4)", + "gpio_i(4)", + "gpio_oe(4)", + "*" + ], + [ + "p_gpio_5", + "gpio_5", + "gpio_o(5)", + "gpio_i(5)", + "gpio_oe(5)", + "*" + ], + [ + "p_gpio_6", + "gpio_6", + "gpio_o(6)", + "gpio_i(6)", + "gpio_oe(6)", + "*" + ], + [ + "p_gpio_7", + "gpio_7", + "gpio_o(7)", + "gpio_i(7)", + "gpio_oe(7)", + "*" + ], + [ + "p_sys_clk", + "sys_clk", + "sys_clk", + "-" + ], + [ + "sys_rst", + "sys_rst", + "sys_rst", + "-" + ], + [ + "p_sys_pll_18_o", + "sys_pll_18_o", + "sys_pll_18_o", + "+" + ], + [ + "p_sys_clksel_0", + "sys_clksel_i(0)", + "sys_clksel_i(0)", + "-" + ], + [ + "p_sys_clksel_1", + "sys_clksel_i(1)", + "sys_clksel_i(1)", + "-" + ], + [ + "p_sys_pll_lck_o", + "sys_pll_lck_o", + "sys_pll_lck_o", + "+" + ], + [ + "power_3", + "vdd" + ], + [ + "ground_3", + "vss" + ], + [ + "iopower_2", + "iovdd" + ], + [ + "ioground_2", + "iovss" + ], + [ + "p_pwm0", + "pwm(0)", + "pwm(0)", + "+" + ], + [ + "p_pwm1", + "pwm(1)", + "pwm(1)", + "+" + ], + [ + "p_eint_0", + "eint(0)", + "eint(0)", + "-" + ], + [ + "p_eint_1", + "eint(1)", + "eint(1)", + "-" + ], + [ + "p_eint_2", + "eint(2)", + "eint(2)", + "-" + ], + [ + "p_spimaster_clk", + "spimaster_clk", + "spimaster_clk", + "+" + ], + [ + "p_spimaster_cs_n", + "spimaster_cs_n", + "spimaster_cs_n", + "+" + ], + [ + "p_spimaster_mosi", + "spimaster_mosi", + "spimaster_mosi", + "+" + ], + [ + "p_spimaster_miso", + "spimaster_miso", + "spimaster_miso", + "-" + ], + [ + "p_sdcard_cmd", + "sdcard_cmd", + "sdcard_cmd_o", + "sdcard_cmd_i", + "sdcard_cmd_oe", + "*" + ], + [ + "p_sdcard_clk", + "sdcard_clk", + "sdcard_clk", + "+" + ], + [ + "p_sdcard_data0", + "sdcard_data0", + "sdcard_data_o(0)", + "sdcard_data_i(0)", + "sdcard_data_oe", + "*" + ], + [ + "p_sdcard_data1", + "sdcard_data1", + "sdcard_data_o(1)", + "sdcard_data_i(1)", + "sdcard_data_oe", + "*" + ], + [ + "p_sdcard_data2", + "sdcard_data2", + "sdcard_data_o(2)", + "sdcard_data_i(2)", + "sdcard_data_oe", + "*" + ], + [ + "p_sdcard_data3", + "sdcard_data3", + "sdcard_data_o(3)", + "sdcard_data_i(3)", + "sdcard_data_oe", + "*" + ], + [ + "power_4", + "vdd" + ], + [ + "ground_4", + "vss" + ], + [ + "nc_0", + "nc(0)", + "nc(0)", + "-" + ], + [ + "nc_1", + "nc(1)", + "nc(1)", + "-" + ], + [ + "nc_2", + "nc(2)", + "nc(2)", + "-" + ], + [ + "nc_3", + "nc(3)", + "nc(3)", + "-" + ], + [ + "nc_4", + "nc(4)", + "nc(4)", + "-" + ], + [ + "nc_5", + "nc(5)", + "nc(5)", + "-" + ], + [ + "nc_6", + "nc(6)", + "nc(6)", + "-" + ], + [ + "nc_7", + "nc(7)", + "nc(7)", + "-" + ], + [ + "nc_8", + "nc(8)", + "nc(8)", + "-" + ], + [ + "nc_9", + "nc(9)", + "nc(9)", + "-" + ], + [ + "nc_10", + "nc(10)", + "nc(10)", + "-" + ], + [ + "nc_11", + "nc(11)", + "nc(11)", + "-" + ], + [ + "nc_12", + "nc(12)", + "nc(12)", + "-" + ], + [ + "nc_13", + "nc(13)", + "nc(13)", + "-" + ], + [ + "nc_14", + "nc(14)", + "nc(14)", + "-" + ], + [ + "nc_15", + "nc(15)", + "nc(15)", + "-" + ], + [ + "nc_16", + "nc(16)", + "nc(16)", + "-" + ], + [ + "nc_17", + "nc(17)", + "nc(17)", + "-" + ], + [ + "nc_18", + "nc(18)", + "nc(18)", + "-" + ], + [ + "nc_19", + "nc(19)", + "nc(19)", + "-" + ], + [ + "nc_20", + "nc(20)", + "nc(20)", + "-" + ], + [ + "nc_21", + "nc(21)", + "nc(21)", + "-" + ], + [ + "nc_22", + "nc(22)", + "nc(22)", + "-" + ], + [ + "nc_23", + "nc(23)", + "nc(23)", + "-" + ] + ], + "pads.north": [ + "p_sdram_dm_0", + "iopower_0", + "ioground_0", + "p_sdram_dq_0", + "p_sdram_dq_1", + "p_sdram_dq_2", + "p_sdram_dq_3", + "p_sdram_dq_4", + "p_sdram_dq_5", + "p_sdram_dq_6", + "p_sdram_dq_7", + "p_sdram_a_0", + "p_sdram_a_1", + "p_sdram_a_2", + "p_sdram_a_3", + "p_sdram_a_4", + "p_sdram_a_5", + "p_sdram_a_6", + "p_sdram_a_7", + "p_sdram_a_8", + "p_sdram_a_9", + "p_sdram_ba_0", + "p_sdram_ba_1", + "p_sdram_clock", + "p_sdram_cke", + "p_sdram_ras_n", + "p_sdram_cas_n", + "p_sdram_we_n", + "p_sdram_cs_n", + "power_0", + "ground_0", + "nc_17" + ], + "pads.south": [ + "p_i2c_sda", + "power_2", + "ground_2", + "p_i2c_scl", + "nc_18", + "nc_19", + "nc_20", + "nc_21", + "p_spisdcard_clk", + "p_spisdcard_cs_n", + "p_spisdcard_mosi", + "p_spisdcard_miso", + "nc_22", + "p_uart_tx", + "p_uart_rx", + "p_gpio_0", + "p_gpio_1", + "p_gpio_2", + "p_gpio_3", + "p_gpio_4", + "p_gpio_5", + "p_gpio_6", + "p_gpio_7", + "p_sys_clk", + "sys_rst", + "nc_23", + "p_sys_pll_18_o", + "p_sys_clksel_0", + "p_sys_clksel_1", + "power_3", + "ground_3", + "p_sys_pll_lck_o" + ], + "pads.west": [ + "p_pwm0", + "iopower_2", + "ioground_2", + "p_pwm1", + "p_eint_0", + "p_eint_1", + "p_eint_2", + "p_spimaster_clk", + "p_spimaster_cs_n", + "p_spimaster_mosi", + "p_spimaster_miso", + "p_sdcard_cmd", + "p_sdcard_clk", + "p_sdcard_data0", + "p_sdcard_data1", + "p_sdcard_data2", + "p_sdcard_data3", + "nc_4", + "nc_5", + "nc_6", + "nc_7", + "nc_8", + "nc_9", + "nc_10", + "nc_11", + "nc_12", + "nc_13", + "nc_14", + "nc_15", + "power_4", + "ground_4", + "nc_16" + ], + "pins.map": { + "eint_0": "p_eint_0", + "eint_1": "p_eint_1", + "eint_2": "p_eint_2", + "gpioe_e10": "p_gpio_10", + "gpioe_e11": "p_gpio_11", + "gpioe_e12": "p_gpio_12", + "gpioe_e13": "p_gpio_13", + "gpioe_e14": "p_gpio_14", + "gpioe_e15": "p_gpio_15", + "gpioe_e8": "p_gpio_8", + "gpioe_e9": "p_gpio_9", + "gpios_s0": "p_gpio_0", + "gpios_s1": "p_gpio_1", + "gpios_s2": "p_gpio_2", + "gpios_s3": "p_gpio_3", + "gpios_s4": "p_gpio_4", + "gpios_s5": "p_gpio_5", + "gpios_s6": "p_gpio_6", + "gpios_s7": "p_gpio_7", + "jtag_tck": "p_jtag_tck", + "jtag_tdi": "p_jtag_tdi", + "jtag_tdo": "p_jtag_tdo", + "jtag_tms": "p_jtag_tms", + "mspi0_ck": "p_spisdcard_clk", + "mspi0_miso": "p_spisdcard_miso", + "mspi0_mosi": "p_spisdcard_mosi", + "mspi0_nss": "p_spisdcard_cs_n", + "mspi1_ck": "p_spimaster_clk", + "mspi1_miso": "p_spimaster_miso", + "mspi1_mosi": "p_spimaster_mosi", + "mspi1_nss": "p_spimaster_cs_n", + "mtwi_scl": "p_i2c_scl", + "mtwi_sda": "p_i2c_sda", + "nc_0": "nc_0", + "nc_1": "nc_1", + "nc_10": "nc_10", + "nc_11": "nc_11", + "nc_12": "nc_12", + "nc_13": "nc_13", + "nc_14": "nc_14", + "nc_15": "nc_15", + "nc_16": "nc_16", + "nc_17": "nc_17", + "nc_18": "nc_18", + "nc_19": "nc_19", + "nc_2": "nc_2", + "nc_20": "nc_20", + "nc_21": "nc_21", + "nc_22": "nc_22", + "nc_23": "nc_23", + "nc_3": "nc_3", + "nc_4": "nc_4", + "nc_5": "nc_5", + "nc_6": "nc_6", + "nc_7": "nc_7", + "nc_8": "nc_8", + "nc_9": "nc_9", + "pwm0_out": "p_pwm0", + "pwm1_out": "p_pwm1", + "sd0_clk": "p_sdcard_clk", + "sd0_cmd": "p_sdcard_cmd", + "sd0_d0": "p_sdcard_data0", + "sd0_d1": "p_sdcard_data1", + "sd0_d2": "p_sdcard_data2", + "sd0_d3": "p_sdcard_data3", + "sdr_ad0": "p_sdram_a_0", + "sdr_ad1": "p_sdram_a_1", + "sdr_ad10": "p_sdram_a_10", + "sdr_ad11": "p_sdram_a_11", + "sdr_ad12": "p_sdram_a_12", + "sdr_ad2": "p_sdram_a_2", + "sdr_ad3": "p_sdram_a_3", + "sdr_ad4": "p_sdram_a_4", + "sdr_ad5": "p_sdram_a_5", + "sdr_ad6": "p_sdram_a_6", + "sdr_ad7": "p_sdram_a_7", + "sdr_ad8": "p_sdram_a_8", + "sdr_ad9": "p_sdram_a_9", + "sdr_ba0": "p_sdram_ba_0", + "sdr_ba1": "p_sdram_ba_1", + "sdr_casn": "p_sdram_cas_n", + "sdr_cke": "p_sdram_cke", + "sdr_clk": "p_sdram_clock", + "sdr_csn0": "p_sdram_cs_n", + "sdr_d0": "p_sdram_dq_0", + "sdr_d1": "p_sdram_dq_1", + "sdr_d10": "p_sdram_dq_10", + "sdr_d11": "p_sdram_dq_11", + "sdr_d12": "p_sdram_dq_12", + "sdr_d13": "p_sdram_dq_13", + "sdr_d14": "p_sdram_dq_14", + "sdr_d15": "p_sdram_dq_15", + "sdr_d2": "p_sdram_dq_2", + "sdr_d3": "p_sdram_dq_3", + "sdr_d4": "p_sdram_dq_4", + "sdr_d5": "p_sdram_dq_5", + "sdr_d6": "p_sdram_dq_6", + "sdr_d7": "p_sdram_dq_7", + "sdr_d8": "p_sdram_dq_8", + "sdr_d9": "p_sdram_dq_9", + "sdr_dqm0": "p_sdram_dm_0", + "sdr_dqm1": "p_sdram_dm_1", + "sdr_rasn": "p_sdram_ras_n", + "sdr_wen": "p_sdram_we_n", + "sys_clk": "p_sys_clk", + "sys_csel0": "p_sys_clksel_0", + "sys_csel1": "p_sys_clksel_1", + "sys_pllock": "p_sys_pll_lck_o", + "sys_pllout": "p_sys_pll_18_o", + "uart0_rx": "p_uart_rx", + "uart0_tx": "p_uart_tx", + "vdde_0": "ioground_0", + "vdde_1": "ioground_1", + "vdde_2": "ioground_2", + "vddi_0": "ground_0", + "vddi_1": "ground_1", + "vddi_2": "ground_2", + "vddi_3": "ground_3", + "vddi_4": "ground_4", + "vsse_0": "iopower_0", + "vsse_1": "iopower_1", + "vsse_2": "iopower_2", + "vssi_0": "power_0", + "vssi_1": "power_1", + "vssi_2": "power_2", + "vssi_3": "power_3", + "vssi_4": "power_4" + }, + "pins.specs": { + "EINT:": [ + "0-", + "1-", + "2-" + ], + "GPIO:": [ + "E8*", + "E9*", + "E10*", + "E11*", + "E12*", + "E13*", + "E14*", + "E15*", + "S0*", + "S1*", + "S2*", + "S3*", + "S4*", + "S5*", + "S6*", + "S7*" + ], + "JTAG:": [ + "TMS-", + "TDI-", + "TDO+", + "TCK+" + ], + "MSPI:0": [ + "CK+", + "NSS+", + "MOSI+", + "MISO-" + ], + "MSPI:1": [ + "CK+", + "NSS+", + "MOSI+", + "MISO-" + ], + "MTWI:": [ + "SDA*", + "SCL+" + ], + "PWM:": [ + "0+", + "1+" + ], + "SD:0": [ + "CMD*", + "CLK+", + "D0*", + "D1*", + "D2*", + "D3*" + ], + "SDR:": [ + "DQM0+", + "D0*", + "D1*", + "D2*", + "D3*", + "D4*", + "D5*", + "D6*", + "D7*", + "AD0+", + "AD1+", + "AD2+", + "AD3+", + "AD4+", + "AD5+", + "AD6+", + "AD7+", + "AD8+", + "AD9+", + "BA0+", + "BA1+", + "CLK+", + "CKE+", + "RASn+", + "CASn+", + "WEn+", + "CSn0+", + "AD10+", + "AD11+", + "AD12+", + "DQM1*", + "D8*", + "D9*", + "D10*", + "D11*", + "D12*", + "D13*", + "D14*", + "D15*" + ], + "SYS:": [ + "CLK-", + "RST-", + "PLLCLK-", + "PLLOUT+", + "CSEL0-", + "CSEL1-", + "PLLOCK+" + ], + "UART:0": [ + "TX+", + "RX-" + ], + "VDD:E": [ + "0-", + "1-", + "2-" + ], + "VDD:I": [ + "0-", + "1-", + "2-", + "3-", + "4-" + ], + "VSS:E": [ + "0-", + "1-", + "2-" + ], + "VSS:I": [ + "0-", + "1-", + "2-", + "3-", + "4-" + ] + } +} diff --git a/experiments11/non_generated/ls180.il b/experiments11/non_generated/ls180.il new file mode 100644 index 0000000..ab4601e --- /dev/null +++ b/experiments11/non_generated/ls180.il @@ -0,0 +1,151270 @@ +# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) +autoidx 3702 +attribute \src "libresoc.v:5.1-277.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" +attribute \generator "nMigen" +module \_fsm + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $0\fsm_state$next[3:0]$25 + attribute \src "libresoc.v:91.3-92.35" + wire width 4 $0\fsm_state[3:0] + attribute \src "libresoc.v:6.7-6.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:97.3-124.6" + wire $0\isdr$next[0:0]$21 + attribute \src "libresoc.v:93.3-94.25" + wire $0\isdr[0:0] + attribute \src "libresoc.v:240.3-267.6" + wire $0\isir$next[0:0]$38 + attribute \src "libresoc.v:95.3-96.25" + wire $0\isir[0:0] + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $10\fsm_state$next[3:0]$35 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $11\fsm_state$next[3:0]$36 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $1\fsm_state$next[3:0]$26 + attribute \src "libresoc.v:46.13-46.29" + wire width 4 $1\fsm_state[3:0] + attribute \src "libresoc.v:97.3-124.6" + wire $1\isdr$next[0:0]$22 + attribute \src "libresoc.v:51.7-51.18" + wire $1\isdr[0:0] + attribute \src "libresoc.v:240.3-267.6" + wire $1\isir$next[0:0]$39 + attribute \src "libresoc.v:56.7-56.18" + wire $1\isir[0:0] + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $2\fsm_state$next[3:0]$27 + attribute \src "libresoc.v:97.3-124.6" + wire $2\isdr$next[0:0]$23 + attribute \src "libresoc.v:240.3-267.6" + wire $2\isir$next[0:0]$40 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $3\fsm_state$next[3:0]$28 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $4\fsm_state$next[3:0]$29 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $5\fsm_state$next[3:0]$30 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $6\fsm_state$next[3:0]$31 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $7\fsm_state$next[3:0]$32 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $8\fsm_state$next[3:0]$33 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $9\fsm_state$next[3:0]$34 + attribute \src "libresoc.v:75.17-75.110" + wire $eq$libresoc.v:75$1_Y + attribute \src "libresoc.v:76.18-76.111" + wire $eq$libresoc.v:76$2_Y + attribute \src "libresoc.v:77.18-77.111" + wire $eq$libresoc.v:77$3_Y + attribute \src "libresoc.v:78.18-78.111" + wire $eq$libresoc.v:78$4_Y + attribute \src "libresoc.v:79.18-79.111" + wire $eq$libresoc.v:79$5_Y + attribute \src "libresoc.v:80.17-80.108" + wire $eq$libresoc.v:80$6_Y + attribute \src "libresoc.v:81.18-81.111" + wire $eq$libresoc.v:81$7_Y + attribute \src "libresoc.v:82.18-82.111" + wire $eq$libresoc.v:82$8_Y + attribute \src "libresoc.v:83.18-83.111" + wire $eq$libresoc.v:83$9_Y + attribute \src "libresoc.v:84.18-84.111" + wire $eq$libresoc.v:84$10_Y + attribute \src "libresoc.v:85.18-85.111" + wire $eq$libresoc.v:85$11_Y + attribute \src "libresoc.v:86.18-86.111" + wire $eq$libresoc.v:86$12_Y + attribute \src "libresoc.v:87.18-87.112" + wire $eq$libresoc.v:87$13_Y + attribute \src "libresoc.v:88.17-88.108" + wire $eq$libresoc.v:88$14_Y + attribute \src "libresoc.v:89.17-89.108" + wire $eq$libresoc.v:89$15_Y + attribute \src "libresoc.v:90.17-90.108" + wire $eq$libresoc.v:90$16_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 10 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire output 1 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + wire width 4 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + wire width 4 \fsm_state$next + attribute \src "libresoc.v:6.7-6.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire output 11 \isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \isdr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire output 4 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire \isir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" + wire \local_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 8 \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 6 \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire output 7 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire output 5 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" + wire \rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire output 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire output 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:75$1 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:75$1_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:76$2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:76$2_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + cell $eq $eq$libresoc.v:77$3 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:77$3_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + cell $eq $eq$libresoc.v:78$4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:78$4_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:79$5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:79$5_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" + cell $eq $eq$libresoc.v:80$6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:80$6_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:81$7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:81$7_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + cell $eq $eq$libresoc.v:82$8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:82$8_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + cell $eq $eq$libresoc.v:83$9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:83$9_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + cell $eq $eq$libresoc.v:84$10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:84$10_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + cell $eq $eq$libresoc.v:85$11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:85$11_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + cell $eq $eq$libresoc.v:86$12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:86$12_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + cell $eq $eq$libresoc.v:87$13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:87$13_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + cell $eq $eq$libresoc.v:88$14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'11 + connect \Y $eq$libresoc.v:88$14_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + cell $eq $eq$libresoc.v:89$15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 3'101 + connect \Y $eq$libresoc.v:89$15_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + cell $eq $eq$libresoc.v:90$16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 4'1000 + connect \Y $eq$libresoc.v:90$16_Y + end + attribute \src "libresoc.v:125.3-239.6" + process $proc$libresoc.v:125$24 + assign { } { } + assign { } { } + assign $0\fsm_state$next[3:0]$25 $1\fsm_state$next[3:0]$26 + attribute \src "libresoc.v:126.5-126.29" + switch \initial + attribute \src "libresoc.v:126.9-126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $2\fsm_state$next[3:0]$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[3:0]$27 4'0001 + case + assign $2\fsm_state$next[3:0]$27 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $3\fsm_state$next[3:0]$28 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[3:0]$28 4'0010 + case + assign $3\fsm_state$next[3:0]$28 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $4\fsm_state$next[3:0]$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[3:0]$29 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fsm_state$next[3:0]$29 4'0100 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $5\fsm_state$next[3:0]$30 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[3:0]$30 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\fsm_state$next[3:0]$30 4'0000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $6\fsm_state$next[3:0]$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fsm_state$next[3:0]$31 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\fsm_state$next[3:0]$31 4'0110 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $7\fsm_state$next[3:0]$32 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\fsm_state$next[3:0]$32 4'0110 + case + assign $7\fsm_state$next[3:0]$32 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $8\fsm_state$next[3:0]$33 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\fsm_state$next[3:0]$33 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\fsm_state$next[3:0]$33 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $9\fsm_state$next[3:0]$34 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\fsm_state$next[3:0]$34 4'1001 + case + assign $9\fsm_state$next[3:0]$34 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $10\fsm_state$next[3:0]$35 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fsm_state$next[3:0]$35 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $10\fsm_state$next[3:0]$35 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $11\fsm_state$next[3:0]$36 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\fsm_state$next[3:0]$36 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $11\fsm_state$next[3:0]$36 4'0010 + end + case + assign $1\fsm_state$next[3:0]$26 \fsm_state + end + sync always + update \fsm_state$next $0\fsm_state$next[3:0]$25 + end + attribute \src "libresoc.v:240.3-267.6" + process $proc$libresoc.v:240$37 + assign { } { } + assign { } { } + assign $0\isir$next[0:0]$38 $1\isir$next[0:0]$39 + attribute \src "libresoc.v:241.5-241.29" + switch \initial + attribute \src "libresoc.v:241.9-241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isir$next[0:0]$39 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isir$next[0:0]$39 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\isir$next[0:0]$39 $2\isir$next[0:0]$40 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isir$next[0:0]$40 1'1 + case + assign $2\isir$next[0:0]$40 \isir + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isir$next[0:0]$39 1'0 + case + assign $1\isir$next[0:0]$39 \isir + end + sync always + update \isir$next $0\isir$next[0:0]$38 + end + attribute \src "libresoc.v:46.13-46.29" + process $proc$libresoc.v:46$42 + assign { } { } + assign $1\fsm_state[3:0] 4'0000 + sync always + sync init + update \fsm_state $1\fsm_state[3:0] + end + attribute \src "libresoc.v:51.7-51.18" + process $proc$libresoc.v:51$43 + assign { } { } + assign $1\isdr[0:0] 1'0 + sync always + sync init + update \isdr $1\isdr[0:0] + end + attribute \src "libresoc.v:56.7-56.18" + process $proc$libresoc.v:56$44 + assign { } { } + assign $1\isir[0:0] 1'0 + sync always + sync init + update \isir $1\isir[0:0] + end + attribute \src "libresoc.v:6.7-6.20" + process $proc$libresoc.v:6$41 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:91.3-92.35" + process $proc$libresoc.v:91$17 + assign { } { } + assign $0\fsm_state[3:0] \fsm_state$next + sync posedge \local_clk + update \fsm_state $0\fsm_state[3:0] + end + attribute \src "libresoc.v:93.3-94.25" + process $proc$libresoc.v:93$18 + assign { } { } + assign $0\isdr[0:0] \isdr$next + sync posedge \local_clk + update \isdr $0\isdr[0:0] + end + attribute \src "libresoc.v:95.3-96.25" + process $proc$libresoc.v:95$19 + assign { } { } + assign $0\isir[0:0] \isir$next + sync posedge \local_clk + update \isir $0\isir[0:0] + end + attribute \src "libresoc.v:97.3-124.6" + process $proc$libresoc.v:97$20 + assign { } { } + assign { } { } + assign $0\isdr$next[0:0]$21 $1\isdr$next[0:0]$22 + attribute \src "libresoc.v:98.5-98.29" + switch \initial + attribute \src "libresoc.v:98.9-98.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isdr$next[0:0]$22 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isdr$next[0:0]$22 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\isdr$next[0:0]$22 $2\isdr$next[0:0]$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isdr$next[0:0]$23 1'1 + case + assign $2\isdr$next[0:0]$23 \isdr + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isdr$next[0:0]$22 1'0 + case + assign $1\isdr$next[0:0]$22 \isdr + end + sync always + update \isdr$next $0\isdr$next[0:0]$21 + end + connect \$9 $eq$libresoc.v:75$1_Y + connect \$11 $eq$libresoc.v:76$2_Y + connect \$13 $eq$libresoc.v:77$3_Y + connect \$15 $eq$libresoc.v:78$4_Y + connect \$17 $eq$libresoc.v:79$5_Y + connect \$1 $eq$libresoc.v:80$6_Y + connect \$19 $eq$libresoc.v:81$7_Y + connect \$21 $eq$libresoc.v:82$8_Y + connect \$23 $eq$libresoc.v:83$9_Y + connect \$25 $eq$libresoc.v:84$10_Y + connect \$27 $eq$libresoc.v:85$11_Y + connect \$29 $eq$libresoc.v:86$12_Y + connect \$31 $eq$libresoc.v:87$13_Y + connect \$3 $eq$libresoc.v:88$14_Y + connect \$5 $eq$libresoc.v:89$15_Y + connect \$7 $eq$libresoc.v:90$16_Y + connect \update \$7 + connect \shift \$5 + connect \capture \$3 + connect \rst \$1 + connect \local_clk \TAP_bus__tck + connect \negjtag_rst \rst + connect \negjtag_clk \TAP_bus__tck + connect \posjtag_rst \rst + connect \posjtag_clk \TAP_bus__tck +end +attribute \src "libresoc.v:281.1-353.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" +attribute \generator "nMigen" +module \_idblock + attribute \src "libresoc.v:326.3-346.6" + wire width 32 $0\TAP_id_sr$next[31:0]$50 + attribute \src "libresoc.v:324.3-325.35" + wire width 32 $0\TAP_id_sr[31:0] + attribute \src "libresoc.v:282.7-282.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:326.3-346.6" + wire width 32 $1\TAP_id_sr$next[31:0]$51 + attribute \src "libresoc.v:292.14-292.31" + wire width 32 $1\TAP_id_sr[31:0] + attribute \src "libresoc.v:326.3-346.6" + wire width 32 $2\TAP_id_sr$next[31:0]$52 + attribute \src "libresoc.v:321.17-321.110" + wire $and$libresoc.v:321$45_Y + attribute \src "libresoc.v:322.17-322.108" + wire $and$libresoc.v:322$46_Y + attribute \src "libresoc.v:323.17-323.109" + wire $and$libresoc.v:323$47_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 5 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" + wire width 32 \TAP_id_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" + wire width 32 \TAP_id_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire output 6 \TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" + wire \_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" + wire \_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" + wire \_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" + wire \_tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" + wire \_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 2 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire input 1 \id_bypass + attribute \src "libresoc.v:282.7-282.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire input 9 \select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 3 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 4 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + cell $and $and$libresoc.v:321$45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \capture + connect \Y $and$libresoc.v:321$45_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + cell $and $and$libresoc.v:322$46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \shift + connect \Y $and$libresoc.v:322$46_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + cell $and $and$libresoc.v:323$47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \update + connect \Y $and$libresoc.v:323$47_Y + end + attribute \src "libresoc.v:282.7-282.20" + process $proc$libresoc.v:282$53 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:292.14-292.31" + process $proc$libresoc.v:292$54 + assign { } { } + assign $1\TAP_id_sr[31:0] 0 + sync always + sync init + update \TAP_id_sr $1\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:324.3-325.35" + process $proc$libresoc.v:324$48 + assign { } { } + assign $0\TAP_id_sr[31:0] \TAP_id_sr$next + sync posedge \posjtag_clk + update \TAP_id_sr $0\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:326.3-346.6" + process $proc$libresoc.v:326$49 + assign { } { } + assign { } { } + assign $0\TAP_id_sr$next[31:0]$50 $1\TAP_id_sr$next[31:0]$51 + attribute \src "libresoc.v:327.5-327.29" + switch \initial + attribute \src "libresoc.v:327.9-327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" + switch { \_shift \_capture } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\TAP_id_sr$next[31:0]$51 6399 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\TAP_id_sr$next[31:0]$51 $2\TAP_id_sr$next[31:0]$52 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" + switch \_bypass + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\TAP_id_sr$next[31:0]$52 [31:1] \TAP_id_sr [31:1] + assign $2\TAP_id_sr$next[31:0]$52 [0] \_tdi + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\TAP_id_sr$next[31:0]$52 { \_tdi \TAP_id_sr [31:1] } + end + case + assign $1\TAP_id_sr$next[31:0]$51 \TAP_id_sr + end + sync always + update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$50 + end + connect \$1 $and$libresoc.v:321$45_Y + connect \$3 $and$libresoc.v:322$46_Y + connect \$5 $and$libresoc.v:323$47_Y + connect \TAP_id_tdo \TAP_id_sr [0] + connect \_bypass \id_bypass + connect \_update \$5 + connect \_shift \$3 + connect \_capture \$1 + connect \_tdi \TAP_bus__tdi +end +attribute \src "libresoc.v:357.1-441.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" +attribute \generator "nMigen" +module \_irblock + attribute \src "libresoc.v:358.7-358.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:419.3-439.6" + wire width 4 $0\ir$next[3:0]$67 + attribute \src "libresoc.v:402.3-403.21" + wire width 4 $0\ir[3:0] + attribute \src "libresoc.v:406.3-418.6" + wire width 4 $0\shift_ir$next[3:0]$64 + attribute \src "libresoc.v:404.3-405.33" + wire width 4 $0\shift_ir[3:0] + attribute \src "libresoc.v:419.3-439.6" + wire width 4 $1\ir$next[3:0]$68 + attribute \src "libresoc.v:377.13-377.22" + wire width 4 $1\ir[3:0] + attribute \src "libresoc.v:406.3-418.6" + wire width 4 $1\shift_ir$next[3:0]$65 + attribute \src "libresoc.v:389.13-389.28" + wire width 4 $1\shift_ir[3:0] + attribute \src "libresoc.v:419.3-439.6" + wire width 4 $2\ir$next[3:0]$69 + attribute \src "libresoc.v:396.17-396.103" + wire $and$libresoc.v:396$55_Y + attribute \src "libresoc.v:397.18-397.105" + wire $and$libresoc.v:397$56_Y + attribute \src "libresoc.v:398.17-398.105" + wire $and$libresoc.v:398$57_Y + attribute \src "libresoc.v:399.17-399.103" + wire $and$libresoc.v:399$58_Y + attribute \src "libresoc.v:400.17-400.104" + wire $and$libresoc.v:400$59_Y + attribute \src "libresoc.v:401.17-401.105" + wire $and$libresoc.v:401$60_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 4 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 1 \capture + attribute \src "libresoc.v:358.7-358.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 output 9 \ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 \ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire input 5 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" + wire width 4 \shift_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" + wire width 4 \shift_ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire output 6 \tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:396$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:396$55_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:397$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:397$56_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:398$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:398$57_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:399$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:399$58_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:400$59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:400$59_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:401$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:401$60_Y + end + attribute \src "libresoc.v:358.7-358.20" + process $proc$libresoc.v:358$70 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:377.13-377.22" + process $proc$libresoc.v:377$71 + assign { } { } + assign $1\ir[3:0] 4'0001 + sync always + sync init + update \ir $1\ir[3:0] + end + attribute \src "libresoc.v:389.13-389.28" + process $proc$libresoc.v:389$72 + assign { } { } + assign $1\shift_ir[3:0] 4'0000 + sync always + sync init + update \shift_ir $1\shift_ir[3:0] + end + attribute \src "libresoc.v:402.3-403.21" + process $proc$libresoc.v:402$61 + assign { } { } + assign $0\ir[3:0] \ir$next + sync posedge \posjtag_clk + update \ir $0\ir[3:0] + end + attribute \src "libresoc.v:404.3-405.33" + process $proc$libresoc.v:404$62 + assign { } { } + assign $0\shift_ir[3:0] \shift_ir$next + sync posedge \posjtag_clk + update \shift_ir $0\shift_ir[3:0] + end + attribute \src "libresoc.v:406.3-418.6" + process $proc$libresoc.v:406$63 + assign { } { } + assign { } { } + assign $0\shift_ir$next[3:0]$64 $1\shift_ir$next[3:0]$65 + attribute \src "libresoc.v:407.5-407.29" + switch \initial + attribute \src "libresoc.v:407.9-407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" + switch { \$5 \$3 \$1 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\shift_ir$next[3:0]$65 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\shift_ir$next[3:0]$65 { \TAP_bus__tdi \shift_ir [3:1] } + case + assign $1\shift_ir$next[3:0]$65 \shift_ir + end + sync always + update \shift_ir$next $0\shift_ir$next[3:0]$64 + end + attribute \src "libresoc.v:419.3-439.6" + process $proc$libresoc.v:419$66 + assign { } { } + assign { } { } + assign { } { } + assign $0\ir$next[3:0]$67 $2\ir$next[3:0]$69 + attribute \src "libresoc.v:420.5-420.29" + switch \initial + attribute \src "libresoc.v:420.9-420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" + switch { \$11 \$9 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\ir$next[3:0]$68 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\ir$next[3:0]$68 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\ir$next[3:0]$68 \shift_ir + case + assign $1\ir$next[3:0]$68 \ir + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ir$next[3:0]$69 4'0001 + case + assign $2\ir$next[3:0]$69 $1\ir$next[3:0]$68 + end + sync always + update \ir$next $0\ir$next[3:0]$67 + end + connect \$9 $and$libresoc.v:396$55_Y + connect \$11 $and$libresoc.v:397$56_Y + connect \$1 $and$libresoc.v:398$57_Y + connect \$3 $and$libresoc.v:399$58_Y + connect \$5 $and$libresoc.v:400$59_Y + connect \$7 $and$libresoc.v:401$60_Y + connect \tdo \ir [0] +end +attribute \src "libresoc.v:445.1-469.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core" +attribute \generator "nMigen" +module \core + attribute \src "libresoc.v:446.7-446.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:460.3-468.6" + wire $0\x$next[0:0]$76 + attribute \src "libresoc.v:458.3-459.19" + wire $0\x[0:0] + attribute \src "libresoc.v:460.3-468.6" + wire $1\x$next[0:0]$77 + attribute \src "libresoc.v:454.7-454.15" + wire $1\x[0:0] + attribute \src "libresoc.v:457.17-457.89" + wire $not$libresoc.v:457$73_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:126" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 2 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:446.7-446.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:125" + wire \x + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:125" + wire \x$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:126" + cell $not $not$libresoc.v:457$73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x + connect \Y $not$libresoc.v:457$73_Y + end + attribute \src "libresoc.v:446.7-446.20" + process $proc$libresoc.v:446$78 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:454.7-454.15" + process $proc$libresoc.v:454$79 + assign { } { } + assign $1\x[0:0] 1'0 + sync always + sync init + update \x $1\x[0:0] + end + attribute \src "libresoc.v:458.3-459.19" + process $proc$libresoc.v:458$74 + assign { } { } + assign $0\x[0:0] \x$next + sync posedge \coresync_clk + update \x $0\x[0:0] + end + attribute \src "libresoc.v:460.3-468.6" + process $proc$libresoc.v:460$75 + assign { } { } + assign { } { } + assign $0\x$next[0:0]$76 $1\x$next[0:0]$77 + attribute \src "libresoc.v:461.5-461.29" + switch \initial + attribute \src "libresoc.v:461.9-461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x$next[0:0]$77 1'0 + case + assign $1\x$next[0:0]$77 \$1 + end + sync always + update \x$next $0\x$next[0:0]$76 + end + connect \$1 $not$libresoc.v:457$73_Y +end +attribute \src "libresoc.v:473.1-1187.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dbg" +attribute \generator "nMigen" +module \dbg + attribute \src "libresoc.v:1003.3-1012.6" + wire $0\d_cr_req[0:0] + attribute \src "libresoc.v:810.3-819.6" + wire $0\d_gpr_req[0:0] + attribute \src "libresoc.v:1013.3-1022.6" + wire $0\d_xer_req[0:0] + attribute \src "libresoc.v:792.3-809.6" + wire $0\dmi_ack_o[0:0] + attribute \src "libresoc.v:1023.3-1053.6" + wire width 64 $0\dmi_dout[63:0] + attribute \src "libresoc.v:994.3-1002.6" + wire $0\dmi_read_log_data$next[0:0]$193 + attribute \src "libresoc.v:770.3-771.51" + wire $0\dmi_read_log_data[0:0] + attribute \src "libresoc.v:985.3-993.6" + wire $0\dmi_read_log_data_1$next[0:0]$190 + attribute \src "libresoc.v:772.3-773.55" + wire $0\dmi_read_log_data_1[0:0] + attribute \src "libresoc.v:820.3-828.6" + wire $0\dmi_req_i_1$next[0:0]$156 + attribute \src "libresoc.v:782.3-783.39" + wire $0\dmi_req_i_1[0:0] + attribute \src "libresoc.v:1144.3-1177.6" + wire $0\do_dmi_log_rd$next[0:0]$220 + attribute \src "libresoc.v:784.3-785.43" + wire $0\do_dmi_log_rd[0:0] + attribute \src "libresoc.v:1114.3-1143.6" + wire $0\do_icreset$next[0:0]$213 + attribute \src "libresoc.v:786.3-787.37" + wire $0\do_icreset[0:0] + attribute \src "libresoc.v:1084.3-1113.6" + wire $0\do_reset$next[0:0]$206 + attribute \src "libresoc.v:788.3-789.33" + wire $0\do_reset[0:0] + attribute \src "libresoc.v:1054.3-1083.6" + wire $0\do_step$next[0:0]$199 + attribute \src "libresoc.v:790.3-791.31" + wire $0\do_step[0:0] + attribute \src "libresoc.v:923.3-950.6" + wire width 7 $0\gspr_index$next[6:0]$178 + attribute \src "libresoc.v:776.3-777.37" + wire width 7 $0\gspr_index[6:0] + attribute \src "libresoc.v:474.7-474.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:951.3-984.6" + wire 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"/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" + wire input 13 \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 20 \d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 19 \d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 18 \d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 17 \d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire width 7 output 15 \d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 16 \d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 14 \d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire input 23 \d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 input 22 \d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire output 21 \d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire output 6 \dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 input 2 \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 input 5 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 output 7 \dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire input 3 \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire input 4 \dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" 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$eq$libresoc.v:747$119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:753$125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:753$125_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:754$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:754$126_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:755$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:755$127_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:761$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:761$133_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:762$134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:762$134_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:763$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:763$135_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:768$140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:768$140_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:769$141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:769$141_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:710$82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:710$82_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:712$84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:712$84_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + cell $not $not$libresoc.v:721$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \do_step + connect \Y $not$libresoc.v:721$93_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:725$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:725$97_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:728$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:728$100_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:733$105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:733$105_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:735$107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:735$107_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:737$109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:737$109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:741$113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:741$113_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:743$115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:743$115_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:749$121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:749$121_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:751$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:751$123_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:756$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:756$128_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:758$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:758$130_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:759$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:759$131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:764$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:764$136_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:766$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:766$138_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" + cell $pos $pos$libresoc.v:726$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } + connect \Y $pos$libresoc.v:726$98_Y + end + attribute \src "libresoc.v:1003.3-1012.6" + process $proc$libresoc.v:1003$195 + assign { } { } + assign { } { } + assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] + attribute \src "libresoc.v:1004.5-1004.29" + switch \initial + attribute \src "libresoc.v:1004.9-1004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\d_cr_req[0:0] \dmi_req_i + case + assign $1\d_cr_req[0:0] 1'0 + end + sync always + update \d_cr_req $0\d_cr_req[0:0] + end + attribute \src "libresoc.v:1013.3-1022.6" + process $proc$libresoc.v:1013$196 + assign { } { } + assign { } { } + assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] + attribute \src "libresoc.v:1014.5-1014.29" + switch \initial + attribute \src "libresoc.v:1014.9-1014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\d_xer_req[0:0] \dmi_req_i + case + assign $1\d_xer_req[0:0] 1'0 + end + sync always + update \d_xer_req $0\d_xer_req[0:0] + end + attribute \src "libresoc.v:1023.3-1053.6" + process $proc$libresoc.v:1023$197 + assign { } { } + assign { } { } + assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] + attribute \src "libresoc.v:1024.5-1024.29" + switch \initial + attribute \src "libresoc.v:1024.9-1024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dmi_dout[63:0] \stat_reg + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_msr + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_dout[63:0] \d_gpr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dmi_dout[63:0] \log_dmi_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_dout[63:0] \d_cr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_dout[63:0] \d_xer_data + case + assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi_dout $0\dmi_dout[63:0] + end + attribute \src "libresoc.v:1054.3-1083.6" + process $proc$libresoc.v:1054$198 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_step$next[0:0]$199 $5\do_step$next[0:0]$204 + attribute \src "libresoc.v:1055.5-1055.29" + switch \initial + attribute \src "libresoc.v:1055.9-1055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$9 \$5 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_step$next[0:0]$200 $2\do_step$next[0:0]$201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_step$next[0:0]$201 $3\do_step$next[0:0]$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$15 \$13 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_step$next[0:0]$202 $4\do_step$next[0:0]$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_step$next[0:0]$203 1'1 + case + assign $4\do_step$next[0:0]$203 1'0 + end + case + assign $3\do_step$next[0:0]$202 1'0 + end + case + assign $2\do_step$next[0:0]$201 1'0 + end + case + assign $1\do_step$next[0:0]$200 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_step$next[0:0]$204 1'0 + case + assign $5\do_step$next[0:0]$204 $1\do_step$next[0:0]$200 + end + sync always + update \do_step$next $0\do_step$next[0:0]$199 + end + attribute \src "libresoc.v:1084.3-1113.6" + process $proc$libresoc.v:1084$205 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_reset$next[0:0]$206 $5\do_reset$next[0:0]$211 + attribute \src "libresoc.v:1085.5-1085.29" + switch \initial + attribute \src "libresoc.v:1085.9-1085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$23 \$19 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_reset$next[0:0]$207 $2\do_reset$next[0:0]$208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_reset$next[0:0]$208 $3\do_reset$next[0:0]$209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$29 \$27 \$25 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_reset$next[0:0]$209 $4\do_reset$next[0:0]$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_reset$next[0:0]$210 1'1 + case + assign $4\do_reset$next[0:0]$210 1'0 + end + case + assign $3\do_reset$next[0:0]$209 1'0 + end + case + assign $2\do_reset$next[0:0]$208 1'0 + end + case + assign $1\do_reset$next[0:0]$207 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_reset$next[0:0]$211 1'0 + case + assign $5\do_reset$next[0:0]$211 $1\do_reset$next[0:0]$207 + end + sync always + update \do_reset$next $0\do_reset$next[0:0]$206 + end + attribute \src "libresoc.v:1114.3-1143.6" + process $proc$libresoc.v:1114$212 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_icreset$next[0:0]$213 $5\do_icreset$next[0:0]$218 + attribute \src "libresoc.v:1115.5-1115.29" + switch \initial + attribute \src "libresoc.v:1115.9-1115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$37 \$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_icreset$next[0:0]$214 $2\do_icreset$next[0:0]$215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_icreset$next[0:0]$215 $3\do_icreset$next[0:0]$216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$43 \$41 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_icreset$next[0:0]$216 $4\do_icreset$next[0:0]$217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" + switch \dmi_din [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_icreset$next[0:0]$217 1'1 + case + assign $4\do_icreset$next[0:0]$217 1'0 + end + case + assign $3\do_icreset$next[0:0]$216 1'0 + end + case + assign $2\do_icreset$next[0:0]$215 1'0 + end + case + assign $1\do_icreset$next[0:0]$214 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_icreset$next[0:0]$218 1'0 + case + assign $5\do_icreset$next[0:0]$218 $1\do_icreset$next[0:0]$214 + end + sync always + update \do_icreset$next $0\do_icreset$next[0:0]$213 + end + attribute \src "libresoc.v:1144.3-1177.6" + process $proc$libresoc.v:1144$219 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_dmi_log_rd$next[0:0]$220 $4\do_dmi_log_rd$next[0:0]$224 + attribute \src "libresoc.v:1145.5-1145.29" + switch \initial + attribute \src "libresoc.v:1145.9-1145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$51 \$47 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$221 $2\do_dmi_log_rd$next[0:0]$222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_dmi_log_rd$next[0:0]$222 $3\do_dmi_log_rd$next[0:0]$223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$57 \$55 \$53 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\do_dmi_log_rd$next[0:0]$223 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\do_dmi_log_rd$next[0:0]$223 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\do_dmi_log_rd$next[0:0]$223 1'1 + case + assign $3\do_dmi_log_rd$next[0:0]$223 1'0 + end + case + assign $2\do_dmi_log_rd$next[0:0]$222 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$221 1'1 + case + assign $1\do_dmi_log_rd$next[0:0]$221 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_dmi_log_rd$next[0:0]$224 1'0 + case + assign $4\do_dmi_log_rd$next[0:0]$224 $1\do_dmi_log_rd$next[0:0]$221 + end + sync always + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$220 + end + attribute \src "libresoc.v:474.7-474.20" + process $proc$libresoc.v:474$225 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:647.7-647.31" + process $proc$libresoc.v:647$226 + assign { } { } + assign $1\dmi_read_log_data[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data $1\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:651.7-651.33" + process $proc$libresoc.v:651$227 + assign { } { } + assign $1\dmi_read_log_data_1[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:657.7-657.25" + process $proc$libresoc.v:657$228 + assign { } { } + assign $1\dmi_req_i_1[0:0] 1'0 + sync always + sync init + update \dmi_req_i_1 $1\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:663.7-663.27" + process $proc$libresoc.v:663$229 + assign { } { } + assign $1\do_dmi_log_rd[0:0] 1'0 + sync always + sync init + update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:667.7-667.24" + process $proc$libresoc.v:667$230 + assign { } { } + assign $1\do_icreset[0:0] 1'0 + sync always + sync init + update \do_icreset $1\do_icreset[0:0] + end + attribute \src "libresoc.v:671.7-671.22" + process $proc$libresoc.v:671$231 + assign { } { } + assign $1\do_reset[0:0] 1'0 + sync always + sync init + update \do_reset $1\do_reset[0:0] + end + attribute \src "libresoc.v:675.7-675.21" + process $proc$libresoc.v:675$232 + assign { } { } + assign $1\do_step[0:0] 1'0 + sync always + sync init + update \do_step $1\do_step[0:0] + end + attribute \src "libresoc.v:679.13-679.31" + process $proc$libresoc.v:679$233 + assign { } { } + assign $1\gspr_index[6:0] 7'0000000 + sync always + sync init + update \gspr_index $1\gspr_index[6:0] + end + attribute \src "libresoc.v:685.14-685.34" + process $proc$libresoc.v:685$234 + assign { } { } + assign $1\log_dmi_addr[31:0] 0 + sync always + sync init + update \log_dmi_addr $1\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:697.7-697.22" + process $proc$libresoc.v:697$235 + assign { } { } + assign $1\stopping[0:0] 1'0 + sync always + sync init + update \stopping $1\stopping[0:0] + end + attribute \src "libresoc.v:703.7-703.24" + process $proc$libresoc.v:703$236 + assign { } { } + assign $1\terminated[0:0] 1'0 + sync always + sync init + update \terminated $1\terminated[0:0] + end + attribute \src "libresoc.v:770.3-771.51" + process $proc$libresoc.v:770$142 + assign { } { } + assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next + sync posedge \clk + update \dmi_read_log_data $0\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:772.3-773.55" + process $proc$libresoc.v:772$143 + assign { } { } + assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next + sync posedge \clk + update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:774.3-775.41" + process $proc$libresoc.v:774$144 + assign { } { } + assign $0\log_dmi_addr[31:0] \log_dmi_addr$next + sync posedge \clk + update \log_dmi_addr $0\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:776.3-777.37" + process $proc$libresoc.v:776$145 + assign { } { } + assign $0\gspr_index[6:0] \gspr_index$next + sync posedge \clk + update \gspr_index $0\gspr_index[6:0] + end + attribute \src "libresoc.v:778.3-779.33" + process $proc$libresoc.v:778$146 + assign { } { } + assign $0\stopping[0:0] \stopping$next + sync posedge \clk + update \stopping $0\stopping[0:0] + end + attribute \src "libresoc.v:780.3-781.37" + process $proc$libresoc.v:780$147 + assign { } { } + assign $0\terminated[0:0] \terminated$next + sync posedge \clk + update \terminated $0\terminated[0:0] + end + attribute \src "libresoc.v:782.3-783.39" + process $proc$libresoc.v:782$148 + assign { } { } + assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next + sync posedge \clk + update \dmi_req_i_1 $0\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:784.3-785.43" + process $proc$libresoc.v:784$149 + assign { } { } + assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next + sync posedge \clk + update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:786.3-787.37" + process $proc$libresoc.v:786$150 + assign { } { } + assign $0\do_icreset[0:0] \do_icreset$next + sync posedge \clk + update \do_icreset $0\do_icreset[0:0] + end + attribute \src "libresoc.v:788.3-789.33" + process $proc$libresoc.v:788$151 + assign { } { } + assign $0\do_reset[0:0] \do_reset$next + sync posedge \clk + update \do_reset $0\do_reset[0:0] + end + attribute \src "libresoc.v:790.3-791.31" + process $proc$libresoc.v:790$152 + assign { } { } + assign $0\do_step[0:0] \do_step$next + sync posedge \clk + update \do_step $0\do_step[0:0] + end + attribute \src "libresoc.v:792.3-809.6" + process $proc$libresoc.v:792$153 + assign { } { } + assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:793.5-793.29" + switch \initial + attribute \src "libresoc.v:793.9-793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_gpr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_cr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_xer_ack + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi_ack_o[0:0] \dmi_req_i + end + sync always + update \dmi_ack_o $0\dmi_ack_o[0:0] + end + attribute \src "libresoc.v:810.3-819.6" + process $proc$libresoc.v:810$154 + assign { } { } + assign { } { } + assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] + attribute \src "libresoc.v:811.5-811.29" + switch \initial + attribute \src "libresoc.v:811.9-811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\d_gpr_req[0:0] \dmi_req_i + case + assign $1\d_gpr_req[0:0] 1'0 + end + sync always + update \d_gpr_req $0\d_gpr_req[0:0] + end + attribute \src "libresoc.v:820.3-828.6" + process $proc$libresoc.v:820$155 + assign { } { } + assign { } { } + assign $0\dmi_req_i_1$next[0:0]$156 $1\dmi_req_i_1$next[0:0]$157 + attribute \src "libresoc.v:821.5-821.29" + switch \initial + attribute \src "libresoc.v:821.9-821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_req_i_1$next[0:0]$157 1'0 + case + assign $1\dmi_req_i_1$next[0:0]$157 \dmi_req_i + end + sync always + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$156 + end + attribute \src "libresoc.v:829.3-878.6" + process $proc$libresoc.v:829$158 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\terminated$next[0:0]$159 $8\terminated$next[0:0]$167 + attribute \src "libresoc.v:830.5-830.29" + switch \initial + attribute \src "libresoc.v:830.9-830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$65 \$61 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\terminated$next[0:0]$160 $2\terminated$next[0:0]$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\terminated$next[0:0]$161 $3\terminated$next[0:0]$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$71 \$69 \$67 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign { } { } + assign $3\terminated$next[0:0]$162 $6\terminated$next[0:0]$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\terminated$next[0:0]$163 1'0 + case + assign $4\terminated$next[0:0]$163 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\terminated$next[0:0]$164 1'0 + case + assign $5\terminated$next[0:0]$164 $4\terminated$next[0:0]$163 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\terminated$next[0:0]$165 1'0 + case + assign $6\terminated$next[0:0]$165 $5\terminated$next[0:0]$164 + end + case + assign $3\terminated$next[0:0]$162 \terminated + end + case + assign $2\terminated$next[0:0]$161 \terminated + end + case + assign $1\terminated$next[0:0]$160 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\terminated$next[0:0]$166 1'1 + case + assign $7\terminated$next[0:0]$166 $1\terminated$next[0:0]$160 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\terminated$next[0:0]$167 1'0 + case + assign $8\terminated$next[0:0]$167 $7\terminated$next[0:0]$166 + end + sync always + update \terminated$next $0\terminated$next[0:0]$159 + end + attribute \src "libresoc.v:879.3-922.6" + process $proc$libresoc.v:879$168 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\stopping$next[0:0]$169 $7\stopping$next[0:0]$176 + attribute \src "libresoc.v:880.5-880.29" + switch \initial + attribute \src "libresoc.v:880.9-880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$79 \$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\stopping$next[0:0]$170 $2\stopping$next[0:0]$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\stopping$next[0:0]$171 $3\stopping$next[0:0]$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$85 \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign $3\stopping$next[0:0]$172 $5\stopping$next[0:0]$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + switch \dmi_din [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\stopping$next[0:0]$173 1'1 + case + assign $4\stopping$next[0:0]$173 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\stopping$next[0:0]$174 1'0 + case + assign $5\stopping$next[0:0]$174 $4\stopping$next[0:0]$173 + end + case + assign $3\stopping$next[0:0]$172 \stopping + end + case + assign $2\stopping$next[0:0]$171 \stopping + end + case + assign $1\stopping$next[0:0]$170 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\stopping$next[0:0]$175 1'1 + case + assign $6\stopping$next[0:0]$175 $1\stopping$next[0:0]$170 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\stopping$next[0:0]$176 1'0 + case + assign $7\stopping$next[0:0]$176 $6\stopping$next[0:0]$175 + end + sync always + update \stopping$next $0\stopping$next[0:0]$169 + end + attribute \src "libresoc.v:923.3-950.6" + process $proc$libresoc.v:923$177 + assign { } { } + assign { } { } + assign { } { } + assign $0\gspr_index$next[6:0]$178 $4\gspr_index$next[6:0]$182 + attribute \src "libresoc.v:924.5-924.29" + switch \initial + attribute \src "libresoc.v:924.9-924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$93 \$89 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\gspr_index$next[6:0]$179 $2\gspr_index$next[6:0]$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\gspr_index$next[6:0]$180 $3\gspr_index$next[6:0]$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$99 \$97 \$95 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\gspr_index$next[6:0]$181 \gspr_index + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $3\gspr_index$next[6:0]$181 \dmi_din [6:0] + case + assign $3\gspr_index$next[6:0]$181 \gspr_index + end + case + assign $2\gspr_index$next[6:0]$180 \gspr_index + end + case + assign $1\gspr_index$next[6:0]$179 \gspr_index + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\gspr_index$next[6:0]$182 7'0000000 + case + assign $4\gspr_index$next[6:0]$182 $1\gspr_index$next[6:0]$179 + end + sync always + update \gspr_index$next $0\gspr_index$next[6:0]$178 + end + attribute \src "libresoc.v:951.3-984.6" + process $proc$libresoc.v:951$183 + assign { } { } + assign { } { } + assign { } { } + assign $0\log_dmi_addr$next[31:0]$184 $4\log_dmi_addr$next[31:0]$188 + attribute \src "libresoc.v:952.5-952.29" + switch \initial + attribute \src "libresoc.v:952.9-952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$107 \$103 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\log_dmi_addr$next[31:0]$185 $2\log_dmi_addr$next[31:0]$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\log_dmi_addr$next[31:0]$186 $3\log_dmi_addr$next[31:0]$187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$113 \$111 \$109 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\log_dmi_addr$next[31:0]$187 \dmi_din [31:0] + case + assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr + end + case + assign $2\log_dmi_addr$next[31:0]$186 \log_dmi_addr + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $1\log_dmi_addr$next[31:0]$185 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$185 [1:0] \$115 [1:0] + case + assign $1\log_dmi_addr$next[31:0]$185 \log_dmi_addr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\log_dmi_addr$next[31:0]$188 0 + case + assign $4\log_dmi_addr$next[31:0]$188 $1\log_dmi_addr$next[31:0]$185 + end + sync always + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$184 + end + attribute \src "libresoc.v:985.3-993.6" + process $proc$libresoc.v:985$189 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data_1$next[0:0]$190 $1\dmi_read_log_data_1$next[0:0]$191 + attribute \src "libresoc.v:986.5-986.29" + switch \initial + attribute \src "libresoc.v:986.9-986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data_1$next[0:0]$191 1'0 + case + assign $1\dmi_read_log_data_1$next[0:0]$191 \dmi_read_log_data + end + sync always + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$190 + end + attribute \src "libresoc.v:994.3-1002.6" + process $proc$libresoc.v:994$192 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data$next[0:0]$193 $1\dmi_read_log_data$next[0:0]$194 + attribute \src "libresoc.v:995.5-995.29" + switch \initial + attribute \src "libresoc.v:995.9-995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data$next[0:0]$194 1'0 + case + assign $1\dmi_read_log_data$next[0:0]$194 \$120 + end + sync always + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$193 + end + connect \$9 $and$libresoc.v:708$80_Y + connect \$99 $eq$libresoc.v:709$81_Y + connect \$101 $not$libresoc.v:710$82_Y + connect \$103 $and$libresoc.v:711$83_Y + connect \$105 $not$libresoc.v:712$84_Y + connect \$107 $and$libresoc.v:713$85_Y + connect \$109 $eq$libresoc.v:714$86_Y + connect \$111 $eq$libresoc.v:715$87_Y + connect \$113 $eq$libresoc.v:716$88_Y + connect \$116 $add$libresoc.v:717$89_Y + connect \$118 $eq$libresoc.v:718$90_Y + connect \$11 $eq$libresoc.v:719$91_Y + connect \$120 $and$libresoc.v:720$92_Y + connect \$122 $not$libresoc.v:721$93_Y + connect \$124 $and$libresoc.v:722$94_Y + connect \$13 $eq$libresoc.v:723$95_Y + connect \$15 $eq$libresoc.v:724$96_Y + connect \$17 $not$libresoc.v:725$97_Y + connect \$1 $pos$libresoc.v:726$98_Y + connect \$19 $and$libresoc.v:727$99_Y + connect \$21 $not$libresoc.v:728$100_Y + connect \$23 $and$libresoc.v:729$101_Y + connect \$25 $eq$libresoc.v:730$102_Y + connect \$27 $eq$libresoc.v:731$103_Y + connect \$29 $eq$libresoc.v:732$104_Y + connect \$31 $not$libresoc.v:733$105_Y + connect \$33 $and$libresoc.v:734$106_Y + connect \$35 $not$libresoc.v:735$107_Y + connect \$37 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 27 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 11 \LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 23 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 20 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 21 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 18 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 19 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 22 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 output 31 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 output 34 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 output 35 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 32 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 33 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 16 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 36 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec19_dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec19_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec19_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec19_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 \dec19_dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \dec19_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec19_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec19_dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec19_dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec19_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec19_dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec19_dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec19_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec19_dec19_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec19_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec30_dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec30_dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute 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attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 \form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 7 \function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 12 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 13 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \in3_sel + attribute \src "libresoc.v:1192.7-1192.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 6 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 32 \opcode_switch$1 + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 15 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 1 \raw_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 3 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 17 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:3249$237 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:3249$237_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3250.9-3276.4" + cell \dec19 \dec19 + connect \dec19_asmcode \dec19_dec19_asmcode + connect \dec19_br \dec19_dec19_br + connect \dec19_cr_in \dec19_dec19_cr_in + connect \dec19_cr_out \dec19_dec19_cr_out + connect \dec19_cry_in \dec19_dec19_cry_in + connect \dec19_cry_out \dec19_dec19_cry_out + connect \dec19_form \dec19_dec19_form + connect \dec19_function_unit \dec19_dec19_function_unit + connect \dec19_in1_sel \dec19_dec19_in1_sel + connect \dec19_in2_sel \dec19_dec19_in2_sel + connect \dec19_in3_sel \dec19_dec19_in3_sel + connect \dec19_internal_op \dec19_dec19_internal_op + connect \dec19_inv_a \dec19_dec19_inv_a + connect \dec19_inv_out \dec19_dec19_inv_out + connect \dec19_is_32b \dec19_dec19_is_32b + connect \dec19_ldst_len \dec19_dec19_ldst_len + connect \dec19_lk \dec19_dec19_lk + connect \dec19_out_sel \dec19_dec19_out_sel + connect \dec19_rc_sel \dec19_dec19_rc_sel + connect \dec19_rsrv \dec19_dec19_rsrv + connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe + connect \dec19_sgn \dec19_dec19_sgn + connect \dec19_sgn_ext \dec19_dec19_sgn_ext + connect \dec19_upd \dec19_dec19_upd + connect \opcode_in \dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3277.9-3303.4" + cell \dec30 \dec30 + connect \dec30_asmcode \dec30_dec30_asmcode + connect \dec30_br \dec30_dec30_br + connect \dec30_cr_in \dec30_dec30_cr_in + connect \dec30_cr_out \dec30_dec30_cr_out + connect \dec30_cry_in \dec30_dec30_cry_in + connect \dec30_cry_out \dec30_dec30_cry_out + connect \dec30_form \dec30_dec30_form + connect \dec30_function_unit \dec30_dec30_function_unit + connect \dec30_in1_sel \dec30_dec30_in1_sel + connect \dec30_in2_sel \dec30_dec30_in2_sel + connect \dec30_in3_sel \dec30_dec30_in3_sel + connect \dec30_internal_op \dec30_dec30_internal_op + connect \dec30_inv_a \dec30_dec30_inv_a + connect \dec30_inv_out \dec30_dec30_inv_out + connect \dec30_is_32b \dec30_dec30_is_32b + connect \dec30_ldst_len \dec30_dec30_ldst_len + connect \dec30_lk \dec30_dec30_lk + connect \dec30_out_sel \dec30_dec30_out_sel + connect \dec30_rc_sel \dec30_dec30_rc_sel + connect \dec30_rsrv \dec30_dec30_rsrv + connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe + connect \dec30_sgn \dec30_dec30_sgn + connect \dec30_sgn_ext \dec30_dec30_sgn_ext + connect \dec30_upd \dec30_dec30_upd + connect \opcode_in \dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3304.9-3330.4" + cell \dec31 \dec31 + connect \dec31_asmcode \dec31_dec31_asmcode + connect \dec31_br \dec31_dec31_br + connect \dec31_cr_in \dec31_dec31_cr_in + connect \dec31_cr_out \dec31_dec31_cr_out + connect \dec31_cry_in \dec31_dec31_cry_in + connect \dec31_cry_out \dec31_dec31_cry_out + connect \dec31_form \dec31_dec31_form + connect \dec31_function_unit \dec31_dec31_function_unit + connect \dec31_in1_sel \dec31_dec31_in1_sel + connect \dec31_in2_sel \dec31_dec31_in2_sel + connect \dec31_in3_sel \dec31_dec31_in3_sel + connect \dec31_internal_op \dec31_dec31_internal_op + connect \dec31_inv_a \dec31_dec31_inv_a + connect \dec31_inv_out \dec31_dec31_inv_out + connect \dec31_is_32b \dec31_dec31_is_32b + connect \dec31_ldst_len \dec31_dec31_ldst_len + connect \dec31_lk \dec31_dec31_lk + connect \dec31_out_sel \dec31_dec31_out_sel + connect \dec31_rc_sel \dec31_dec31_rc_sel + connect \dec31_rsrv \dec31_dec31_rsrv + connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe + connect \dec31_sgn \dec31_dec31_sgn + connect \dec31_sgn_ext \dec31_dec31_sgn_ext + connect \dec31_upd \dec31_dec31_upd + connect \opcode_in \dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3331.9-3357.4" + cell \dec58 \dec58 + connect \dec58_asmcode \dec58_dec58_asmcode + connect \dec58_br \dec58_dec58_br + connect \dec58_cr_in \dec58_dec58_cr_in + connect \dec58_cr_out \dec58_dec58_cr_out + connect \dec58_cry_in \dec58_dec58_cry_in + connect \dec58_cry_out \dec58_dec58_cry_out + connect \dec58_form \dec58_dec58_form + connect \dec58_function_unit \dec58_dec58_function_unit + connect \dec58_in1_sel \dec58_dec58_in1_sel + connect \dec58_in2_sel \dec58_dec58_in2_sel + connect \dec58_in3_sel \dec58_dec58_in3_sel + connect \dec58_internal_op \dec58_dec58_internal_op + connect \dec58_inv_a \dec58_dec58_inv_a + connect \dec58_inv_out \dec58_dec58_inv_out + connect \dec58_is_32b \dec58_dec58_is_32b + connect \dec58_ldst_len \dec58_dec58_ldst_len + connect \dec58_lk \dec58_dec58_lk + connect \dec58_out_sel \dec58_dec58_out_sel + connect \dec58_rc_sel \dec58_dec58_rc_sel + connect \dec58_rsrv \dec58_dec58_rsrv + connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe + connect \dec58_sgn \dec58_dec58_sgn + connect \dec58_sgn_ext \dec58_dec58_sgn_ext + connect \dec58_upd \dec58_dec58_upd + connect \opcode_in \dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3358.9-3384.4" + cell \dec62 \dec62 + connect \dec62_asmcode \dec62_dec62_asmcode + connect \dec62_br \dec62_dec62_br + connect \dec62_cr_in \dec62_dec62_cr_in + connect \dec62_cr_out \dec62_dec62_cr_out + connect \dec62_cry_in \dec62_dec62_cry_in + connect \dec62_cry_out \dec62_dec62_cry_out + connect \dec62_form \dec62_dec62_form + connect \dec62_function_unit \dec62_dec62_function_unit + connect \dec62_in1_sel \dec62_dec62_in1_sel + connect \dec62_in2_sel \dec62_dec62_in2_sel + connect \dec62_in3_sel \dec62_dec62_in3_sel + connect \dec62_internal_op \dec62_dec62_internal_op + connect \dec62_inv_a \dec62_dec62_inv_a + connect \dec62_inv_out \dec62_dec62_inv_out + connect \dec62_is_32b \dec62_dec62_is_32b + connect \dec62_ldst_len \dec62_dec62_ldst_len + connect \dec62_lk \dec62_dec62_lk + connect \dec62_out_sel \dec62_dec62_out_sel + connect \dec62_rc_sel \dec62_dec62_rc_sel + connect \dec62_rsrv \dec62_dec62_rsrv + connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe + connect \dec62_sgn \dec62_dec62_sgn + connect \dec62_sgn_ext \dec62_dec62_sgn_ext + connect \dec62_upd \dec62_dec62_upd + connect \opcode_in \dec62_opcode_in + end + attribute \src "libresoc.v:1192.7-1192.20" + process $proc$libresoc.v:1192$262 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:3385.3-3523.6" + process $proc$libresoc.v:3385$238 + assign { } { } + assign { } { } + assign { } { } + assign $0\asmcode[7:0] $2\asmcode[7:0] + attribute \src "libresoc.v:3386.5-3386.29" + switch \initial + attribute \src "libresoc.v:3386.9-3386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\asmcode[7:0] \dec19_dec19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\asmcode[7:0] \dec30_dec30_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\asmcode[7:0] \dec31_dec31_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\asmcode[7:0] \dec58_dec58_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\asmcode[7:0] \dec62_dec62_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\asmcode[7:0] 8'00000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\asmcode[7:0] 8'00001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\asmcode[7:0] 8'00000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\asmcode[7:0] 8'00001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\asmcode[7:0] 8'00010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\asmcode[7:0] 8'00010010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\asmcode[7:0] 8'00010100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\asmcode[7:0] 8'00010101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\asmcode[7:0] 8'00011101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\asmcode[7:0] 8'00011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\asmcode[7:0] 8'01001110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\asmcode[7:0] 8'01001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\asmcode[7:0] 8'01011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\asmcode[7:0] 8'01011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\asmcode[7:0] 8'01011110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\asmcode[7:0] 8'01011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\asmcode[7:0] 8'01100111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\asmcode[7:0] 8'01101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\asmcode[7:0] 8'10000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\asmcode[7:0] 8'10001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\asmcode[7:0] 8'10001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\asmcode[7:0] 8'10011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\asmcode[7:0] 8'10011001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\asmcode[7:0] 8'10011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\asmcode[7:0] 8'10100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\asmcode[7:0] 8'10101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\asmcode[7:0] 8'10110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\asmcode[7:0] 8'10110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\asmcode[7:0] 8'10111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\asmcode[7:0] 8'10111011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\asmcode[7:0] 8'11000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\asmcode[7:0] 8'11001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\asmcode[7:0] 8'11001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\asmcode[7:0] 8'11010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\asmcode[7:0] 8'11010010 + case + assign $1\asmcode[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\asmcode[7:0] 8'00010011 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\asmcode[7:0] 8'10000110 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\asmcode[7:0] 8'10011100 + case + assign $2\asmcode[7:0] $1\asmcode[7:0] + end + sync always + update \asmcode $0\asmcode[7:0] + end + attribute \src "libresoc.v:3524.3-3665.6" + process $proc$libresoc.v:3524$239 + assign { } { } + assign { } { } + assign { } { } + assign $0\in1_sel[2:0] $2\in1_sel[2:0] + attribute \src "libresoc.v:3525.5-3525.29" + switch \initial + attribute \src "libresoc.v:3525.9-3525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in1_sel[2:0] \dec19_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in1_sel[2:0] \dec30_dec30_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in1_sel[2:0] \dec31_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in1_sel[2:0] \dec58_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in1_sel[2:0] \dec62_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + case + assign $1\in1_sel[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + case + assign $2\in1_sel[2:0] $1\in1_sel[2:0] + end + sync always + update \in1_sel $0\in1_sel[2:0] + end + attribute \src "libresoc.v:3666.3-3807.6" + process $proc$libresoc.v:3666$240 + assign { } { } + assign { } { } + assign { } { } + assign $0\in2_sel[3:0] $2\in2_sel[3:0] + attribute \src "libresoc.v:3667.5-3667.29" + switch \initial + attribute \src "libresoc.v:3667.9-3667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in2_sel[3:0] \dec19_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in2_sel[3:0] \dec30_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in2_sel[3:0] \dec31_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in2_sel[3:0] \dec58_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in2_sel[3:0] \dec62_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in2_sel[3:0] 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + case + assign $1\in2_sel[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + case + assign $2\in2_sel[3:0] $1\in2_sel[3:0] + end + sync always + update \in2_sel $0\in2_sel[3:0] + end + attribute \src "libresoc.v:3808.3-3949.6" + process $proc$libresoc.v:3808$241 + assign { } { } + assign { } { } + assign { } { } + assign $0\in3_sel[1:0] $2\in3_sel[1:0] + attribute \src "libresoc.v:3809.5-3809.29" + switch \initial + attribute \src "libresoc.v:3809.9-3809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in3_sel[1:0] \dec19_dec19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in3_sel[1:0] \dec30_dec30_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in3_sel[1:0] \dec31_dec31_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in3_sel[1:0] \dec58_dec58_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in3_sel[1:0] \dec62_dec62_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + case + assign $1\in3_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + case + assign $2\in3_sel[1:0] $1\in3_sel[1:0] + end + sync always + update \in3_sel $0\in3_sel[1:0] + end + attribute \src "libresoc.v:3950.3-4091.6" + process $proc$libresoc.v:3950$242 + assign { } { } + assign { } { } + assign { } { } + assign $0\out_sel[1:0] $2\out_sel[1:0] + attribute \src "libresoc.v:3951.5-3951.29" + switch \initial + attribute \src "libresoc.v:3951.9-3951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\out_sel[1:0] \dec19_dec19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\out_sel[1:0] \dec30_dec30_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\out_sel[1:0] \dec31_dec31_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\out_sel[1:0] \dec58_dec58_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\out_sel[1:0] \dec62_dec62_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\out_sel[1:0] 2'10 + case + assign $1\out_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\out_sel[1:0] 2'01 + case + assign $2\out_sel[1:0] $1\out_sel[1:0] + end + sync always + update \out_sel $0\out_sel[1:0] + end + attribute \src "libresoc.v:4092.3-4233.6" + process $proc$libresoc.v:4092$243 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_in[2:0] $2\cr_in[2:0] + attribute \src "libresoc.v:4093.5-4093.29" + switch \initial + attribute \src "libresoc.v:4093.9-4093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_in[2:0] \dec19_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_in[2:0] \dec30_dec30_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_in[2:0] \dec31_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_in[2:0] \dec58_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_in[2:0] \dec62_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + case + assign $1\cr_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_in[2:0] 3'000 + case + assign $2\cr_in[2:0] $1\cr_in[2:0] + end + sync always + update \cr_in $0\cr_in[2:0] + end + attribute \src "libresoc.v:4234.3-4375.6" + process $proc$libresoc.v:4234$244 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_out[2:0] $2\cr_out[2:0] + attribute \src "libresoc.v:4235.5-4235.29" + switch \initial + attribute \src "libresoc.v:4235.9-4235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_out[2:0] \dec19_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_out[2:0] \dec30_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_out[2:0] \dec31_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_out[2:0] \dec58_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_out[2:0] \dec62_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + case + assign $1\cr_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_out[2:0] 3'000 + case + assign $2\cr_out[2:0] $1\cr_out[2:0] + end + sync always + update \cr_out $0\cr_out[2:0] + end + attribute \src "libresoc.v:4376.3-4517.6" + process $proc$libresoc.v:4376$245 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_len[3:0] $2\ldst_len[3:0] + attribute \src "libresoc.v:4377.5-4377.29" + switch \initial + attribute \src "libresoc.v:4377.9-4377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ldst_len[3:0] \dec19_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\ldst_len[3:0] \dec30_dec30_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\ldst_len[3:0] \dec58_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + case + assign $1\ldst_len[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + case + assign $2\ldst_len[3:0] $1\ldst_len[3:0] + end + sync always + update \ldst_len $0\ldst_len[3:0] + end + attribute \src "libresoc.v:4518.3-4659.6" + process $proc$libresoc.v:4518$246 + assign { } { } + assign { } { } + assign { } { } + assign $0\upd[1:0] $2\upd[1:0] + attribute \src "libresoc.v:4519.5-4519.29" + switch \initial + attribute \src "libresoc.v:4519.9-4519.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\upd[1:0] \dec19_dec19_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\upd[1:0] \dec30_dec30_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\upd[1:0] \dec31_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\upd[1:0] \dec58_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\upd[1:0] \dec62_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\upd[1:0] 2'00 + case + assign $1\upd[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\upd[1:0] 2'00 + case + assign $2\upd[1:0] $1\upd[1:0] + end + sync always + update \upd $0\upd[1:0] + end + attribute \src "libresoc.v:4660.3-4801.6" + process $proc$libresoc.v:4660$247 + assign { } { } + assign { } { } + assign { } { } + assign $0\rc_sel[1:0] $2\rc_sel[1:0] + attribute \src "libresoc.v:4661.5-4661.29" + switch \initial + attribute \src "libresoc.v:4661.9-4661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rc_sel[1:0] \dec19_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rc_sel[1:0] \dec30_dec30_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rc_sel[1:0] \dec31_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rc_sel[1:0] \dec58_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rc_sel[1:0] \dec62_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + case + assign $1\rc_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rc_sel[1:0] 2'00 + case + assign $2\rc_sel[1:0] $1\rc_sel[1:0] + end + sync always + update \rc_sel $0\rc_sel[1:0] + end + attribute \src "libresoc.v:4802.3-4943.6" + process $proc$libresoc.v:4802$248 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_in[1:0] $2\cry_in[1:0] + attribute \src "libresoc.v:4803.5-4803.29" + switch \initial + attribute \src "libresoc.v:4803.9-4803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_in[1:0] \dec19_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_in[1:0] \dec30_dec30_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_in[1:0] \dec31_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_in[1:0] \dec58_dec58_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_in[1:0] \dec62_dec62_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + case + assign $1\cry_in[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_in[1:0] 2'00 + case + assign $2\cry_in[1:0] $1\cry_in[1:0] + end + sync always + update \cry_in $0\cry_in[1:0] + end + attribute \src "libresoc.v:4944.3-5085.6" + process $proc$libresoc.v:4944$249 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_a[0:0] $2\inv_a[0:0] + attribute \src "libresoc.v:4945.5-4945.29" + switch \initial + attribute \src "libresoc.v:4945.9-4945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_a[0:0] \dec19_dec19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_a[0:0] \dec30_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_a[0:0] \dec31_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_a[0:0] \dec58_dec58_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_a[0:0] \dec62_dec62_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + case + assign $1\inv_a[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_a[0:0] 1'0 + case + assign $2\inv_a[0:0] $1\inv_a[0:0] + end + sync always + update \inv_a $0\inv_a[0:0] + end + attribute \src "libresoc.v:5086.3-5227.6" + process $proc$libresoc.v:5086$250 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_out[0:0] $2\inv_out[0:0] + attribute \src "libresoc.v:5087.5-5087.29" + switch \initial + attribute \src "libresoc.v:5087.9-5087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_out[0:0] \dec19_dec19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_out[0:0] \dec30_dec30_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_out[0:0] \dec31_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_out[0:0] \dec58_dec58_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_out[0:0] \dec62_dec62_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + case + assign $1\inv_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_out[0:0] 1'0 + case + assign $2\inv_out[0:0] $1\inv_out[0:0] + end + sync always + update \inv_out $0\inv_out[0:0] + end + attribute \src "libresoc.v:5228.3-5369.6" + process $proc$libresoc.v:5228$251 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_out[0:0] $2\cry_out[0:0] + attribute \src "libresoc.v:5229.5-5229.29" + switch \initial + attribute \src "libresoc.v:5229.9-5229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_out[0:0] \dec19_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_out[0:0] \dec30_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_out[0:0] \dec31_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_out[0:0] \dec58_dec58_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_out[0:0] \dec62_dec62_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + case + assign $1\cry_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_out[0:0] 1'0 + case + assign $2\cry_out[0:0] $1\cry_out[0:0] + end + sync always + update \cry_out $0\cry_out[0:0] + end + attribute \src "libresoc.v:5370.3-5511.6" + process $proc$libresoc.v:5370$252 + assign { } { } + assign { } { } + assign { } { } + assign $0\br[0:0] $2\br[0:0] + attribute \src "libresoc.v:5371.5-5371.29" + switch \initial + attribute \src "libresoc.v:5371.9-5371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\br[0:0] \dec19_dec19_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\br[0:0] \dec30_dec30_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\br[0:0] \dec31_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\br[0:0] \dec58_dec58_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\br[0:0] \dec62_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\br[0:0] 1'0 + case + assign $1\br[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\br[0:0] 1'0 + case + assign $2\br[0:0] $1\br[0:0] + end + sync always + update \br $0\br[0:0] + end + attribute \src "libresoc.v:5512.3-5653.6" + process $proc$libresoc.v:5512$253 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] + attribute \src "libresoc.v:5513.5-5513.29" + switch \initial + attribute \src "libresoc.v:5513.9-5513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + case + assign $1\sgn_ext[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + case + assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] + end + sync always + update \sgn_ext $0\sgn_ext[0:0] + end + attribute \src "libresoc.v:5654.3-5795.6" + process $proc$libresoc.v:5654$254 + assign { } { } + assign { } { } + assign { } { } + assign $0\rsrv[0:0] $2\rsrv[0:0] + attribute \src "libresoc.v:5655.5-5655.29" + switch \initial + attribute \src "libresoc.v:5655.9-5655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rsrv[0:0] \dec19_dec19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rsrv[0:0] \dec30_dec30_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rsrv[0:0] \dec31_dec31_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rsrv[0:0] \dec58_dec58_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rsrv[0:0] \dec62_dec62_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + case + assign $1\rsrv[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rsrv[0:0] 1'0 + case + assign $2\rsrv[0:0] $1\rsrv[0:0] + end + sync always + update \rsrv $0\rsrv[0:0] + end + attribute \src "libresoc.v:5796.3-5937.6" + process $proc$libresoc.v:5796$255 + assign { } { } + assign { } { } + assign { } { } + assign $0\is_32b[0:0] $2\is_32b[0:0] + attribute \src "libresoc.v:5797.5-5797.29" + switch \initial + attribute \src "libresoc.v:5797.9-5797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\is_32b[0:0] \dec19_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\is_32b[0:0] \dec30_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\is_32b[0:0] \dec31_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\is_32b[0:0] \dec58_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\is_32b[0:0] \dec62_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + case + assign $1\is_32b[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\is_32b[0:0] 1'0 + case + assign $2\is_32b[0:0] $1\is_32b[0:0] + end + sync always + update \is_32b $0\is_32b[0:0] + end + attribute \src "libresoc.v:5938.3-6079.6" + process $proc$libresoc.v:5938$256 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn[0:0] $2\sgn[0:0] + attribute \src "libresoc.v:5939.5-5939.29" + switch \initial + attribute \src "libresoc.v:5939.9-5939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn[0:0] \dec19_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn[0:0] \dec30_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn[0:0] \dec31_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn[0:0] \dec58_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn[0:0] \dec62_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn[0:0] 1'0 + case + assign $1\sgn[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn[0:0] 1'0 + case + assign $2\sgn[0:0] $1\sgn[0:0] + end + sync always + update \sgn $0\sgn[0:0] + end + attribute \src "libresoc.v:6080.3-6221.6" + process $proc$libresoc.v:6080$257 + assign { } { } + assign { } { } + assign { } { } + assign $0\lk[0:0] $2\lk[0:0] + attribute \src "libresoc.v:6081.5-6081.29" + switch \initial + attribute \src "libresoc.v:6081.9-6081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\lk[0:0] \dec19_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\lk[0:0] \dec30_dec30_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\lk[0:0] \dec31_dec31_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\lk[0:0] \dec58_dec58_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\lk[0:0] \dec62_dec62_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\lk[0:0] 1'0 + case + assign $1\lk[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\lk[0:0] 1'0 + case + assign $2\lk[0:0] $1\lk[0:0] + end + sync always + update \lk $0\lk[0:0] + end + attribute \src "libresoc.v:6222.3-6363.6" + process $proc$libresoc.v:6222$258 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] + attribute \src "libresoc.v:6223.5-6223.29" + switch \initial + attribute \src "libresoc.v:6223.9-6223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + case + assign $1\sgl_pipe[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + case + assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] + end + sync always + update \sgl_pipe $0\sgl_pipe[0:0] + end + attribute \src "libresoc.v:6364.3-6505.6" + process $proc$libresoc.v:6364$259 + assign { } { } + assign { } { } + assign { } { } + assign $0\function_unit[11:0] $2\function_unit[11:0] + attribute \src "libresoc.v:6365.5-6365.29" + switch \initial + attribute \src "libresoc.v:6365.9-6365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\function_unit[11:0] \dec19_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\function_unit[11:0] \dec30_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\function_unit[11:0] \dec31_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\function_unit[11:0] \dec58_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\function_unit[11:0] \dec62_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + case + assign $1\function_unit[11:0] 12'000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + case + assign $2\function_unit[11:0] $1\function_unit[11:0] + end + sync always + update \function_unit $0\function_unit[11:0] + end + attribute \src "libresoc.v:6506.3-6647.6" + process $proc$libresoc.v:6506$260 + assign { } { } + assign { } { } + assign { } { } + assign $0\internal_op[6:0] $2\internal_op[6:0] + attribute \src "libresoc.v:6507.5-6507.29" + switch \initial + attribute \src "libresoc.v:6507.9-6507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\internal_op[6:0] \dec19_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\internal_op[6:0] \dec30_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\internal_op[6:0] \dec31_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\internal_op[6:0] \dec58_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\internal_op[6:0] \dec62_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\internal_op[6:0] 7'1001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\internal_op[6:0] 7'0000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + case + assign $1\internal_op[6:0] 7'0000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\internal_op[6:0] 7'0000101 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\internal_op[6:0] 7'1000100 + case + assign $2\internal_op[6:0] $1\internal_op[6:0] + end + sync always + update \internal_op $0\internal_op[6:0] + end + attribute \src "libresoc.v:6648.3-6789.6" + process $proc$libresoc.v:6648$261 + assign { } { } + assign { } { } + assign { } { } + assign $0\form[4:0] $2\form[4:0] + attribute \src "libresoc.v:6649.5-6649.29" + switch \initial + attribute \src "libresoc.v:6649.9-6649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\form[4:0] \dec19_dec19_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\form[4:0] \dec30_dec30_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\form[4:0] \dec31_dec31_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\form[4:0] \dec58_dec58_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\form[4:0] \dec62_dec62_form + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\form[4:0] 5'00011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\form[4:0] 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\form[4:0] 5'00100 + case + assign $1\form[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\form[4:0] 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\form[4:0] 5'00000 + case + assign $2\form[4:0] $1\form[4:0] + end + sync always + update \form $0\form[4:0] + end + connect \$2 $ternary$libresoc.v:3249$237_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR \opcode_in [20:11] + connect \MB \opcode_in [10:6] + connect \ME \opcode_in [5:1] + connect \SH \opcode_in [15:11] + connect \BC \opcode_in [10:6] + connect \TO \opcode_in [25:21] + connect \DS \opcode_in [15:2] + connect \D \opcode_in [15:0] + connect \BH \opcode_in [12:11] + connect \BI \opcode_in [20:16] + connect \BO \opcode_in [25:21] + connect \FXM \opcode_in [19:12] + connect \BT \opcode_in [25:21] + connect \BA \opcode_in [20:16] + connect \BB \opcode_in [15:11] + connect \CR \opcode_in [10:1] + connect \BF \opcode_in [25:23] + connect \BD \opcode_in [15:2] + connect \OE \opcode_in [10] + connect \Rc \opcode_in [0] + connect \AA \opcode_in [1] + connect \LK \opcode_in [0] + connect \LI \opcode_in [25:2] + connect \ME32 \opcode_in [5:1] + connect \MB32 \opcode_in [10:6] + connect \sh { \opcode_in [1] \opcode_in [15:11] } + connect \SH32 \opcode_in [15:11] + connect \L \opcode_in [21] + connect \UI \opcode_in [15:0] + connect \SI \opcode_in [15:0] + connect \RB \opcode_in [15:11] + connect \RA \opcode_in [20:16] + connect \RT \opcode_in [25:21] + connect \RS \opcode_in [25:21] + connect \opcode_in \$2 + connect \opcode_switch$1 \opcode_in + connect \dec62_opcode_in \opcode_in + connect \dec58_opcode_in \opcode_in + connect \dec31_opcode_in \opcode_in + connect \dec30_opcode_in \opcode_in + connect \dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:7128.1-8635.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" +attribute \generator "nMigen" +module \dec19 + attribute \src "libresoc.v:7646.3-7697.6" + wire width 8 $0\dec19_asmcode[7:0] + attribute \src "libresoc.v:7854.3-7905.6" + wire $0\dec19_br[0:0] + attribute \src "libresoc.v:8530.3-8581.6" + wire width 3 $0\dec19_cr_in[2:0] + attribute \src "libresoc.v:8582.3-8633.6" + wire width 3 $0\dec19_cr_out[2:0] + attribute \src "libresoc.v:7594.3-7645.6" + wire width 2 $0\dec19_cry_in[1:0] + attribute \src "libresoc.v:7802.3-7853.6" + wire $0\dec19_cry_out[0:0] + attribute \src "libresoc.v:8270.3-8321.6" + wire width 5 $0\dec19_form[4:0] + attribute \src "libresoc.v:7386.3-7437.6" + wire width 12 $0\dec19_function_unit[11:0] + attribute \src "libresoc.v:8322.3-8373.6" + wire width 3 $0\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8374.3-8425.6" + wire width 4 $0\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8426.3-8477.6" + wire width 2 $0\dec19_in3_sel[1:0] + attribute \src "libresoc.v:7958.3-8009.6" + wire width 7 $0\dec19_internal_op[6:0] + attribute \src "libresoc.v:7698.3-7749.6" + wire $0\dec19_inv_a[0:0] + attribute \src "libresoc.v:7750.3-7801.6" + wire $0\dec19_inv_out[0:0] + attribute \src "libresoc.v:8062.3-8113.6" + wire $0\dec19_is_32b[0:0] + attribute \src "libresoc.v:7438.3-7489.6" + wire width 4 $0\dec19_ldst_len[3:0] + attribute \src "libresoc.v:8166.3-8217.6" + wire $0\dec19_lk[0:0] + attribute \src "libresoc.v:8478.3-8529.6" + wire width 2 $0\dec19_out_sel[1:0] + attribute \src "libresoc.v:7542.3-7593.6" + wire width 2 $0\dec19_rc_sel[1:0] + attribute \src "libresoc.v:8010.3-8061.6" + wire $0\dec19_rsrv[0:0] + attribute \src "libresoc.v:8218.3-8269.6" + wire $0\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8114.3-8165.6" + wire $0\dec19_sgn[0:0] + attribute \src "libresoc.v:7906.3-7957.6" + wire $0\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:7490.3-7541.6" + wire width 2 $0\dec19_upd[1:0] + attribute \src "libresoc.v:7129.7-7129.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:7646.3-7697.6" + wire width 8 $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:7854.3-7905.6" + wire $1\dec19_br[0:0] + attribute \src "libresoc.v:8530.3-8581.6" + wire width 3 $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:8582.3-8633.6" + wire width 3 $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:7594.3-7645.6" + wire width 2 $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:7802.3-7853.6" + wire $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:8270.3-8321.6" + wire width 5 $1\dec19_form[4:0] + attribute \src "libresoc.v:7386.3-7437.6" + wire width 12 $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:8322.3-8373.6" + wire width 3 $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8374.3-8425.6" + wire width 4 $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8426.3-8477.6" + wire width 2 $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:7958.3-8009.6" + wire width 7 $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:7698.3-7749.6" + wire $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:7750.3-7801.6" + wire $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:8062.3-8113.6" + wire $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:7438.3-7489.6" + wire width 4 $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:8166.3-8217.6" + wire $1\dec19_lk[0:0] + attribute \src "libresoc.v:8478.3-8529.6" + wire width 2 $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:7542.3-7593.6" + wire width 2 $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:8010.3-8061.6" + wire $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:8218.3-8269.6" + wire $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8114.3-8165.6" + wire $1\dec19_sgn[0:0] + attribute \src "libresoc.v:7906.3-7957.6" + wire $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:7490.3-7541.6" + wire width 2 $1\dec19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec19_upd + attribute \src "libresoc.v:7129.7-7129.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \src "libresoc.v:7129.7-7129.20" + process $proc$libresoc.v:7129$287 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:7386.3-7437.6" + process $proc$libresoc.v:7386$263 + assign { } { } + assign { } { } + assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:7387.5-7387.29" + switch \initial + attribute \src "libresoc.v:7387.9-7387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + case + assign $1\dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec19_function_unit $0\dec19_function_unit[11:0] + end + attribute \src "libresoc.v:7438.3-7489.6" + process $proc$libresoc.v:7438$264 + assign { } { } + assign { } { } + assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:7439.5-7439.29" + switch \initial + attribute \src "libresoc.v:7439.9-7439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + case + assign $1\dec19_ldst_len[3:0] 4'0000 + end + sync always + update \dec19_ldst_len $0\dec19_ldst_len[3:0] + end + attribute \src "libresoc.v:7490.3-7541.6" + process $proc$libresoc.v:7490$265 + assign { } { } + assign { } { } + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "libresoc.v:7491.5-7491.29" + switch \initial + attribute \src "libresoc.v:7491.9-7491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + case + assign $1\dec19_upd[1:0] 2'00 + end + sync always + update \dec19_upd $0\dec19_upd[1:0] + end + attribute \src "libresoc.v:7542.3-7593.6" + process $proc$libresoc.v:7542$266 + assign { } { } + assign { } { } + assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:7543.5-7543.29" + switch \initial + attribute \src "libresoc.v:7543.9-7543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + case + assign $1\dec19_rc_sel[1:0] 2'00 + end + sync always + update \dec19_rc_sel $0\dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:7594.3-7645.6" + process $proc$libresoc.v:7594$267 + assign { } { } + assign { } { } + assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:7595.5-7595.29" + switch \initial + attribute \src "libresoc.v:7595.9-7595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + case + assign $1\dec19_cry_in[1:0] 2'00 + end + sync always + update \dec19_cry_in $0\dec19_cry_in[1:0] + end + attribute \src "libresoc.v:7646.3-7697.6" + process $proc$libresoc.v:7646$268 + assign { } { } + assign { } { } + assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:7647.5-7647.29" + switch \initial + attribute \src "libresoc.v:7647.9-7647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'10010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001000 + case + assign $1\dec19_asmcode[7:0] 8'00000000 + end + sync always + update \dec19_asmcode $0\dec19_asmcode[7:0] + end + attribute \src "libresoc.v:7698.3-7749.6" + process $proc$libresoc.v:7698$269 + assign { } { } + assign { } { } + assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:7699.5-7699.29" + switch \initial + attribute \src "libresoc.v:7699.9-7699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + case + assign $1\dec19_inv_a[0:0] 1'0 + end + sync always + update \dec19_inv_a $0\dec19_inv_a[0:0] + end + attribute \src "libresoc.v:7750.3-7801.6" + process $proc$libresoc.v:7750$270 + assign { } { } + assign { } { } + assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:7751.5-7751.29" + switch \initial + attribute \src "libresoc.v:7751.9-7751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + case + assign $1\dec19_inv_out[0:0] 1'0 + end + sync always + update \dec19_inv_out $0\dec19_inv_out[0:0] + end + attribute \src "libresoc.v:7802.3-7853.6" + process $proc$libresoc.v:7802$271 + assign { } { } + assign { } { } + assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:7803.5-7803.29" + switch \initial + attribute \src "libresoc.v:7803.9-7803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + case + assign $1\dec19_cry_out[0:0] 1'0 + end + sync always + update \dec19_cry_out $0\dec19_cry_out[0:0] + end + attribute \src "libresoc.v:7854.3-7905.6" + process $proc$libresoc.v:7854$272 + assign { } { } + assign { } { } + assign $0\dec19_br[0:0] $1\dec19_br[0:0] + attribute \src "libresoc.v:7855.5-7855.29" + switch \initial + attribute \src "libresoc.v:7855.9-7855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + case + assign $1\dec19_br[0:0] 1'0 + end + sync always + update \dec19_br $0\dec19_br[0:0] + end + attribute \src "libresoc.v:7906.3-7957.6" + process $proc$libresoc.v:7906$273 + assign { } { } + assign { } { } + assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:7907.5-7907.29" + switch \initial + attribute \src "libresoc.v:7907.9-7907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + case + assign $1\dec19_sgn_ext[0:0] 1'0 + end + sync always + update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] + end + attribute \src "libresoc.v:7958.3-8009.6" + process $proc$libresoc.v:7958$274 + assign { } { } + assign { } { } + assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:7959.5-7959.29" + switch \initial + attribute \src "libresoc.v:7959.9-7959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + case + assign $1\dec19_internal_op[6:0] 7'0000000 + end + sync always + update \dec19_internal_op $0\dec19_internal_op[6:0] + end + attribute \src "libresoc.v:8010.3-8061.6" + process $proc$libresoc.v:8010$275 + assign { } { } + assign { } { } + assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:8011.5-8011.29" + switch \initial + attribute \src "libresoc.v:8011.9-8011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + case + assign $1\dec19_rsrv[0:0] 1'0 + end + sync always + update \dec19_rsrv $0\dec19_rsrv[0:0] + end + attribute \src "libresoc.v:8062.3-8113.6" + process $proc$libresoc.v:8062$276 + assign { } { } + assign { } { } + assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:8063.5-8063.29" + switch \initial + attribute \src "libresoc.v:8063.9-8063.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + case + assign $1\dec19_is_32b[0:0] 1'0 + end + sync always + update \dec19_is_32b $0\dec19_is_32b[0:0] + end + attribute \src "libresoc.v:8114.3-8165.6" + process $proc$libresoc.v:8114$277 + assign { } { } + assign { } { } + assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] + attribute \src "libresoc.v:8115.5-8115.29" + switch \initial + attribute \src "libresoc.v:8115.9-8115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + case + assign $1\dec19_sgn[0:0] 1'0 + end + sync always + update \dec19_sgn $0\dec19_sgn[0:0] + end + attribute \src "libresoc.v:8166.3-8217.6" + process $proc$libresoc.v:8166$278 + assign { } { } + assign { } { } + assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] + attribute \src "libresoc.v:8167.5-8167.29" + switch \initial + attribute \src "libresoc.v:8167.9-8167.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + case + assign $1\dec19_lk[0:0] 1'0 + end + sync always + update \dec19_lk $0\dec19_lk[0:0] + end + attribute \src "libresoc.v:8218.3-8269.6" + process $proc$libresoc.v:8218$279 + assign { } { } + assign { } { } + assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8219.5-8219.29" + switch \initial + attribute \src "libresoc.v:8219.9-8219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + case + assign $1\dec19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:8270.3-8321.6" + process $proc$libresoc.v:8270$280 + assign { } { } + assign { } { } + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "libresoc.v:8271.5-8271.29" + switch \initial + attribute \src "libresoc.v:8271.9-8271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + case + assign $1\dec19_form[4:0] 5'00000 + end + sync always + update \dec19_form $0\dec19_form[4:0] + end + attribute \src "libresoc.v:8322.3-8373.6" + process $proc$libresoc.v:8322$281 + assign { } { } + assign { } { } + assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8323.5-8323.29" + switch \initial + attribute \src "libresoc.v:8323.9-8323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + case + assign $1\dec19_in1_sel[2:0] 3'000 + end + sync always + update \dec19_in1_sel $0\dec19_in1_sel[2:0] + end + attribute \src "libresoc.v:8374.3-8425.6" + process $proc$libresoc.v:8374$282 + assign { } { } + assign { } { } + assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8375.5-8375.29" + switch \initial + attribute \src "libresoc.v:8375.9-8375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + case + assign $1\dec19_in2_sel[3:0] 4'0000 + end + sync always + update \dec19_in2_sel $0\dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:8426.3-8477.6" + process $proc$libresoc.v:8426$283 + assign { } { } + assign { } { } + assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:8427.5-8427.29" + switch \initial + attribute \src "libresoc.v:8427.9-8427.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + case + assign $1\dec19_in3_sel[1:0] 2'00 + end + sync always + update \dec19_in3_sel $0\dec19_in3_sel[1:0] + end + attribute \src "libresoc.v:8478.3-8529.6" + process $proc$libresoc.v:8478$284 + assign { } { } + assign { } { } + assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:8479.5-8479.29" + switch \initial + attribute \src "libresoc.v:8479.9-8479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + case + assign $1\dec19_out_sel[1:0] 2'00 + end + sync always + update \dec19_out_sel $0\dec19_out_sel[1:0] + end + attribute \src "libresoc.v:8530.3-8581.6" + process $proc$libresoc.v:8530$285 + assign { } { } + assign { } { } + assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:8531.5-8531.29" + switch \initial + attribute \src "libresoc.v:8531.9-8531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + case + assign $1\dec19_cr_in[2:0] 3'000 + end + sync always + update \dec19_cr_in $0\dec19_cr_in[2:0] + end + attribute \src "libresoc.v:8582.3-8633.6" + process $proc$libresoc.v:8582$286 + assign { } { } + assign { } { } + assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:8583.5-8583.29" + switch \initial + attribute \src "libresoc.v:8583.9-8583.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + case + assign $1\dec19_cr_out[2:0] 3'000 + end + sync always + update \dec19_cr_out $0\dec19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:8639.1-10676.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2" +attribute \generator "nMigen" +module \dec2 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $0\cia[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\cr_in1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_in1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\cr_in2$1[2:0]$306 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\cr_in2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_in2_ok$2[0:0]$307 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_in2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\cr_out[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_out_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $0\cr_rd[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_rd_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $0\cr_wr[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_wr_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $0\ea[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\ea_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$3[0:0]$309 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$4[0:0]$310 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$5[0:0]$311 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$6[0:0]$312 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$7[0:0]$313 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$8[0:0]$314 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$9[0:0]$315 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal[0:0]$308 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\fast1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\fast2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\fasto1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\fasto1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\fasto2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\fasto2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 12 $0\fn_unit[11:0] + attribute \src "libresoc.v:8640.7-8640.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 2 $0\input_carry[1:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 32 $0\insn[31:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 7 $0\insn_type[6:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\is_32bit[0:0] + attribute \src "libresoc.v:10430.3-10449.6" + wire $0\is_priv_insn[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $0\reg1[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\reg1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $0\reg2[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\reg2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $0\reg3[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\reg3_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $0\rego[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\rego_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $0\spr1[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $0\spro[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\spro_ok[0:0] + attribute \src "libresoc.v:10384.3-10393.6" + wire $0\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:10420.3-10429.6" + wire width 13 $0\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:10394.3-10409.6" + wire width 3 $0\tmp_xer_in[2:0] + attribute \src "libresoc.v:10410.3-10419.6" + wire $0\tmp_xer_out[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 13 $0\trapaddr[12:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $0\traptype[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\xer_in[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\xer_out[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $1\cia[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\cr_in1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_in1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\cr_in2$1[2:0]$316 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\cr_in2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_in2_ok$2[0:0]$317 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_in2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\cr_out[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_out_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $1\cr_rd[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_rd_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $1\cr_wr[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_wr_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $1\ea[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\ea_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$3[0:0]$319 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$4[0:0]$320 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$5[0:0]$321 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$6[0:0]$322 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$7[0:0]$323 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$8[0:0]$324 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$9[0:0]$325 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal[0:0]$318 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\fast1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\fast2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\fasto1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\fasto1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\fasto2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\fasto2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 12 $1\fn_unit[11:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 2 $1\input_carry[1:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 32 $1\insn[31:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 7 $1\insn_type[6:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\is_32bit[0:0] + attribute \src "libresoc.v:10430.3-10449.6" + wire $1\is_priv_insn[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\rc_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $1\reg1[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\reg1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $1\reg2[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\reg2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $1\reg3[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\reg3_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $1\rego[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\rego_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $1\spr1[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $1\spro[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\spro_ok[0:0] + attribute \src "libresoc.v:10384.3-10393.6" + wire $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:10420.3-10429.6" + wire width 13 $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:10394.3-10409.6" + wire width 3 $1\tmp_xer_in[2:0] + attribute \src "libresoc.v:10410.3-10419.6" + wire $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 13 $1\trapaddr[12:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $1\traptype[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\xer_in[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\xer_out[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $2\asmcode[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $2\cia[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\cr_in1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_in1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\cr_in2$1[2:0]$326 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\cr_in2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_in2_ok$2[0:0]$327 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_in2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\cr_out[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_out_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $2\cr_rd[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_rd_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $2\cr_wr[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_wr_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $2\ea[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\ea_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$3[0:0]$329 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$4[0:0]$330 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$5[0:0]$331 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$6[0:0]$332 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$7[0:0]$333 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$8[0:0]$334 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$9[0:0]$335 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal[0:0]$328 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\fast1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\fast1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\fast2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\fast2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\fasto1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\fasto1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\fasto2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\fasto2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 12 $2\fn_unit[11:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 2 $2\input_carry[1:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 32 $2\insn[31:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 7 $2\insn_type[6:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\is_32bit[0:0] + attribute \src "libresoc.v:10430.3-10449.6" + wire $2\is_priv_insn[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\lk[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $2\msr[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\oe_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\rc[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\rc_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $2\reg1[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\reg1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $2\reg2[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\reg2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $2\reg3[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\reg3_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $2\rego[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\rego_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $2\spr1[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\spr1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $2\spro[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\spro_ok[0:0] + attribute \src "libresoc.v:10394.3-10409.6" + wire width 3 $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 13 $2\trapaddr[12:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $2\traptype[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\xer_in[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\xer_out[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $3\asmcode[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $3\cia[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\cr_in1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_in1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\cr_in2$1[2:0]$336 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\cr_in2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_in2_ok$2[0:0]$337 + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_in2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\cr_out[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_out_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $3\cr_rd[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_rd_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $3\cr_wr[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_wr_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire 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attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec_o_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec_opcode_in + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_rc_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 8 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 9 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 50 \exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 51 \exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 52 \exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 53 \exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 54 \exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 55 \exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 56 \exc_$signal$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 57 \exc_$signal$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:903" + wire \ext_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 22 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 24 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 26 \fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 28 \fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \fasto2_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 12 output 42 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:906" + wire \illeg_ok + attribute \src "libresoc.v:8640.7-8640.15" + wire \initial + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 2 output 48 \input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 32 output 40 \insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 32 \insn_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" + wire width 32 \insn_in$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:283" + wire width 32 \insn_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312" + wire width 32 \insn_in$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367" + wire width 32 \insn_in$41 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 output 41 \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire output 63 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:44" + wire \is_priv_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire output 43 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 46 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:905" + wire \priv_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 4 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 44 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 45 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 10 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 11 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 12 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 13 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 14 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 15 \reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 6 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \rego_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 2 \sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 18 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 19 \spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute 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attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute 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"reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 16 \spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + wire width 8 \tmp_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_in2$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in2_ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \tmp_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \tmp_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \tmp_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \tmp_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \tmp_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute 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attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute 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attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute 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width 8 \tmp_tmp_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \tmp_tmp_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$27 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 12 \tmp_tmp_fn_unit + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 2 \tmp_tmp_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 32 \tmp_tmp_insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 \tmp_tmp_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire \tmp_tmp_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire \tmp_tmp_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \tmp_tmp_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_tmp_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 \tmp_tmp_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \tmp_tmp_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 \tmp_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + wire \tmp_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 output 58 \trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 output 49 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 output 20 \xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + wire output 21 \xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:909" + cell $and $and$libresoc.v:10239$296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_eint + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:10239$296_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + cell $and $and$libresoc.v:10240$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_dec [63] + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:10240$297_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:911" + cell $and $and$libresoc.v:10241$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_priv_insn + connect \B \cur_msr [14] + connect \Y $and$libresoc.v:10241$298_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:960" + cell $eq $eq$libresoc.v:10231$288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$libresoc.v:10231$288_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + cell $eq $eq$libresoc.v:10232$289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$libresoc.v:10232$289_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" + cell $eq $eq$libresoc.v:10234$291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$libresoc.v:10234$291_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" + cell $eq $eq$libresoc.v:10235$292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:10235$292_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" + cell $eq $eq$libresoc.v:10236$293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0001010 + connect \Y $eq$libresoc.v:10236$293_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" + cell $eq $eq$libresoc.v:10237$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:10237$294_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + cell $eq $eq$libresoc.v:10238$295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0111111 + connect \Y $eq$libresoc.v:10238$295_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912" + cell $eq $eq$libresoc.v:10242$299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $eq$libresoc.v:10242$299_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + cell $or $or$libresoc.v:10233$290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \B \$30 + connect \Y $or$libresoc.v:10233$290_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10243.7-10280.4" + cell \dec \dec + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BO \dec_BO + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \LK \dec_LK + connect \OE \dec_OE + connect \RA \dec_RA + connect \RB \dec_RB + connect \RS \dec_RS + connect \RT \dec_RT + connect \Rc \dec_Rc + connect \SPR \dec_SPR + connect \XL_BT \dec_XL_BT + connect \XL_XO \dec_XL_XO + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \asmcode \dec_asmcode + connect \bigendian \bigendian + connect \cr_in \dec_cr_in + connect \cr_out \dec_cr_out + connect \cry_in \dec_cry_in + connect \function_unit \dec_function_unit + connect \in1_sel \dec_in1_sel + connect \in2_sel \dec_in2_sel + connect \in3_sel \dec_in3_sel + connect \internal_op \dec_internal_op + connect \is_32b \dec_is_32b + connect \lk \dec_lk + connect \opcode_in \dec_opcode_in + connect \out_sel \dec_out_sel + connect \raw_opcode_in \raw_opcode_in + connect \rc_sel \dec_rc_sel + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10281.9-10295.4" + cell \dec_a \dec_a + connect \BO \dec_BO + connect \RA \dec_RA + connect \RS \dec_RS + connect \SPR \dec_SPR + connect \XL_XO \dec_XL_XO + connect \fast_a \dec_a_fast_a + connect \fast_a_ok \dec_a_fast_a_ok + connect \internal_op \dec_internal_op + connect \reg_a \dec_a_reg_a + connect \reg_a_ok \dec_a_reg_a_ok + connect \sel_in \dec_a_sel_in + connect \spr_a \dec_a_spr_a + connect \spr_a_ok \dec_a_spr_a_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10296.9-10306.4" + cell \dec_b \dec_b + connect \RB \dec_RB + connect \RS \dec_RS + connect \XL_XO \dec_XL_XO + connect \fast_b \dec_b_fast_b + connect \fast_b_ok \dec_b_fast_b_ok + connect \internal_op \dec_internal_op + connect \reg_b \dec_b_reg_b + connect \reg_b_ok \dec_b_reg_b_ok + connect \sel_in \dec_b_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10307.9-10313.4" + cell \dec_c \dec_c + connect \RB \dec_RB + connect \RS \dec_RS + connect \reg_c \dec_c_reg_c + connect \reg_c_ok \dec_c_reg_c_ok + connect \sel_in \dec_c_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10314.13-10333.4" + cell \dec_cr_in \dec_cr_in$10 + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \X_BFA \dec_X_BFA + connect \cr_bitfield \dec_cr_in_cr_bitfield + connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b + connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok + connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o + connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok + connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok + connect \cr_fxm \dec_cr_in_cr_fxm + connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok + connect \insn_in \dec_cr_in_insn_in + connect \internal_op \dec_internal_op + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10334.14-10346.4" + cell \dec_cr_out \dec_cr_out$11 + connect \FXM \dec_FXM + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield \dec_cr_out_cr_bitfield + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \cr_fxm \dec_cr_out_cr_fxm + connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok + connect \insn_in \dec_cr_out_insn_in + connect \internal_op \dec_internal_op + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10347.9-10360.4" + cell \dec_o \dec_o + connect \BO \dec_BO + connect \RA \dec_RA + connect \RT \dec_RT + connect \SPR \dec_SPR + connect \fast_o \dec_o_fast_o + connect \fast_o_ok \dec_o_fast_o_ok + connect \internal_op \dec_internal_op + connect \reg_o \dec_o_reg_o + connect \reg_o_ok \dec_o_reg_o_ok + connect \sel_in \dec_o_sel_in + connect \spr_o \dec_o_spr_o + connect \spr_o_ok \dec_o_spr_o_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10361.10-10370.4" + cell \dec_o2 \dec_o2 + connect \RA \dec_RA + connect \fast_o \dec_o2_fast_o + connect \fast_o_ok \dec_o2_fast_o_ok + connect \internal_op \dec_internal_op + connect \lk \dec_o2_lk + connect \reg_o \dec_o2_reg_o + connect \reg_o_ok \dec_o2_reg_o_ok + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10371.10-10377.4" + cell \dec_oe \dec_oe + connect \OE \dec_OE + connect \internal_op \dec_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10378.10-10383.4" + cell \dec_rc \dec_rc + connect \Rc \dec_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:10384.3-10393.6" + process $proc$libresoc.v:10384$300 + assign { } { } + assign { } { } + assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:10385.5-10385.29" + switch \initial + attribute \src "libresoc.v:10385.9-10385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:762" + switch \dec_lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_lk[0:0] \dec_LK + case + assign $1\tmp_tmp_lk[0:0] 1'0 + end + sync always + update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] + end + attribute \src "libresoc.v:10394.3-10409.6" + process $proc$libresoc.v:10394$301 + assign { } { } + assign { } { } + assign { } { } + assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:10395.5-10395.29" + switch \initial + attribute \src "libresoc.v:10395.9-10395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_in[2:0] 3'111 + case + assign $1\tmp_xer_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\tmp_xer_in[2:0] 3'001 + case + assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] + end + sync always + update \tmp_xer_in $0\tmp_xer_in[2:0] + end + attribute \src "libresoc.v:10410.3-10419.6" + process $proc$libresoc.v:10410$302 + assign { } { } + assign { } { } + assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:10411.5-10411.29" + switch \initial + attribute \src "libresoc.v:10411.9-10411.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_out[0:0] 1'1 + case + assign $1\tmp_xer_out[0:0] 1'0 + end + sync always + update \tmp_xer_out $0\tmp_xer_out[0:0] + end + attribute \src "libresoc.v:10420.3-10429.6" + process $proc$libresoc.v:10420$303 + assign { } { } + assign { } { } + assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:10421.5-10421.29" + switch \initial + attribute \src "libresoc.v:10421.9-10421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 + case + assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 + end + sync always + update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] + end + attribute \src "libresoc.v:10430.3-10449.6" + process $proc$libresoc.v:10430$304 + assign { } { } + assign { } { } + assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] + attribute \src "libresoc.v:10431.5-10431.29" + switch \initial + attribute \src "libresoc.v:10431.9-10431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45" + switch \dec_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 + assign { } { } + assign $1\is_priv_insn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 , 7'0110001 + assign { } { } + assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" + switch \tmp_tmp_insn [20] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\is_priv_insn[0:0] 1'1 + case + assign $2\is_priv_insn[0:0] 1'0 + end + case + assign $1\is_priv_insn[0:0] 1'0 + end + sync always + update \is_priv_insn $0\is_priv_insn[0:0] + end + attribute \src "libresoc.v:10450.3-10607.6" + process $proc$libresoc.v:10450$305 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_out[2:0] $1\cr_out[2:0] + assign $0\lk[0:0] $1\lk[0:0] + assign $0\cia[63:0] $1\cia[63:0] + assign $0\cr_in1[2:0] $1\cr_in1[2:0] + assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] + assign $0\cr_in2[2:0] $1\cr_in2[2:0] + assign $0\cr_in2$1[2:0]$306 $1\cr_in2$1[2:0]$316 + assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] + assign $0\cr_in2_ok$2[0:0]$307 $1\cr_in2_ok$2[0:0]$317 + assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] + assign $0\cr_rd[7:0] $1\cr_rd[7:0] + assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] + assign $0\cr_wr[7:0] $1\cr_wr[7:0] + assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] + assign $0\ea[4:0] $1\ea[4:0] + assign $0\ea_ok[0:0] $1\ea_ok[0:0] + assign $0\exc_$signal[0:0]$308 $1\exc_$signal[0:0]$318 + assign $0\exc_$signal$3[0:0]$309 $1\exc_$signal$3[0:0]$319 + assign $0\exc_$signal$4[0:0]$310 $1\exc_$signal$4[0:0]$320 + assign $0\exc_$signal$5[0:0]$311 $1\exc_$signal$5[0:0]$321 + assign $0\exc_$signal$6[0:0]$312 $1\exc_$signal$6[0:0]$322 + assign $0\exc_$signal$7[0:0]$313 $1\exc_$signal$7[0:0]$323 + assign $0\exc_$signal$8[0:0]$314 $1\exc_$signal$8[0:0]$324 + assign $0\exc_$signal$9[0:0]$315 $1\exc_$signal$9[0:0]$325 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fn_unit[11:0] $1\fn_unit[11:0] + assign $0\input_carry[1:0] $1\input_carry[1:0] + assign $0\insn[31:0] $1\insn[31:0] + assign $0\insn_type[6:0] $1\insn_type[6:0] + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + assign $0\msr[63:0] $1\msr[63:0] + assign $0\oe[0:0] $1\oe[0:0] + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + assign $0\rc[0:0] $1\rc[0:0] + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + assign $0\reg1[4:0] $1\reg1[4:0] + assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] + assign $0\reg2[4:0] $1\reg2[4:0] + assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] + assign $0\reg3[4:0] $1\reg3[4:0] + assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] + assign $0\rego[4:0] $1\rego[4:0] + assign $0\rego_ok[0:0] $1\rego_ok[0:0] + assign $0\spr1[9:0] $1\spr1[9:0] + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + assign $0\spro[9:0] $1\spro[9:0] + assign $0\spro_ok[0:0] $1\spro_ok[0:0] + assign $0\trapaddr[12:0] $1\trapaddr[12:0] + assign $0\traptype[7:0] $1\traptype[7:0] + assign $0\xer_in[2:0] $1\xer_in[2:0] + assign $0\xer_out[0:0] $1\xer_out[0:0] + assign $0\fasto1[2:0] $5\fasto1[2:0] + assign $0\fasto1_ok[0:0] $5\fasto1_ok[0:0] + assign $0\fasto2[2:0] $5\fasto2[2:0] + assign $0\fasto2_ok[0:0] $5\fasto2_ok[0:0] + assign $0\fast1[2:0] $5\fast1[2:0] + assign $0\fast1_ok[0:0] $5\fast1_ok[0:0] + assign $0\fast2[2:0] $5\fast2[2:0] + assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] + assign $0\asmcode[7:0] \dec_asmcode + attribute \src "libresoc.v:10451.5-10451.29" + switch \initial + attribute \src "libresoc.v:10451.9-10451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:916" + switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } + attribute \src "libresoc.v:0.0-0.0" + case 5'----1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\asmcode[7:0] $2\asmcode[7:0] + assign $1\cr_out[2:0] $2\cr_out[2:0] + assign $1\lk[0:0] $2\lk[0:0] + assign $1\cia[63:0] $2\cia[63:0] + assign $1\cr_in1[2:0] $2\cr_in1[2:0] + assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] + assign $1\cr_in2[2:0] $2\cr_in2[2:0] + assign $1\cr_in2$1[2:0]$316 $2\cr_in2$1[2:0]$326 + assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] + assign $1\cr_in2_ok$2[0:0]$317 $2\cr_in2_ok$2[0:0]$327 + assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] + assign $1\cr_rd[7:0] $2\cr_rd[7:0] + assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] + assign $1\cr_wr[7:0] $2\cr_wr[7:0] + assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] + assign $1\ea[4:0] $2\ea[4:0] + assign $1\ea_ok[0:0] $2\ea_ok[0:0] + assign $1\exc_$signal[0:0]$318 $2\exc_$signal[0:0]$328 + assign $1\exc_$signal$3[0:0]$319 $2\exc_$signal$3[0:0]$329 + assign $1\exc_$signal$4[0:0]$320 $2\exc_$signal$4[0:0]$330 + assign $1\exc_$signal$5[0:0]$321 $2\exc_$signal$5[0:0]$331 + assign $1\exc_$signal$6[0:0]$322 $2\exc_$signal$6[0:0]$332 + assign $1\exc_$signal$7[0:0]$323 $2\exc_$signal$7[0:0]$333 + assign $1\exc_$signal$8[0:0]$324 $2\exc_$signal$8[0:0]$334 + assign $1\exc_$signal$9[0:0]$325 $2\exc_$signal$9[0:0]$335 + assign $1\fast1[2:0] $2\fast1[2:0] + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + assign $1\fast2[2:0] $2\fast2[2:0] + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + assign $1\fasto1[2:0] $2\fasto1[2:0] + assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] + assign $1\fasto2[2:0] $2\fasto2[2:0] + assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0] + assign $1\fn_unit[11:0] $2\fn_unit[11:0] + assign $1\input_carry[1:0] $2\input_carry[1:0] + assign $1\insn[31:0] $2\insn[31:0] + assign $1\insn_type[6:0] $2\insn_type[6:0] + assign $1\is_32bit[0:0] $2\is_32bit[0:0] + assign $1\msr[63:0] $2\msr[63:0] + assign $1\oe[0:0] $2\oe[0:0] + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + assign $1\rc[0:0] $2\rc[0:0] + assign $1\rc_ok[0:0] $2\rc_ok[0:0] + assign $1\reg1[4:0] $2\reg1[4:0] + assign $1\reg1_ok[0:0] $2\reg1_ok[0:0] + assign $1\reg2[4:0] $2\reg2[4:0] + assign $1\reg2_ok[0:0] $2\reg2_ok[0:0] + assign $1\reg3[4:0] $2\reg3[4:0] + assign $1\reg3_ok[0:0] $2\reg3_ok[0:0] + assign $1\rego[4:0] $2\rego[4:0] + assign $1\rego_ok[0:0] $2\rego_ok[0:0] + assign $1\spr1[9:0] $2\spr1[9:0] + assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] + assign $1\spro[9:0] $2\spro[9:0] + assign $1\spro_ok[0:0] $2\spro_ok[0:0] + assign $1\trapaddr[12:0] $2\trapaddr[12:0] + assign $1\traptype[7:0] $2\traptype[7:0] + assign $1\xer_in[2:0] $2\xer_in[2:0] + assign $1\xer_out[0:0] $2\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$335 $2\exc_$signal$8[0:0]$334 $2\exc_$signal$7[0:0]$333 $2\exc_$signal$6[0:0]$332 $2\exc_$signal$5[0:0]$331 $2\exc_$signal$4[0:0]$330 $2\exc_$signal$3[0:0]$329 $2\exc_$signal[0:0]$328 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[2:0] $2\cr_in2_ok$2[0:0]$327 $2\cr_in2$1[2:0]$326 $2\cr_in2_ok[0:0] $2\cr_in2[2:0] $2\cr_in1_ok[0:0] $2\cr_in1[2:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[4:0] $2\reg2_ok[0:0] $2\reg2[4:0] $2\reg1_ok[0:0] $2\reg1[4:0] $2\ea_ok[0:0] $2\ea[4:0] $2\rego_ok[0:0] $2\rego[4:0] $2\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\insn[31:0] \dec_opcode_in + assign $2\insn_type[6:0] 7'0111111 + assign $2\fn_unit[11:0] 12'000010000000 + assign $2\trapaddr[12:0] 13'0000001100000 + assign $2\traptype[7:0] 8'00000010 + assign $2\msr[63:0] \cur_msr + assign $2\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\asmcode[7:0] $3\asmcode[7:0] + assign $2\cr_out[2:0] $3\cr_out[2:0] + assign $2\lk[0:0] $3\lk[0:0] + assign $2\cia[63:0] $3\cia[63:0] + assign $2\cr_in1[2:0] $3\cr_in1[2:0] + assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] + assign $2\cr_in2[2:0] $3\cr_in2[2:0] + assign $2\cr_in2$1[2:0]$326 $3\cr_in2$1[2:0]$336 + assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$327 $3\cr_in2_ok$2[0:0]$337 + assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $3\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $3\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] + assign $2\ea[4:0] $3\ea[4:0] + assign $2\ea_ok[0:0] $3\ea_ok[0:0] + assign $2\exc_$signal[0:0]$328 $3\exc_$signal[0:0]$338 + assign $2\exc_$signal$3[0:0]$329 $3\exc_$signal$3[0:0]$339 + assign $2\exc_$signal$4[0:0]$330 $3\exc_$signal$4[0:0]$340 + assign $2\exc_$signal$5[0:0]$331 $3\exc_$signal$5[0:0]$341 + assign $2\exc_$signal$6[0:0]$332 $3\exc_$signal$6[0:0]$342 + assign $2\exc_$signal$7[0:0]$333 $3\exc_$signal$7[0:0]$343 + assign $2\exc_$signal$8[0:0]$334 $3\exc_$signal$8[0:0]$344 + assign $2\exc_$signal$9[0:0]$335 $3\exc_$signal$9[0:0]$345 + assign $2\fast1[2:0] $3\fast1[2:0] + assign $2\fast1_ok[0:0] $3\fast1_ok[0:0] + assign $2\fast2[2:0] $3\fast2[2:0] + assign $2\fast2_ok[0:0] $3\fast2_ok[0:0] + assign $2\fasto1[2:0] $3\fasto1[2:0] + assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] + assign $2\fasto2[2:0] $3\fasto2[2:0] + assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0] + assign $2\fn_unit[11:0] $3\fn_unit[11:0] + assign $2\input_carry[1:0] $3\input_carry[1:0] + assign $2\insn[31:0] $3\insn[31:0] + assign $2\insn_type[6:0] $3\insn_type[6:0] + assign $2\is_32bit[0:0] $3\is_32bit[0:0] + assign $2\msr[63:0] $3\msr[63:0] + assign $2\oe[0:0] $3\oe[0:0] + assign $2\oe_ok[0:0] $3\oe_ok[0:0] + assign $2\rc[0:0] $3\rc[0:0] + assign $2\rc_ok[0:0] $3\rc_ok[0:0] + assign $2\reg1[4:0] $3\reg1[4:0] + assign $2\reg1_ok[0:0] $3\reg1_ok[0:0] + assign $2\reg2[4:0] $3\reg2[4:0] + assign $2\reg2_ok[0:0] $3\reg2_ok[0:0] + assign $2\reg3[4:0] $3\reg3[4:0] + assign $2\reg3_ok[0:0] $3\reg3_ok[0:0] + assign $2\rego[4:0] $3\rego[4:0] + assign $2\rego_ok[0:0] $3\rego_ok[0:0] + assign $2\spr1[9:0] $3\spr1[9:0] + assign $2\spr1_ok[0:0] $3\spr1_ok[0:0] + assign $2\spro[9:0] $3\spro[9:0] + assign $2\spro_ok[0:0] $3\spro_ok[0:0] + assign $2\trapaddr[12:0] $3\trapaddr[12:0] + assign $2\traptype[7:0] $3\traptype[7:0] + assign $2\xer_in[2:0] $3\xer_in[2:0] + assign $2\xer_out[0:0] $3\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$345 $3\exc_$signal$8[0:0]$344 $3\exc_$signal$7[0:0]$343 $3\exc_$signal$6[0:0]$342 $3\exc_$signal$5[0:0]$341 $3\exc_$signal$4[0:0]$340 $3\exc_$signal$3[0:0]$339 $3\exc_$signal[0:0]$338 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$337 $3\cr_in2$1[2:0]$336 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[11:0] 12'000010000000 + assign $3\trapaddr[12:0] 13'0000001001000 + assign $3\traptype[7:0] 8'00000010 + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$337 $3\cr_in2$1[2:0]$336 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[11:0] 12'000010000000 + assign $3\trapaddr[12:0] 13'0000001000000 + assign $3\traptype[7:0] 8'01000000 + assign { $3\exc_$signal$9[0:0]$345 $3\exc_$signal$8[0:0]$344 $3\exc_$signal$7[0:0]$343 $3\exc_$signal$6[0:0]$342 $3\exc_$signal$5[0:0]$341 $3\exc_$signal$4[0:0]$340 $3\exc_$signal$3[0:0]$339 $3\exc_$signal[0:0]$338 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\asmcode[7:0] $4\asmcode[7:0] + assign $2\cr_out[2:0] $4\cr_out[2:0] + assign $2\lk[0:0] $4\lk[0:0] + assign $2\cia[63:0] $4\cia[63:0] + assign $2\cr_in1[2:0] $4\cr_in1[2:0] + assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] + assign $2\cr_in2[2:0] $4\cr_in2[2:0] + assign $2\cr_in2$1[2:0]$326 $4\cr_in2$1[2:0]$346 + assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$327 $4\cr_in2_ok$2[0:0]$347 + assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $4\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $4\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] + assign $2\ea[4:0] $4\ea[4:0] + assign $2\ea_ok[0:0] $4\ea_ok[0:0] + assign $2\exc_$signal[0:0]$328 $4\exc_$signal[0:0]$348 + assign $2\exc_$signal$3[0:0]$329 $4\exc_$signal$3[0:0]$349 + assign $2\exc_$signal$4[0:0]$330 $4\exc_$signal$4[0:0]$350 + assign $2\exc_$signal$5[0:0]$331 $4\exc_$signal$5[0:0]$351 + assign $2\exc_$signal$6[0:0]$332 $4\exc_$signal$6[0:0]$352 + assign $2\exc_$signal$7[0:0]$333 $4\exc_$signal$7[0:0]$353 + assign $2\exc_$signal$8[0:0]$334 $4\exc_$signal$8[0:0]$354 + assign $2\exc_$signal$9[0:0]$335 $4\exc_$signal$9[0:0]$355 + assign $2\fast1[2:0] $4\fast1[2:0] + assign $2\fast1_ok[0:0] $4\fast1_ok[0:0] + assign $2\fast2[2:0] $4\fast2[2:0] + assign $2\fast2_ok[0:0] $4\fast2_ok[0:0] + assign $2\fasto1[2:0] $4\fasto1[2:0] + assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] + assign $2\fasto2[2:0] $4\fasto2[2:0] + assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0] + assign $2\fn_unit[11:0] $4\fn_unit[11:0] + assign $2\input_carry[1:0] $4\input_carry[1:0] + assign $2\insn[31:0] $4\insn[31:0] + assign $2\insn_type[6:0] $4\insn_type[6:0] + assign $2\is_32bit[0:0] $4\is_32bit[0:0] + assign $2\msr[63:0] $4\msr[63:0] + assign $2\oe[0:0] $4\oe[0:0] + assign $2\oe_ok[0:0] $4\oe_ok[0:0] + assign $2\rc[0:0] $4\rc[0:0] + assign $2\rc_ok[0:0] $4\rc_ok[0:0] + assign $2\reg1[4:0] $4\reg1[4:0] + assign $2\reg1_ok[0:0] $4\reg1_ok[0:0] + assign $2\reg2[4:0] $4\reg2[4:0] + assign $2\reg2_ok[0:0] $4\reg2_ok[0:0] + assign $2\reg3[4:0] $4\reg3[4:0] + assign $2\reg3_ok[0:0] $4\reg3_ok[0:0] + assign $2\rego[4:0] $4\rego[4:0] + assign $2\rego_ok[0:0] $4\rego_ok[0:0] + assign $2\spr1[9:0] $4\spr1[9:0] + assign $2\spr1_ok[0:0] $4\spr1_ok[0:0] + assign $2\spro[9:0] $4\spro[9:0] + assign $2\spro_ok[0:0] $4\spro_ok[0:0] + assign $2\trapaddr[12:0] $4\trapaddr[12:0] + assign $2\traptype[7:0] $4\traptype[7:0] + assign $2\xer_in[2:0] $4\xer_in[2:0] + assign $2\xer_out[0:0] $4\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:926" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$355 $4\exc_$signal$8[0:0]$354 $4\exc_$signal$7[0:0]$353 $4\exc_$signal$6[0:0]$352 $4\exc_$signal$5[0:0]$351 $4\exc_$signal$4[0:0]$350 $4\exc_$signal$3[0:0]$349 $4\exc_$signal[0:0]$348 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$347 $4\cr_in2$1[2:0]$346 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[11:0] 12'000010000000 + assign $4\trapaddr[12:0] 13'0000000111000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$355 $4\exc_$signal$8[0:0]$354 $4\exc_$signal$7[0:0]$353 $4\exc_$signal$6[0:0]$352 $4\exc_$signal$5[0:0]$351 $4\exc_$signal$4[0:0]$350 $4\exc_$signal$3[0:0]$349 $4\exc_$signal[0:0]$348 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$347 $4\cr_in2$1[2:0]$346 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[11:0] 12'000010000000 + assign $4\trapaddr[12:0] 13'0000000110000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + end + end + attribute \src "libresoc.v:0.0-0.0" + case 5'---1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000010010000 + assign $1\traptype[7:0] 8'00100000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'--1-- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001010000 + assign $1\traptype[7:0] 8'00010000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'-1--- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[7:0] 8'00000010 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'1---- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[7:0] 8'10000000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + switch \$32 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $5\fasto1[2:0] 3'011 + assign $5\fasto1_ok[0:0] 1'1 + assign $5\fasto2[2:0] 3'100 + assign $5\fasto2_ok[0:0] 1'1 + case + assign $5\fasto1[2:0] $1\fasto1[2:0] + assign $5\fasto1_ok[0:0] $1\fasto1_ok[0:0] + assign $5\fasto2[2:0] $1\fasto2[2:0] + assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $5\fast1[2:0] 3'011 + assign $5\fast1_ok[0:0] 1'1 + assign $5\fast2[2:0] 3'100 + assign $5\fast2_ok[0:0] 1'1 + case + assign $5\fast1[2:0] $1\fast1[2:0] + assign $5\fast1_ok[0:0] $1\fast1_ok[0:0] + assign $5\fast2[2:0] $1\fast2[2:0] + assign $5\fast2_ok[0:0] $1\fast2_ok[0:0] + end + sync always + update \asmcode $0\asmcode[7:0] + update \cr_out $0\cr_out[2:0] + update \lk $0\lk[0:0] + update \cia $0\cia[63:0] + update \cr_in1 $0\cr_in1[2:0] + update \cr_in1_ok $0\cr_in1_ok[0:0] + update \cr_in2 $0\cr_in2[2:0] + update \cr_in2$1 $0\cr_in2$1[2:0]$306 + update \cr_in2_ok $0\cr_in2_ok[0:0] + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$307 + update \cr_out_ok $0\cr_out_ok[0:0] + update \cr_rd $0\cr_rd[7:0] + update \cr_rd_ok $0\cr_rd_ok[0:0] + update \cr_wr $0\cr_wr[7:0] + update \cr_wr_ok $0\cr_wr_ok[0:0] + update \ea $0\ea[4:0] + update \ea_ok $0\ea_ok[0:0] + update \exc_$signal $0\exc_$signal[0:0]$308 + update \exc_$signal$3 $0\exc_$signal$3[0:0]$309 + update \exc_$signal$4 $0\exc_$signal$4[0:0]$310 + update \exc_$signal$5 $0\exc_$signal$5[0:0]$311 + update \exc_$signal$6 $0\exc_$signal$6[0:0]$312 + update \exc_$signal$7 $0\exc_$signal$7[0:0]$313 + update \exc_$signal$8 $0\exc_$signal$8[0:0]$314 + update \exc_$signal$9 $0\exc_$signal$9[0:0]$315 + update \fast1 $0\fast1[2:0] + update \fast1_ok $0\fast1_ok[0:0] + update \fast2 $0\fast2[2:0] + update \fast2_ok $0\fast2_ok[0:0] + update \fasto1 $0\fasto1[2:0] + update \fasto1_ok $0\fasto1_ok[0:0] + update \fasto2 $0\fasto2[2:0] + update \fasto2_ok $0\fasto2_ok[0:0] + update \fn_unit $0\fn_unit[11:0] + update \input_carry $0\input_carry[1:0] + update \insn $0\insn[31:0] + update \insn_type $0\insn_type[6:0] + update \is_32bit $0\is_32bit[0:0] + update \msr $0\msr[63:0] + update \oe $0\oe[0:0] + update \oe_ok $0\oe_ok[0:0] + update \rc $0\rc[0:0] + update \rc_ok $0\rc_ok[0:0] + update \reg1 $0\reg1[4:0] + update \reg1_ok $0\reg1_ok[0:0] + update \reg2 $0\reg2[4:0] + update \reg2_ok $0\reg2_ok[0:0] + update \reg3 $0\reg3[4:0] + update \reg3_ok $0\reg3_ok[0:0] + update \rego $0\rego[4:0] + update \rego_ok $0\rego_ok[0:0] + update \spr1 $0\spr1[9:0] + update \spr1_ok $0\spr1_ok[0:0] + update \spro $0\spro[9:0] + update \spro_ok $0\spro_ok[0:0] + update \trapaddr $0\trapaddr[12:0] + update \traptype $0\traptype[7:0] + update \xer_in $0\xer_in[2:0] + update \xer_out $0\xer_out[0:0] + end + attribute \src "libresoc.v:8640.7-8640.20" + process $proc$libresoc.v:8640$356 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \$28 $eq$libresoc.v:10231$288_Y + connect \$30 $eq$libresoc.v:10232$289_Y + connect \$32 $or$libresoc.v:10233$290_Y + connect \$34 $eq$libresoc.v:10234$291_Y + connect \$42 $eq$libresoc.v:10235$292_Y + connect \$44 $eq$libresoc.v:10236$293_Y + connect \$46 $eq$libresoc.v:10237$294_Y + connect \$48 $eq$libresoc.v:10238$295_Y + connect \$50 $and$libresoc.v:10239$296_Y + connect \$52 $and$libresoc.v:10240$297_Y + connect \$54 $and$libresoc.v:10241$298_Y + connect \$56 $eq$libresoc.v:10242$299_Y + connect \dec2_exc_$signal 1'0 + connect \dec2_exc_$signal$12 1'0 + connect \dec2_exc_$signal$13 1'0 + connect \dec2_exc_$signal$14 1'0 + connect \dec2_exc_$signal$15 1'0 + connect \dec2_exc_$signal$16 1'0 + connect \dec2_exc_$signal$17 1'0 + connect \dec2_exc_$signal$18 1'0 + connect \tmp_asmcode 8'00000000 + connect \tmp_tmp_traptype 8'00000000 + connect \tmp_tmp_exc_$signal 1'0 + connect \tmp_tmp_exc_$signal$21 1'0 + connect \tmp_tmp_exc_$signal$22 1'0 + connect \tmp_tmp_exc_$signal$23 1'0 + connect \tmp_tmp_exc_$signal$24 1'0 + connect \tmp_tmp_exc_$signal$25 1'0 + connect \tmp_tmp_exc_$signal$26 1'0 + connect \tmp_tmp_exc_$signal$27 1'0 + connect \illeg_ok \$56 + connect \priv_ok \$54 + connect \dec_irq_ok \$52 + connect \ext_irq_ok \$50 + connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } + connect { \tmp_cr_in2_ok$20 \tmp_cr_in2$19 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } + connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } + connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } + connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } + connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } + connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } + connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } + connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } + connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } + connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } + connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } + connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } + connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } + connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } + connect \dec_o2_lk \tmp_tmp_lk + connect \sel_in \dec_out_sel + connect \dec_o_sel_in \dec_out_sel + connect \dec_c_sel_in \dec_in3_sel + connect \dec_b_sel_in \dec_in2_sel + connect \dec_a_sel_in \dec_in1_sel + connect \insn_in$41 \dec_opcode_in + connect \insn_in$40 \dec_opcode_in + connect \insn_in$39 \dec_opcode_in + connect \insn_in$38 \dec_opcode_in + connect \insn_in$37 \dec_opcode_in + connect \tmp_tmp_insn \dec_opcode_in + connect \tmp_tmp_is_32bit \dec_is_32b + connect \tmp_tmp_input_carry \dec_cry_in + connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } + connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } + connect \tmp_tmp_fn_unit \dec_function_unit + connect \tmp_tmp_insn_type \dec_internal_op + connect \tmp_tmp_cia \cur_pc + connect \tmp_tmp_msr \cur_msr + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_cr_out + connect \dec_cr_in_sel_in \dec_cr_in + connect \dec_oe_sel_in \dec_rc_sel + connect \dec_rc_sel_in \dec_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$36 \dec_opcode_in + connect \insn_in \dec_opcode_in +end +attribute \src "libresoc.v:10680.1-11827.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" +attribute \generator "nMigen" +module \dec30 + attribute \src "libresoc.v:11123.3-11159.6" + wire width 8 $0\dec30_asmcode[7:0] + attribute \src "libresoc.v:11271.3-11307.6" + wire $0\dec30_br[0:0] + attribute \src "libresoc.v:11752.3-11788.6" + wire width 3 $0\dec30_cr_in[2:0] + attribute \src "libresoc.v:11789.3-11825.6" + wire width 3 $0\dec30_cr_out[2:0] + attribute \src "libresoc.v:11086.3-11122.6" + wire width 2 $0\dec30_cry_in[1:0] + attribute \src "libresoc.v:11234.3-11270.6" + wire $0\dec30_cry_out[0:0] + attribute \src "libresoc.v:11567.3-11603.6" + wire width 5 $0\dec30_form[4:0] + attribute \src "libresoc.v:10938.3-10974.6" + wire width 12 $0\dec30_function_unit[11:0] + attribute \src "libresoc.v:11604.3-11640.6" + wire width 3 $0\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11641.3-11677.6" + wire width 4 $0\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11678.3-11714.6" + wire width 2 $0\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11345.3-11381.6" + wire width 7 $0\dec30_internal_op[6:0] + attribute \src "libresoc.v:11160.3-11196.6" + wire $0\dec30_inv_a[0:0] + attribute \src "libresoc.v:11197.3-11233.6" + wire $0\dec30_inv_out[0:0] + attribute \src "libresoc.v:11419.3-11455.6" + wire $0\dec30_is_32b[0:0] + attribute \src "libresoc.v:10975.3-11011.6" + wire width 4 $0\dec30_ldst_len[3:0] + attribute \src "libresoc.v:11493.3-11529.6" + wire $0\dec30_lk[0:0] + attribute \src "libresoc.v:11715.3-11751.6" + wire width 2 $0\dec30_out_sel[1:0] + attribute \src "libresoc.v:11049.3-11085.6" + wire width 2 $0\dec30_rc_sel[1:0] + attribute \src "libresoc.v:11382.3-11418.6" + wire $0\dec30_rsrv[0:0] + attribute \src "libresoc.v:11530.3-11566.6" + wire $0\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11456.3-11492.6" + wire $0\dec30_sgn[0:0] + attribute \src "libresoc.v:11308.3-11344.6" + wire $0\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:11012.3-11048.6" + wire width 2 $0\dec30_upd[1:0] + attribute \src "libresoc.v:10681.7-10681.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:11123.3-11159.6" + wire width 8 $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:11271.3-11307.6" + wire $1\dec30_br[0:0] + attribute \src "libresoc.v:11752.3-11788.6" + wire width 3 $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:11789.3-11825.6" + wire width 3 $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:11086.3-11122.6" + wire width 2 $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:11234.3-11270.6" + wire $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:11567.3-11603.6" + wire width 5 $1\dec30_form[4:0] + attribute \src "libresoc.v:10938.3-10974.6" + wire width 12 $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:11604.3-11640.6" + wire width 3 $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11641.3-11677.6" + wire width 4 $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11678.3-11714.6" + wire width 2 $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11345.3-11381.6" + wire width 7 $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:11160.3-11196.6" + wire $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:11197.3-11233.6" + wire $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:11419.3-11455.6" + wire $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:10975.3-11011.6" + wire width 4 $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:11493.3-11529.6" + wire $1\dec30_lk[0:0] + attribute \src "libresoc.v:11715.3-11751.6" + wire width 2 $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:11049.3-11085.6" + wire width 2 $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:11382.3-11418.6" + wire $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:11530.3-11566.6" + wire $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11456.3-11492.6" + wire $1\dec30_sgn[0:0] + attribute \src "libresoc.v:11308.3-11344.6" + wire $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:11012.3-11048.6" + wire width 2 $1\dec30_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec30_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec30_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec30_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec30_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec30_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec30_upd + attribute \src "libresoc.v:10681.7-10681.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 4 \opcode_switch + attribute \src "libresoc.v:10681.7-10681.20" + process $proc$libresoc.v:10681$381 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:10938.3-10974.6" + process $proc$libresoc.v:10938$357 + assign { } { } + assign { } { } + assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:10939.5-10939.29" + switch \initial + attribute \src "libresoc.v:10939.9-10939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + case + assign $1\dec30_function_unit[11:0] 12'000000000000 + end + sync always + update \dec30_function_unit $0\dec30_function_unit[11:0] + end + attribute \src "libresoc.v:10975.3-11011.6" + process $proc$libresoc.v:10975$358 + assign { } { } + assign { } { } + assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:10976.5-10976.29" + switch \initial + attribute \src "libresoc.v:10976.9-10976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + case + assign $1\dec30_ldst_len[3:0] 4'0000 + end + sync always + update \dec30_ldst_len $0\dec30_ldst_len[3:0] + end + attribute \src "libresoc.v:11012.3-11048.6" + process $proc$libresoc.v:11012$359 + assign { } { } + assign { } { } + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "libresoc.v:11013.5-11013.29" + switch \initial + attribute \src "libresoc.v:11013.9-11013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + case + assign $1\dec30_upd[1:0] 2'00 + end + sync always + update \dec30_upd $0\dec30_upd[1:0] + end + attribute \src "libresoc.v:11049.3-11085.6" + process $proc$libresoc.v:11049$360 + assign { } { } + assign { } { } + assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:11050.5-11050.29" + switch \initial + attribute \src "libresoc.v:11050.9-11050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + case + assign $1\dec30_rc_sel[1:0] 2'00 + end + sync always + update \dec30_rc_sel $0\dec30_rc_sel[1:0] + end + attribute \src "libresoc.v:11086.3-11122.6" + process $proc$libresoc.v:11086$361 + assign { } { } + assign { } { } + assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:11087.5-11087.29" + switch \initial + attribute \src "libresoc.v:11087.9-11087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + case + assign $1\dec30_cry_in[1:0] 2'00 + end + sync always + update \dec30_cry_in $0\dec30_cry_in[1:0] + end + attribute \src "libresoc.v:11123.3-11159.6" + process $proc$libresoc.v:11123$362 + assign { } { } + assign { } { } + assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:11124.5-11124.29" + switch \initial + attribute \src "libresoc.v:11124.9-11124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010011 + case + assign $1\dec30_asmcode[7:0] 8'00000000 + end + sync always + update \dec30_asmcode $0\dec30_asmcode[7:0] + end + attribute \src "libresoc.v:11160.3-11196.6" + process $proc$libresoc.v:11160$363 + assign { } { } + assign { } { } + assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:11161.5-11161.29" + switch \initial + attribute \src "libresoc.v:11161.9-11161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + case + assign $1\dec30_inv_a[0:0] 1'0 + end + sync always + update \dec30_inv_a $0\dec30_inv_a[0:0] + end + attribute \src "libresoc.v:11197.3-11233.6" + process $proc$libresoc.v:11197$364 + assign { } { } + assign { } { } + assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:11198.5-11198.29" + switch \initial + attribute \src "libresoc.v:11198.9-11198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + case + assign $1\dec30_inv_out[0:0] 1'0 + end + sync always + update \dec30_inv_out $0\dec30_inv_out[0:0] + end + attribute \src "libresoc.v:11234.3-11270.6" + process $proc$libresoc.v:11234$365 + assign { } { } + assign { } { } + assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:11235.5-11235.29" + switch \initial + attribute \src "libresoc.v:11235.9-11235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + case + assign $1\dec30_cry_out[0:0] 1'0 + end + sync always + update \dec30_cry_out $0\dec30_cry_out[0:0] + end + attribute \src "libresoc.v:11271.3-11307.6" + process $proc$libresoc.v:11271$366 + assign { } { } + assign { } { } + assign $0\dec30_br[0:0] $1\dec30_br[0:0] + attribute \src "libresoc.v:11272.5-11272.29" + switch \initial + attribute \src "libresoc.v:11272.9-11272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + case + assign $1\dec30_br[0:0] 1'0 + end + sync always + update \dec30_br $0\dec30_br[0:0] + end + attribute \src "libresoc.v:11308.3-11344.6" + process $proc$libresoc.v:11308$367 + assign { } { } + assign { } { } + assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:11309.5-11309.29" + switch \initial + attribute \src "libresoc.v:11309.9-11309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + case + assign $1\dec30_sgn_ext[0:0] 1'0 + end + sync always + update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] + end + attribute \src "libresoc.v:11345.3-11381.6" + process $proc$libresoc.v:11345$368 + assign { } { } + assign { } { } + assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:11346.5-11346.29" + switch \initial + attribute \src "libresoc.v:11346.9-11346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + case + assign $1\dec30_internal_op[6:0] 7'0000000 + end + sync always + update \dec30_internal_op $0\dec30_internal_op[6:0] + end + attribute \src "libresoc.v:11382.3-11418.6" + process $proc$libresoc.v:11382$369 + assign { } { } + assign { } { } + assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:11383.5-11383.29" + switch \initial + attribute \src "libresoc.v:11383.9-11383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + case + assign $1\dec30_rsrv[0:0] 1'0 + end + sync always + update \dec30_rsrv $0\dec30_rsrv[0:0] + end + attribute \src "libresoc.v:11419.3-11455.6" + process $proc$libresoc.v:11419$370 + assign { } { } + assign { } { } + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:11420.5-11420.29" + switch \initial + attribute \src "libresoc.v:11420.9-11420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + case + assign $1\dec30_is_32b[0:0] 1'0 + end + sync always + update \dec30_is_32b $0\dec30_is_32b[0:0] + end + attribute \src "libresoc.v:11456.3-11492.6" + process $proc$libresoc.v:11456$371 + assign { } { } + assign { } { } + assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] + attribute \src "libresoc.v:11457.5-11457.29" + switch \initial + attribute \src "libresoc.v:11457.9-11457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + case + assign $1\dec30_sgn[0:0] 1'0 + end + sync always + update \dec30_sgn $0\dec30_sgn[0:0] + end + attribute \src "libresoc.v:11493.3-11529.6" + process $proc$libresoc.v:11493$372 + assign { } { } + assign { } { } + assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] + attribute \src "libresoc.v:11494.5-11494.29" + switch \initial + attribute \src "libresoc.v:11494.9-11494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + case + assign $1\dec30_lk[0:0] 1'0 + end + sync always + update \dec30_lk $0\dec30_lk[0:0] + end + attribute \src "libresoc.v:11530.3-11566.6" + process $proc$libresoc.v:11530$373 + assign { } { } + assign { } { } + assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11531.5-11531.29" + switch \initial + attribute \src "libresoc.v:11531.9-11531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + case + assign $1\dec30_sgl_pipe[0:0] 1'0 + end + sync always + update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] + end + attribute \src "libresoc.v:11567.3-11603.6" + process $proc$libresoc.v:11567$374 + assign { } { } + assign { } { } + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "libresoc.v:11568.5-11568.29" + switch \initial + attribute \src "libresoc.v:11568.9-11568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + case + assign $1\dec30_form[4:0] 5'00000 + end + sync always + update \dec30_form $0\dec30_form[4:0] + end + attribute \src "libresoc.v:11604.3-11640.6" + process $proc$libresoc.v:11604$375 + assign { } { } + assign { } { } + assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11605.5-11605.29" + switch \initial + attribute \src "libresoc.v:11605.9-11605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + case + assign $1\dec30_in1_sel[2:0] 3'000 + end + sync always + update \dec30_in1_sel $0\dec30_in1_sel[2:0] + end + attribute \src "libresoc.v:11641.3-11677.6" + process $proc$libresoc.v:11641$376 + assign { } { } + assign { } { } + assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11642.5-11642.29" + switch \initial + attribute \src "libresoc.v:11642.9-11642.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + case + assign $1\dec30_in2_sel[3:0] 4'0000 + end + sync always + update \dec30_in2_sel $0\dec30_in2_sel[3:0] + end + attribute \src "libresoc.v:11678.3-11714.6" + process $proc$libresoc.v:11678$377 + assign { } { } + assign { } { } + assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11679.5-11679.29" + switch \initial + attribute \src "libresoc.v:11679.9-11679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + case + assign $1\dec30_in3_sel[1:0] 2'00 + end + sync always + update \dec30_in3_sel $0\dec30_in3_sel[1:0] + end + attribute \src "libresoc.v:11715.3-11751.6" + process $proc$libresoc.v:11715$378 + assign { } { } + assign { } { } + assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:11716.5-11716.29" + switch \initial + attribute \src "libresoc.v:11716.9-11716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + case + assign $1\dec30_out_sel[1:0] 2'00 + end + sync always + update \dec30_out_sel $0\dec30_out_sel[1:0] + end + attribute \src "libresoc.v:11752.3-11788.6" + process $proc$libresoc.v:11752$379 + assign { } { } + assign { } { } + assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:11753.5-11753.29" + switch \initial + attribute \src "libresoc.v:11753.9-11753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + case + assign $1\dec30_cr_in[2:0] 3'000 + end + sync always + update \dec30_cr_in $0\dec30_cr_in[2:0] + end + attribute \src "libresoc.v:11789.3-11825.6" + process $proc$libresoc.v:11789$380 + assign { } { } + assign { } { } + assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:11790.5-11790.29" + switch \initial + attribute \src "libresoc.v:11790.9-11790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + case + assign $1\dec30_cr_out[2:0] 3'000 + end + sync always + update \dec30_cr_out $0\dec30_cr_out[2:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:11831.1-18201.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" +attribute \generator "nMigen" +module \dec31 + attribute \src "libresoc.v:16900.3-16960.6" + wire width 8 $0\dec31_asmcode[7:0] + attribute \src "libresoc.v:17754.3-17814.6" + wire $0\dec31_br[0:0] + attribute \src "libresoc.v:17205.3-17265.6" + wire width 3 $0\dec31_cr_in[2:0] + attribute \src "libresoc.v:17266.3-17326.6" + wire width 3 $0\dec31_cr_out[2:0] + attribute \src "libresoc.v:17510.3-17570.6" + wire width 2 $0\dec31_cry_in[1:0] + attribute \src "libresoc.v:17693.3-17753.6" + wire $0\dec31_cry_out[0:0] + attribute \src "libresoc.v:16839.3-16899.6" + wire width 5 $0\dec31_form[4:0] + attribute \src "libresoc.v:16717.3-16777.6" + wire width 12 $0\dec31_function_unit[11:0] + attribute \src "libresoc.v:16961.3-17021.6" + wire width 3 $0\dec31_in1_sel[2:0] + attribute \src "libresoc.v:17022.3-17082.6" + wire width 4 $0\dec31_in2_sel[3:0] + attribute \src "libresoc.v:17083.3-17143.6" + wire width 2 $0\dec31_in3_sel[1:0] + attribute \src "libresoc.v:16778.3-16838.6" + wire width 7 $0\dec31_internal_op[6:0] + attribute \src "libresoc.v:17571.3-17631.6" + wire $0\dec31_inv_a[0:0] + attribute \src "libresoc.v:17632.3-17692.6" + wire $0\dec31_inv_out[0:0] + attribute \src "libresoc.v:17937.3-17997.6" + wire $0\dec31_is_32b[0:0] + attribute \src "libresoc.v:17327.3-17387.6" + wire width 4 $0\dec31_ldst_len[3:0] + attribute \src "libresoc.v:18059.3-18119.6" + wire $0\dec31_lk[0:0] + attribute \src "libresoc.v:17144.3-17204.6" + wire width 2 $0\dec31_out_sel[1:0] + attribute \src "libresoc.v:17449.3-17509.6" + wire width 2 $0\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17876.3-17936.6" + wire $0\dec31_rsrv[0:0] + attribute \src "libresoc.v:18120.3-18180.6" + wire $0\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:17998.3-18058.6" + wire $0\dec31_sgn[0:0] + attribute \src "libresoc.v:17815.3-17875.6" + wire $0\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17388.3-17448.6" + wire width 2 $0\dec31_upd[1:0] + attribute \src "libresoc.v:11832.7-11832.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:16900.3-16960.6" + wire width 8 $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:17754.3-17814.6" + wire $1\dec31_br[0:0] + attribute \src "libresoc.v:17205.3-17265.6" + wire width 3 $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:17266.3-17326.6" + wire width 3 $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:17510.3-17570.6" + wire width 2 $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:17693.3-17753.6" + wire $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:16839.3-16899.6" + wire width 5 $1\dec31_form[4:0] + attribute \src "libresoc.v:16717.3-16777.6" + wire width 12 $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:16961.3-17021.6" + wire width 3 $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:17022.3-17082.6" + wire width 4 $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:17083.3-17143.6" + wire width 2 $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:16778.3-16838.6" + wire width 7 $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:17571.3-17631.6" + wire $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:17632.3-17692.6" + wire $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:17937.3-17997.6" + wire $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:17327.3-17387.6" + wire width 4 $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:18059.3-18119.6" + wire $1\dec31_lk[0:0] + attribute \src "libresoc.v:17144.3-17204.6" + wire width 2 $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:17449.3-17509.6" + wire width 2 $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17876.3-17936.6" + wire $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:18120.3-18180.6" + wire $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:17998.3-18058.6" + wire $1\dec31_sgn[0:0] + attribute \src "libresoc.v:17815.3-17875.6" + wire $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17388.3-17448.6" + wire width 2 $1\dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub0_dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec31_dec_sub0_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub10_dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute 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attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute 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\enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec31_dec_sub9_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_upd + attribute \src "libresoc.v:11832.7-11832.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:16231.18-16257.4" + cell \dec31_dec_sub0 \dec31_dec_sub0 + connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode + connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br + connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in + connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out + connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in + connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out + connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form + connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit + connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel + connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel + connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel + connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op + connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a + connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out + connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b + connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len + connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk + connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel + connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel + connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv + connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn + connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd + connect \opcode_in \dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16258.19-16284.4" + cell \dec31_dec_sub10 \dec31_dec_sub10 + connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode + connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br + connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in + connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out + connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in + connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out + connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form + connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit + connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel + connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel + connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel + connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op + connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a + connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out + connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b + connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len + connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk + connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel + connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel + connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv + connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn + connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd + connect \opcode_in \dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16285.19-16311.4" + cell \dec31_dec_sub11 \dec31_dec_sub11 + connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode + connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br + connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in + connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out + connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in + connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out + connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form + connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit + connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel + connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel + connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel + connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op + connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a + connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out + connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b + connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len + connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk + connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel + connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel + connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv + connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn + connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd + connect \opcode_in \dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16312.19-16338.4" + cell \dec31_dec_sub15 \dec31_dec_sub15 + connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode + connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br + connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in + connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out + connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in + connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out + connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form + connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit + connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel + connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel + connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel + connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op + connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a + connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out + connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b + connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len + connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk + connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel + connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel + connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv + connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn + connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd + connect \opcode_in \dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16339.19-16365.4" + cell \dec31_dec_sub16 \dec31_dec_sub16 + connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode + connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br + connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in + connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out + connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in + connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out + connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form + connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit + connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel + connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel + connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel + connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op + connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a + connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out + connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b + connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len + connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk + connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel + connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel + connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv + connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn + connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd + connect \opcode_in \dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16366.19-16392.4" + cell \dec31_dec_sub18 \dec31_dec_sub18 + connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode + connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br + connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in + connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out + connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in + connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out + connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form + connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit + connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel + connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel + connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel + connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op + connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a + connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out + connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b + connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len + connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk + connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel + connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel + connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv + connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn + connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd + connect \opcode_in \dec31_dec_sub18_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16393.19-16419.4" + cell \dec31_dec_sub19 \dec31_dec_sub19 + connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode + connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br + connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in + connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out + connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in + connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out + connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form + connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit + connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel + connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel + connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel + connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op + connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a + connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out + connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b + connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len + connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk + connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel + connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel + connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv + connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn + connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd + connect \opcode_in \dec31_dec_sub19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16420.19-16446.4" + cell \dec31_dec_sub20 \dec31_dec_sub20 + connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode + connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br + connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in + connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out + connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in + connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out + connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form + connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit + connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel + connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel + connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel + connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op + connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a + connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out + connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b + connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len + connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk + connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel + connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel + connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv + connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn + connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd + connect \opcode_in \dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16447.19-16473.4" + cell \dec31_dec_sub21 \dec31_dec_sub21 + connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode + connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br + connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in + connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out + connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in + connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out + connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form + connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit + connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel + connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel + connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel + connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op + connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a + connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out + connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b + connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len + connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk + connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel + connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel + connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv + connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn + connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd + connect \opcode_in \dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16474.19-16500.4" + cell \dec31_dec_sub22 \dec31_dec_sub22 + connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode + connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br + connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in + connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out + connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in + connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out + connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form + connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit + connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel + connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel + connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel + connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op + connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a + connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out + connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b + connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len + connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk + connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel + connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel + connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv + connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn + connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd + connect \opcode_in \dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16501.19-16527.4" + cell \dec31_dec_sub23 \dec31_dec_sub23 + connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode + connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br + connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in + connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out + connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in + connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out + connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form + connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit + connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel + connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel + connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel + connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op + connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a + connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out + connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b + connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len + connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk + connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel + connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel + connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv + connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn + connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd + connect \opcode_in \dec31_dec_sub23_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16528.19-16554.4" + cell \dec31_dec_sub24 \dec31_dec_sub24 + connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode + connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br + connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in + connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out + connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in + connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out + connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form + connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit + connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel + connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel + connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel + connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op + connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a + connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out + connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b + connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len + connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk + connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel + connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel + connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv + connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn + connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd + connect \opcode_in \dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16555.19-16581.4" + cell \dec31_dec_sub26 \dec31_dec_sub26 + connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode + connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br + connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in + connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out + connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in + connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out + connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form + connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit + connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel + connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel + connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel + connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op + connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a + connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out + connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b + connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len + connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk + connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel + connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel + connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv + connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn + connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd + connect \opcode_in \dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16582.19-16608.4" + cell \dec31_dec_sub27 \dec31_dec_sub27 + connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode + connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br + connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in + connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out + connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in + connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out + connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form + connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit + connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel + connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel + connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel + connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op + connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a + connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out + connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b + connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len + connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk + connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel + connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel + connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv + connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn + connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd + connect \opcode_in \dec31_dec_sub27_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16609.19-16635.4" + cell \dec31_dec_sub28 \dec31_dec_sub28 + connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode + connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br + connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in + connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out + connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in + connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out + connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form + connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit + connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel + connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel + connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel + connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op + connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a + connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out + connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b + connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len + connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk + connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel + connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel + connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv + connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn + connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd + connect \opcode_in \dec31_dec_sub28_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16636.18-16662.4" + cell \dec31_dec_sub4 \dec31_dec_sub4 + connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode + connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br + connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in + connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out + connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in + connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out + connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form + connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit + connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel + connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel + connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel + connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op + connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a + connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out + connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b + connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len + connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk + connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel + connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel + connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv + connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn + connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd + connect \opcode_in \dec31_dec_sub4_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16663.18-16689.4" + cell \dec31_dec_sub8 \dec31_dec_sub8 + connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode + connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br + connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in + connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out + connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in + connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out + connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form + connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit + connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel + connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel + connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel + connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op + connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a + connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out + connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b + connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len + connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk + connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel + connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel + connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv + connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn + connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd + connect \opcode_in \dec31_dec_sub8_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16690.18-16716.4" + cell \dec31_dec_sub9 \dec31_dec_sub9 + connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode + connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br + connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in + connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out + connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in + connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out + connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form + connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit + connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel + connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel + connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel + connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op + connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a + connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out + connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b + connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len + connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk + connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel + connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel + connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv + connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn + connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd + connect \opcode_in \dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:11832.7-11832.20" + process $proc$libresoc.v:11832$406 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:16717.3-16777.6" + process $proc$libresoc.v:16717$382 + assign { } { } + assign { } { } + assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:16718.5-16718.29" + switch \initial + attribute \src "libresoc.v:16718.9-16718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit + case + assign $1\dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_function_unit $0\dec31_function_unit[11:0] + end + attribute \src "libresoc.v:16778.3-16838.6" + process $proc$libresoc.v:16778$383 + assign { } { } + assign { } { } + assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:16779.5-16779.29" + switch \initial + attribute \src "libresoc.v:16779.9-16779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op + case + assign $1\dec31_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_internal_op $0\dec31_internal_op[6:0] + end + attribute \src "libresoc.v:16839.3-16899.6" + process $proc$libresoc.v:16839$384 + assign { } { } + assign { } { } + assign $0\dec31_form[4:0] $1\dec31_form[4:0] + attribute \src "libresoc.v:16840.5-16840.29" + switch \initial + attribute \src "libresoc.v:16840.9-16840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form + case + assign $1\dec31_form[4:0] 5'00000 + end + sync always + update \dec31_form $0\dec31_form[4:0] + end + attribute \src "libresoc.v:16900.3-16960.6" + process $proc$libresoc.v:16900$385 + assign { } { } + assign { } { } + assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:16901.5-16901.29" + switch \initial + attribute \src "libresoc.v:16901.9-16901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode + case + assign $1\dec31_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_asmcode $0\dec31_asmcode[7:0] + end + attribute \src "libresoc.v:16961.3-17021.6" + process $proc$libresoc.v:16961$386 + assign { } { } + assign { } { } + assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:16962.5-16962.29" + switch \initial + attribute \src "libresoc.v:16962.9-16962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel + case + assign $1\dec31_in1_sel[2:0] 3'000 + end + sync always + update \dec31_in1_sel $0\dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:17022.3-17082.6" + process $proc$libresoc.v:17022$387 + assign { } { } + assign { } { } + assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:17023.5-17023.29" + switch \initial + attribute \src "libresoc.v:17023.9-17023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel + case + assign $1\dec31_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_in2_sel $0\dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:17083.3-17143.6" + process $proc$libresoc.v:17083$388 + assign { } { } + assign { } { } + assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:17084.5-17084.29" + switch \initial + attribute \src "libresoc.v:17084.9-17084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel + case + assign $1\dec31_in3_sel[1:0] 2'00 + end + sync always + update \dec31_in3_sel $0\dec31_in3_sel[1:0] + end + attribute \src "libresoc.v:17144.3-17204.6" + process $proc$libresoc.v:17144$389 + assign { } { } + assign { } { } + assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:17145.5-17145.29" + switch \initial + attribute \src "libresoc.v:17145.9-17145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel + case + assign $1\dec31_out_sel[1:0] 2'00 + end + sync always + update \dec31_out_sel $0\dec31_out_sel[1:0] + end + attribute \src "libresoc.v:17205.3-17265.6" + process $proc$libresoc.v:17205$390 + assign { } { } + assign { } { } + assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:17206.5-17206.29" + switch \initial + attribute \src "libresoc.v:17206.9-17206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in + case + assign $1\dec31_cr_in[2:0] 3'000 + end + sync always + update \dec31_cr_in $0\dec31_cr_in[2:0] + end + attribute \src "libresoc.v:17266.3-17326.6" + process $proc$libresoc.v:17266$391 + assign { } { } + assign { } { } + assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:17267.5-17267.29" + switch \initial + attribute \src "libresoc.v:17267.9-17267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out + case + assign $1\dec31_cr_out[2:0] 3'000 + end + sync always + update \dec31_cr_out $0\dec31_cr_out[2:0] + end + attribute \src "libresoc.v:17327.3-17387.6" + process $proc$libresoc.v:17327$392 + assign { } { } + assign { } { } + assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:17328.5-17328.29" + switch \initial + attribute \src "libresoc.v:17328.9-17328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len + case + assign $1\dec31_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_ldst_len $0\dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:17388.3-17448.6" + process $proc$libresoc.v:17388$393 + assign { } { } + assign { } { } + assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] + attribute \src "libresoc.v:17389.5-17389.29" + switch \initial + attribute \src "libresoc.v:17389.9-17389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd + case + assign $1\dec31_upd[1:0] 2'00 + end + sync always + update \dec31_upd $0\dec31_upd[1:0] + end + attribute \src "libresoc.v:17449.3-17509.6" + process $proc$libresoc.v:17449$394 + assign { } { } + assign { } { } + assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17450.5-17450.29" + switch \initial + attribute \src "libresoc.v:17450.9-17450.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel + case + assign $1\dec31_rc_sel[1:0] 2'00 + end + sync always + update \dec31_rc_sel $0\dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:17510.3-17570.6" + process $proc$libresoc.v:17510$395 + assign { } { } + assign { } { } + assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:17511.5-17511.29" + switch \initial + attribute \src "libresoc.v:17511.9-17511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in + case + assign $1\dec31_cry_in[1:0] 2'00 + end + sync always + update \dec31_cry_in $0\dec31_cry_in[1:0] + end + attribute \src "libresoc.v:17571.3-17631.6" + process $proc$libresoc.v:17571$396 + assign { } { } + assign { } { } + assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:17572.5-17572.29" + switch \initial + attribute \src "libresoc.v:17572.9-17572.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a + case + assign $1\dec31_inv_a[0:0] 1'0 + end + sync always + update \dec31_inv_a $0\dec31_inv_a[0:0] + end + attribute \src "libresoc.v:17632.3-17692.6" + process $proc$libresoc.v:17632$397 + assign { } { } + assign { } { } + assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:17633.5-17633.29" + switch \initial + attribute \src "libresoc.v:17633.9-17633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out + case + assign $1\dec31_inv_out[0:0] 1'0 + end + sync always + update \dec31_inv_out $0\dec31_inv_out[0:0] + end + attribute \src "libresoc.v:17693.3-17753.6" + process $proc$libresoc.v:17693$398 + assign { } { } + assign { } { } + assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:17694.5-17694.29" + switch \initial + attribute \src "libresoc.v:17694.9-17694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out + case + assign $1\dec31_cry_out[0:0] 1'0 + end + sync always + update \dec31_cry_out $0\dec31_cry_out[0:0] + end + attribute \src "libresoc.v:17754.3-17814.6" + process $proc$libresoc.v:17754$399 + assign { } { } + assign { } { } + assign $0\dec31_br[0:0] $1\dec31_br[0:0] + attribute \src "libresoc.v:17755.5-17755.29" + switch \initial + attribute \src "libresoc.v:17755.9-17755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br + case + assign $1\dec31_br[0:0] 1'0 + end + sync always + update \dec31_br $0\dec31_br[0:0] + end + attribute \src "libresoc.v:17815.3-17875.6" + process $proc$libresoc.v:17815$400 + assign { } { } + assign { } { } + assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17816.5-17816.29" + switch \initial + attribute \src "libresoc.v:17816.9-17816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + case + assign $1\dec31_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] + end + attribute \src "libresoc.v:17876.3-17936.6" + process $proc$libresoc.v:17876$401 + assign { } { } + assign { } { } + assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:17877.5-17877.29" + switch \initial + attribute \src "libresoc.v:17877.9-17877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv + case + assign $1\dec31_rsrv[0:0] 1'0 + end + sync always + update \dec31_rsrv $0\dec31_rsrv[0:0] + end + attribute \src "libresoc.v:17937.3-17997.6" + process $proc$libresoc.v:17937$402 + assign { } { } + assign { } { } + assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:17938.5-17938.29" + switch \initial + attribute \src "libresoc.v:17938.9-17938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b + case + assign $1\dec31_is_32b[0:0] 1'0 + end + sync always + update \dec31_is_32b $0\dec31_is_32b[0:0] + end + attribute \src "libresoc.v:17998.3-18058.6" + process $proc$libresoc.v:17998$403 + assign { } { } + assign { } { } + assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] + attribute \src "libresoc.v:17999.5-17999.29" + switch \initial + attribute \src "libresoc.v:17999.9-17999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn + case + assign $1\dec31_sgn[0:0] 1'0 + end + sync always + update \dec31_sgn $0\dec31_sgn[0:0] + end + attribute \src "libresoc.v:18059.3-18119.6" + process $proc$libresoc.v:18059$404 + assign { } { } + assign { } { } + assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] + attribute \src "libresoc.v:18060.5-18060.29" + switch \initial + attribute \src "libresoc.v:18060.9-18060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk + case + assign $1\dec31_lk[0:0] 1'0 + end + sync always + update \dec31_lk $0\dec31_lk[0:0] + end + attribute \src "libresoc.v:18120.3-18180.6" + process $proc$libresoc.v:18120$405 + assign { } { } + assign { } { } + assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:18121.5-18121.29" + switch \initial + attribute \src "libresoc.v:18121.9-18121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + case + assign $1\dec31_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] + end + connect \dec31_dec_sub4_opcode_in \opcode_in + connect \dec31_dec_sub24_opcode_in \opcode_in + connect \dec31_dec_sub8_opcode_in \opcode_in + connect \dec31_dec_sub18_opcode_in \opcode_in + connect \dec31_dec_sub16_opcode_in \opcode_in + connect \dec31_dec_sub23_opcode_in \opcode_in + connect \dec31_dec_sub21_opcode_in \opcode_in + connect \dec31_dec_sub20_opcode_in \opcode_in + connect \dec31_dec_sub15_opcode_in \opcode_in + connect \dec31_dec_sub27_opcode_in \opcode_in + connect \dec31_dec_sub11_opcode_in \opcode_in + connect \dec31_dec_sub9_opcode_in \opcode_in + connect \dec31_dec_sub22_opcode_in \opcode_in + connect \dec31_dec_sub19_opcode_in \opcode_in + connect \dec31_dec_sub26_opcode_in \opcode_in + connect \dec31_dec_sub0_opcode_in \opcode_in + connect \dec31_dec_sub28_opcode_in \opcode_in + connect \dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:18205.1-18920.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" +attribute \generator "nMigen" +module \dec31_dec_sub0 + attribute \src "libresoc.v:18558.3-18576.6" + wire width 8 $0\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18634.3-18652.6" + wire $0\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18881.3-18899.6" + wire width 3 $0\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18900.3-18918.6" + wire width 3 $0\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18539.3-18557.6" + wire width 2 $0\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18615.3-18633.6" + wire $0\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18786.3-18804.6" + wire width 5 $0\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18463.3-18481.6" + wire width 12 $0\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18805.3-18823.6" + wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18824.3-18842.6" + wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18843.3-18861.6" + wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18672.3-18690.6" + wire width 7 $0\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18577.3-18595.6" + wire $0\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18596.3-18614.6" + wire $0\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18710.3-18728.6" + wire $0\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18482.3-18500.6" + wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18748.3-18766.6" + wire $0\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18862.3-18880.6" + wire width 2 $0\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18520.3-18538.6" + wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18691.3-18709.6" + wire $0\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18767.3-18785.6" + wire $0\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18729.3-18747.6" + wire $0\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18653.3-18671.6" + wire $0\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18501.3-18519.6" + wire width 2 $0\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:18206.7-18206.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:18558.3-18576.6" + wire width 8 $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18634.3-18652.6" + wire $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18881.3-18899.6" + wire width 3 $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18900.3-18918.6" + wire width 3 $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18539.3-18557.6" + wire width 2 $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18615.3-18633.6" + wire $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18786.3-18804.6" + wire width 5 $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18463.3-18481.6" + wire width 12 $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18805.3-18823.6" + wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18824.3-18842.6" + wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18843.3-18861.6" + wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18672.3-18690.6" + wire width 7 $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18577.3-18595.6" + wire $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18596.3-18614.6" + wire $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18710.3-18728.6" + wire $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18482.3-18500.6" + wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18748.3-18766.6" + wire $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18862.3-18880.6" + wire width 2 $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18520.3-18538.6" + wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18691.3-18709.6" + wire $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18767.3-18785.6" + wire $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18729.3-18747.6" + wire $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18653.3-18671.6" + wire $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18501.3-18519.6" + wire width 2 $1\dec31_dec_sub0_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub0_upd + attribute \src "libresoc.v:18206.7-18206.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:18206.7-18206.20" + process $proc$libresoc.v:18206$431 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:18463.3-18481.6" + process $proc$libresoc.v:18463$407 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18464.5-18464.29" + switch \initial + attribute \src "libresoc.v:18464.9-18464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] + end + attribute \src "libresoc.v:18482.3-18500.6" + process $proc$libresoc.v:18482$408 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18483.5-18483.29" + switch \initial + attribute \src "libresoc.v:18483.9-18483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "libresoc.v:18501.3-18519.6" + process $proc$libresoc.v:18501$409 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:18502.5-18502.29" + switch \initial + attribute \src "libresoc.v:18502.9-18502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] + end + attribute \src "libresoc.v:18520.3-18538.6" + process $proc$libresoc.v:18520$410 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18521.5-18521.29" + switch \initial + attribute \src "libresoc.v:18521.9-18521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "libresoc.v:18539.3-18557.6" + process $proc$libresoc.v:18539$411 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18540.5-18540.29" + switch \initial + attribute \src "libresoc.v:18540.9-18540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] + end + attribute \src "libresoc.v:18558.3-18576.6" + process $proc$libresoc.v:18558$412 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18559.5-18559.29" + switch \initial + attribute \src "libresoc.v:18559.9-18559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 + case + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] + end + attribute \src "libresoc.v:18577.3-18595.6" + process $proc$libresoc.v:18577$413 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18578.5-18578.29" + switch \initial + attribute \src "libresoc.v:18578.9-18578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] + end + attribute \src "libresoc.v:18596.3-18614.6" + process $proc$libresoc.v:18596$414 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18597.5-18597.29" + switch \initial + attribute \src "libresoc.v:18597.9-18597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] + end + attribute \src "libresoc.v:18615.3-18633.6" + process $proc$libresoc.v:18615$415 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18616.5-18616.29" + switch \initial + attribute \src "libresoc.v:18616.9-18616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] + end + attribute \src "libresoc.v:18634.3-18652.6" + process $proc$libresoc.v:18634$416 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18635.5-18635.29" + switch \initial + attribute \src "libresoc.v:18635.9-18635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + case + assign $1\dec31_dec_sub0_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] + end + attribute \src "libresoc.v:18653.3-18671.6" + process $proc$libresoc.v:18653$417 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18654.5-18654.29" + switch \initial + attribute \src "libresoc.v:18654.9-18654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] + end + attribute \src "libresoc.v:18672.3-18690.6" + process $proc$libresoc.v:18672$418 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18673.5-18673.29" + switch \initial + attribute \src "libresoc.v:18673.9-18673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:18691.3-18709.6" + process $proc$libresoc.v:18691$419 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18692.5-18692.29" + switch \initial + attribute \src "libresoc.v:18692.9-18692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] + end + attribute \src "libresoc.v:18710.3-18728.6" + process $proc$libresoc.v:18710$420 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18711.5-18711.29" + switch \initial + attribute \src "libresoc.v:18711.9-18711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] + end + attribute \src "libresoc.v:18729.3-18747.6" + process $proc$libresoc.v:18729$421 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18730.5-18730.29" + switch \initial + attribute \src "libresoc.v:18730.9-18730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] + end + attribute \src "libresoc.v:18748.3-18766.6" + process $proc$libresoc.v:18748$422 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18749.5-18749.29" + switch \initial + attribute \src "libresoc.v:18749.9-18749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] + end + attribute \src "libresoc.v:18767.3-18785.6" + process $proc$libresoc.v:18767$423 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18768.5-18768.29" + switch \initial + attribute \src "libresoc.v:18768.9-18768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] + end + attribute \src "libresoc.v:18786.3-18804.6" + process $proc$libresoc.v:18786$424 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18787.5-18787.29" + switch \initial + attribute \src "libresoc.v:18787.9-18787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'11000 + case + assign $1\dec31_dec_sub0_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + end + attribute \src "libresoc.v:18805.3-18823.6" + process $proc$libresoc.v:18805$425 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18806.5-18806.29" + switch \initial + attribute \src "libresoc.v:18806.9-18806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "libresoc.v:18824.3-18842.6" + process $proc$libresoc.v:18824$426 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18825.5-18825.29" + switch \initial + attribute \src "libresoc.v:18825.9-18825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "libresoc.v:18843.3-18861.6" + process $proc$libresoc.v:18843$427 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18844.5-18844.29" + switch \initial + attribute \src "libresoc.v:18844.9-18844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] + end + attribute \src "libresoc.v:18862.3-18880.6" + process $proc$libresoc.v:18862$428 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18863.5-18863.29" + switch \initial + attribute \src "libresoc.v:18863.9-18863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] + end + attribute \src "libresoc.v:18881.3-18899.6" + process $proc$libresoc.v:18881$429 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18882.5-18882.29" + switch \initial + attribute \src "libresoc.v:18882.9-18882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:18900.3-18918.6" + process $proc$libresoc.v:18900$430 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18901.5-18901.29" + switch \initial + attribute \src "libresoc.v:18901.9-18901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:18924.1-20071.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" +attribute \generator "nMigen" +module \dec31_dec_sub10 + attribute \src "libresoc.v:19367.3-19403.6" + wire width 8 $0\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19515.3-19551.6" + wire $0\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:19996.3-20032.6" + wire width 3 $0\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:20033.3-20069.6" + wire width 3 $0\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:19330.3-19366.6" + wire width 2 $0\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19478.3-19514.6" + wire $0\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19811.3-19847.6" + wire width 5 $0\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19182.3-19218.6" + wire width 12 $0\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19848.3-19884.6" + wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19885.3-19921.6" + wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19922.3-19958.6" + wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19589.3-19625.6" + wire width 7 $0\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19404.3-19440.6" + wire $0\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19441.3-19477.6" + wire $0\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19663.3-19699.6" + wire $0\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19219.3-19255.6" + wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19737.3-19773.6" + wire $0\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:19959.3-19995.6" + wire width 2 $0\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:19293.3-19329.6" + wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19626.3-19662.6" + wire $0\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19774.3-19810.6" + wire $0\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19700.3-19736.6" + wire $0\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19552.3-19588.6" + wire $0\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19256.3-19292.6" + wire width 2 $0\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:18925.7-18925.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19367.3-19403.6" + wire width 8 $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19515.3-19551.6" + wire $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:19996.3-20032.6" + wire width 3 $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:20033.3-20069.6" + wire width 3 $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:19330.3-19366.6" + wire width 2 $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19478.3-19514.6" + wire $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19811.3-19847.6" + wire width 5 $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19182.3-19218.6" + wire width 12 $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19848.3-19884.6" + wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19885.3-19921.6" + wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19922.3-19958.6" + wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19589.3-19625.6" + wire width 7 $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19404.3-19440.6" + wire $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19441.3-19477.6" + wire $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19663.3-19699.6" + wire $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19219.3-19255.6" + wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19737.3-19773.6" + wire $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:19959.3-19995.6" + wire width 2 $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:19293.3-19329.6" + wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19626.3-19662.6" + wire $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19774.3-19810.6" + wire $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19700.3-19736.6" + wire $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19552.3-19588.6" + wire $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19256.3-19292.6" + wire width 2 $1\dec31_dec_sub10_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub10_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub10_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub10_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub10_upd + attribute \src "libresoc.v:18925.7-18925.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:18925.7-18925.20" + process $proc$libresoc.v:18925$456 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19182.3-19218.6" + process $proc$libresoc.v:19182$432 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19183.5-19183.29" + switch \initial + attribute \src "libresoc.v:19183.9-19183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] + end + attribute \src "libresoc.v:19219.3-19255.6" + process $proc$libresoc.v:19219$433 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19220.5-19220.29" + switch \initial + attribute \src "libresoc.v:19220.9-19220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] + end + attribute \src "libresoc.v:19256.3-19292.6" + process $proc$libresoc.v:19256$434 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:19257.5-19257.29" + switch \initial + attribute \src "libresoc.v:19257.9-19257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] + end + attribute \src "libresoc.v:19293.3-19329.6" + process $proc$libresoc.v:19293$435 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19294.5-19294.29" + switch \initial + attribute \src "libresoc.v:19294.9-19294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "libresoc.v:19330.3-19366.6" + process $proc$libresoc.v:19330$436 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19331.5-19331.29" + switch \initial + attribute \src "libresoc.v:19331.9-19331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] + end + attribute \src "libresoc.v:19367.3-19403.6" + process $proc$libresoc.v:19367$437 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19368.5-19368.29" + switch \initial + attribute \src "libresoc.v:19368.9-19368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + case + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] + end + attribute \src "libresoc.v:19404.3-19440.6" + process $proc$libresoc.v:19404$438 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19405.5-19405.29" + switch \initial + attribute \src "libresoc.v:19405.9-19405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] + end + attribute \src "libresoc.v:19441.3-19477.6" + process $proc$libresoc.v:19441$439 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19442.5-19442.29" + switch \initial + attribute \src "libresoc.v:19442.9-19442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] + end + attribute \src "libresoc.v:19478.3-19514.6" + process $proc$libresoc.v:19478$440 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19479.5-19479.29" + switch \initial + attribute \src "libresoc.v:19479.9-19479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] + end + attribute \src "libresoc.v:19515.3-19551.6" + process $proc$libresoc.v:19515$441 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:19516.5-19516.29" + switch \initial + attribute \src "libresoc.v:19516.9-19516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + case + assign $1\dec31_dec_sub10_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] + end + attribute \src "libresoc.v:19552.3-19588.6" + process $proc$libresoc.v:19552$442 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19553.5-19553.29" + switch \initial + attribute \src "libresoc.v:19553.9-19553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] + end + attribute \src "libresoc.v:19589.3-19625.6" + process $proc$libresoc.v:19589$443 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19590.5-19590.29" + switch \initial + attribute \src "libresoc.v:19590.9-19590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] + end + attribute \src "libresoc.v:19626.3-19662.6" + process $proc$libresoc.v:19626$444 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19627.5-19627.29" + switch \initial + attribute \src "libresoc.v:19627.9-19627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] + end + attribute \src "libresoc.v:19663.3-19699.6" + process $proc$libresoc.v:19663$445 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19664.5-19664.29" + switch \initial + attribute \src "libresoc.v:19664.9-19664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] + end + attribute \src "libresoc.v:19700.3-19736.6" + process $proc$libresoc.v:19700$446 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19701.5-19701.29" + switch \initial + attribute \src "libresoc.v:19701.9-19701.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] + end + attribute \src "libresoc.v:19737.3-19773.6" + process $proc$libresoc.v:19737$447 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:19738.5-19738.29" + switch \initial + attribute \src "libresoc.v:19738.9-19738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] + end + attribute \src "libresoc.v:19774.3-19810.6" + process $proc$libresoc.v:19774$448 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19775.5-19775.29" + switch \initial + attribute \src "libresoc.v:19775.9-19775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] + end + attribute \src "libresoc.v:19811.3-19847.6" + process $proc$libresoc.v:19811$449 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19812.5-19812.29" + switch \initial + attribute \src "libresoc.v:19812.9-19812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub10_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] + end + attribute \src "libresoc.v:19848.3-19884.6" + process $proc$libresoc.v:19848$450 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19849.5-19849.29" + switch \initial + attribute \src "libresoc.v:19849.9-19849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] + end + attribute \src "libresoc.v:19885.3-19921.6" + process $proc$libresoc.v:19885$451 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19886.5-19886.29" + switch \initial + attribute \src "libresoc.v:19886.9-19886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] + end + attribute \src "libresoc.v:19922.3-19958.6" + process $proc$libresoc.v:19922$452 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19923.5-19923.29" + switch \initial + attribute \src "libresoc.v:19923.9-19923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] + end + attribute \src "libresoc.v:19959.3-19995.6" + process $proc$libresoc.v:19959$453 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:19960.5-19960.29" + switch \initial + attribute \src "libresoc.v:19960.9-19960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] + end + attribute \src "libresoc.v:19996.3-20032.6" + process $proc$libresoc.v:19996$454 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:19997.5-19997.29" + switch \initial + attribute \src "libresoc.v:19997.9-19997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] + end + attribute \src "libresoc.v:20033.3-20069.6" + process $proc$libresoc.v:20033$455 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:20034.5-20034.29" + switch \initial + attribute \src "libresoc.v:20034.9-20034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:20075.1-21654.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" +attribute \generator "nMigen" +module \dec31_dec_sub11 + attribute \src "libresoc.v:20608.3-20662.6" + wire width 8 $0\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20828.3-20882.6" + wire $0\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:21543.3-21597.6" + wire width 3 $0\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21598.3-21652.6" + wire width 3 $0\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:20553.3-20607.6" + wire width 2 $0\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20773.3-20827.6" + wire $0\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:21268.3-21322.6" + wire width 5 $0\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:20333.3-20387.6" + wire width 12 $0\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:21323.3-21377.6" + wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21378.3-21432.6" + wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21433.3-21487.6" + wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:20938.3-20992.6" + wire width 7 $0\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20663.3-20717.6" + wire $0\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20718.3-20772.6" + wire $0\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:21048.3-21102.6" + wire $0\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:20388.3-20442.6" + wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:21158.3-21212.6" + wire $0\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21488.3-21542.6" + wire width 2 $0\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:20498.3-20552.6" + wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:20993.3-21047.6" + wire $0\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:21213.3-21267.6" + wire $0\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:21103.3-21157.6" + wire $0\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:20883.3-20937.6" + wire $0\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20443.3-20497.6" + wire width 2 $0\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:20076.7-20076.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20608.3-20662.6" + wire width 8 $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20828.3-20882.6" + wire $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:21543.3-21597.6" + wire width 3 $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21598.3-21652.6" + wire width 3 $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:20553.3-20607.6" + wire width 2 $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20773.3-20827.6" + wire $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:21268.3-21322.6" + wire width 5 $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:20333.3-20387.6" + wire width 12 $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:21323.3-21377.6" + wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21378.3-21432.6" + wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21433.3-21487.6" + wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:20938.3-20992.6" + wire width 7 $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20663.3-20717.6" + wire $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20718.3-20772.6" + wire $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:21048.3-21102.6" + wire $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:20388.3-20442.6" + wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:21158.3-21212.6" + wire $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21488.3-21542.6" + wire width 2 $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:20498.3-20552.6" + wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:20993.3-21047.6" + wire $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:21213.3-21267.6" + wire $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:21103.3-21157.6" + wire $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:20883.3-20937.6" + wire $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20443.3-20497.6" + wire width 2 $1\dec31_dec_sub11_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub11_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub11_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub11_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub11_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub11_upd + attribute \src "libresoc.v:20076.7-20076.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:20076.7-20076.20" + process $proc$libresoc.v:20076$481 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20333.3-20387.6" + process $proc$libresoc.v:20333$457 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:20334.5-20334.29" + switch \initial + attribute \src "libresoc.v:20334.9-20334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] + end + attribute \src "libresoc.v:20388.3-20442.6" + process $proc$libresoc.v:20388$458 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:20389.5-20389.29" + switch \initial + attribute \src "libresoc.v:20389.9-20389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] + end + attribute \src "libresoc.v:20443.3-20497.6" + process $proc$libresoc.v:20443$459 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:20444.5-20444.29" + switch \initial + attribute \src "libresoc.v:20444.9-20444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] + end + attribute \src "libresoc.v:20498.3-20552.6" + process $proc$libresoc.v:20498$460 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:20499.5-20499.29" + switch \initial + attribute \src "libresoc.v:20499.9-20499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:20553.3-20607.6" + process $proc$libresoc.v:20553$461 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20554.5-20554.29" + switch \initial + attribute \src "libresoc.v:20554.9-20554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] + end + attribute \src "libresoc.v:20608.3-20662.6" + process $proc$libresoc.v:20608$462 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20609.5-20609.29" + switch \initial + attribute \src "libresoc.v:20609.9-20609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 + case + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] + end + attribute \src "libresoc.v:20663.3-20717.6" + process $proc$libresoc.v:20663$463 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20664.5-20664.29" + switch \initial + attribute \src "libresoc.v:20664.9-20664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] + end + attribute \src "libresoc.v:20718.3-20772.6" + process $proc$libresoc.v:20718$464 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:20719.5-20719.29" + switch \initial + attribute \src "libresoc.v:20719.9-20719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] + end + attribute \src "libresoc.v:20773.3-20827.6" + process $proc$libresoc.v:20773$465 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:20774.5-20774.29" + switch \initial + attribute \src "libresoc.v:20774.9-20774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] + end + attribute \src "libresoc.v:20828.3-20882.6" + process $proc$libresoc.v:20828$466 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:20829.5-20829.29" + switch \initial + attribute \src "libresoc.v:20829.9-20829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + case + assign $1\dec31_dec_sub11_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] + end + attribute \src "libresoc.v:20883.3-20937.6" + process $proc$libresoc.v:20883$467 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20884.5-20884.29" + switch \initial + attribute \src "libresoc.v:20884.9-20884.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] + end + attribute \src "libresoc.v:20938.3-20992.6" + process $proc$libresoc.v:20938$468 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20939.5-20939.29" + switch \initial + attribute \src "libresoc.v:20939.9-20939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:20993.3-21047.6" + process $proc$libresoc.v:20993$469 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:20994.5-20994.29" + switch \initial + attribute \src "libresoc.v:20994.9-20994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] + end + attribute \src "libresoc.v:21048.3-21102.6" + process $proc$libresoc.v:21048$470 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:21049.5-21049.29" + switch \initial + attribute \src "libresoc.v:21049.9-21049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:21103.3-21157.6" + process $proc$libresoc.v:21103$471 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:21104.5-21104.29" + switch \initial + attribute \src "libresoc.v:21104.9-21104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] + end + attribute \src "libresoc.v:21158.3-21212.6" + process $proc$libresoc.v:21158$472 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21159.5-21159.29" + switch \initial + attribute \src "libresoc.v:21159.9-21159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] + end + attribute \src "libresoc.v:21213.3-21267.6" + process $proc$libresoc.v:21213$473 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:21214.5-21214.29" + switch \initial + attribute \src "libresoc.v:21214.9-21214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] + end + attribute \src "libresoc.v:21268.3-21322.6" + process $proc$libresoc.v:21268$474 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:21269.5-21269.29" + switch \initial + attribute \src "libresoc.v:21269.9-21269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub11_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] + end + attribute \src "libresoc.v:21323.3-21377.6" + process $proc$libresoc.v:21323$475 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21324.5-21324.29" + switch \initial + attribute \src "libresoc.v:21324.9-21324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "libresoc.v:21378.3-21432.6" + process $proc$libresoc.v:21378$476 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21379.5-21379.29" + switch \initial + attribute \src "libresoc.v:21379.9-21379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:21433.3-21487.6" + process $proc$libresoc.v:21433$477 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:21434.5-21434.29" + switch \initial + attribute \src "libresoc.v:21434.9-21434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] + end + attribute \src "libresoc.v:21488.3-21542.6" + process $proc$libresoc.v:21488$478 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:21489.5-21489.29" + switch \initial + attribute \src "libresoc.v:21489.9-21489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] + end + attribute \src "libresoc.v:21543.3-21597.6" + process $proc$libresoc.v:21543$479 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21544.5-21544.29" + switch \initial + attribute \src "libresoc.v:21544.9-21544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:21598.3-21652.6" + process $proc$libresoc.v:21598$480 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:21599.5-21599.29" + switch \initial + attribute \src "libresoc.v:21599.9-21599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:21658.1-24389.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" +attribute \generator "nMigen" +module \dec31_dec_sub15 + attribute \src "libresoc.v:22431.3-22533.6" + wire width 8 $0\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22843.3-22945.6" + wire $0\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:24182.3-24284.6" + wire width 3 $0\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24285.3-24387.6" + wire width 3 $0\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:22328.3-22430.6" + wire width 2 $0\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22740.3-22842.6" + wire $0\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:23667.3-23769.6" + wire width 5 $0\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:21916.3-22018.6" + wire width 12 $0\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:23770.3-23872.6" + wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23873.3-23975.6" + wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:23976.3-24078.6" + wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:23049.3-23151.6" + wire width 7 $0\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:22534.3-22636.6" + wire $0\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22637.3-22739.6" + wire $0\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:23255.3-23357.6" + wire $0\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:22019.3-22121.6" + wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:23461.3-23563.6" + wire $0\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:24079.3-24181.6" + wire width 2 $0\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:22225.3-22327.6" + wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:23152.3-23254.6" + wire $0\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23564.3-23666.6" + wire $0\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23358.3-23460.6" + wire $0\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:22946.3-23048.6" + wire $0\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:22122.3-22224.6" + wire width 2 $0\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:21659.7-21659.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:22431.3-22533.6" + wire width 8 $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22843.3-22945.6" + wire $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:24182.3-24284.6" + wire width 3 $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24285.3-24387.6" + wire width 3 $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:22328.3-22430.6" + wire width 2 $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22740.3-22842.6" + wire $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:23667.3-23769.6" + wire width 5 $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:21916.3-22018.6" + wire width 12 $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:23770.3-23872.6" + wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23873.3-23975.6" + wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:23976.3-24078.6" + wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:23049.3-23151.6" + wire width 7 $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:22534.3-22636.6" + wire $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22637.3-22739.6" + wire $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:23255.3-23357.6" + wire $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:22019.3-22121.6" + wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:23461.3-23563.6" + wire $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:24079.3-24181.6" + wire width 2 $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:22225.3-22327.6" + wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:23152.3-23254.6" + wire $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23564.3-23666.6" + wire $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23358.3-23460.6" + wire $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:22946.3-23048.6" + wire $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:22122.3-22224.6" + wire width 2 $1\dec31_dec_sub15_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub15_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub15_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub15_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub15_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub15_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub15_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub15_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub15_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub15_upd + attribute \src "libresoc.v:21659.7-21659.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:21659.7-21659.20" + process $proc$libresoc.v:21659$506 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21916.3-22018.6" + process $proc$libresoc.v:21916$482 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:21917.5-21917.29" + switch \initial + attribute \src "libresoc.v:21917.9-21917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] + end + attribute \src "libresoc.v:22019.3-22121.6" + process $proc$libresoc.v:22019$483 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:22020.5-22020.29" + switch \initial + attribute \src "libresoc.v:22020.9-22020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] + end + attribute \src "libresoc.v:22122.3-22224.6" + process $proc$libresoc.v:22122$484 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:22123.5-22123.29" + switch \initial + attribute \src "libresoc.v:22123.9-22123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] + end + attribute \src "libresoc.v:22225.3-22327.6" + process $proc$libresoc.v:22225$485 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:22226.5-22226.29" + switch \initial + attribute \src "libresoc.v:22226.9-22226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] + end + attribute \src "libresoc.v:22328.3-22430.6" + process $proc$libresoc.v:22328$486 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22329.5-22329.29" + switch \initial + attribute \src "libresoc.v:22329.9-22329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] + end + attribute \src "libresoc.v:22431.3-22533.6" + process $proc$libresoc.v:22431$487 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22432.5-22432.29" + switch \initial + attribute \src "libresoc.v:22432.9-22432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + case + assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] + end + attribute \src "libresoc.v:22534.3-22636.6" + process $proc$libresoc.v:22534$488 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22535.5-22535.29" + switch \initial + attribute \src "libresoc.v:22535.9-22535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] + end + attribute \src "libresoc.v:22637.3-22739.6" + process $proc$libresoc.v:22637$489 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:22638.5-22638.29" + switch \initial + attribute \src "libresoc.v:22638.9-22638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] + end + attribute \src "libresoc.v:22740.3-22842.6" + process $proc$libresoc.v:22740$490 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:22741.5-22741.29" + switch \initial + attribute \src "libresoc.v:22741.9-22741.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] + end + attribute \src "libresoc.v:22843.3-22945.6" + process $proc$libresoc.v:22843$491 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:22844.5-22844.29" + switch \initial + attribute \src "libresoc.v:22844.9-22844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + case + assign $1\dec31_dec_sub15_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] + end + attribute \src "libresoc.v:22946.3-23048.6" + process $proc$libresoc.v:22946$492 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:22947.5-22947.29" + switch \initial + attribute \src "libresoc.v:22947.9-22947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] + end + attribute \src "libresoc.v:23049.3-23151.6" + process $proc$libresoc.v:23049$493 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:23050.5-23050.29" + switch \initial + attribute \src "libresoc.v:23050.9-23050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] + end + attribute \src "libresoc.v:23152.3-23254.6" + process $proc$libresoc.v:23152$494 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23153.5-23153.29" + switch \initial + attribute \src "libresoc.v:23153.9-23153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] + end + attribute \src "libresoc.v:23255.3-23357.6" + process $proc$libresoc.v:23255$495 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:23256.5-23256.29" + switch \initial + attribute \src "libresoc.v:23256.9-23256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] + end + attribute \src "libresoc.v:23358.3-23460.6" + process $proc$libresoc.v:23358$496 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:23359.5-23359.29" + switch \initial + attribute \src "libresoc.v:23359.9-23359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] + end + attribute \src "libresoc.v:23461.3-23563.6" + process $proc$libresoc.v:23461$497 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:23462.5-23462.29" + switch \initial + attribute \src "libresoc.v:23462.9-23462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] + end + attribute \src "libresoc.v:23564.3-23666.6" + process $proc$libresoc.v:23564$498 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23565.5-23565.29" + switch \initial + attribute \src "libresoc.v:23565.9-23565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] + end + attribute \src "libresoc.v:23667.3-23769.6" + process $proc$libresoc.v:23667$499 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:23668.5-23668.29" + switch \initial + attribute \src "libresoc.v:23668.9-23668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + case + assign $1\dec31_dec_sub15_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] + end + attribute \src "libresoc.v:23770.3-23872.6" + process $proc$libresoc.v:23770$500 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23771.5-23771.29" + switch \initial + attribute \src "libresoc.v:23771.9-23771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] + end + attribute \src "libresoc.v:23873.3-23975.6" + process $proc$libresoc.v:23873$501 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:23874.5-23874.29" + switch \initial + attribute \src "libresoc.v:23874.9-23874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] + end + attribute \src "libresoc.v:23976.3-24078.6" + process $proc$libresoc.v:23976$502 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:23977.5-23977.29" + switch \initial + attribute \src "libresoc.v:23977.9-23977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] + end + attribute \src "libresoc.v:24079.3-24181.6" + process $proc$libresoc.v:24079$503 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:24080.5-24080.29" + switch \initial + attribute \src "libresoc.v:24080.9-24080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] + end + attribute \src "libresoc.v:24182.3-24284.6" + process $proc$libresoc.v:24182$504 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24183.5-24183.29" + switch \initial + attribute \src "libresoc.v:24183.9-24183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] + end + attribute \src "libresoc.v:24285.3-24387.6" + process $proc$libresoc.v:24285$505 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:24286.5-24286.29" + switch \initial + attribute \src "libresoc.v:24286.9-24286.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:24393.1-24892.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" +attribute \generator "nMigen" +module \dec31_dec_sub16 + attribute \src "libresoc.v:24701.3-24710.6" + wire width 8 $0\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24741.3-24750.6" + wire $0\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24871.3-24880.6" + wire width 3 $0\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24881.3-24890.6" + wire width 3 $0\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24691.3-24700.6" + wire width 2 $0\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24731.3-24740.6" + wire $0\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24821.3-24830.6" + wire width 5 $0\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24651.3-24660.6" + wire width 12 $0\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24831.3-24840.6" + wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24841.3-24850.6" + wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24851.3-24860.6" + wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24761.3-24770.6" + wire width 7 $0\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24711.3-24720.6" + wire $0\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24721.3-24730.6" + wire $0\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24781.3-24790.6" + wire $0\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24661.3-24670.6" + wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24801.3-24810.6" + wire $0\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24861.3-24870.6" + wire width 2 $0\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24681.3-24690.6" + wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24771.3-24780.6" + wire $0\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24811.3-24820.6" + wire $0\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24791.3-24800.6" + wire $0\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24751.3-24760.6" + wire $0\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24671.3-24680.6" + wire width 2 $0\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:24394.7-24394.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:24701.3-24710.6" + wire width 8 $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24741.3-24750.6" + wire $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24871.3-24880.6" + wire width 3 $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24881.3-24890.6" + wire width 3 $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24691.3-24700.6" + wire width 2 $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24731.3-24740.6" + wire $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24821.3-24830.6" + wire width 5 $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24651.3-24660.6" + wire width 12 $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24831.3-24840.6" + wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24841.3-24850.6" + wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24851.3-24860.6" + wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24761.3-24770.6" + wire width 7 $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24711.3-24720.6" + wire $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24721.3-24730.6" + wire $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24781.3-24790.6" + wire $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24661.3-24670.6" + wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24801.3-24810.6" + wire $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24861.3-24870.6" + wire width 2 $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24681.3-24690.6" + wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24771.3-24780.6" + wire $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24811.3-24820.6" + wire $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24791.3-24800.6" + wire $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24751.3-24760.6" + wire $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24671.3-24680.6" + wire width 2 $1\dec31_dec_sub16_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub16_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub16_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub16_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub16_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub16_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub16_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub16_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub16_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub16_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub16_upd + attribute \src "libresoc.v:24394.7-24394.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:24394.7-24394.20" + process $proc$libresoc.v:24394$531 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:24651.3-24660.6" + process $proc$libresoc.v:24651$507 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24652.5-24652.29" + switch \initial + attribute \src "libresoc.v:24652.9-24652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] + end + attribute \src "libresoc.v:24661.3-24670.6" + process $proc$libresoc.v:24661$508 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24662.5-24662.29" + switch \initial + attribute \src "libresoc.v:24662.9-24662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] + end + attribute \src "libresoc.v:24671.3-24680.6" + process $proc$libresoc.v:24671$509 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:24672.5-24672.29" + switch \initial + attribute \src "libresoc.v:24672.9-24672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] + end + attribute \src "libresoc.v:24681.3-24690.6" + process $proc$libresoc.v:24681$510 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24682.5-24682.29" + switch \initial + attribute \src "libresoc.v:24682.9-24682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] + end + attribute \src "libresoc.v:24691.3-24700.6" + process $proc$libresoc.v:24691$511 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24692.5-24692.29" + switch \initial + attribute \src "libresoc.v:24692.9-24692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] + end + attribute \src "libresoc.v:24701.3-24710.6" + process $proc$libresoc.v:24701$512 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24702.5-24702.29" + switch \initial + attribute \src "libresoc.v:24702.9-24702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 + case + assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] + end + attribute \src "libresoc.v:24711.3-24720.6" + process $proc$libresoc.v:24711$513 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24712.5-24712.29" + switch \initial + attribute \src "libresoc.v:24712.9-24712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] + end + attribute \src "libresoc.v:24721.3-24730.6" + process $proc$libresoc.v:24721$514 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24722.5-24722.29" + switch \initial + attribute \src "libresoc.v:24722.9-24722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] + end + attribute \src "libresoc.v:24731.3-24740.6" + process $proc$libresoc.v:24731$515 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24732.5-24732.29" + switch \initial + attribute \src "libresoc.v:24732.9-24732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] + end + attribute \src "libresoc.v:24741.3-24750.6" + process $proc$libresoc.v:24741$516 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24742.5-24742.29" + switch \initial + attribute \src "libresoc.v:24742.9-24742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_br[0:0] 1'0 + case + assign $1\dec31_dec_sub16_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] + end + attribute \src "libresoc.v:24751.3-24760.6" + process $proc$libresoc.v:24751$517 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24752.5-24752.29" + switch \initial + attribute \src "libresoc.v:24752.9-24752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] + end + attribute \src "libresoc.v:24761.3-24770.6" + process $proc$libresoc.v:24761$518 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24762.5-24762.29" + switch \initial + attribute \src "libresoc.v:24762.9-24762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] + end + attribute \src "libresoc.v:24771.3-24780.6" + process $proc$libresoc.v:24771$519 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24772.5-24772.29" + switch \initial + attribute \src "libresoc.v:24772.9-24772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] + end + attribute \src "libresoc.v:24781.3-24790.6" + process $proc$libresoc.v:24781$520 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24782.5-24782.29" + switch \initial + attribute \src "libresoc.v:24782.9-24782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + end + attribute \src "libresoc.v:24791.3-24800.6" + process $proc$libresoc.v:24791$521 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24792.5-24792.29" + switch \initial + attribute \src "libresoc.v:24792.9-24792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] + end + attribute \src "libresoc.v:24801.3-24810.6" + process $proc$libresoc.v:24801$522 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24802.5-24802.29" + switch \initial + attribute \src "libresoc.v:24802.9-24802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] + end + attribute \src "libresoc.v:24811.3-24820.6" + process $proc$libresoc.v:24811$523 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24812.5-24812.29" + switch \initial + attribute \src "libresoc.v:24812.9-24812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] + end + attribute \src "libresoc.v:24821.3-24830.6" + process $proc$libresoc.v:24821$524 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24822.5-24822.29" + switch \initial + attribute \src "libresoc.v:24822.9-24822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub16_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + end + attribute \src "libresoc.v:24831.3-24840.6" + process $proc$libresoc.v:24831$525 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24832.5-24832.29" + switch \initial + attribute \src "libresoc.v:24832.9-24832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] + end + attribute \src "libresoc.v:24841.3-24850.6" + process $proc$libresoc.v:24841$526 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24842.5-24842.29" + switch \initial + attribute \src "libresoc.v:24842.9-24842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] + end + attribute \src "libresoc.v:24851.3-24860.6" + process $proc$libresoc.v:24851$527 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24852.5-24852.29" + switch \initial + attribute \src "libresoc.v:24852.9-24852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] + end + attribute \src "libresoc.v:24861.3-24870.6" + process $proc$libresoc.v:24861$528 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24862.5-24862.29" + switch \initial + attribute \src "libresoc.v:24862.9-24862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] + end + attribute \src "libresoc.v:24871.3-24880.6" + process $proc$libresoc.v:24871$529 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24872.5-24872.29" + switch \initial + attribute \src "libresoc.v:24872.9-24872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] + end + attribute \src "libresoc.v:24881.3-24890.6" + process $proc$libresoc.v:24881$530 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24882.5-24882.29" + switch \initial + attribute \src "libresoc.v:24882.9-24882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:24896.1-25683.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" +attribute \generator "nMigen" +module \dec31_dec_sub18 + attribute \src "libresoc.v:25264.3-25285.6" + wire width 8 $0\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25352.3-25373.6" + wire $0\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25638.3-25659.6" + wire width 3 $0\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25660.3-25681.6" + wire width 3 $0\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25242.3-25263.6" + wire width 2 $0\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25330.3-25351.6" + wire $0\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25528.3-25549.6" + wire width 5 $0\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25154.3-25175.6" + wire width 12 $0\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25550.3-25571.6" + wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25572.3-25593.6" + wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25594.3-25615.6" + wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25396.3-25417.6" + wire width 7 $0\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25286.3-25307.6" + wire $0\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25308.3-25329.6" + wire $0\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25440.3-25461.6" + wire $0\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25176.3-25197.6" + wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25484.3-25505.6" + wire $0\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25616.3-25637.6" + wire width 2 $0\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25220.3-25241.6" + wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25418.3-25439.6" + wire $0\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25506.3-25527.6" + wire $0\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25462.3-25483.6" + wire $0\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25374.3-25395.6" + wire $0\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25198.3-25219.6" + wire width 2 $0\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:24897.7-24897.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:25264.3-25285.6" + wire width 8 $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25352.3-25373.6" + wire $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25638.3-25659.6" + wire width 3 $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25660.3-25681.6" + wire width 3 $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25242.3-25263.6" + wire width 2 $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25330.3-25351.6" + wire $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25528.3-25549.6" + wire width 5 $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25154.3-25175.6" + wire width 12 $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25550.3-25571.6" + wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25572.3-25593.6" + wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25594.3-25615.6" + wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25396.3-25417.6" + wire width 7 $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25286.3-25307.6" + wire $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25308.3-25329.6" + wire $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25440.3-25461.6" + wire $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25176.3-25197.6" + wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25484.3-25505.6" + wire $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25616.3-25637.6" + wire width 2 $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25220.3-25241.6" + wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25418.3-25439.6" + wire $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25506.3-25527.6" + wire $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25462.3-25483.6" + wire $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25374.3-25395.6" + wire $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25198.3-25219.6" + wire width 2 $1\dec31_dec_sub18_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub18_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub18_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub18_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub18_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub18_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub18_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub18_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub18_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub18_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub18_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub18_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub18_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub18_upd + attribute \src "libresoc.v:24897.7-24897.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:24897.7-24897.20" + process $proc$libresoc.v:24897$556 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25154.3-25175.6" + process $proc$libresoc.v:25154$532 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25155.5-25155.29" + switch \initial + attribute \src "libresoc.v:25155.9-25155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + case + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] + end + attribute \src "libresoc.v:25176.3-25197.6" + process $proc$libresoc.v:25176$533 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25177.5-25177.29" + switch \initial + attribute \src "libresoc.v:25177.9-25177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] + end + attribute \src "libresoc.v:25198.3-25219.6" + process $proc$libresoc.v:25198$534 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:25199.5-25199.29" + switch \initial + attribute \src "libresoc.v:25199.9-25199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + end + attribute \src "libresoc.v:25220.3-25241.6" + process $proc$libresoc.v:25220$535 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25221.5-25221.29" + switch \initial + attribute \src "libresoc.v:25221.9-25221.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] + end + attribute \src "libresoc.v:25242.3-25263.6" + process $proc$libresoc.v:25242$536 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25243.5-25243.29" + switch \initial + attribute \src "libresoc.v:25243.9-25243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] + end + attribute \src "libresoc.v:25264.3-25285.6" + process $proc$libresoc.v:25264$537 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25265.5-25265.29" + switch \initial + attribute \src "libresoc.v:25265.9-25265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 + case + assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] + end + attribute \src "libresoc.v:25286.3-25307.6" + process $proc$libresoc.v:25286$538 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25287.5-25287.29" + switch \initial + attribute \src "libresoc.v:25287.9-25287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] + end + attribute \src "libresoc.v:25308.3-25329.6" + process $proc$libresoc.v:25308$539 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25309.5-25309.29" + switch \initial + attribute \src "libresoc.v:25309.9-25309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] + end + attribute \src "libresoc.v:25330.3-25351.6" + process $proc$libresoc.v:25330$540 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25331.5-25331.29" + switch \initial + attribute \src "libresoc.v:25331.9-25331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] + end + attribute \src "libresoc.v:25352.3-25373.6" + process $proc$libresoc.v:25352$541 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25353.5-25353.29" + switch \initial + attribute \src "libresoc.v:25353.9-25353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + case + assign $1\dec31_dec_sub18_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] + end + attribute \src "libresoc.v:25374.3-25395.6" + process $proc$libresoc.v:25374$542 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25375.5-25375.29" + switch \initial + attribute \src "libresoc.v:25375.9-25375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] + end + attribute \src "libresoc.v:25396.3-25417.6" + process $proc$libresoc.v:25396$543 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25397.5-25397.29" + switch \initial + attribute \src "libresoc.v:25397.9-25397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + case + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + end + attribute \src "libresoc.v:25418.3-25439.6" + process $proc$libresoc.v:25418$544 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25419.5-25419.29" + switch \initial + attribute \src "libresoc.v:25419.9-25419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] + end + attribute \src "libresoc.v:25440.3-25461.6" + process $proc$libresoc.v:25440$545 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25441.5-25441.29" + switch \initial + attribute \src "libresoc.v:25441.9-25441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + end + attribute \src "libresoc.v:25462.3-25483.6" + process $proc$libresoc.v:25462$546 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25463.5-25463.29" + switch \initial + attribute \src "libresoc.v:25463.9-25463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] + end + attribute \src "libresoc.v:25484.3-25505.6" + process $proc$libresoc.v:25484$547 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25485.5-25485.29" + switch \initial + attribute \src "libresoc.v:25485.9-25485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] + end + attribute \src "libresoc.v:25506.3-25527.6" + process $proc$libresoc.v:25506$548 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25507.5-25507.29" + switch \initial + attribute \src "libresoc.v:25507.9-25507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] + end + attribute \src "libresoc.v:25528.3-25549.6" + process $proc$libresoc.v:25528$549 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25529.5-25529.29" + switch \initial + attribute \src "libresoc.v:25529.9-25529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub18_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + end + attribute \src "libresoc.v:25550.3-25571.6" + process $proc$libresoc.v:25550$550 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25551.5-25551.29" + switch \initial + attribute \src "libresoc.v:25551.9-25551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] + end + attribute \src "libresoc.v:25572.3-25593.6" + process $proc$libresoc.v:25572$551 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25573.5-25573.29" + switch \initial + attribute \src "libresoc.v:25573.9-25573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] + end + attribute \src "libresoc.v:25594.3-25615.6" + process $proc$libresoc.v:25594$552 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25595.5-25595.29" + switch \initial + attribute \src "libresoc.v:25595.9-25595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] + end + attribute \src "libresoc.v:25616.3-25637.6" + process $proc$libresoc.v:25616$553 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25617.5-25617.29" + switch \initial + attribute \src "libresoc.v:25617.9-25617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] + end + attribute \src "libresoc.v:25638.3-25659.6" + process $proc$libresoc.v:25638$554 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25639.5-25639.29" + switch \initial + attribute \src "libresoc.v:25639.9-25639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] + end + attribute \src "libresoc.v:25660.3-25681.6" + process $proc$libresoc.v:25660$555 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25661.5-25661.29" + switch \initial + attribute \src "libresoc.v:25661.9-25661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:25687.1-26402.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" +attribute \generator "nMigen" +module \dec31_dec_sub19 + attribute \src "libresoc.v:26040.3-26058.6" + wire width 8 $0\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:26116.3-26134.6" + wire $0\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:26363.3-26381.6" + wire width 3 $0\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26382.3-26400.6" + wire width 3 $0\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:26021.3-26039.6" + wire width 2 $0\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:26097.3-26115.6" + wire $0\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:26268.3-26286.6" + wire width 5 $0\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:25945.3-25963.6" + wire width 12 $0\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:26287.3-26305.6" + wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26306.3-26324.6" + wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26325.3-26343.6" + wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26154.3-26172.6" + wire width 7 $0\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:26059.3-26077.6" + wire $0\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:26078.3-26096.6" + wire $0\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:26192.3-26210.6" + wire $0\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:25964.3-25982.6" + wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:26230.3-26248.6" + wire $0\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26344.3-26362.6" + wire width 2 $0\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:26002.3-26020.6" + wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:26173.3-26191.6" + wire $0\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26249.3-26267.6" + wire $0\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26211.3-26229.6" + wire $0\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:26135.3-26153.6" + wire $0\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:25983.3-26001.6" + wire width 2 $0\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:25688.7-25688.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26040.3-26058.6" + wire width 8 $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:26116.3-26134.6" + wire $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:26363.3-26381.6" + wire width 3 $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26382.3-26400.6" + wire width 3 $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:26021.3-26039.6" + wire width 2 $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:26097.3-26115.6" + wire $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:26268.3-26286.6" + wire width 5 $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:25945.3-25963.6" + wire width 12 $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:26287.3-26305.6" + wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26306.3-26324.6" + wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26325.3-26343.6" + wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26154.3-26172.6" + wire width 7 $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:26059.3-26077.6" + wire $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:26078.3-26096.6" + wire $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:26192.3-26210.6" + wire $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:25964.3-25982.6" + wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:26230.3-26248.6" + wire $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26344.3-26362.6" + wire width 2 $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:26002.3-26020.6" + wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:26173.3-26191.6" + wire $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26249.3-26267.6" + wire $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26211.3-26229.6" + wire $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:26135.3-26153.6" + wire $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:25983.3-26001.6" + wire width 2 $1\dec31_dec_sub19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub19_upd + attribute \src "libresoc.v:25688.7-25688.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:25688.7-25688.20" + process $proc$libresoc.v:25688$581 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:25945.3-25963.6" + process $proc$libresoc.v:25945$557 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:25946.5-25946.29" + switch \initial + attribute \src "libresoc.v:25946.9-25946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + case + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] + end + attribute \src "libresoc.v:25964.3-25982.6" + process $proc$libresoc.v:25964$558 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:25965.5-25965.29" + switch \initial + attribute \src "libresoc.v:25965.9-25965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] + end + attribute \src "libresoc.v:25983.3-26001.6" + process $proc$libresoc.v:25983$559 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:25984.5-25984.29" + switch \initial + attribute \src "libresoc.v:25984.9-25984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + end + attribute \src "libresoc.v:26002.3-26020.6" + process $proc$libresoc.v:26002$560 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:26003.5-26003.29" + switch \initial + attribute \src "libresoc.v:26003.9-26003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:26021.3-26039.6" + process $proc$libresoc.v:26021$561 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:26022.5-26022.29" + switch \initial + attribute \src "libresoc.v:26022.9-26022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] + end + attribute \src "libresoc.v:26040.3-26058.6" + process $proc$libresoc.v:26040$562 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:26041.5-26041.29" + switch \initial + attribute \src "libresoc.v:26041.9-26041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 + case + assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] + end + attribute \src "libresoc.v:26059.3-26077.6" + process $proc$libresoc.v:26059$563 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:26060.5-26060.29" + switch \initial + attribute \src "libresoc.v:26060.9-26060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] + end + attribute \src "libresoc.v:26078.3-26096.6" + process $proc$libresoc.v:26078$564 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:26079.5-26079.29" + switch \initial + attribute \src "libresoc.v:26079.9-26079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] + end + attribute \src "libresoc.v:26097.3-26115.6" + process $proc$libresoc.v:26097$565 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:26098.5-26098.29" + switch \initial + attribute \src "libresoc.v:26098.9-26098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] + end + attribute \src "libresoc.v:26116.3-26134.6" + process $proc$libresoc.v:26116$566 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:26117.5-26117.29" + switch \initial + attribute \src "libresoc.v:26117.9-26117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + case + assign $1\dec31_dec_sub19_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] + end + attribute \src "libresoc.v:26135.3-26153.6" + process $proc$libresoc.v:26135$567 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:26136.5-26136.29" + switch \initial + attribute \src "libresoc.v:26136.9-26136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] + end + attribute \src "libresoc.v:26154.3-26172.6" + process $proc$libresoc.v:26154$568 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:26155.5-26155.29" + switch \initial + attribute \src "libresoc.v:26155.9-26155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:26173.3-26191.6" + process $proc$libresoc.v:26173$569 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26174.5-26174.29" + switch \initial + attribute \src "libresoc.v:26174.9-26174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] + end + attribute \src "libresoc.v:26192.3-26210.6" + process $proc$libresoc.v:26192$570 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:26193.5-26193.29" + switch \initial + attribute \src "libresoc.v:26193.9-26193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + end + attribute \src "libresoc.v:26211.3-26229.6" + process $proc$libresoc.v:26211$571 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:26212.5-26212.29" + switch \initial + attribute \src "libresoc.v:26212.9-26212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] + end + attribute \src "libresoc.v:26230.3-26248.6" + process $proc$libresoc.v:26230$572 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26231.5-26231.29" + switch \initial + attribute \src "libresoc.v:26231.9-26231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] + end + attribute \src "libresoc.v:26249.3-26267.6" + process $proc$libresoc.v:26249$573 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26250.5-26250.29" + switch \initial + attribute \src "libresoc.v:26250.9-26250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:26268.3-26286.6" + process $proc$libresoc.v:26268$574 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:26269.5-26269.29" + switch \initial + attribute \src "libresoc.v:26269.9-26269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub19_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + end + attribute \src "libresoc.v:26287.3-26305.6" + process $proc$libresoc.v:26287$575 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26288.5-26288.29" + switch \initial + attribute \src "libresoc.v:26288.9-26288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] + end + attribute \src "libresoc.v:26306.3-26324.6" + process $proc$libresoc.v:26306$576 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26307.5-26307.29" + switch \initial + attribute \src "libresoc.v:26307.9-26307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] + end + attribute \src "libresoc.v:26325.3-26343.6" + process $proc$libresoc.v:26325$577 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26326.5-26326.29" + switch \initial + attribute \src "libresoc.v:26326.9-26326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] + end + attribute \src "libresoc.v:26344.3-26362.6" + process $proc$libresoc.v:26344$578 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:26345.5-26345.29" + switch \initial + attribute \src "libresoc.v:26345.9-26345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 + case + assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] + end + attribute \src "libresoc.v:26363.3-26381.6" + process $proc$libresoc.v:26363$579 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26364.5-26364.29" + switch \initial + attribute \src "libresoc.v:26364.9-26364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:26382.3-26400.6" + process $proc$libresoc.v:26382$580 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:26383.5-26383.29" + switch \initial + attribute \src "libresoc.v:26383.9-26383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:26406.1-27265.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" +attribute \generator "nMigen" +module \dec31_dec_sub20 + attribute \src "libresoc.v:26789.3-26813.6" + wire width 8 $0\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26889.3-26913.6" + wire $0\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:27214.3-27238.6" + wire width 3 $0\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27239.3-27263.6" + wire width 3 $0\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:26764.3-26788.6" + wire width 2 $0\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26864.3-26888.6" + wire $0\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:27089.3-27113.6" + wire width 5 $0\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:26664.3-26688.6" + wire width 12 $0\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:27114.3-27138.6" + wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:27139.3-27163.6" + wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27164.3-27188.6" + wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:26939.3-26963.6" + wire width 7 $0\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26814.3-26838.6" + wire $0\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26839.3-26863.6" + wire $0\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:26989.3-27013.6" + wire $0\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:26689.3-26713.6" + wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:27039.3-27063.6" + wire $0\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:27189.3-27213.6" + wire width 2 $0\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:26739.3-26763.6" + wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:26964.3-26988.6" + wire $0\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:27064.3-27088.6" + wire $0\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:27014.3-27038.6" + wire $0\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:26914.3-26938.6" + wire $0\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26714.3-26738.6" + wire width 2 $0\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:26407.7-26407.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26789.3-26813.6" + wire width 8 $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26889.3-26913.6" + wire $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:27214.3-27238.6" + wire width 3 $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27239.3-27263.6" + wire width 3 $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:26764.3-26788.6" + wire width 2 $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26864.3-26888.6" + wire $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:27089.3-27113.6" + wire width 5 $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:26664.3-26688.6" + wire width 12 $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:27114.3-27138.6" + wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:27139.3-27163.6" + wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27164.3-27188.6" + wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:26939.3-26963.6" + wire width 7 $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26814.3-26838.6" + wire $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26839.3-26863.6" + wire $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:26989.3-27013.6" + wire $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:26689.3-26713.6" + wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:27039.3-27063.6" + wire $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:27189.3-27213.6" + wire width 2 $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:26739.3-26763.6" + wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:26964.3-26988.6" + wire $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:27064.3-27088.6" + wire $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:27014.3-27038.6" + wire $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:26914.3-26938.6" + wire $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26714.3-26738.6" + wire width 2 $1\dec31_dec_sub20_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub20_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub20_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub20_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub20_upd + attribute \src "libresoc.v:26407.7-26407.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:26407.7-26407.20" + process $proc$libresoc.v:26407$606 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26664.3-26688.6" + process $proc$libresoc.v:26664$582 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:26665.5-26665.29" + switch \initial + attribute \src "libresoc.v:26665.9-26665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] + end + attribute \src "libresoc.v:26689.3-26713.6" + process $proc$libresoc.v:26689$583 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:26690.5-26690.29" + switch \initial + attribute \src "libresoc.v:26690.9-26690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:26714.3-26738.6" + process $proc$libresoc.v:26714$584 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:26715.5-26715.29" + switch \initial + attribute \src "libresoc.v:26715.9-26715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + end + attribute \src "libresoc.v:26739.3-26763.6" + process $proc$libresoc.v:26739$585 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:26740.5-26740.29" + switch \initial + attribute \src "libresoc.v:26740.9-26740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] + end + attribute \src "libresoc.v:26764.3-26788.6" + process $proc$libresoc.v:26764$586 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26765.5-26765.29" + switch \initial + attribute \src "libresoc.v:26765.9-26765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] + end + attribute \src "libresoc.v:26789.3-26813.6" + process $proc$libresoc.v:26789$587 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26790.5-26790.29" + switch \initial + attribute \src "libresoc.v:26790.9-26790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 + case + assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] + end + attribute \src "libresoc.v:26814.3-26838.6" + process $proc$libresoc.v:26814$588 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26815.5-26815.29" + switch \initial + attribute \src "libresoc.v:26815.9-26815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] + end + attribute \src "libresoc.v:26839.3-26863.6" + process $proc$libresoc.v:26839$589 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:26840.5-26840.29" + switch \initial + attribute \src "libresoc.v:26840.9-26840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] + end + attribute \src "libresoc.v:26864.3-26888.6" + process $proc$libresoc.v:26864$590 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:26865.5-26865.29" + switch \initial + attribute \src "libresoc.v:26865.9-26865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] + end + attribute \src "libresoc.v:26889.3-26913.6" + process $proc$libresoc.v:26889$591 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:26890.5-26890.29" + switch \initial + attribute \src "libresoc.v:26890.9-26890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:26914.3-26938.6" + process $proc$libresoc.v:26914$592 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26915.5-26915.29" + switch \initial + attribute \src "libresoc.v:26915.9-26915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:26939.3-26963.6" + process $proc$libresoc.v:26939$593 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26940.5-26940.29" + switch \initial + attribute \src "libresoc.v:26940.9-26940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + end + attribute \src "libresoc.v:26964.3-26988.6" + process $proc$libresoc.v:26964$594 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:26965.5-26965.29" + switch \initial + attribute \src "libresoc.v:26965.9-26965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] + end + attribute \src "libresoc.v:26989.3-27013.6" + process $proc$libresoc.v:26989$595 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:26990.5-26990.29" + switch \initial + attribute \src "libresoc.v:26990.9-26990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + end + attribute \src "libresoc.v:27014.3-27038.6" + process $proc$libresoc.v:27014$596 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:27015.5-27015.29" + switch \initial + attribute \src "libresoc.v:27015.9-27015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:27039.3-27063.6" + process $proc$libresoc.v:27039$597 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:27040.5-27040.29" + switch \initial + attribute \src "libresoc.v:27040.9-27040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] + end + attribute \src "libresoc.v:27064.3-27088.6" + process $proc$libresoc.v:27064$598 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:27065.5-27065.29" + switch \initial + attribute \src "libresoc.v:27065.9-27065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + end + attribute \src "libresoc.v:27089.3-27113.6" + process $proc$libresoc.v:27089$599 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:27090.5-27090.29" + switch \initial + attribute \src "libresoc.v:27090.9-27090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub20_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + end + attribute \src "libresoc.v:27114.3-27138.6" + process $proc$libresoc.v:27114$600 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:27115.5-27115.29" + switch \initial + attribute \src "libresoc.v:27115.9-27115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:27139.3-27163.6" + process $proc$libresoc.v:27139$601 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27140.5-27140.29" + switch \initial + attribute \src "libresoc.v:27140.9-27140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:27164.3-27188.6" + process $proc$libresoc.v:27164$602 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:27165.5-27165.29" + switch \initial + attribute \src "libresoc.v:27165.9-27165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + end + attribute \src "libresoc.v:27189.3-27213.6" + process $proc$libresoc.v:27189$603 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:27190.5-27190.29" + switch \initial + attribute \src "libresoc.v:27190.9-27190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] + end + attribute \src "libresoc.v:27214.3-27238.6" + process $proc$libresoc.v:27214$604 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27215.5-27215.29" + switch \initial + attribute \src "libresoc.v:27215.9-27215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:27239.3-27263.6" + process $proc$libresoc.v:27239$605 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:27240.5-27240.29" + switch \initial + attribute \src "libresoc.v:27240.9-27240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:27269.1-28686.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" +attribute \generator "nMigen" +module \dec31_dec_sub21 + attribute \src "libresoc.v:28311.3-28341.6" + wire width 8 $0\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:27919.3-27967.6" + wire $0\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:28587.3-28635.6" + wire width 3 $0\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28636.3-28684.6" + wire width 3 $0\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:27723.3-27771.6" + wire width 2 $0\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27870.3-27918.6" + wire $0\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:28342.3-28390.6" + wire width 5 $0\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:27527.3-27575.6" + wire width 12 $0\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:28391.3-28439.6" + wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28440.3-28488.6" + wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28489.3-28537.6" + wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:28066.3-28114.6" + wire width 7 $0\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:27772.3-27820.6" + wire $0\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27821.3-27869.6" + wire $0\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:28115.3-28163.6" + wire $0\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:27576.3-27624.6" + wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:28213.3-28261.6" + wire $0\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28538.3-28586.6" + wire width 2 $0\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:27674.3-27722.6" + wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:28017.3-28065.6" + wire $0\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:28262.3-28310.6" + wire $0\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28164.3-28212.6" + wire $0\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:27968.3-28016.6" + wire $0\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:27625.3-27673.6" + wire width 2 $0\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:27270.7-27270.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:28311.3-28341.6" + wire width 8 $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:27919.3-27967.6" + wire $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:28587.3-28635.6" + wire width 3 $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28636.3-28684.6" + wire width 3 $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:27723.3-27771.6" + wire width 2 $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27870.3-27918.6" + wire $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:28342.3-28390.6" + wire width 5 $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:27527.3-27575.6" + wire width 12 $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:28391.3-28439.6" + wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28440.3-28488.6" + wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28489.3-28537.6" + wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:28066.3-28114.6" + wire width 7 $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:27772.3-27820.6" + wire $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27821.3-27869.6" + wire $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:28115.3-28163.6" + wire $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:27576.3-27624.6" + wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:28213.3-28261.6" + wire $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28538.3-28586.6" + wire width 2 $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:27674.3-27722.6" + wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:28017.3-28065.6" + wire $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:28262.3-28310.6" + wire $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28164.3-28212.6" + wire $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:27968.3-28016.6" + wire $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:27625.3-27673.6" + wire width 2 $1\dec31_dec_sub21_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub21_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub21_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub21_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub21_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub21_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub21_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub21_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub21_upd + attribute \src "libresoc.v:27270.7-27270.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:27270.7-27270.20" + process $proc$libresoc.v:27270$631 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:27527.3-27575.6" + process $proc$libresoc.v:27527$607 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:27528.5-27528.29" + switch \initial + attribute \src "libresoc.v:27528.9-27528.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] + end + attribute \src "libresoc.v:27576.3-27624.6" + process $proc$libresoc.v:27576$608 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:27577.5-27577.29" + switch \initial + attribute \src "libresoc.v:27577.9-27577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "libresoc.v:27625.3-27673.6" + process $proc$libresoc.v:27625$609 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:27626.5-27626.29" + switch \initial + attribute \src "libresoc.v:27626.9-27626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] + end + attribute \src "libresoc.v:27674.3-27722.6" + process $proc$libresoc.v:27674$610 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:27675.5-27675.29" + switch \initial + attribute \src "libresoc.v:27675.9-27675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] + end + attribute \src "libresoc.v:27723.3-27771.6" + process $proc$libresoc.v:27723$611 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27724.5-27724.29" + switch \initial + attribute \src "libresoc.v:27724.9-27724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] + end + attribute \src "libresoc.v:27772.3-27820.6" + process $proc$libresoc.v:27772$612 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27773.5-27773.29" + switch \initial + attribute \src "libresoc.v:27773.9-27773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] + end + attribute \src "libresoc.v:27821.3-27869.6" + process $proc$libresoc.v:27821$613 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:27822.5-27822.29" + switch \initial + attribute \src "libresoc.v:27822.9-27822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] + end + attribute \src "libresoc.v:27870.3-27918.6" + process $proc$libresoc.v:27870$614 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:27871.5-27871.29" + switch \initial + attribute \src "libresoc.v:27871.9-27871.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] + end + attribute \src "libresoc.v:27919.3-27967.6" + process $proc$libresoc.v:27919$615 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:27920.5-27920.29" + switch \initial + attribute \src "libresoc.v:27920.9-27920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] + end + attribute \src "libresoc.v:27968.3-28016.6" + process $proc$libresoc.v:27968$616 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:27969.5-27969.29" + switch \initial + attribute \src "libresoc.v:27969.9-27969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "libresoc.v:28017.3-28065.6" + process $proc$libresoc.v:28017$617 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:28018.5-28018.29" + switch \initial + attribute \src "libresoc.v:28018.9-28018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] + end + attribute \src "libresoc.v:28066.3-28114.6" + process $proc$libresoc.v:28066$618 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:28067.5-28067.29" + switch \initial + attribute \src "libresoc.v:28067.9-28067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + end + attribute \src "libresoc.v:28115.3-28163.6" + process $proc$libresoc.v:28115$619 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:28116.5-28116.29" + switch \initial + attribute \src "libresoc.v:28116.9-28116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] + end + attribute \src "libresoc.v:28164.3-28212.6" + process $proc$libresoc.v:28164$620 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:28165.5-28165.29" + switch \initial + attribute \src "libresoc.v:28165.9-28165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] + end + attribute \src "libresoc.v:28213.3-28261.6" + process $proc$libresoc.v:28213$621 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28214.5-28214.29" + switch \initial + attribute \src "libresoc.v:28214.9-28214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] + end + attribute \src "libresoc.v:28262.3-28310.6" + process $proc$libresoc.v:28262$622 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28263.5-28263.29" + switch \initial + attribute \src "libresoc.v:28263.9-28263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] + end + attribute \src "libresoc.v:28311.3-28341.6" + process $proc$libresoc.v:28311$623 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:28312.5-28312.29" + switch \initial + attribute \src "libresoc.v:28312.9-28312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 + case + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] + end + attribute \src "libresoc.v:28342.3-28390.6" + process $proc$libresoc.v:28342$624 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:28343.5-28343.29" + switch \initial + attribute \src "libresoc.v:28343.9-28343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub21_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] + end + attribute \src "libresoc.v:28391.3-28439.6" + process $proc$libresoc.v:28391$625 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28392.5-28392.29" + switch \initial + attribute \src "libresoc.v:28392.9-28392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "libresoc.v:28440.3-28488.6" + process $proc$libresoc.v:28440$626 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28441.5-28441.29" + switch \initial + attribute \src "libresoc.v:28441.9-28441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "libresoc.v:28489.3-28537.6" + process $proc$libresoc.v:28489$627 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:28490.5-28490.29" + switch \initial + attribute \src "libresoc.v:28490.9-28490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] + end + attribute \src "libresoc.v:28538.3-28586.6" + process $proc$libresoc.v:28538$628 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:28539.5-28539.29" + switch \initial + attribute \src "libresoc.v:28539.9-28539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] + end + attribute \src "libresoc.v:28587.3-28635.6" + process $proc$libresoc.v:28587$629 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28588.5-28588.29" + switch \initial + attribute \src "libresoc.v:28588.9-28588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] + end + attribute \src "libresoc.v:28636.3-28684.6" + process $proc$libresoc.v:28636$630 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:28637.5-28637.29" + switch \initial + attribute \src "libresoc.v:28637.9-28637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:28690.1-30269.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" +attribute \generator "nMigen" +module \dec31_dec_sub22 + attribute \src "libresoc.v:29223.3-29277.6" + wire width 8 $0\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29443.3-29497.6" + wire $0\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:30158.3-30212.6" + wire width 3 $0\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30213.3-30267.6" + wire width 3 $0\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:29168.3-29222.6" + wire width 2 $0\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29388.3-29442.6" + wire $0\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29883.3-29937.6" + wire width 5 $0\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:28948.3-29002.6" + wire width 12 $0\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:29938.3-29992.6" + wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:29993.3-30047.6" + wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:30048.3-30102.6" + wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:29553.3-29607.6" + wire width 7 $0\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29278.3-29332.6" + wire $0\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29333.3-29387.6" + wire $0\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29663.3-29717.6" + wire $0\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:29003.3-29057.6" + wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:29773.3-29827.6" + wire $0\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:30103.3-30157.6" + wire width 2 $0\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:29113.3-29167.6" + wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:29608.3-29662.6" + wire $0\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29828.3-29882.6" + wire $0\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29718.3-29772.6" + wire $0\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29498.3-29552.6" + wire $0\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:29058.3-29112.6" + wire width 2 $0\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:28691.7-28691.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:29223.3-29277.6" + wire width 8 $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29443.3-29497.6" + wire $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:30158.3-30212.6" + wire width 3 $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30213.3-30267.6" + wire width 3 $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:29168.3-29222.6" + wire width 2 $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29388.3-29442.6" + wire $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29883.3-29937.6" + wire width 5 $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:28948.3-29002.6" + wire width 12 $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:29938.3-29992.6" + wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:29993.3-30047.6" + wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:30048.3-30102.6" + wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:29553.3-29607.6" + wire width 7 $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29278.3-29332.6" + wire $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29333.3-29387.6" + wire $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29663.3-29717.6" + wire $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:29003.3-29057.6" + wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:29773.3-29827.6" + wire $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:30103.3-30157.6" + wire width 2 $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:29113.3-29167.6" + wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:29608.3-29662.6" + wire $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29828.3-29882.6" + wire $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29718.3-29772.6" + wire $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29498.3-29552.6" + wire $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:29058.3-29112.6" + wire width 2 $1\dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub22_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub22_upd + attribute \src "libresoc.v:28691.7-28691.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:28691.7-28691.20" + process $proc$libresoc.v:28691$656 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:28948.3-29002.6" + process $proc$libresoc.v:28948$632 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:28949.5-28949.29" + switch \initial + attribute \src "libresoc.v:28949.9-28949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] + end + attribute \src "libresoc.v:29003.3-29057.6" + process $proc$libresoc.v:29003$633 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:29004.5-29004.29" + switch \initial + attribute \src "libresoc.v:29004.9-29004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:29058.3-29112.6" + process $proc$libresoc.v:29058$634 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:29059.5-29059.29" + switch \initial + attribute \src "libresoc.v:29059.9-29059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] + end + attribute \src "libresoc.v:29113.3-29167.6" + process $proc$libresoc.v:29113$635 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:29114.5-29114.29" + switch \initial + attribute \src "libresoc.v:29114.9-29114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "libresoc.v:29168.3-29222.6" + process $proc$libresoc.v:29168$636 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29169.5-29169.29" + switch \initial + attribute \src "libresoc.v:29169.9-29169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] + end + attribute \src "libresoc.v:29223.3-29277.6" + process $proc$libresoc.v:29223$637 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29224.5-29224.29" + switch \initial + attribute \src "libresoc.v:29224.9-29224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 + case + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] + end + attribute \src "libresoc.v:29278.3-29332.6" + process $proc$libresoc.v:29278$638 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29279.5-29279.29" + switch \initial + attribute \src "libresoc.v:29279.9-29279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] + end + attribute \src "libresoc.v:29333.3-29387.6" + process $proc$libresoc.v:29333$639 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29334.5-29334.29" + switch \initial + attribute \src "libresoc.v:29334.9-29334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] + end + attribute \src "libresoc.v:29388.3-29442.6" + process $proc$libresoc.v:29388$640 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29389.5-29389.29" + switch \initial + attribute \src "libresoc.v:29389.9-29389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] + end + attribute \src "libresoc.v:29443.3-29497.6" + process $proc$libresoc.v:29443$641 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:29444.5-29444.29" + switch \initial + attribute \src "libresoc.v:29444.9-29444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] + end + attribute \src "libresoc.v:29498.3-29552.6" + process $proc$libresoc.v:29498$642 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:29499.5-29499.29" + switch \initial + attribute \src "libresoc.v:29499.9-29499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "libresoc.v:29553.3-29607.6" + process $proc$libresoc.v:29553$643 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29554.5-29554.29" + switch \initial + attribute \src "libresoc.v:29554.9-29554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:29608.3-29662.6" + process $proc$libresoc.v:29608$644 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29609.5-29609.29" + switch \initial + attribute \src "libresoc.v:29609.9-29609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] + end + attribute \src "libresoc.v:29663.3-29717.6" + process $proc$libresoc.v:29663$645 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:29664.5-29664.29" + switch \initial + attribute \src "libresoc.v:29664.9-29664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:29718.3-29772.6" + process $proc$libresoc.v:29718$646 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29719.5-29719.29" + switch \initial + attribute \src "libresoc.v:29719.9-29719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:29773.3-29827.6" + process $proc$libresoc.v:29773$647 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:29774.5-29774.29" + switch \initial + attribute \src "libresoc.v:29774.9-29774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] + end + attribute \src "libresoc.v:29828.3-29882.6" + process $proc$libresoc.v:29828$648 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29829.5-29829.29" + switch \initial + attribute \src "libresoc.v:29829.9-29829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] + end + attribute \src "libresoc.v:29883.3-29937.6" + process $proc$libresoc.v:29883$649 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:29884.5-29884.29" + switch \initial + attribute \src "libresoc.v:29884.9-29884.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub22_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] + end + attribute \src "libresoc.v:29938.3-29992.6" + process $proc$libresoc.v:29938$650 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:29939.5-29939.29" + switch \initial + attribute \src "libresoc.v:29939.9-29939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:29993.3-30047.6" + process $proc$libresoc.v:29993$651 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:29994.5-29994.29" + switch \initial + attribute \src "libresoc.v:29994.9-29994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:30048.3-30102.6" + process $proc$libresoc.v:30048$652 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:30049.5-30049.29" + switch \initial + attribute \src "libresoc.v:30049.9-30049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] + end + attribute \src "libresoc.v:30103.3-30157.6" + process $proc$libresoc.v:30103$653 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:30104.5-30104.29" + switch \initial + attribute \src "libresoc.v:30104.9-30104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] + end + attribute \src "libresoc.v:30158.3-30212.6" + process $proc$libresoc.v:30158$654 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30159.5-30159.29" + switch \initial + attribute \src "libresoc.v:30159.9-30159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:30213.3-30267.6" + process $proc$libresoc.v:30213$655 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:30214.5-30214.29" + switch \initial + attribute \src "libresoc.v:30214.9-30214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:30273.1-31708.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" +attribute \generator "nMigen" +module \dec31_dec_sub23 + attribute \src "libresoc.v:30776.3-30824.6" + wire width 8 $0\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:30972.3-31020.6" + wire $0\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:31609.3-31657.6" + wire width 3 $0\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31658.3-31706.6" + wire width 3 $0\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:30727.3-30775.6" + wire width 2 $0\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30923.3-30971.6" + wire $0\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:31364.3-31412.6" + wire width 5 $0\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:30531.3-30579.6" + wire width 12 $0\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:31413.3-31461.6" + wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31462.3-31510.6" + wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:31511.3-31559.6" + wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:31070.3-31118.6" + wire width 7 $0\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:30825.3-30873.6" + wire $0\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:30874.3-30922.6" + wire $0\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:31168.3-31216.6" + wire $0\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:30580.3-30628.6" + wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:31266.3-31314.6" + wire $0\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:31560.3-31608.6" + wire width 2 $0\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:30678.3-30726.6" + wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:31119.3-31167.6" + wire $0\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:31315.3-31363.6" + wire $0\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:31217.3-31265.6" + wire $0\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:31021.3-31069.6" + wire $0\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:30629.3-30677.6" + wire width 2 $0\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:30274.7-30274.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:30776.3-30824.6" + wire width 8 $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:30972.3-31020.6" + wire $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:31609.3-31657.6" + wire width 3 $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31658.3-31706.6" + wire width 3 $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:30727.3-30775.6" + wire width 2 $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30923.3-30971.6" + wire $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:31364.3-31412.6" + wire width 5 $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:30531.3-30579.6" + wire width 12 $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:31413.3-31461.6" + wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31462.3-31510.6" + wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:31511.3-31559.6" + wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:31070.3-31118.6" + wire width 7 $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:30825.3-30873.6" + wire $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:30874.3-30922.6" + wire $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:31168.3-31216.6" + wire $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:30580.3-30628.6" + wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:31266.3-31314.6" + wire $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:31560.3-31608.6" + wire width 2 $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:30678.3-30726.6" + wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:31119.3-31167.6" + wire $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:31315.3-31363.6" + wire $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:31217.3-31265.6" + wire $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:31021.3-31069.6" + wire $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:30629.3-30677.6" + wire width 2 $1\dec31_dec_sub23_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub23_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub23_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub23_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub23_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub23_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub23_upd + attribute \src "libresoc.v:30274.7-30274.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:30274.7-30274.20" + process $proc$libresoc.v:30274$681 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:30531.3-30579.6" + process $proc$libresoc.v:30531$657 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:30532.5-30532.29" + switch \initial + attribute \src "libresoc.v:30532.9-30532.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] + end + attribute \src "libresoc.v:30580.3-30628.6" + process $proc$libresoc.v:30580$658 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:30581.5-30581.29" + switch \initial + attribute \src "libresoc.v:30581.9-30581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] + end + attribute \src "libresoc.v:30629.3-30677.6" + process $proc$libresoc.v:30629$659 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:30630.5-30630.29" + switch \initial + attribute \src "libresoc.v:30630.9-30630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] + end + attribute \src "libresoc.v:30678.3-30726.6" + process $proc$libresoc.v:30678$660 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:30679.5-30679.29" + switch \initial + attribute \src "libresoc.v:30679.9-30679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] + end + attribute \src "libresoc.v:30727.3-30775.6" + process $proc$libresoc.v:30727$661 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30728.5-30728.29" + switch \initial + attribute \src "libresoc.v:30728.9-30728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] + end + attribute \src "libresoc.v:30776.3-30824.6" + process $proc$libresoc.v:30776$662 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:30777.5-30777.29" + switch \initial + attribute \src "libresoc.v:30777.9-30777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 + case + assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] + end + attribute \src "libresoc.v:30825.3-30873.6" + process $proc$libresoc.v:30825$663 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:30826.5-30826.29" + switch \initial + attribute \src "libresoc.v:30826.9-30826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] + end + attribute \src "libresoc.v:30874.3-30922.6" + process $proc$libresoc.v:30874$664 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:30875.5-30875.29" + switch \initial + attribute \src "libresoc.v:30875.9-30875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] + end + attribute \src "libresoc.v:30923.3-30971.6" + process $proc$libresoc.v:30923$665 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:30924.5-30924.29" + switch \initial + attribute \src "libresoc.v:30924.9-30924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] + end + attribute \src "libresoc.v:30972.3-31020.6" + process $proc$libresoc.v:30972$666 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:30973.5-30973.29" + switch \initial + attribute \src "libresoc.v:30973.9-30973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] + end + attribute \src "libresoc.v:31021.3-31069.6" + process $proc$libresoc.v:31021$667 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:31022.5-31022.29" + switch \initial + attribute \src "libresoc.v:31022.9-31022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] + end + attribute \src "libresoc.v:31070.3-31118.6" + process $proc$libresoc.v:31070$668 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:31071.5-31071.29" + switch \initial + attribute \src "libresoc.v:31071.9-31071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] + end + attribute \src "libresoc.v:31119.3-31167.6" + process $proc$libresoc.v:31119$669 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:31120.5-31120.29" + switch \initial + attribute \src "libresoc.v:31120.9-31120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] + end + attribute \src "libresoc.v:31168.3-31216.6" + process $proc$libresoc.v:31168$670 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:31169.5-31169.29" + switch \initial + attribute \src "libresoc.v:31169.9-31169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] + end + attribute \src "libresoc.v:31217.3-31265.6" + process $proc$libresoc.v:31217$671 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:31218.5-31218.29" + switch \initial + attribute \src "libresoc.v:31218.9-31218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] + end + attribute \src "libresoc.v:31266.3-31314.6" + process $proc$libresoc.v:31266$672 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:31267.5-31267.29" + switch \initial + attribute \src "libresoc.v:31267.9-31267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] + end + attribute \src "libresoc.v:31315.3-31363.6" + process $proc$libresoc.v:31315$673 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:31316.5-31316.29" + switch \initial + attribute \src "libresoc.v:31316.9-31316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] + end + attribute \src "libresoc.v:31364.3-31412.6" + process $proc$libresoc.v:31364$674 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:31365.5-31365.29" + switch \initial + attribute \src "libresoc.v:31365.9-31365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub23_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + end + attribute \src "libresoc.v:31413.3-31461.6" + process $proc$libresoc.v:31413$675 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31414.5-31414.29" + switch \initial + attribute \src "libresoc.v:31414.9-31414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "libresoc.v:31462.3-31510.6" + process $proc$libresoc.v:31462$676 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:31463.5-31463.29" + switch \initial + attribute \src "libresoc.v:31463.9-31463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "libresoc.v:31511.3-31559.6" + process $proc$libresoc.v:31511$677 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:31512.5-31512.29" + switch \initial + attribute \src "libresoc.v:31512.9-31512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] + end + attribute \src "libresoc.v:31560.3-31608.6" + process $proc$libresoc.v:31560$678 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:31561.5-31561.29" + switch \initial + attribute \src "libresoc.v:31561.9-31561.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] + end + attribute \src "libresoc.v:31609.3-31657.6" + process $proc$libresoc.v:31609$679 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31610.5-31610.29" + switch \initial + attribute \src "libresoc.v:31610.9-31610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] + end + attribute \src "libresoc.v:31658.3-31706.6" + process $proc$libresoc.v:31658$680 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:31659.5-31659.29" + switch \initial + attribute \src "libresoc.v:31659.9-31659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:31712.1-32427.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" +attribute \generator "nMigen" +module \dec31_dec_sub24 + attribute \src "libresoc.v:32065.3-32083.6" + wire width 8 $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:32141.3-32159.6" + wire $0\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32388.3-32406.6" + wire width 3 $0\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32407.3-32425.6" + wire width 3 $0\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:32046.3-32064.6" + wire width 2 $0\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:32122.3-32140.6" + wire $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:32293.3-32311.6" + wire width 5 $0\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:31970.3-31988.6" + wire width 12 $0\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:32312.3-32330.6" + wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32331.3-32349.6" + wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32350.3-32368.6" + wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32179.3-32197.6" + wire width 7 $0\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:32084.3-32102.6" + wire $0\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:32103.3-32121.6" + wire $0\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:32217.3-32235.6" + wire $0\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:31989.3-32007.6" + wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:32255.3-32273.6" + wire $0\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32369.3-32387.6" + wire width 2 $0\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:32027.3-32045.6" + wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:32198.3-32216.6" + wire $0\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32274.3-32292.6" + wire $0\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32236.3-32254.6" + wire $0\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32160.3-32178.6" + wire $0\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:32008.3-32026.6" + wire width 2 $0\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:31713.7-31713.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:32065.3-32083.6" + wire width 8 $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:32141.3-32159.6" + wire $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32388.3-32406.6" + wire width 3 $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32407.3-32425.6" + wire width 3 $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:32046.3-32064.6" + wire width 2 $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:32122.3-32140.6" + wire $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:32293.3-32311.6" + wire width 5 $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:31970.3-31988.6" + wire width 12 $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:32312.3-32330.6" + wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32331.3-32349.6" + wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32350.3-32368.6" + wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32179.3-32197.6" + wire width 7 $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:32084.3-32102.6" + wire $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:32103.3-32121.6" + wire $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:32217.3-32235.6" + wire $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:31989.3-32007.6" + wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:32255.3-32273.6" + wire $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32369.3-32387.6" + wire width 2 $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:32027.3-32045.6" + wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:32198.3-32216.6" + wire $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32274.3-32292.6" + wire $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32236.3-32254.6" + wire $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32160.3-32178.6" + wire $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:32008.3-32026.6" + wire width 2 $1\dec31_dec_sub24_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub24_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub24_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub24_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub24_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub24_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub24_upd + attribute \src "libresoc.v:31713.7-31713.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:31713.7-31713.20" + process $proc$libresoc.v:31713$706 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31970.3-31988.6" + process $proc$libresoc.v:31970$682 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:31971.5-31971.29" + switch \initial + attribute \src "libresoc.v:31971.9-31971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] + end + attribute \src "libresoc.v:31989.3-32007.6" + process $proc$libresoc.v:31989$683 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:31990.5-31990.29" + switch \initial + attribute \src "libresoc.v:31990.9-31990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] + end + attribute \src "libresoc.v:32008.3-32026.6" + process $proc$libresoc.v:32008$684 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:32009.5-32009.29" + switch \initial + attribute \src "libresoc.v:32009.9-32009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] + end + attribute \src "libresoc.v:32027.3-32045.6" + process $proc$libresoc.v:32027$685 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:32028.5-32028.29" + switch \initial + attribute \src "libresoc.v:32028.9-32028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "libresoc.v:32046.3-32064.6" + process $proc$libresoc.v:32046$686 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:32047.5-32047.29" + switch \initial + attribute \src "libresoc.v:32047.9-32047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] + end + attribute \src "libresoc.v:32065.3-32083.6" + process $proc$libresoc.v:32065$687 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:32066.5-32066.29" + switch \initial + attribute \src "libresoc.v:32066.9-32066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 + case + assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] + end + attribute \src "libresoc.v:32084.3-32102.6" + process $proc$libresoc.v:32084$688 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:32085.5-32085.29" + switch \initial + attribute \src "libresoc.v:32085.9-32085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] + end + attribute \src "libresoc.v:32103.3-32121.6" + process $proc$libresoc.v:32103$689 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:32104.5-32104.29" + switch \initial + attribute \src "libresoc.v:32104.9-32104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] + end + attribute \src "libresoc.v:32122.3-32140.6" + process $proc$libresoc.v:32122$690 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:32123.5-32123.29" + switch \initial + attribute \src "libresoc.v:32123.9-32123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] + end + attribute \src "libresoc.v:32141.3-32159.6" + process $proc$libresoc.v:32141$691 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32142.5-32142.29" + switch \initial + attribute \src "libresoc.v:32142.9-32142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + case + assign $1\dec31_dec_sub24_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] + end + attribute \src "libresoc.v:32160.3-32178.6" + process $proc$libresoc.v:32160$692 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:32161.5-32161.29" + switch \initial + attribute \src "libresoc.v:32161.9-32161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] + end + attribute \src "libresoc.v:32179.3-32197.6" + process $proc$libresoc.v:32179$693 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:32180.5-32180.29" + switch \initial + attribute \src "libresoc.v:32180.9-32180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] + end + attribute \src "libresoc.v:32198.3-32216.6" + process $proc$libresoc.v:32198$694 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32199.5-32199.29" + switch \initial + attribute \src "libresoc.v:32199.9-32199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] + end + attribute \src "libresoc.v:32217.3-32235.6" + process $proc$libresoc.v:32217$695 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:32218.5-32218.29" + switch \initial + attribute \src "libresoc.v:32218.9-32218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] + end + attribute \src "libresoc.v:32236.3-32254.6" + process $proc$libresoc.v:32236$696 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32237.5-32237.29" + switch \initial + attribute \src "libresoc.v:32237.9-32237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] + end + attribute \src "libresoc.v:32255.3-32273.6" + process $proc$libresoc.v:32255$697 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32256.5-32256.29" + switch \initial + attribute \src "libresoc.v:32256.9-32256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] + end + attribute \src "libresoc.v:32274.3-32292.6" + process $proc$libresoc.v:32274$698 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32275.5-32275.29" + switch \initial + attribute \src "libresoc.v:32275.9-32275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] + end + attribute \src "libresoc.v:32293.3-32311.6" + process $proc$libresoc.v:32293$699 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:32294.5-32294.29" + switch \initial + attribute \src "libresoc.v:32294.9-32294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub24_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + end + attribute \src "libresoc.v:32312.3-32330.6" + process $proc$libresoc.v:32312$700 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32313.5-32313.29" + switch \initial + attribute \src "libresoc.v:32313.9-32313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] + end + attribute \src "libresoc.v:32331.3-32349.6" + process $proc$libresoc.v:32331$701 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32332.5-32332.29" + switch \initial + attribute \src "libresoc.v:32332.9-32332.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "libresoc.v:32350.3-32368.6" + process $proc$libresoc.v:32350$702 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32351.5-32351.29" + switch \initial + attribute \src "libresoc.v:32351.9-32351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] + end + attribute \src "libresoc.v:32369.3-32387.6" + process $proc$libresoc.v:32369$703 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:32370.5-32370.29" + switch \initial + attribute \src "libresoc.v:32370.9-32370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] + end + attribute \src "libresoc.v:32388.3-32406.6" + process $proc$libresoc.v:32388$704 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32389.5-32389.29" + switch \initial + attribute \src "libresoc.v:32389.9-32389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] + end + attribute \src "libresoc.v:32407.3-32425.6" + process $proc$libresoc.v:32407$705 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:32408.5-32408.29" + switch \initial + attribute \src "libresoc.v:32408.9-32408.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:32431.1-33938.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" +attribute \generator "nMigen" +module \dec31_dec_sub26 + attribute \src "libresoc.v:32949.3-33000.6" + wire width 8 $0\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:33157.3-33208.6" + wire $0\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33833.3-33884.6" + wire width 3 $0\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33885.3-33936.6" + wire width 3 $0\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:32897.3-32948.6" + wire width 2 $0\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:33105.3-33156.6" + wire $0\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:33573.3-33624.6" + wire width 5 $0\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:32689.3-32740.6" + wire width 12 $0\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:33625.3-33676.6" + wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33677.3-33728.6" + wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33729.3-33780.6" + wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33261.3-33312.6" + wire width 7 $0\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:33001.3-33052.6" + wire $0\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:33053.3-33104.6" + wire $0\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:33365.3-33416.6" + wire $0\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:32741.3-32792.6" + wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:33469.3-33520.6" + wire $0\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33781.3-33832.6" + wire width 2 $0\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:32845.3-32896.6" + wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:33313.3-33364.6" + wire $0\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33521.3-33572.6" + wire $0\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33417.3-33468.6" + wire $0\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33209.3-33260.6" + wire $0\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:32793.3-32844.6" + wire width 2 $0\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:32432.7-32432.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:32949.3-33000.6" + wire width 8 $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:33157.3-33208.6" + wire $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33833.3-33884.6" + wire width 3 $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33885.3-33936.6" + wire width 3 $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:32897.3-32948.6" + wire width 2 $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:33105.3-33156.6" + wire $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:33573.3-33624.6" + wire width 5 $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:32689.3-32740.6" + wire width 12 $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:33625.3-33676.6" + wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33677.3-33728.6" + wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33729.3-33780.6" + wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33261.3-33312.6" + wire width 7 $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:33001.3-33052.6" + wire $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:33053.3-33104.6" + wire $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:33365.3-33416.6" + wire $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:32741.3-32792.6" + wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:33469.3-33520.6" + wire $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33781.3-33832.6" + wire width 2 $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:32845.3-32896.6" + wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:33313.3-33364.6" + wire $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33521.3-33572.6" + wire $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33417.3-33468.6" + wire $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33209.3-33260.6" + wire $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:32793.3-32844.6" + wire width 2 $1\dec31_dec_sub26_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub26_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub26_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub26_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub26_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub26_upd + attribute \src "libresoc.v:32432.7-32432.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:32432.7-32432.20" + process $proc$libresoc.v:32432$731 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:32689.3-32740.6" + process $proc$libresoc.v:32689$707 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:32690.5-32690.29" + switch \initial + attribute \src "libresoc.v:32690.9-32690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] + end + attribute \src "libresoc.v:32741.3-32792.6" + process $proc$libresoc.v:32741$708 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:32742.5-32742.29" + switch \initial + attribute \src "libresoc.v:32742.9-32742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:32793.3-32844.6" + process $proc$libresoc.v:32793$709 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:32794.5-32794.29" + switch \initial + attribute \src "libresoc.v:32794.9-32794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] + end + attribute \src "libresoc.v:32845.3-32896.6" + process $proc$libresoc.v:32845$710 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:32846.5-32846.29" + switch \initial + attribute \src "libresoc.v:32846.9-32846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:32897.3-32948.6" + process $proc$libresoc.v:32897$711 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:32898.5-32898.29" + switch \initial + attribute \src "libresoc.v:32898.9-32898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] + end + attribute \src "libresoc.v:32949.3-33000.6" + process $proc$libresoc.v:32949$712 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:32950.5-32950.29" + switch \initial + attribute \src "libresoc.v:32950.9-32950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 + case + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] + end + attribute \src "libresoc.v:33001.3-33052.6" + process $proc$libresoc.v:33001$713 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:33002.5-33002.29" + switch \initial + attribute \src "libresoc.v:33002.9-33002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:33053.3-33104.6" + process $proc$libresoc.v:33053$714 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:33054.5-33054.29" + switch \initial + attribute \src "libresoc.v:33054.9-33054.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:33105.3-33156.6" + process $proc$libresoc.v:33105$715 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:33106.5-33106.29" + switch \initial + attribute \src "libresoc.v:33106.9-33106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:33157.3-33208.6" + process $proc$libresoc.v:33157$716 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33158.5-33158.29" + switch \initial + attribute \src "libresoc.v:33158.9-33158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + case + assign $1\dec31_dec_sub26_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] + end + attribute \src "libresoc.v:33209.3-33260.6" + process $proc$libresoc.v:33209$717 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:33210.5-33210.29" + switch \initial + attribute \src "libresoc.v:33210.9-33210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] + end + attribute \src "libresoc.v:33261.3-33312.6" + process $proc$libresoc.v:33261$718 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:33262.5-33262.29" + switch \initial + attribute \src "libresoc.v:33262.9-33262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:33313.3-33364.6" + process $proc$libresoc.v:33313$719 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33314.5-33314.29" + switch \initial + attribute \src "libresoc.v:33314.9-33314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] + end + attribute \src "libresoc.v:33365.3-33416.6" + process $proc$libresoc.v:33365$720 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:33366.5-33366.29" + switch \initial + attribute \src "libresoc.v:33366.9-33366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:33417.3-33468.6" + process $proc$libresoc.v:33417$721 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33418.5-33418.29" + switch \initial + attribute \src "libresoc.v:33418.9-33418.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:33469.3-33520.6" + process $proc$libresoc.v:33469$722 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33470.5-33470.29" + switch \initial + attribute \src "libresoc.v:33470.9-33470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] + end + attribute \src "libresoc.v:33521.3-33572.6" + process $proc$libresoc.v:33521$723 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33522.5-33522.29" + switch \initial + attribute \src "libresoc.v:33522.9-33522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] + end + attribute \src "libresoc.v:33573.3-33624.6" + process $proc$libresoc.v:33573$724 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:33574.5-33574.29" + switch \initial + attribute \src "libresoc.v:33574.9-33574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + case + assign $1\dec31_dec_sub26_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] + end + attribute \src "libresoc.v:33625.3-33676.6" + process $proc$libresoc.v:33625$725 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33626.5-33626.29" + switch \initial + attribute \src "libresoc.v:33626.9-33626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:33677.3-33728.6" + process $proc$libresoc.v:33677$726 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33678.5-33678.29" + switch \initial + attribute \src "libresoc.v:33678.9-33678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:33729.3-33780.6" + process $proc$libresoc.v:33729$727 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33730.5-33730.29" + switch \initial + attribute \src "libresoc.v:33730.9-33730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] + end + attribute \src "libresoc.v:33781.3-33832.6" + process $proc$libresoc.v:33781$728 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:33782.5-33782.29" + switch \initial + attribute \src "libresoc.v:33782.9-33782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] + end + attribute \src "libresoc.v:33833.3-33884.6" + process $proc$libresoc.v:33833$729 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33834.5-33834.29" + switch \initial + attribute \src "libresoc.v:33834.9-33834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:33885.3-33936.6" + process $proc$libresoc.v:33885$730 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:33886.5-33886.29" + switch \initial + attribute \src "libresoc.v:33886.9-33886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:33942.1-34657.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" +attribute \generator "nMigen" +module \dec31_dec_sub27 + attribute \src "libresoc.v:34295.3-34313.6" + wire width 8 $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34371.3-34389.6" + wire $0\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34618.3-34636.6" + wire width 3 $0\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34637.3-34655.6" + wire width 3 $0\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34276.3-34294.6" + wire width 2 $0\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34352.3-34370.6" + wire $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34523.3-34541.6" + wire width 5 $0\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34200.3-34218.6" + wire width 12 $0\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34542.3-34560.6" + wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34561.3-34579.6" + wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34580.3-34598.6" + wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34409.3-34427.6" + wire width 7 $0\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:34314.3-34332.6" + wire $0\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34333.3-34351.6" + wire $0\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34447.3-34465.6" + wire $0\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34219.3-34237.6" + wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34485.3-34503.6" + wire $0\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34599.3-34617.6" + wire width 2 $0\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34257.3-34275.6" + wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34428.3-34446.6" + wire $0\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34504.3-34522.6" + wire $0\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34466.3-34484.6" + wire $0\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34390.3-34408.6" + wire $0\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34238.3-34256.6" + wire width 2 $0\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:33943.7-33943.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:34295.3-34313.6" + wire width 8 $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34371.3-34389.6" + wire $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34618.3-34636.6" + wire width 3 $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34637.3-34655.6" + wire width 3 $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34276.3-34294.6" + wire width 2 $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34352.3-34370.6" + wire $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34523.3-34541.6" + wire width 5 $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34200.3-34218.6" + wire width 12 $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34542.3-34560.6" + wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34561.3-34579.6" + wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34580.3-34598.6" + wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34409.3-34427.6" + wire width 7 $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:34314.3-34332.6" + wire $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34333.3-34351.6" + wire $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34447.3-34465.6" + wire $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34219.3-34237.6" + wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34485.3-34503.6" + wire $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34599.3-34617.6" + wire width 2 $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34257.3-34275.6" + wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34428.3-34446.6" + wire $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34504.3-34522.6" + wire $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34466.3-34484.6" + wire $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34390.3-34408.6" + wire $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34238.3-34256.6" + wire width 2 $1\dec31_dec_sub27_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub27_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub27_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub27_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub27_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub27_upd + attribute \src "libresoc.v:33943.7-33943.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:33943.7-33943.20" + process $proc$libresoc.v:33943$756 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34200.3-34218.6" + process $proc$libresoc.v:34200$732 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34201.5-34201.29" + switch \initial + attribute \src "libresoc.v:34201.9-34201.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] + end + attribute \src "libresoc.v:34219.3-34237.6" + process $proc$libresoc.v:34219$733 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34220.5-34220.29" + switch \initial + attribute \src "libresoc.v:34220.9-34220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] + end + attribute \src "libresoc.v:34238.3-34256.6" + process $proc$libresoc.v:34238$734 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:34239.5-34239.29" + switch \initial + attribute \src "libresoc.v:34239.9-34239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] + end + attribute \src "libresoc.v:34257.3-34275.6" + process $proc$libresoc.v:34257$735 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34258.5-34258.29" + switch \initial + attribute \src "libresoc.v:34258.9-34258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "libresoc.v:34276.3-34294.6" + process $proc$libresoc.v:34276$736 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34277.5-34277.29" + switch \initial + attribute \src "libresoc.v:34277.9-34277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] + end + attribute \src "libresoc.v:34295.3-34313.6" + process $proc$libresoc.v:34295$737 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34296.5-34296.29" + switch \initial + attribute \src "libresoc.v:34296.9-34296.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 + case + assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] + end + attribute \src "libresoc.v:34314.3-34332.6" + process $proc$libresoc.v:34314$738 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34315.5-34315.29" + switch \initial + attribute \src "libresoc.v:34315.9-34315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] + end + attribute \src "libresoc.v:34333.3-34351.6" + process $proc$libresoc.v:34333$739 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34334.5-34334.29" + switch \initial + attribute \src "libresoc.v:34334.9-34334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] + end + attribute \src "libresoc.v:34352.3-34370.6" + process $proc$libresoc.v:34352$740 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34353.5-34353.29" + switch \initial + attribute \src "libresoc.v:34353.9-34353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] + end + attribute \src "libresoc.v:34371.3-34389.6" + process $proc$libresoc.v:34371$741 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34372.5-34372.29" + switch \initial + attribute \src "libresoc.v:34372.9-34372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + case + assign $1\dec31_dec_sub27_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] + end + attribute \src "libresoc.v:34390.3-34408.6" + process $proc$libresoc.v:34390$742 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34391.5-34391.29" + switch \initial + attribute \src "libresoc.v:34391.9-34391.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] + end + attribute \src "libresoc.v:34409.3-34427.6" + process $proc$libresoc.v:34409$743 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:34410.5-34410.29" + switch \initial + attribute \src "libresoc.v:34410.9-34410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] + end + attribute \src "libresoc.v:34428.3-34446.6" + process $proc$libresoc.v:34428$744 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34429.5-34429.29" + switch \initial + attribute \src "libresoc.v:34429.9-34429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] + end + attribute \src "libresoc.v:34447.3-34465.6" + process $proc$libresoc.v:34447$745 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34448.5-34448.29" + switch \initial + attribute \src "libresoc.v:34448.9-34448.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] + end + attribute \src "libresoc.v:34466.3-34484.6" + process $proc$libresoc.v:34466$746 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34467.5-34467.29" + switch \initial + attribute \src "libresoc.v:34467.9-34467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] + end + attribute \src "libresoc.v:34485.3-34503.6" + process $proc$libresoc.v:34485$747 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34486.5-34486.29" + switch \initial + attribute \src "libresoc.v:34486.9-34486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] + end + attribute \src "libresoc.v:34504.3-34522.6" + process $proc$libresoc.v:34504$748 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34505.5-34505.29" + switch \initial + attribute \src "libresoc.v:34505.9-34505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] + end + attribute \src "libresoc.v:34523.3-34541.6" + process $proc$libresoc.v:34523$749 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34524.5-34524.29" + switch \initial + attribute \src "libresoc.v:34524.9-34524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub27_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] + end + attribute \src "libresoc.v:34542.3-34560.6" + process $proc$libresoc.v:34542$750 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34543.5-34543.29" + switch \initial + attribute \src "libresoc.v:34543.9-34543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] + end + attribute \src "libresoc.v:34561.3-34579.6" + process $proc$libresoc.v:34561$751 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34562.5-34562.29" + switch \initial + attribute \src "libresoc.v:34562.9-34562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "libresoc.v:34580.3-34598.6" + process $proc$libresoc.v:34580$752 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34581.5-34581.29" + switch \initial + attribute \src "libresoc.v:34581.9-34581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] + end + attribute \src "libresoc.v:34599.3-34617.6" + process $proc$libresoc.v:34599$753 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34600.5-34600.29" + switch \initial + attribute \src "libresoc.v:34600.9-34600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] + end + attribute \src "libresoc.v:34618.3-34636.6" + process $proc$libresoc.v:34618$754 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34619.5-34619.29" + switch \initial + attribute \src "libresoc.v:34619.9-34619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] + end + attribute \src "libresoc.v:34637.3-34655.6" + process $proc$libresoc.v:34637$755 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34638.5-34638.29" + switch \initial + attribute \src "libresoc.v:34638.9-34638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:34661.1-35808.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" +attribute \generator "nMigen" +module \dec31_dec_sub28 + attribute \src "libresoc.v:35104.3-35140.6" + wire width 8 $0\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:35252.3-35288.6" + wire $0\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35733.3-35769.6" + wire width 3 $0\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35770.3-35806.6" + wire width 3 $0\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:35067.3-35103.6" + wire width 2 $0\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:35215.3-35251.6" + wire $0\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35548.3-35584.6" + wire width 5 $0\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:34919.3-34955.6" + wire width 12 $0\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:35585.3-35621.6" + wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35622.3-35658.6" + wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35659.3-35695.6" + wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35326.3-35362.6" + wire width 7 $0\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35141.3-35177.6" + wire $0\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35178.3-35214.6" + wire $0\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35400.3-35436.6" + wire $0\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:34956.3-34992.6" + wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:35474.3-35510.6" + wire $0\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35696.3-35732.6" + wire width 2 $0\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:35030.3-35066.6" + wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:35363.3-35399.6" + wire $0\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35511.3-35547.6" + wire $0\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35437.3-35473.6" + wire $0\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:35289.3-35325.6" + wire $0\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:34993.3-35029.6" + wire width 2 $0\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:34662.7-34662.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:35104.3-35140.6" + wire width 8 $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:35252.3-35288.6" + wire $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35733.3-35769.6" + wire width 3 $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35770.3-35806.6" + wire width 3 $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:35067.3-35103.6" + wire width 2 $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:35215.3-35251.6" + wire $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35548.3-35584.6" + wire width 5 $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:34919.3-34955.6" + wire width 12 $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:35585.3-35621.6" + wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35622.3-35658.6" + wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35659.3-35695.6" + wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35326.3-35362.6" + wire width 7 $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35141.3-35177.6" + wire $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35178.3-35214.6" + wire $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35400.3-35436.6" + wire $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:34956.3-34992.6" + wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:35474.3-35510.6" + wire $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35696.3-35732.6" + wire width 2 $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:35030.3-35066.6" + wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:35363.3-35399.6" + wire $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35511.3-35547.6" + wire $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35437.3-35473.6" + wire $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:35289.3-35325.6" + wire $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:34993.3-35029.6" + wire width 2 $1\dec31_dec_sub28_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub28_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub28_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub28_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub28_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub28_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub28_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub28_upd + attribute \src "libresoc.v:34662.7-34662.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:34662.7-34662.20" + process $proc$libresoc.v:34662$781 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34919.3-34955.6" + process $proc$libresoc.v:34919$757 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:34920.5-34920.29" + switch \initial + attribute \src "libresoc.v:34920.9-34920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + case + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] + end + attribute \src "libresoc.v:34956.3-34992.6" + process $proc$libresoc.v:34956$758 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:34957.5-34957.29" + switch \initial + attribute \src "libresoc.v:34957.9-34957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "libresoc.v:34993.3-35029.6" + process $proc$libresoc.v:34993$759 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:34994.5-34994.29" + switch \initial + attribute \src "libresoc.v:34994.9-34994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] + end + attribute \src "libresoc.v:35030.3-35066.6" + process $proc$libresoc.v:35030$760 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:35031.5-35031.29" + switch \initial + attribute \src "libresoc.v:35031.9-35031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "libresoc.v:35067.3-35103.6" + process $proc$libresoc.v:35067$761 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:35068.5-35068.29" + switch \initial + attribute \src "libresoc.v:35068.9-35068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] + end + attribute \src "libresoc.v:35104.3-35140.6" + process $proc$libresoc.v:35104$762 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:35105.5-35105.29" + switch \initial + attribute \src "libresoc.v:35105.9-35105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 + case + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] + end + attribute \src "libresoc.v:35141.3-35177.6" + process $proc$libresoc.v:35141$763 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35142.5-35142.29" + switch \initial + attribute \src "libresoc.v:35142.9-35142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] + end + attribute \src "libresoc.v:35178.3-35214.6" + process $proc$libresoc.v:35178$764 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35179.5-35179.29" + switch \initial + attribute \src "libresoc.v:35179.9-35179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] + end + attribute \src "libresoc.v:35215.3-35251.6" + process $proc$libresoc.v:35215$765 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35216.5-35216.29" + switch \initial + attribute \src "libresoc.v:35216.9-35216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] + end + attribute \src "libresoc.v:35252.3-35288.6" + process $proc$libresoc.v:35252$766 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35253.5-35253.29" + switch \initial + attribute \src "libresoc.v:35253.9-35253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + case + assign $1\dec31_dec_sub28_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] + end + attribute \src "libresoc.v:35289.3-35325.6" + process $proc$libresoc.v:35289$767 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:35290.5-35290.29" + switch \initial + attribute \src "libresoc.v:35290.9-35290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] + end + attribute \src "libresoc.v:35326.3-35362.6" + process $proc$libresoc.v:35326$768 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35327.5-35327.29" + switch \initial + attribute \src "libresoc.v:35327.9-35327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] + end + attribute \src "libresoc.v:35363.3-35399.6" + process $proc$libresoc.v:35363$769 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35364.5-35364.29" + switch \initial + attribute \src "libresoc.v:35364.9-35364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] + end + attribute \src "libresoc.v:35400.3-35436.6" + process $proc$libresoc.v:35400$770 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:35401.5-35401.29" + switch \initial + attribute \src "libresoc.v:35401.9-35401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] + end + attribute \src "libresoc.v:35437.3-35473.6" + process $proc$libresoc.v:35437$771 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:35438.5-35438.29" + switch \initial + attribute \src "libresoc.v:35438.9-35438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] + end + attribute \src "libresoc.v:35474.3-35510.6" + process $proc$libresoc.v:35474$772 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35475.5-35475.29" + switch \initial + attribute \src "libresoc.v:35475.9-35475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] + end + attribute \src "libresoc.v:35511.3-35547.6" + process $proc$libresoc.v:35511$773 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35512.5-35512.29" + switch \initial + attribute \src "libresoc.v:35512.9-35512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] + end + attribute \src "libresoc.v:35548.3-35584.6" + process $proc$libresoc.v:35548$774 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:35549.5-35549.29" + switch \initial + attribute \src "libresoc.v:35549.9-35549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub28_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] + end + attribute \src "libresoc.v:35585.3-35621.6" + process $proc$libresoc.v:35585$775 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35586.5-35586.29" + switch \initial + attribute \src "libresoc.v:35586.9-35586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "libresoc.v:35622.3-35658.6" + process $proc$libresoc.v:35622$776 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35623.5-35623.29" + switch \initial + attribute \src "libresoc.v:35623.9-35623.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] + end + attribute \src "libresoc.v:35659.3-35695.6" + process $proc$libresoc.v:35659$777 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35660.5-35660.29" + switch \initial + attribute \src "libresoc.v:35660.9-35660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] + end + attribute \src "libresoc.v:35696.3-35732.6" + process $proc$libresoc.v:35696$778 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:35697.5-35697.29" + switch \initial + attribute \src "libresoc.v:35697.9-35697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] + end + attribute \src "libresoc.v:35733.3-35769.6" + process $proc$libresoc.v:35733$779 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35734.5-35734.29" + switch \initial + attribute \src "libresoc.v:35734.9-35734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] + end + attribute \src "libresoc.v:35770.3-35806.6" + process $proc$libresoc.v:35770$780 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:35771.5-35771.29" + switch \initial + attribute \src "libresoc.v:35771.9-35771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:35812.1-36383.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" +attribute \generator "nMigen" +module \dec31_dec_sub4 + attribute \src "libresoc.v:36135.3-36147.6" + wire width 8 $0\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:36187.3-36199.6" + wire $0\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:36356.3-36368.6" + wire width 3 $0\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:36369.3-36381.6" + wire width 3 $0\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:36122.3-36134.6" + wire width 2 $0\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:36174.3-36186.6" + wire $0\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36291.3-36303.6" + wire width 5 $0\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:36070.3-36082.6" + wire width 12 $0\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:36304.3-36316.6" + wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36317.3-36329.6" + wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36330.3-36342.6" + wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36213.3-36225.6" + wire width 7 $0\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36148.3-36160.6" + wire $0\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36161.3-36173.6" + wire $0\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36239.3-36251.6" + wire $0\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:36083.3-36095.6" + wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:36265.3-36277.6" + wire $0\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36343.3-36355.6" + wire width 2 $0\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:36109.3-36121.6" + wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:36226.3-36238.6" + wire $0\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36278.3-36290.6" + wire $0\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36252.3-36264.6" + wire $0\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36200.3-36212.6" + wire $0\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:36096.3-36108.6" + wire width 2 $0\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:35813.7-35813.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:36135.3-36147.6" + wire width 8 $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:36187.3-36199.6" + wire $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:36356.3-36368.6" + wire width 3 $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:36369.3-36381.6" + wire width 3 $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:36122.3-36134.6" + wire width 2 $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:36174.3-36186.6" + wire $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36291.3-36303.6" + wire width 5 $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:36070.3-36082.6" + wire width 12 $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:36304.3-36316.6" + wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36317.3-36329.6" + wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36330.3-36342.6" + wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36213.3-36225.6" + wire width 7 $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36148.3-36160.6" + wire $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36161.3-36173.6" + wire $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36239.3-36251.6" + wire $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:36083.3-36095.6" + wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:36265.3-36277.6" + wire $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36343.3-36355.6" + wire width 2 $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:36109.3-36121.6" + wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:36226.3-36238.6" + wire $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36278.3-36290.6" + wire $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36252.3-36264.6" + wire $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36200.3-36212.6" + wire $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:36096.3-36108.6" + wire width 2 $1\dec31_dec_sub4_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub4_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub4_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub4_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub4_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub4_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub4_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub4_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub4_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub4_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub4_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub4_upd + attribute \src "libresoc.v:35813.7-35813.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:35813.7-35813.20" + process $proc$libresoc.v:35813$806 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:36070.3-36082.6" + process $proc$libresoc.v:36070$782 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:36071.5-36071.29" + switch \initial + attribute \src "libresoc.v:36071.9-36071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + case + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] + end + attribute \src "libresoc.v:36083.3-36095.6" + process $proc$libresoc.v:36083$783 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:36084.5-36084.29" + switch \initial + attribute \src "libresoc.v:36084.9-36084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] + end + attribute \src "libresoc.v:36096.3-36108.6" + process $proc$libresoc.v:36096$784 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:36097.5-36097.29" + switch \initial + attribute \src "libresoc.v:36097.9-36097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + end + attribute \src "libresoc.v:36109.3-36121.6" + process $proc$libresoc.v:36109$785 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:36110.5-36110.29" + switch \initial + attribute \src "libresoc.v:36110.9-36110.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] + end + attribute \src "libresoc.v:36122.3-36134.6" + process $proc$libresoc.v:36122$786 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:36123.5-36123.29" + switch \initial + attribute \src "libresoc.v:36123.9-36123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] + end + attribute \src "libresoc.v:36135.3-36147.6" + process $proc$libresoc.v:36135$787 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:36136.5-36136.29" + switch \initial + attribute \src "libresoc.v:36136.9-36136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 + case + assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] + end + attribute \src "libresoc.v:36148.3-36160.6" + process $proc$libresoc.v:36148$788 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36149.5-36149.29" + switch \initial + attribute \src "libresoc.v:36149.9-36149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] + end + attribute \src "libresoc.v:36161.3-36173.6" + process $proc$libresoc.v:36161$789 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36162.5-36162.29" + switch \initial + attribute \src "libresoc.v:36162.9-36162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] + end + attribute \src "libresoc.v:36174.3-36186.6" + process $proc$libresoc.v:36174$790 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36175.5-36175.29" + switch \initial + attribute \src "libresoc.v:36175.9-36175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] + end + attribute \src "libresoc.v:36187.3-36199.6" + process $proc$libresoc.v:36187$791 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:36188.5-36188.29" + switch \initial + attribute \src "libresoc.v:36188.9-36188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + case + assign $1\dec31_dec_sub4_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] + end + attribute \src "libresoc.v:36200.3-36212.6" + process $proc$libresoc.v:36200$792 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:36201.5-36201.29" + switch \initial + attribute \src "libresoc.v:36201.9-36201.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] + end + attribute \src "libresoc.v:36213.3-36225.6" + process $proc$libresoc.v:36213$793 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36214.5-36214.29" + switch \initial + attribute \src "libresoc.v:36214.9-36214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + case + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + end + attribute \src "libresoc.v:36226.3-36238.6" + process $proc$libresoc.v:36226$794 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36227.5-36227.29" + switch \initial + attribute \src "libresoc.v:36227.9-36227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] + end + attribute \src "libresoc.v:36239.3-36251.6" + process $proc$libresoc.v:36239$795 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:36240.5-36240.29" + switch \initial + attribute \src "libresoc.v:36240.9-36240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] + end + attribute \src "libresoc.v:36252.3-36264.6" + process $proc$libresoc.v:36252$796 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36253.5-36253.29" + switch \initial + attribute \src "libresoc.v:36253.9-36253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] + end + attribute \src "libresoc.v:36265.3-36277.6" + process $proc$libresoc.v:36265$797 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36266.5-36266.29" + switch \initial + attribute \src "libresoc.v:36266.9-36266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] + end + attribute \src "libresoc.v:36278.3-36290.6" + process $proc$libresoc.v:36278$798 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36279.5-36279.29" + switch \initial + attribute \src "libresoc.v:36279.9-36279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] + end + attribute \src "libresoc.v:36291.3-36303.6" + process $proc$libresoc.v:36291$799 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:36292.5-36292.29" + switch \initial + attribute \src "libresoc.v:36292.9-36292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub4_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + end + attribute \src "libresoc.v:36304.3-36316.6" + process $proc$libresoc.v:36304$800 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36305.5-36305.29" + switch \initial + attribute \src "libresoc.v:36305.9-36305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] + end + attribute \src "libresoc.v:36317.3-36329.6" + process $proc$libresoc.v:36317$801 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36318.5-36318.29" + switch \initial + attribute \src "libresoc.v:36318.9-36318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] + end + attribute \src "libresoc.v:36330.3-36342.6" + process $proc$libresoc.v:36330$802 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36331.5-36331.29" + switch \initial + attribute \src "libresoc.v:36331.9-36331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] + end + attribute \src "libresoc.v:36343.3-36355.6" + process $proc$libresoc.v:36343$803 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:36344.5-36344.29" + switch \initial + attribute \src "libresoc.v:36344.9-36344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] + end + attribute \src "libresoc.v:36356.3-36368.6" + process $proc$libresoc.v:36356$804 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:36357.5-36357.29" + switch \initial + attribute \src "libresoc.v:36357.9-36357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] + end + attribute \src "libresoc.v:36369.3-36381.6" + process $proc$libresoc.v:36369$805 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:36370.5-36370.29" + switch \initial + attribute \src "libresoc.v:36370.9-36370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:36387.1-37678.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" +attribute \generator "nMigen" +module \dec31_dec_sub8 + attribute \src "libresoc.v:36860.3-36902.6" + wire width 8 $0\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:37032.3-37074.6" + wire $0\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:37591.3-37633.6" + wire width 3 $0\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37634.3-37676.6" + wire width 3 $0\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:36817.3-36859.6" + wire width 2 $0\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:36989.3-37031.6" + wire $0\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:37376.3-37418.6" + wire width 5 $0\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:36645.3-36687.6" + wire width 12 $0\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:37419.3-37461.6" + wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37462.3-37504.6" + wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37505.3-37547.6" + wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:37118.3-37160.6" + wire width 7 $0\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:36903.3-36945.6" + wire $0\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:36946.3-36988.6" + wire $0\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:37204.3-37246.6" + wire $0\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:36688.3-36730.6" + wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:37290.3-37332.6" + wire $0\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37548.3-37590.6" + wire width 2 $0\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:36774.3-36816.6" + wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:37161.3-37203.6" + wire $0\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37333.3-37375.6" + wire $0\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37247.3-37289.6" + wire $0\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:37075.3-37117.6" + wire $0\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:36731.3-36773.6" + wire width 2 $0\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:36388.7-36388.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:36860.3-36902.6" + wire width 8 $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:37032.3-37074.6" + wire $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:37591.3-37633.6" + wire width 3 $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37634.3-37676.6" + wire width 3 $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:36817.3-36859.6" + wire width 2 $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:36989.3-37031.6" + wire $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:37376.3-37418.6" + wire width 5 $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:36645.3-36687.6" + wire width 12 $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:37419.3-37461.6" + wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37462.3-37504.6" + wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37505.3-37547.6" + wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:37118.3-37160.6" + wire width 7 $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:36903.3-36945.6" + wire $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:36946.3-36988.6" + wire $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:37204.3-37246.6" + wire $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:36688.3-36730.6" + wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:37290.3-37332.6" + wire $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37548.3-37590.6" + wire width 2 $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:36774.3-36816.6" + wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:37161.3-37203.6" + wire $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37333.3-37375.6" + wire $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37247.3-37289.6" + wire $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:37075.3-37117.6" + wire $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:36731.3-36773.6" + wire width 2 $1\dec31_dec_sub8_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub8_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub8_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub8_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub8_upd + attribute \src "libresoc.v:36388.7-36388.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:36388.7-36388.20" + process $proc$libresoc.v:36388$831 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:36645.3-36687.6" + process $proc$libresoc.v:36645$807 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:36646.5-36646.29" + switch \initial + attribute \src "libresoc.v:36646.9-36646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] + end + attribute \src "libresoc.v:36688.3-36730.6" + process $proc$libresoc.v:36688$808 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:36689.5-36689.29" + switch \initial + attribute \src "libresoc.v:36689.9-36689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "libresoc.v:36731.3-36773.6" + process $proc$libresoc.v:36731$809 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:36732.5-36732.29" + switch \initial + attribute \src "libresoc.v:36732.9-36732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] + end + attribute \src "libresoc.v:36774.3-36816.6" + process $proc$libresoc.v:36774$810 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:36775.5-36775.29" + switch \initial + attribute \src "libresoc.v:36775.9-36775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "libresoc.v:36817.3-36859.6" + process $proc$libresoc.v:36817$811 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:36818.5-36818.29" + switch \initial + attribute \src "libresoc.v:36818.9-36818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] + end + attribute \src "libresoc.v:36860.3-36902.6" + process $proc$libresoc.v:36860$812 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:36861.5-36861.29" + switch \initial + attribute \src "libresoc.v:36861.9-36861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 + case + assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] + end + attribute \src "libresoc.v:36903.3-36945.6" + process $proc$libresoc.v:36903$813 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:36904.5-36904.29" + switch \initial + attribute \src "libresoc.v:36904.9-36904.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] + end + attribute \src "libresoc.v:36946.3-36988.6" + process $proc$libresoc.v:36946$814 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:36947.5-36947.29" + switch \initial + attribute \src "libresoc.v:36947.9-36947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] + end + attribute \src "libresoc.v:36989.3-37031.6" + process $proc$libresoc.v:36989$815 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:36990.5-36990.29" + switch \initial + attribute \src "libresoc.v:36990.9-36990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] + end + attribute \src "libresoc.v:37032.3-37074.6" + process $proc$libresoc.v:37032$816 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:37033.5-37033.29" + switch \initial + attribute \src "libresoc.v:37033.9-37033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + case + assign $1\dec31_dec_sub8_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] + end + attribute \src "libresoc.v:37075.3-37117.6" + process $proc$libresoc.v:37075$817 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:37076.5-37076.29" + switch \initial + attribute \src "libresoc.v:37076.9-37076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] + end + attribute \src "libresoc.v:37118.3-37160.6" + process $proc$libresoc.v:37118$818 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:37119.5-37119.29" + switch \initial + attribute \src "libresoc.v:37119.9-37119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] + end + attribute \src "libresoc.v:37161.3-37203.6" + process $proc$libresoc.v:37161$819 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37162.5-37162.29" + switch \initial + attribute \src "libresoc.v:37162.9-37162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] + end + attribute \src "libresoc.v:37204.3-37246.6" + process $proc$libresoc.v:37204$820 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:37205.5-37205.29" + switch \initial + attribute \src "libresoc.v:37205.9-37205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + end + attribute \src "libresoc.v:37247.3-37289.6" + process $proc$libresoc.v:37247$821 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:37248.5-37248.29" + switch \initial + attribute \src "libresoc.v:37248.9-37248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] + end + attribute \src "libresoc.v:37290.3-37332.6" + process $proc$libresoc.v:37290$822 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37291.5-37291.29" + switch \initial + attribute \src "libresoc.v:37291.9-37291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] + end + attribute \src "libresoc.v:37333.3-37375.6" + process $proc$libresoc.v:37333$823 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37334.5-37334.29" + switch \initial + attribute \src "libresoc.v:37334.9-37334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] + end + attribute \src "libresoc.v:37376.3-37418.6" + process $proc$libresoc.v:37376$824 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:37377.5-37377.29" + switch \initial + attribute \src "libresoc.v:37377.9-37377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub8_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] + end + attribute \src "libresoc.v:37419.3-37461.6" + process $proc$libresoc.v:37419$825 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37420.5-37420.29" + switch \initial + attribute \src "libresoc.v:37420.9-37420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "libresoc.v:37462.3-37504.6" + process $proc$libresoc.v:37462$826 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37463.5-37463.29" + switch \initial + attribute \src "libresoc.v:37463.9-37463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "libresoc.v:37505.3-37547.6" + process $proc$libresoc.v:37505$827 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:37506.5-37506.29" + switch \initial + attribute \src "libresoc.v:37506.9-37506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] + end + attribute \src "libresoc.v:37548.3-37590.6" + process $proc$libresoc.v:37548$828 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:37549.5-37549.29" + switch \initial + attribute \src "libresoc.v:37549.9-37549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] + end + attribute \src "libresoc.v:37591.3-37633.6" + process $proc$libresoc.v:37591$829 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37592.5-37592.29" + switch \initial + attribute \src "libresoc.v:37592.9-37592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] + end + attribute \src "libresoc.v:37634.3-37676.6" + process $proc$libresoc.v:37634$830 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:37635.5-37635.29" + switch \initial + attribute \src "libresoc.v:37635.9-37635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:37682.1-39261.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" +attribute \generator "nMigen" +module \dec31_dec_sub9 + attribute \src "libresoc.v:38215.3-38269.6" + wire width 8 $0\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38435.3-38489.6" + wire $0\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:39150.3-39204.6" + wire width 3 $0\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39205.3-39259.6" + wire width 3 $0\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:38160.3-38214.6" + wire width 2 $0\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38380.3-38434.6" + wire $0\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38875.3-38929.6" + wire width 5 $0\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:37940.3-37994.6" + wire width 12 $0\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:38930.3-38984.6" + wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:38985.3-39039.6" + wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:39040.3-39094.6" + wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:38545.3-38599.6" + wire width 7 $0\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38270.3-38324.6" + wire $0\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38325.3-38379.6" + wire $0\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38655.3-38709.6" + wire $0\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:37995.3-38049.6" + wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:38765.3-38819.6" + wire $0\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:39095.3-39149.6" + wire width 2 $0\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:38105.3-38159.6" + wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:38600.3-38654.6" + wire $0\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38820.3-38874.6" + wire $0\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38710.3-38764.6" + wire $0\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38490.3-38544.6" + wire $0\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:38050.3-38104.6" + wire width 2 $0\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:37683.7-37683.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:38215.3-38269.6" + wire width 8 $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38435.3-38489.6" + wire $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:39150.3-39204.6" + wire width 3 $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39205.3-39259.6" + wire width 3 $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:38160.3-38214.6" + wire width 2 $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38380.3-38434.6" + wire $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38875.3-38929.6" + wire width 5 $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:37940.3-37994.6" + wire width 12 $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:38930.3-38984.6" + wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:38985.3-39039.6" + wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:39040.3-39094.6" + wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:38545.3-38599.6" + wire width 7 $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38270.3-38324.6" + wire $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38325.3-38379.6" + wire $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38655.3-38709.6" + wire $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:37995.3-38049.6" + wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:38765.3-38819.6" + wire $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:39095.3-39149.6" + wire width 2 $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:38105.3-38159.6" + wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:38600.3-38654.6" + wire $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38820.3-38874.6" + wire $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38710.3-38764.6" + wire $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38490.3-38544.6" + wire $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:38050.3-38104.6" + wire width 2 $1\dec31_dec_sub9_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub9_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub9_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub9_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub9_upd + attribute \src "libresoc.v:37683.7-37683.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:37683.7-37683.20" + process $proc$libresoc.v:37683$856 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:37940.3-37994.6" + process $proc$libresoc.v:37940$832 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:37941.5-37941.29" + switch \initial + attribute \src "libresoc.v:37941.9-37941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] + end + attribute \src "libresoc.v:37995.3-38049.6" + process $proc$libresoc.v:37995$833 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:37996.5-37996.29" + switch \initial + attribute \src "libresoc.v:37996.9-37996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] + end + attribute \src "libresoc.v:38050.3-38104.6" + process $proc$libresoc.v:38050$834 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:38051.5-38051.29" + switch \initial + attribute \src "libresoc.v:38051.9-38051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] + end + attribute \src "libresoc.v:38105.3-38159.6" + process $proc$libresoc.v:38105$835 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:38106.5-38106.29" + switch \initial + attribute \src "libresoc.v:38106.9-38106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:38160.3-38214.6" + process $proc$libresoc.v:38160$836 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38161.5-38161.29" + switch \initial + attribute \src "libresoc.v:38161.9-38161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] + end + attribute \src "libresoc.v:38215.3-38269.6" + process $proc$libresoc.v:38215$837 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38216.5-38216.29" + switch \initial + attribute \src "libresoc.v:38216.9-38216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 + case + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] + end + attribute \src "libresoc.v:38270.3-38324.6" + process $proc$libresoc.v:38270$838 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38271.5-38271.29" + switch \initial + attribute \src "libresoc.v:38271.9-38271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] + end + attribute \src "libresoc.v:38325.3-38379.6" + process $proc$libresoc.v:38325$839 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38326.5-38326.29" + switch \initial + attribute \src "libresoc.v:38326.9-38326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] + end + attribute \src "libresoc.v:38380.3-38434.6" + process $proc$libresoc.v:38380$840 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38381.5-38381.29" + switch \initial + attribute \src "libresoc.v:38381.9-38381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] + end + attribute \src "libresoc.v:38435.3-38489.6" + process $proc$libresoc.v:38435$841 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:38436.5-38436.29" + switch \initial + attribute \src "libresoc.v:38436.9-38436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + case + assign $1\dec31_dec_sub9_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] + end + attribute \src "libresoc.v:38490.3-38544.6" + process $proc$libresoc.v:38490$842 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:38491.5-38491.29" + switch \initial + attribute \src "libresoc.v:38491.9-38491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] + end + attribute \src "libresoc.v:38545.3-38599.6" + process $proc$libresoc.v:38545$843 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38546.5-38546.29" + switch \initial + attribute \src "libresoc.v:38546.9-38546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:38600.3-38654.6" + process $proc$libresoc.v:38600$844 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38601.5-38601.29" + switch \initial + attribute \src "libresoc.v:38601.9-38601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] + end + attribute \src "libresoc.v:38655.3-38709.6" + process $proc$libresoc.v:38655$845 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:38656.5-38656.29" + switch \initial + attribute \src "libresoc.v:38656.9-38656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:38710.3-38764.6" + process $proc$libresoc.v:38710$846 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38711.5-38711.29" + switch \initial + attribute \src "libresoc.v:38711.9-38711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] + end + attribute \src "libresoc.v:38765.3-38819.6" + process $proc$libresoc.v:38765$847 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:38766.5-38766.29" + switch \initial + attribute \src "libresoc.v:38766.9-38766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] + end + attribute \src "libresoc.v:38820.3-38874.6" + process $proc$libresoc.v:38820$848 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38821.5-38821.29" + switch \initial + attribute \src "libresoc.v:38821.9-38821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] + end + attribute \src "libresoc.v:38875.3-38929.6" + process $proc$libresoc.v:38875$849 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:38876.5-38876.29" + switch \initial + attribute \src "libresoc.v:38876.9-38876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub9_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] + end + attribute \src "libresoc.v:38930.3-38984.6" + process $proc$libresoc.v:38930$850 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:38931.5-38931.29" + switch \initial + attribute \src "libresoc.v:38931.9-38931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] + end + attribute \src "libresoc.v:38985.3-39039.6" + process $proc$libresoc.v:38985$851 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:38986.5-38986.29" + switch \initial + attribute \src "libresoc.v:38986.9-38986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:39040.3-39094.6" + process $proc$libresoc.v:39040$852 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:39041.5-39041.29" + switch \initial + attribute \src "libresoc.v:39041.9-39041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] + end + attribute \src "libresoc.v:39095.3-39149.6" + process $proc$libresoc.v:39095$853 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:39096.5-39096.29" + switch \initial + attribute \src "libresoc.v:39096.9-39096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] + end + attribute \src "libresoc.v:39150.3-39204.6" + process $proc$libresoc.v:39150$854 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39151.5-39151.29" + switch \initial + attribute \src "libresoc.v:39151.9-39151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:39205.3-39259.6" + process $proc$libresoc.v:39205$855 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:39206.5-39206.29" + switch \initial + attribute \src "libresoc.v:39206.9-39206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:39265.1-39908.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" +attribute \generator "nMigen" +module \dec58 + attribute \src "libresoc.v:39603.3-39618.6" + wire width 8 $0\dec58_asmcode[7:0] + attribute \src "libresoc.v:39667.3-39682.6" + wire $0\dec58_br[0:0] + attribute \src "libresoc.v:39875.3-39890.6" + wire width 3 $0\dec58_cr_in[2:0] + attribute \src "libresoc.v:39891.3-39906.6" + wire width 3 $0\dec58_cr_out[2:0] + attribute \src "libresoc.v:39587.3-39602.6" + wire width 2 $0\dec58_cry_in[1:0] + attribute \src "libresoc.v:39651.3-39666.6" + wire $0\dec58_cry_out[0:0] + attribute \src "libresoc.v:39795.3-39810.6" + wire width 5 $0\dec58_form[4:0] + attribute \src "libresoc.v:39523.3-39538.6" + wire width 12 $0\dec58_function_unit[11:0] + attribute \src "libresoc.v:39811.3-39826.6" + wire width 3 $0\dec58_in1_sel[2:0] + attribute \src "libresoc.v:39827.3-39842.6" + wire width 4 $0\dec58_in2_sel[3:0] + attribute \src "libresoc.v:39843.3-39858.6" + wire width 2 $0\dec58_in3_sel[1:0] + attribute \src "libresoc.v:39699.3-39714.6" + wire width 7 $0\dec58_internal_op[6:0] + attribute \src "libresoc.v:39619.3-39634.6" + wire $0\dec58_inv_a[0:0] + attribute \src "libresoc.v:39635.3-39650.6" + wire $0\dec58_inv_out[0:0] + attribute \src "libresoc.v:39731.3-39746.6" + wire $0\dec58_is_32b[0:0] + attribute \src "libresoc.v:39539.3-39554.6" + wire width 4 $0\dec58_ldst_len[3:0] + attribute \src "libresoc.v:39763.3-39778.6" + wire $0\dec58_lk[0:0] + attribute \src "libresoc.v:39859.3-39874.6" + wire width 2 $0\dec58_out_sel[1:0] + attribute \src "libresoc.v:39571.3-39586.6" + wire width 2 $0\dec58_rc_sel[1:0] + attribute \src "libresoc.v:39715.3-39730.6" + wire $0\dec58_rsrv[0:0] + attribute \src "libresoc.v:39779.3-39794.6" + wire $0\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:39747.3-39762.6" + wire $0\dec58_sgn[0:0] + attribute \src "libresoc.v:39683.3-39698.6" + wire $0\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:39555.3-39570.6" + wire width 2 $0\dec58_upd[1:0] + attribute \src "libresoc.v:39266.7-39266.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:39603.3-39618.6" + wire width 8 $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:39667.3-39682.6" + wire $1\dec58_br[0:0] + attribute \src "libresoc.v:39875.3-39890.6" + wire width 3 $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:39891.3-39906.6" + wire width 3 $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:39587.3-39602.6" + wire width 2 $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:39651.3-39666.6" + wire $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:39795.3-39810.6" + wire width 5 $1\dec58_form[4:0] + attribute \src "libresoc.v:39523.3-39538.6" + wire width 12 $1\dec58_function_unit[11:0] + attribute \src "libresoc.v:39811.3-39826.6" + wire width 3 $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:39827.3-39842.6" + wire width 4 $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:39843.3-39858.6" + wire width 2 $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:39699.3-39714.6" + wire width 7 $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:39619.3-39634.6" + wire $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:39635.3-39650.6" + wire $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:39731.3-39746.6" + wire $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:39539.3-39554.6" + wire width 4 $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:39763.3-39778.6" + wire $1\dec58_lk[0:0] + attribute \src "libresoc.v:39859.3-39874.6" + wire width 2 $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:39571.3-39586.6" + wire width 2 $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:39715.3-39730.6" + wire $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:39779.3-39794.6" + wire $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:39747.3-39762.6" + wire $1\dec58_sgn[0:0] + attribute \src "libresoc.v:39683.3-39698.6" + wire $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:39555.3-39570.6" + wire width 2 $1\dec58_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec58_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec58_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec58_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec58_upd + attribute \src "libresoc.v:39266.7-39266.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 2 \opcode_switch + attribute \src "libresoc.v:39266.7-39266.20" + process $proc$libresoc.v:39266$881 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:39523.3-39538.6" + process $proc$libresoc.v:39523$857 + assign { } { } + assign { } { } + assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] + attribute \src "libresoc.v:39524.5-39524.29" + switch \initial + attribute \src "libresoc.v:39524.9-39524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + case + assign $1\dec58_function_unit[11:0] 12'000000000000 + end + sync always + update \dec58_function_unit $0\dec58_function_unit[11:0] + end + attribute \src "libresoc.v:39539.3-39554.6" + process $proc$libresoc.v:39539$858 + assign { } { } + assign { } { } + assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:39540.5-39540.29" + switch \initial + attribute \src "libresoc.v:39540.9-39540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'0100 + case + assign $1\dec58_ldst_len[3:0] 4'0000 + end + sync always + update \dec58_ldst_len $0\dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:39555.3-39570.6" + process $proc$libresoc.v:39555$859 + assign { } { } + assign { } { } + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "libresoc.v:39556.5-39556.29" + switch \initial + attribute \src "libresoc.v:39556.9-39556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + case + assign $1\dec58_upd[1:0] 2'00 + end + sync always + update \dec58_upd $0\dec58_upd[1:0] + end + attribute \src "libresoc.v:39571.3-39586.6" + process $proc$libresoc.v:39571$860 + assign { } { } + assign { } { } + assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:39572.5-39572.29" + switch \initial + attribute \src "libresoc.v:39572.9-39572.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + case + assign $1\dec58_rc_sel[1:0] 2'00 + end + sync always + update \dec58_rc_sel $0\dec58_rc_sel[1:0] + end + attribute \src "libresoc.v:39587.3-39602.6" + process $proc$libresoc.v:39587$861 + assign { } { } + assign { } { } + assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:39588.5-39588.29" + switch \initial + attribute \src "libresoc.v:39588.9-39588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + case + assign $1\dec58_cry_in[1:0] 2'00 + end + sync always + update \dec58_cry_in $0\dec58_cry_in[1:0] + end + attribute \src "libresoc.v:39603.3-39618.6" + process $proc$libresoc.v:39603$862 + assign { } { } + assign { } { } + assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:39604.5-39604.29" + switch \initial + attribute \src "libresoc.v:39604.9-39604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01100010 + case + assign $1\dec58_asmcode[7:0] 8'00000000 + end + sync always + update \dec58_asmcode $0\dec58_asmcode[7:0] + end + attribute \src "libresoc.v:39619.3-39634.6" + process $proc$libresoc.v:39619$863 + assign { } { } + assign { } { } + assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:39620.5-39620.29" + switch \initial + attribute \src "libresoc.v:39620.9-39620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + case + assign $1\dec58_inv_a[0:0] 1'0 + end + sync always + update \dec58_inv_a $0\dec58_inv_a[0:0] + end + attribute \src "libresoc.v:39635.3-39650.6" + process $proc$libresoc.v:39635$864 + assign { } { } + assign { } { } + assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:39636.5-39636.29" + switch \initial + attribute \src "libresoc.v:39636.9-39636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + case + assign $1\dec58_inv_out[0:0] 1'0 + end + sync always + update \dec58_inv_out $0\dec58_inv_out[0:0] + end + attribute \src "libresoc.v:39651.3-39666.6" + process $proc$libresoc.v:39651$865 + assign { } { } + assign { } { } + assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:39652.5-39652.29" + switch \initial + attribute \src "libresoc.v:39652.9-39652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + case + assign $1\dec58_cry_out[0:0] 1'0 + end + sync always + update \dec58_cry_out $0\dec58_cry_out[0:0] + end + attribute \src "libresoc.v:39667.3-39682.6" + process $proc$libresoc.v:39667$866 + assign { } { } + assign { } { } + assign $0\dec58_br[0:0] $1\dec58_br[0:0] + attribute \src "libresoc.v:39668.5-39668.29" + switch \initial + attribute \src "libresoc.v:39668.9-39668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + case + assign $1\dec58_br[0:0] 1'0 + end + sync always + update \dec58_br $0\dec58_br[0:0] + end + attribute \src "libresoc.v:39683.3-39698.6" + process $proc$libresoc.v:39683$867 + assign { } { } + assign { } { } + assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:39684.5-39684.29" + switch \initial + attribute \src "libresoc.v:39684.9-39684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'1 + case + assign $1\dec58_sgn_ext[0:0] 1'0 + end + sync always + update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] + end + attribute \src "libresoc.v:39699.3-39714.6" + process $proc$libresoc.v:39699$868 + assign { } { } + assign { } { } + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:39700.5-39700.29" + switch \initial + attribute \src "libresoc.v:39700.9-39700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + case + assign $1\dec58_internal_op[6:0] 7'0000000 + end + sync always + update \dec58_internal_op $0\dec58_internal_op[6:0] + end + attribute \src "libresoc.v:39715.3-39730.6" + process $proc$libresoc.v:39715$869 + assign { } { } + assign { } { } + assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:39716.5-39716.29" + switch \initial + attribute \src "libresoc.v:39716.9-39716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + case + assign $1\dec58_rsrv[0:0] 1'0 + end + sync always + update \dec58_rsrv $0\dec58_rsrv[0:0] + end + attribute \src "libresoc.v:39731.3-39746.6" + process $proc$libresoc.v:39731$870 + assign { } { } + assign { } { } + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:39732.5-39732.29" + switch \initial + attribute \src "libresoc.v:39732.9-39732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + case + assign $1\dec58_is_32b[0:0] 1'0 + end + sync always + update \dec58_is_32b $0\dec58_is_32b[0:0] + end + attribute \src "libresoc.v:39747.3-39762.6" + process $proc$libresoc.v:39747$871 + assign { } { } + assign { } { } + assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] + attribute \src "libresoc.v:39748.5-39748.29" + switch \initial + attribute \src "libresoc.v:39748.9-39748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + case + assign $1\dec58_sgn[0:0] 1'0 + end + sync always + update \dec58_sgn $0\dec58_sgn[0:0] + end + attribute \src "libresoc.v:39763.3-39778.6" + process $proc$libresoc.v:39763$872 + assign { } { } + assign { } { } + assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] + attribute \src "libresoc.v:39764.5-39764.29" + switch \initial + attribute \src "libresoc.v:39764.9-39764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + case + assign $1\dec58_lk[0:0] 1'0 + end + sync always + update \dec58_lk $0\dec58_lk[0:0] + end + attribute \src "libresoc.v:39779.3-39794.6" + process $proc$libresoc.v:39779$873 + assign { } { } + assign { } { } + assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:39780.5-39780.29" + switch \initial + attribute \src "libresoc.v:39780.9-39780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + case + assign $1\dec58_sgl_pipe[0:0] 1'0 + end + sync always + update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] + end + attribute \src "libresoc.v:39795.3-39810.6" + process $proc$libresoc.v:39795$874 + assign { } { } + assign { } { } + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "libresoc.v:39796.5-39796.29" + switch \initial + attribute \src "libresoc.v:39796.9-39796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + case + assign $1\dec58_form[4:0] 5'00000 + end + sync always + update \dec58_form $0\dec58_form[4:0] + end + attribute \src "libresoc.v:39811.3-39826.6" + process $proc$libresoc.v:39811$875 + assign { } { } + assign { } { } + assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:39812.5-39812.29" + switch \initial + attribute \src "libresoc.v:39812.9-39812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + case + assign $1\dec58_in1_sel[2:0] 3'000 + end + sync always + update \dec58_in1_sel $0\dec58_in1_sel[2:0] + end + attribute \src "libresoc.v:39827.3-39842.6" + process $proc$libresoc.v:39827$876 + assign { } { } + assign { } { } + assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:39828.5-39828.29" + switch \initial + attribute \src "libresoc.v:39828.9-39828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + case + assign $1\dec58_in2_sel[3:0] 4'0000 + end + sync always + update \dec58_in2_sel $0\dec58_in2_sel[3:0] + end + attribute \src "libresoc.v:39843.3-39858.6" + process $proc$libresoc.v:39843$877 + assign { } { } + assign { } { } + assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:39844.5-39844.29" + switch \initial + attribute \src "libresoc.v:39844.9-39844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + case + assign $1\dec58_in3_sel[1:0] 2'00 + end + sync always + update \dec58_in3_sel $0\dec58_in3_sel[1:0] + end + attribute \src "libresoc.v:39859.3-39874.6" + process $proc$libresoc.v:39859$878 + assign { } { } + assign { } { } + assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:39860.5-39860.29" + switch \initial + attribute \src "libresoc.v:39860.9-39860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + case + assign $1\dec58_out_sel[1:0] 2'00 + end + sync always + update \dec58_out_sel $0\dec58_out_sel[1:0] + end + attribute \src "libresoc.v:39875.3-39890.6" + process $proc$libresoc.v:39875$879 + assign { } { } + assign { } { } + assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:39876.5-39876.29" + switch \initial + attribute \src "libresoc.v:39876.9-39876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + case + assign $1\dec58_cr_in[2:0] 3'000 + end + sync always + update \dec58_cr_in $0\dec58_cr_in[2:0] + end + attribute \src "libresoc.v:39891.3-39906.6" + process $proc$libresoc.v:39891$880 + assign { } { } + assign { } { } + assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:39892.5-39892.29" + switch \initial + attribute \src "libresoc.v:39892.9-39892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + case + assign $1\dec58_cr_out[2:0] 3'000 + end + sync always + update \dec58_cr_out $0\dec58_cr_out[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:39912.1-40483.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" +attribute \generator "nMigen" +module \dec62 + attribute \src "libresoc.v:40235.3-40247.6" + wire width 8 $0\dec62_asmcode[7:0] + attribute \src "libresoc.v:40287.3-40299.6" + wire $0\dec62_br[0:0] + attribute \src "libresoc.v:40456.3-40468.6" + wire width 3 $0\dec62_cr_in[2:0] + attribute \src "libresoc.v:40469.3-40481.6" + wire width 3 $0\dec62_cr_out[2:0] + attribute \src "libresoc.v:40222.3-40234.6" + wire width 2 $0\dec62_cry_in[1:0] + attribute \src "libresoc.v:40274.3-40286.6" + wire $0\dec62_cry_out[0:0] + attribute \src "libresoc.v:40391.3-40403.6" + wire width 5 $0\dec62_form[4:0] + attribute \src "libresoc.v:40170.3-40182.6" + wire width 12 $0\dec62_function_unit[11:0] + attribute \src "libresoc.v:40404.3-40416.6" + wire width 3 $0\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40417.3-40429.6" + wire width 4 $0\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40430.3-40442.6" + wire width 2 $0\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40313.3-40325.6" + wire width 7 $0\dec62_internal_op[6:0] + attribute \src "libresoc.v:40248.3-40260.6" + wire $0\dec62_inv_a[0:0] + attribute \src "libresoc.v:40261.3-40273.6" + wire $0\dec62_inv_out[0:0] + attribute \src "libresoc.v:40339.3-40351.6" + wire $0\dec62_is_32b[0:0] + attribute \src "libresoc.v:40183.3-40195.6" + wire width 4 $0\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40365.3-40377.6" + wire $0\dec62_lk[0:0] + attribute \src "libresoc.v:40443.3-40455.6" + wire width 2 $0\dec62_out_sel[1:0] + attribute \src "libresoc.v:40209.3-40221.6" + wire width 2 $0\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40326.3-40338.6" + wire $0\dec62_rsrv[0:0] + attribute \src "libresoc.v:40378.3-40390.6" + wire $0\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40352.3-40364.6" + wire $0\dec62_sgn[0:0] + attribute \src "libresoc.v:40300.3-40312.6" + wire $0\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40196.3-40208.6" + wire width 2 $0\dec62_upd[1:0] + attribute \src "libresoc.v:39913.7-39913.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:40235.3-40247.6" + wire width 8 $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:40287.3-40299.6" + wire $1\dec62_br[0:0] + attribute \src "libresoc.v:40456.3-40468.6" + wire width 3 $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:40469.3-40481.6" + wire width 3 $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:40222.3-40234.6" + wire width 2 $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:40274.3-40286.6" + wire $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:40391.3-40403.6" + wire width 5 $1\dec62_form[4:0] + attribute \src "libresoc.v:40170.3-40182.6" + wire width 12 $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:40404.3-40416.6" + wire width 3 $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40417.3-40429.6" + wire width 4 $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40430.3-40442.6" + wire width 2 $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40313.3-40325.6" + wire width 7 $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:40248.3-40260.6" + wire $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:40261.3-40273.6" + wire $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:40339.3-40351.6" + wire $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:40183.3-40195.6" + wire width 4 $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40365.3-40377.6" + wire $1\dec62_lk[0:0] + attribute \src "libresoc.v:40443.3-40455.6" + wire width 2 $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:40209.3-40221.6" + wire width 2 $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40326.3-40338.6" + wire $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:40378.3-40390.6" + wire $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40352.3-40364.6" + wire $1\dec62_sgn[0:0] + attribute \src "libresoc.v:40300.3-40312.6" + wire $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40196.3-40208.6" + wire width 2 $1\dec62_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec62_upd + attribute \src "libresoc.v:39913.7-39913.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 2 \opcode_switch + attribute \src "libresoc.v:39913.7-39913.20" + process $proc$libresoc.v:39913$906 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:40170.3-40182.6" + process $proc$libresoc.v:40170$882 + assign { } { } + assign { } { } + assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:40171.5-40171.29" + switch \initial + attribute \src "libresoc.v:40171.9-40171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + case + assign $1\dec62_function_unit[11:0] 12'000000000000 + end + sync always + update \dec62_function_unit $0\dec62_function_unit[11:0] + end + attribute \src "libresoc.v:40183.3-40195.6" + process $proc$libresoc.v:40183$883 + assign { } { } + assign { } { } + assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40184.5-40184.29" + switch \initial + attribute \src "libresoc.v:40184.9-40184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + case + assign $1\dec62_ldst_len[3:0] 4'0000 + end + sync always + update \dec62_ldst_len $0\dec62_ldst_len[3:0] + end + attribute \src "libresoc.v:40196.3-40208.6" + process $proc$libresoc.v:40196$884 + assign { } { } + assign { } { } + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "libresoc.v:40197.5-40197.29" + switch \initial + attribute \src "libresoc.v:40197.9-40197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_upd[1:0] 2'01 + case + assign $1\dec62_upd[1:0] 2'00 + end + sync always + update \dec62_upd $0\dec62_upd[1:0] + end + attribute \src "libresoc.v:40209.3-40221.6" + process $proc$libresoc.v:40209$885 + assign { } { } + assign { } { } + assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40210.5-40210.29" + switch \initial + attribute \src "libresoc.v:40210.9-40210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + case + assign $1\dec62_rc_sel[1:0] 2'00 + end + sync always + update \dec62_rc_sel $0\dec62_rc_sel[1:0] + end + attribute \src "libresoc.v:40222.3-40234.6" + process $proc$libresoc.v:40222$886 + assign { } { } + assign { } { } + assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:40223.5-40223.29" + switch \initial + attribute \src "libresoc.v:40223.9-40223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + case + assign $1\dec62_cry_in[1:0] 2'00 + end + sync always + update \dec62_cry_in $0\dec62_cry_in[1:0] + end + attribute \src "libresoc.v:40235.3-40247.6" + process $proc$libresoc.v:40235$887 + assign { } { } + assign { } { } + assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:40236.5-40236.29" + switch \initial + attribute \src "libresoc.v:40236.9-40236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101111 + case + assign $1\dec62_asmcode[7:0] 8'00000000 + end + sync always + update \dec62_asmcode $0\dec62_asmcode[7:0] + end + attribute \src "libresoc.v:40248.3-40260.6" + process $proc$libresoc.v:40248$888 + assign { } { } + assign { } { } + assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:40249.5-40249.29" + switch \initial + attribute \src "libresoc.v:40249.9-40249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + case + assign $1\dec62_inv_a[0:0] 1'0 + end + sync always + update \dec62_inv_a $0\dec62_inv_a[0:0] + end + attribute \src "libresoc.v:40261.3-40273.6" + process $proc$libresoc.v:40261$889 + assign { } { } + assign { } { } + assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:40262.5-40262.29" + switch \initial + attribute \src "libresoc.v:40262.9-40262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + case + assign $1\dec62_inv_out[0:0] 1'0 + end + sync always + update \dec62_inv_out $0\dec62_inv_out[0:0] + end + attribute \src "libresoc.v:40274.3-40286.6" + process $proc$libresoc.v:40274$890 + assign { } { } + assign { } { } + assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:40275.5-40275.29" + switch \initial + attribute \src "libresoc.v:40275.9-40275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + case + assign $1\dec62_cry_out[0:0] 1'0 + end + sync always + update \dec62_cry_out $0\dec62_cry_out[0:0] + end + attribute \src "libresoc.v:40287.3-40299.6" + process $proc$libresoc.v:40287$891 + assign { } { } + assign { } { } + assign $0\dec62_br[0:0] $1\dec62_br[0:0] + attribute \src "libresoc.v:40288.5-40288.29" + switch \initial + attribute \src "libresoc.v:40288.9-40288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + case + assign $1\dec62_br[0:0] 1'0 + end + sync always + update \dec62_br $0\dec62_br[0:0] + end + attribute \src "libresoc.v:40300.3-40312.6" + process $proc$libresoc.v:40300$892 + assign { } { } + assign { } { } + assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40301.5-40301.29" + switch \initial + attribute \src "libresoc.v:40301.9-40301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + case + assign $1\dec62_sgn_ext[0:0] 1'0 + end + sync always + update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:40313.3-40325.6" + process $proc$libresoc.v:40313$893 + assign { } { } + assign { } { } + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:40314.5-40314.29" + switch \initial + attribute \src "libresoc.v:40314.9-40314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + case + assign $1\dec62_internal_op[6:0] 7'0000000 + end + sync always + update \dec62_internal_op $0\dec62_internal_op[6:0] + end + attribute \src "libresoc.v:40326.3-40338.6" + process $proc$libresoc.v:40326$894 + assign { } { } + assign { } { } + assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:40327.5-40327.29" + switch \initial + attribute \src "libresoc.v:40327.9-40327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + case + assign $1\dec62_rsrv[0:0] 1'0 + end + sync always + update \dec62_rsrv $0\dec62_rsrv[0:0] + end + attribute \src "libresoc.v:40339.3-40351.6" + process $proc$libresoc.v:40339$895 + assign { } { } + assign { } { } + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:40340.5-40340.29" + switch \initial + attribute \src "libresoc.v:40340.9-40340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + case + assign $1\dec62_is_32b[0:0] 1'0 + end + sync always + update \dec62_is_32b $0\dec62_is_32b[0:0] + end + attribute \src "libresoc.v:40352.3-40364.6" + process $proc$libresoc.v:40352$896 + assign { } { } + assign { } { } + assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] + attribute \src "libresoc.v:40353.5-40353.29" + switch \initial + attribute \src "libresoc.v:40353.9-40353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + case + assign $1\dec62_sgn[0:0] 1'0 + end + sync always + update \dec62_sgn $0\dec62_sgn[0:0] + end + attribute \src "libresoc.v:40365.3-40377.6" + process $proc$libresoc.v:40365$897 + assign { } { } + assign { } { } + assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] + attribute \src "libresoc.v:40366.5-40366.29" + switch \initial + attribute \src "libresoc.v:40366.9-40366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + case + assign $1\dec62_lk[0:0] 1'0 + end + sync always + update \dec62_lk $0\dec62_lk[0:0] + end + attribute \src "libresoc.v:40378.3-40390.6" + process $proc$libresoc.v:40378$898 + assign { } { } + assign { } { } + assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40379.5-40379.29" + switch \initial + attribute \src "libresoc.v:40379.9-40379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + case + assign $1\dec62_sgl_pipe[0:0] 1'0 + end + sync always + update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] + end + attribute \src "libresoc.v:40391.3-40403.6" + process $proc$libresoc.v:40391$899 + assign { } { } + assign { } { } + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "libresoc.v:40392.5-40392.29" + switch \initial + attribute \src "libresoc.v:40392.9-40392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + case + assign $1\dec62_form[4:0] 5'00000 + end + sync always + update \dec62_form $0\dec62_form[4:0] + end + attribute \src "libresoc.v:40404.3-40416.6" + process $proc$libresoc.v:40404$900 + assign { } { } + assign { } { } + assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40405.5-40405.29" + switch \initial + attribute \src "libresoc.v:40405.9-40405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + case + assign $1\dec62_in1_sel[2:0] 3'000 + end + sync always + update \dec62_in1_sel $0\dec62_in1_sel[2:0] + end + attribute \src "libresoc.v:40417.3-40429.6" + process $proc$libresoc.v:40417$901 + assign { } { } + assign { } { } + assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40418.5-40418.29" + switch \initial + attribute \src "libresoc.v:40418.9-40418.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + case + assign $1\dec62_in2_sel[3:0] 4'0000 + end + sync always + update \dec62_in2_sel $0\dec62_in2_sel[3:0] + end + attribute \src "libresoc.v:40430.3-40442.6" + process $proc$libresoc.v:40430$902 + assign { } { } + assign { } { } + assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40431.5-40431.29" + switch \initial + attribute \src "libresoc.v:40431.9-40431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + case + assign $1\dec62_in3_sel[1:0] 2'00 + end + sync always + update \dec62_in3_sel $0\dec62_in3_sel[1:0] + end + attribute \src "libresoc.v:40443.3-40455.6" + process $proc$libresoc.v:40443$903 + assign { } { } + assign { } { } + assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:40444.5-40444.29" + switch \initial + attribute \src "libresoc.v:40444.9-40444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + case + assign $1\dec62_out_sel[1:0] 2'00 + end + sync always + update \dec62_out_sel $0\dec62_out_sel[1:0] + end + attribute \src "libresoc.v:40456.3-40468.6" + process $proc$libresoc.v:40456$904 + assign { } { } + assign { } { } + assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:40457.5-40457.29" + switch \initial + attribute \src "libresoc.v:40457.9-40457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + case + assign $1\dec62_cr_in[2:0] 3'000 + end + sync always + update \dec62_cr_in $0\dec62_cr_in[2:0] + end + attribute \src "libresoc.v:40469.3-40481.6" + process $proc$libresoc.v:40469$905 + assign { } { } + assign { } { } + assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:40470.5-40470.29" + switch \initial + attribute \src "libresoc.v:40470.9-40470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + case + assign $1\dec62_cr_out[2:0] 3'000 + end + sync always + update \dec62_cr_out $0\dec62_cr_out[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:40487.1-40992.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" +attribute \generator "nMigen" +module \dec_a + attribute \src "libresoc.v:40921.3-40956.6" + wire width 3 $0\fast_a[2:0] + attribute \src "libresoc.v:40921.3-40956.6" + wire $0\fast_a_ok[0:0] + attribute \src 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\B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:41117$929_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $eq $eq$libresoc.v:41119$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:41119$931_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + cell $not $not$libresoc.v:41118$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:41118$930_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + cell $not $not$libresoc.v:41120$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:41120$932_Y + end + attribute \src "libresoc.v:40997.7-40997.20" + process $proc$libresoc.v:40997$937 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:41121.3-41135.6" + process $proc$libresoc.v:41121$933 + assign { } { } + assign { } { } + assign $0\reg_b[4:0] $1\reg_b[4:0] + attribute \src "libresoc.v:41122.5-41122.29" + switch \initial + attribute \src "libresoc.v:41122.9-41122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\reg_b[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $1\reg_b[4:0] \RS + case + assign $1\reg_b[4:0] 5'00000 + end + sync always + update \reg_b $0\reg_b[4:0] + end + attribute \src "libresoc.v:41136.3-41150.6" + process $proc$libresoc.v:41136$934 + assign { } { } + assign { } { } + assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] + attribute \src "libresoc.v:41137.5-41137.29" + switch \initial + attribute \src "libresoc.v:41137.9-41137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + case + assign $1\reg_b_ok[0:0] 1'0 + end + sync always + update \reg_b_ok $0\reg_b_ok[0:0] + end + attribute \src "libresoc.v:41151.3-41168.6" + process $proc$libresoc.v:41151$935 + assign { } { } + assign { } { } + assign $0\fast_b[2:0] $1\fast_b[2:0] + attribute \src "libresoc.v:41152.5-41152.29" + switch \initial + attribute \src "libresoc.v:41152.9-41152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast_b[2:0] $2\fast_b[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + switch { \XL_XO [5] \$3 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b[2:0] 3'010 + case + assign $2\fast_b[2:0] 3'000 + end + case + assign $1\fast_b[2:0] 3'000 + end + sync always + update \fast_b $0\fast_b[2:0] + end + attribute \src "libresoc.v:41169.3-41186.6" + process $proc$libresoc.v:41169$936 + assign { } { } + assign { } { } + assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] + attribute \src "libresoc.v:41170.5-41170.29" + switch \initial + attribute \src "libresoc.v:41170.9-41170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + 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$0\reg_c[4:0] + attribute \src "libresoc.v:41224.3-41238.6" + wire $0\reg_c_ok[0:0] + attribute \src "libresoc.v:41209.3-41223.6" + wire width 5 $1\reg_c[4:0] + attribute \src "libresoc.v:41224.3-41238.6" + wire $1\reg_c_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \RS + attribute \src "libresoc.v:41192.7-41192.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 1 \reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:41192.7-41192.20" + process $proc$libresoc.v:41192$940 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:41209.3-41223.6" + process $proc$libresoc.v:41209$938 + assign { } { } + assign { } { } + assign $0\reg_c[4:0] $1\reg_c[4:0] + attribute \src "libresoc.v:41210.5-41210.29" + switch \initial + attribute \src "libresoc.v:41210.9-41210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c[4:0] \RS + case + assign $1\reg_c[4:0] 5'00000 + end + sync always + update \reg_c $0\reg_c[4:0] + end + attribute \src "libresoc.v:41224.3-41238.6" + process $proc$libresoc.v:41224$939 + assign { } { } + assign { } { } + assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] + attribute \src "libresoc.v:41225.5-41225.29" + switch \initial + attribute \src "libresoc.v:41225.9-41225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + case + assign $1\reg_c_ok[0:0] 1'0 + end + sync always + update \reg_c_ok $0\reg_c_ok[0:0] + end +end +attribute \src "libresoc.v:41243.1-41548.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in + attribute \src "libresoc.v:41442.3-41468.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:41469.3-41479.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:41420.3-41430.6" + wire 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 12 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 11 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 16 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 15 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 13 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 14 \FXM + attribute \src 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\enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:41386$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:41386$942_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:41388$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:41388$944_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:41385$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:41385$941_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:41387$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:41387$943_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:41389.9-41392.4" + cell \ppick \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:41244.7-41244.20" + process $proc$libresoc.v:41244$955 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:41393.3-41419.6" + process $proc$libresoc.v:41393$945 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41394.5-41394.29" + switch \initial + attribute \src "libresoc.v:41394.9-41394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:41420.3-41430.6" + process $proc$libresoc.v:41420$946 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:41421.5-41421.29" + switch \initial + attribute \src "libresoc.v:41421.9-41421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:41431.3-41441.6" + process $proc$libresoc.v:41431$947 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41432.5-41432.29" + switch \initial + attribute \src "libresoc.v:41432.9-41432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:41442.3-41468.6" + process $proc$libresoc.v:41442$948 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41443.5-41443.29" + switch \initial + attribute \src "libresoc.v:41443.9-41443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:41469.3-41479.6" + process $proc$libresoc.v:41469$949 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:41470.5-41470.29" + switch \initial + attribute \src "libresoc.v:41470.9-41470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:41480.3-41490.6" + process $proc$libresoc.v:41480$950 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:41481.5-41481.29" + switch \initial + attribute \src "libresoc.v:41481.9-41481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:41491.3-41501.6" + process $proc$libresoc.v:41491$951 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:41492.5-41492.29" + switch \initial + attribute \src "libresoc.v:41492.9-41492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:41502.3-41512.6" + process $proc$libresoc.v:41502$952 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:41503.5-41503.29" + switch \initial + attribute \src "libresoc.v:41503.9-41503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:41513.3-41528.6" + process $proc$libresoc.v:41513$953 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:41514.5-41514.29" + switch \initial + attribute \src "libresoc.v:41514.9-41514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:41529.3-41547.6" + process $proc$libresoc.v:41529$954 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:41530.5-41530.29" + switch \initial + attribute \src "libresoc.v:41530.9-41530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:41385$941_Y + connect \$3 $and$libresoc.v:41386$942_Y + connect \$5 $eq$libresoc.v:41387$943_Y + connect \$7 $and$libresoc.v:41388$944_Y +end +attribute \src "libresoc.v:41552.1-41795.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out + attribute \src "libresoc.v:41709.3-41727.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:41679.3-41697.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41760.3-41794.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:41698.3-41708.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41553.7-41553.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:41728.3-41738.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:41739.3-41759.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:41709.3-41727.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41679.3-41697.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41760.3-41794.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:41698.3-41708.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41728.3-41738.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:41739.3-41759.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:41760.3-41794.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:41739.3-41759.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:41760.3-41794.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:41739.3-41759.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:41760.3-41794.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:41672.17-41672.117" + wire $eq$libresoc.v:41672$956_Y + attribute \src "libresoc.v:41673.17-41673.117" + wire $eq$libresoc.v:41673$957_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 8 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 10 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 6 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 4 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \cr_fxm_ok + attribute \src "libresoc.v:41553.7-41553.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 11 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src 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\enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:42152$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42152$965_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:42153$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42153$966_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:42154$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42154$967_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + cell $not $not$libresoc.v:42155$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$libresoc.v:42155$968_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42156.14-42162.4" + cell \sprmap$2 \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + end + attribute \src "libresoc.v:41800.7-41800.20" + process $proc$libresoc.v:41800$975 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42163.3-42177.6" + process $proc$libresoc.v:42163$969 + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + attribute \src "libresoc.v:42164.5-42164.29" + switch \initial + attribute \src "libresoc.v:42164.9-42164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o[4:0] \RT + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o[4:0] \RA + case + assign $1\reg_o[4:0] 5'00000 + end + sync always + update \reg_o $0\reg_o[4:0] + end + attribute \src "libresoc.v:42178.3-42192.6" + process $proc$libresoc.v:42178$970 + assign { } { } + assign { } { } + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42179.5-42179.29" + switch \initial + attribute \src "libresoc.v:42179.9-42179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o_ok $0\reg_o_ok[0:0] + end + attribute \src "libresoc.v:42193.3-42203.6" + process $proc$libresoc.v:42193$971 + assign { } { } + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:42194.5-42194.29" + switch \initial + attribute \src "libresoc.v:42194.9-42194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end + sync always + update \spr $0\spr[9:0] + end + attribute \src "libresoc.v:42204.3-42219.6" + process $proc$libresoc.v:42204$972 + assign { } { } + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:42205.5-42205.29" + switch \initial + attribute \src "libresoc.v:42205.9-42205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sprmap_spr_i[9:0] \spr + case + assign $2\sprmap_spr_i[9:0] 10'0000000000 + end + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] + end + attribute \src "libresoc.v:42220.3-42236.6" + process $proc$libresoc.v:42220$973 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:42221.5-42221.29" + switch \initial + attribute \src "libresoc.v:42221.9-42221.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\spr_o[9:0] $2\spr_o[9:0] + assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $2\spr_o[9:0] 10'0000000000 + assign $2\spr_o_ok[0:0] 1'0 + end + case + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o $0\spr_o[9:0] + update \spr_o_ok $0\spr_o_ok[0:0] + end + attribute \src "libresoc.v:42237.3-42275.6" + process $proc$libresoc.v:42237$974 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $3\fast_o[2:0] + assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] + attribute \src "libresoc.v:42238.5-42238.29" + switch \initial + attribute \src "libresoc.v:42238.9-42238.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $2\fast_o[2:0] 3'000 + assign $2\fast_o_ok[0:0] 1'0 + end + case + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0001000 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] $4\fast_o[2:0] + assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $4\fast_o[2:0] 3'000 + assign $4\fast_o_ok[0:0] 1'1 + case + assign $4\fast_o[2:0] $1\fast_o[2:0] + assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] 3'011 + assign $3\fast_o_ok[0:0] 1'1 + case + assign $3\fast_o[2:0] $1\fast_o[2:0] + assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + sync always + update \fast_o $0\fast_o[2:0] + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$libresoc.v:42152$965_Y + connect \$3 $eq$libresoc.v:42153$966_Y + connect \$5 $eq$libresoc.v:42154$967_Y + connect \$7 $not$libresoc.v:42155$968_Y +end +attribute \src "libresoc.v:42280.1-42441.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" +attribute \generator "nMigen" +module \dec_o2 + attribute \src "libresoc.v:42401.3-42420.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:42421.3-42440.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:42281.7-42281.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42387.3-42400.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:42387.3-42400.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:42401.3-42420.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:42421.3-42440.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:42387.3-42400.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:42387.3-42400.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42401.3-42420.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:42421.3-42440.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:42385.17-42385.108" + wire $eq$libresoc.v:42385$976_Y + attribute \src "libresoc.v:42386.17-42386.100" + wire width 6 $extend$libresoc.v:42386$977_Y + attribute \src "libresoc.v:42386.17-42386.100" + wire width 6 $pos$libresoc.v:42386$978_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 4 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \fast_o_ok + attribute \src "libresoc.v:42281.7-42281.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 8 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" + wire input 1 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \reg_o_ok + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 input 6 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + cell $eq $eq$libresoc.v:42385$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:42385$976_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:42386$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A \RA + connect \Y $extend$libresoc.v:42386$977_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:42386$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $extend$libresoc.v:42386$977_Y + connect \Y $pos$libresoc.v:42386$978_Y + end + attribute \src "libresoc.v:42281.7-42281.20" + process $proc$libresoc.v:42281$982 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42387.3-42400.6" + process $proc$libresoc.v:42387$979 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42388.5-42388.29" + switch \initial + attribute \src "libresoc.v:42388.9-42388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\reg_o[4:0] \$3 [4:0] + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o[4:0] 5'00000 + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o $0\reg_o[4:0] + update \reg_o_ok $0\reg_o_ok[0:0] + end + attribute \src "libresoc.v:42401.3-42420.6" + process $proc$libresoc.v:42401$980 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:42402.5-42402.29" + switch \initial + attribute \src "libresoc.v:42402.9-42402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o[2:0] 3'001 + case + assign $2\fast_o[2:0] 3'000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o[2:0] 3'100 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:42421.3-42440.6" + process $proc$libresoc.v:42421$981 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:42422.5-42422.29" + switch \initial + attribute \src "libresoc.v:42422.9-42422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o_ok[0:0] 1'1 + case + assign $2\fast_o_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$libresoc.v:42385$976_Y + connect \$3 $pos$libresoc.v:42386$978_Y +end +attribute \src "libresoc.v:42445.1-42579.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" +attribute \generator "nMigen" +module \dec_oe + attribute \src "libresoc.v:42446.7-42446.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42537.3-42557.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:42558.3-42578.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:42537.3-42557.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:42558.3-42578.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:42537.3-42557.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:42558.3-42578.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 4 \OE + attribute \src "libresoc.v:42446.7-42446.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:42446.7-42446.20" + process $proc$libresoc.v:42446$985 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42537.3-42557.6" + process $proc$libresoc.v:42537$983 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:42538.5-42538.29" + switch \initial + attribute \src "libresoc.v:42538.9-42538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:42558.3-42578.6" + process $proc$libresoc.v:42558$984 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:42559.5-42559.29" + switch \initial + attribute \src "libresoc.v:42559.9-42559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:42583.1-42637.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" +attribute \generator "nMigen" +module \dec_rc + attribute \src "libresoc.v:42584.7-42584.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42599.3-42617.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:42618.3-42636.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:42599.3-42617.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:42618.3-42636.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 3 \Rc + attribute \src "libresoc.v:42584.7-42584.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:42584.7-42584.20" + process $proc$libresoc.v:42584$988 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42599.3-42617.6" + process $proc$libresoc.v:42599$986 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:42600.5-42600.29" + switch \initial + attribute \src "libresoc.v:42600.9-42600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:42618.3-42636.6" + process $proc$libresoc.v:42618$987 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:42619.5-42619.29" + switch \initial + attribute \src "libresoc.v:42619.9-42619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:42641.1-43020.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.imem" +attribute \generator "nMigen" +module \imem + attribute \src "libresoc.v:42972.3-42981.6" + wire $0\a_busy_o[0:0] + attribute \src "libresoc.v:42952.3-42971.6" + wire width 45 $0\f_badaddr_o$next[44:0]$1057 + attribute \src "libresoc.v:42783.3-42784.39" + wire width 45 $0\f_badaddr_o[44:0] + attribute \src "libresoc.v:42982.3-42999.6" + wire $0\f_busy_o[0:0] + attribute \src "libresoc.v:42929.3-42951.6" + wire $0\f_fetch_err_o$next[0:0]$1052 + attribute \src "libresoc.v:42785.3-42786.43" + wire $0\f_fetch_err_o[0:0] + attribute \src "libresoc.v:43000.3-43017.6" + wire width 64 $0\f_instr_o[63:0] + attribute \src "libresoc.v:42906.3-42928.6" + wire width 45 $0\ibus__adr$next[44:0]$1047 + attribute \src "libresoc.v:42787.3-42788.35" + wire width 45 $0\ibus__adr[44:0] + attribute \src "libresoc.v:42797.3-42824.6" + wire $0\ibus__cyc$next[0:0]$1023 + attribute \src "libresoc.v:42795.3-42796.35" + wire $0\ibus__cyc[0:0] + attribute \src "libresoc.v:42853.3-42880.6" + wire width 8 $0\ibus__sel$next[7:0]$1035 + attribute \src "libresoc.v:42791.3-42792.35" + wire width 8 $0\ibus__sel[7:0] + attribute \src "libresoc.v:42825.3-42852.6" + wire $0\ibus__stb$next[0:0]$1029 + attribute \src "libresoc.v:42793.3-42794.35" + wire $0\ibus__stb[0:0] + attribute \src "libresoc.v:42881.3-42905.6" + wire width 64 $0\ibus_rdata$next[63:0]$1041 + attribute \src "libresoc.v:42789.3-42790.37" + wire width 64 $0\ibus_rdata[63:0] + attribute \src "libresoc.v:42642.7-42642.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42972.3-42981.6" + wire $1\a_busy_o[0:0] + attribute \src "libresoc.v:42952.3-42971.6" + wire width 45 $1\f_badaddr_o$next[44:0]$1058 + attribute \src "libresoc.v:42706.14-42706.44" + wire width 45 $1\f_badaddr_o[44:0] + attribute \src "libresoc.v:42982.3-42999.6" + wire $1\f_busy_o[0:0] + attribute \src "libresoc.v:42929.3-42951.6" + wire $1\f_fetch_err_o$next[0:0]$1053 + attribute \src "libresoc.v:42713.7-42713.27" + wire $1\f_fetch_err_o[0:0] + attribute \src "libresoc.v:43000.3-43017.6" + wire width 64 $1\f_instr_o[63:0] + attribute \src "libresoc.v:42906.3-42928.6" + wire width 45 $1\ibus__adr$next[44:0]$1048 + attribute \src "libresoc.v:42727.14-42727.42" + wire width 45 $1\ibus__adr[44:0] + attribute \src "libresoc.v:42797.3-42824.6" + wire $1\ibus__cyc$next[0:0]$1024 + attribute \src "libresoc.v:42732.7-42732.23" + wire $1\ibus__cyc[0:0] + attribute \src "libresoc.v:42853.3-42880.6" + wire width 8 $1\ibus__sel$next[7:0]$1036 + attribute \src "libresoc.v:42741.13-42741.30" + wire width 8 $1\ibus__sel[7:0] + attribute \src "libresoc.v:42825.3-42852.6" + wire $1\ibus__stb$next[0:0]$1030 + attribute \src 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\$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" + wire \a_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 input 2 \a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" + wire \a_stall_i + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire input 4 \f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 9 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 14 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 \ibus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 8 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 13 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 10 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 12 \ibus__sel + attribute \src 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\B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$11 + connect \Y $and$libresoc.v:42759$991_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:42765$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$21 + connect \Y $and$libresoc.v:42765$997_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:42770$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$31 + connect \Y $and$libresoc.v:42770$1002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:42773$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$1 + connect \Y $and$libresoc.v:42773$1005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:42776$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$41 + connect \Y $and$libresoc.v:42776$1008_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + cell $and $and$libresoc.v:42777$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:42777$1009_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + cell $and $and$libresoc.v:42779$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:42779$1011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:42758$990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42758$990_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:42761$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42761$993_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:42762$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42762$994_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:42764$996 + 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$not$libresoc.v:42782$1014_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42757$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $or$libresoc.v:42757$989_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42760$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42760$992_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42763$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $or$libresoc.v:42763$995_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42766$998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42766$998_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42768$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \$27 + connect \Y $or$libresoc.v:42768$1000_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42771$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42771$1003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42774$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$35 + connect \B \$37 + connect \Y $or$libresoc.v:42774$1006_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42781$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42781$1013_Y + end + attribute \src "libresoc.v:42642.7-42642.20" + process $proc$libresoc.v:42642$1064 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42706.14-42706.44" + process $proc$libresoc.v:42706$1065 + assign { } { } + assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \f_badaddr_o $1\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:42713.7-42713.27" + process $proc$libresoc.v:42713$1066 + assign { } { } + assign $1\f_fetch_err_o[0:0] 1'0 + sync always + sync init + update \f_fetch_err_o $1\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:42727.14-42727.42" + process $proc$libresoc.v:42727$1067 + assign { } { } + assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus__adr $1\ibus__adr[44:0] + end + attribute \src "libresoc.v:42732.7-42732.23" + process $proc$libresoc.v:42732$1068 + assign { } { } + assign $1\ibus__cyc[0:0] 1'0 + sync always + sync init + update \ibus__cyc $1\ibus__cyc[0:0] + end + attribute \src "libresoc.v:42741.13-42741.30" + process $proc$libresoc.v:42741$1069 + assign { } { } + assign $1\ibus__sel[7:0] 8'00000000 + sync always + sync init + update \ibus__sel $1\ibus__sel[7:0] + end + attribute \src "libresoc.v:42746.7-42746.23" + process $proc$libresoc.v:42746$1070 + assign { } { } + assign $1\ibus__stb[0:0] 1'0 + sync always + sync init + update \ibus__stb $1\ibus__stb[0:0] + end + attribute \src "libresoc.v:42750.14-42750.47" + process $proc$libresoc.v:42750$1071 + assign { } { } + assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus_rdata $1\ibus_rdata[63:0] + end + attribute \src "libresoc.v:42783.3-42784.39" + process $proc$libresoc.v:42783$1015 + assign { } { } + assign $0\f_badaddr_o[44:0] \f_badaddr_o$next + sync posedge \clk + update \f_badaddr_o $0\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:42785.3-42786.43" + process $proc$libresoc.v:42785$1016 + assign { } { } + assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next + sync posedge \clk + update \f_fetch_err_o $0\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:42787.3-42788.35" + process $proc$libresoc.v:42787$1017 + assign { } { } + assign $0\ibus__adr[44:0] \ibus__adr$next + sync posedge \clk + update \ibus__adr $0\ibus__adr[44:0] + end + attribute \src "libresoc.v:42789.3-42790.37" + process $proc$libresoc.v:42789$1018 + assign { } { } + assign $0\ibus_rdata[63:0] \ibus_rdata$next + sync posedge \clk + update \ibus_rdata $0\ibus_rdata[63:0] + end + attribute \src "libresoc.v:42791.3-42792.35" + process $proc$libresoc.v:42791$1019 + assign { } { } + assign $0\ibus__sel[7:0] \ibus__sel$next + sync posedge \clk + update \ibus__sel $0\ibus__sel[7:0] + end + attribute \src "libresoc.v:42793.3-42794.35" + process $proc$libresoc.v:42793$1020 + assign { } { } + assign $0\ibus__stb[0:0] \ibus__stb$next + sync posedge \clk + update \ibus__stb $0\ibus__stb[0:0] + end + attribute \src "libresoc.v:42795.3-42796.35" + process $proc$libresoc.v:42795$1021 + assign { } { } + assign $0\ibus__cyc[0:0] \ibus__cyc$next + sync posedge \clk + update \ibus__cyc $0\ibus__cyc[0:0] + end + attribute \src "libresoc.v:42797.3-42824.6" + process $proc$libresoc.v:42797$1022 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__cyc$next[0:0]$1023 $4\ibus__cyc$next[0:0]$1027 + attribute \src "libresoc.v:42798.5-42798.29" + switch \initial + attribute \src "libresoc.v:42798.9-42798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__cyc$next[0:0]$1024 $2\ibus__cyc$next[0:0]$1025 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$3 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__cyc$next[0:0]$1025 $3\ibus__cyc$next[0:0]$1026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__cyc$next[0:0]$1026 1'0 + case + assign $3\ibus__cyc$next[0:0]$1026 \ibus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__cyc$next[0:0]$1025 1'1 + case + assign $2\ibus__cyc$next[0:0]$1025 \ibus__cyc + end + case + assign $1\ibus__cyc$next[0:0]$1024 \ibus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__cyc$next[0:0]$1027 1'0 + case + assign $4\ibus__cyc$next[0:0]$1027 $1\ibus__cyc$next[0:0]$1024 + end + sync always + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$1023 + end + attribute \src "libresoc.v:42825.3-42852.6" + process $proc$libresoc.v:42825$1028 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__stb$next[0:0]$1029 $4\ibus__stb$next[0:0]$1033 + attribute \src "libresoc.v:42826.5-42826.29" + switch \initial + attribute \src "libresoc.v:42826.9-42826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__stb$next[0:0]$1030 $2\ibus__stb$next[0:0]$1031 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$13 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__stb$next[0:0]$1031 $3\ibus__stb$next[0:0]$1032 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__stb$next[0:0]$1032 1'0 + case + assign $3\ibus__stb$next[0:0]$1032 \ibus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__stb$next[0:0]$1031 1'1 + case + assign $2\ibus__stb$next[0:0]$1031 \ibus__stb + end + case + assign $1\ibus__stb$next[0:0]$1030 \ibus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__stb$next[0:0]$1033 1'0 + case + assign $4\ibus__stb$next[0:0]$1033 $1\ibus__stb$next[0:0]$1030 + end + sync always + update \ibus__stb$next $0\ibus__stb$next[0:0]$1029 + end + attribute \src "libresoc.v:42853.3-42880.6" + process $proc$libresoc.v:42853$1034 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__sel$next[7:0]$1035 $4\ibus__sel$next[7:0]$1039 + attribute \src "libresoc.v:42854.5-42854.29" + switch \initial + attribute \src "libresoc.v:42854.9-42854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__sel$next[7:0]$1036 $2\ibus__sel$next[7:0]$1037 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$23 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__sel$next[7:0]$1037 $3\ibus__sel$next[7:0]$1038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__sel$next[7:0]$1038 8'00000000 + case + assign $3\ibus__sel$next[7:0]$1038 \ibus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__sel$next[7:0]$1037 8'11111111 + case + assign $2\ibus__sel$next[7:0]$1037 \ibus__sel + end + case + assign $1\ibus__sel$next[7:0]$1036 \ibus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__sel$next[7:0]$1039 8'00000000 + case + assign $4\ibus__sel$next[7:0]$1039 $1\ibus__sel$next[7:0]$1036 + end + sync always + update \ibus__sel$next $0\ibus__sel$next[7:0]$1035 + end + attribute \src "libresoc.v:42881.3-42905.6" + process $proc$libresoc.v:42881$1040 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus_rdata$next[63:0]$1041 $4\ibus_rdata$next[63:0]$1045 + attribute \src "libresoc.v:42882.5-42882.29" + switch \initial + attribute \src "libresoc.v:42882.9-42882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus_rdata$next[63:0]$1042 $2\ibus_rdata$next[63:0]$1043 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$33 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus_rdata$next[63:0]$1043 $3\ibus_rdata$next[63:0]$1044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus_rdata$next[63:0]$1044 \ibus__dat_r + case + assign $3\ibus_rdata$next[63:0]$1044 \ibus_rdata + end + case + assign $2\ibus_rdata$next[63:0]$1043 \ibus_rdata + end + case + assign $1\ibus_rdata$next[63:0]$1042 \ibus_rdata + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus_rdata$next[63:0]$1045 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\ibus_rdata$next[63:0]$1045 $1\ibus_rdata$next[63:0]$1042 + end + sync always + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$1041 + end + attribute \src "libresoc.v:42906.3-42928.6" + process $proc$libresoc.v:42906$1046 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__adr$next[44:0]$1047 $3\ibus__adr$next[44:0]$1050 + attribute \src "libresoc.v:42907.5-42907.29" + switch \initial + attribute \src "libresoc.v:42907.9-42907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__adr$next[44:0]$1048 $2\ibus__adr$next[44:0]$1049 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$43 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\ibus__adr$next[44:0]$1049 \ibus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__adr$next[44:0]$1049 \a_pc_i [47:3] + case + assign $2\ibus__adr$next[44:0]$1049 \ibus__adr + end + case + assign $1\ibus__adr$next[44:0]$1048 \ibus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__adr$next[44:0]$1050 45'000000000000000000000000000000000000000000000 + case + assign $3\ibus__adr$next[44:0]$1050 $1\ibus__adr$next[44:0]$1048 + end + sync always + update \ibus__adr$next $0\ibus__adr$next[44:0]$1047 + end + attribute \src "libresoc.v:42929.3-42951.6" + process $proc$libresoc.v:42929$1051 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_fetch_err_o$next[0:0]$1052 $3\f_fetch_err_o$next[0:0]$1055 + attribute \src "libresoc.v:42930.5-42930.29" + switch \initial + attribute \src "libresoc.v:42930.9-42930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$1053 $2\f_fetch_err_o$next[0:0]$1054 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$47 \$45 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$1054 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$1054 1'0 + case + assign $2\f_fetch_err_o$next[0:0]$1054 \f_fetch_err_o + end + case + assign $1\f_fetch_err_o$next[0:0]$1053 \f_fetch_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\f_fetch_err_o$next[0:0]$1055 1'0 + case + assign $3\f_fetch_err_o$next[0:0]$1055 $1\f_fetch_err_o$next[0:0]$1053 + end + sync always + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$1052 + end + attribute \src "libresoc.v:42952.3-42971.6" + process $proc$libresoc.v:42952$1056 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_badaddr_o$next[44:0]$1057 $3\f_badaddr_o$next[44:0]$1060 + attribute \src "libresoc.v:42953.5-42953.29" + switch \initial + attribute \src "libresoc.v:42953.9-42953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_badaddr_o$next[44:0]$1058 $2\f_badaddr_o$next[44:0]$1059 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$51 \$49 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_badaddr_o$next[44:0]$1059 \ibus__adr + case + assign $2\f_badaddr_o$next[44:0]$1059 \f_badaddr_o + end + case + assign $1\f_badaddr_o$next[44:0]$1058 \f_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\f_badaddr_o$next[44:0]$1060 45'000000000000000000000000000000000000000000000 + case + assign $3\f_badaddr_o$next[44:0]$1060 $1\f_badaddr_o$next[44:0]$1058 + end + sync always + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$1057 + end + attribute \src "libresoc.v:42972.3-42981.6" + process $proc$libresoc.v:42972$1061 + assign { } { } + assign { } { } + assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] + attribute \src "libresoc.v:42973.5-42973.29" + switch \initial + attribute \src "libresoc.v:42973.9-42973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a_busy_o[0:0] \ibus__cyc + case + assign $1\a_busy_o[0:0] 1'0 + end + sync always + update \a_busy_o $0\a_busy_o[0:0] + end + attribute \src "libresoc.v:42982.3-42999.6" + process $proc$libresoc.v:42982$1062 + assign { } { } + assign { } { } + assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] + attribute \src "libresoc.v:42983.5-42983.29" + switch \initial + attribute \src "libresoc.v:42983.9-42983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_busy_o[0:0] $2\f_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_busy_o[0:0] \ibus__cyc + end + case + assign $1\f_busy_o[0:0] 1'0 + end + sync always + update \f_busy_o $0\f_busy_o[0:0] + end + attribute \src "libresoc.v:43000.3-43017.6" + process $proc$libresoc.v:43000$1063 + assign { } { } + assign { } { } + assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] + attribute \src "libresoc.v:43001.5-43001.29" + switch \initial + attribute \src "libresoc.v:43001.9-43001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_instr_o[63:0] $2\f_instr_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_instr_o[63:0] \ibus_rdata + end + case + assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \f_instr_o $0\f_instr_o[63:0] + end + connect \$9 $or$libresoc.v:42757$989_Y + connect \$11 $not$libresoc.v:42758$990_Y + connect \$13 $and$libresoc.v:42759$991_Y + connect \$15 $or$libresoc.v:42760$992_Y + connect \$17 $not$libresoc.v:42761$993_Y + connect \$1 $not$libresoc.v:42762$994_Y + connect \$19 $or$libresoc.v:42763$995_Y + connect \$21 $not$libresoc.v:42764$996_Y + connect \$23 $and$libresoc.v:42765$997_Y + connect \$25 $or$libresoc.v:42766$998_Y + connect \$27 $not$libresoc.v:42767$999_Y + connect \$29 $or$libresoc.v:42768$1000_Y + connect \$31 $not$libresoc.v:42769$1001_Y + connect \$33 $and$libresoc.v:42770$1002_Y + connect \$35 $or$libresoc.v:42771$1003_Y + connect \$37 $not$libresoc.v:42772$1004_Y + connect \$3 $and$libresoc.v:42773$1005_Y + connect \$39 $or$libresoc.v:42774$1006_Y + connect \$41 $not$libresoc.v:42775$1007_Y + connect \$43 $and$libresoc.v:42776$1008_Y + connect \$45 $and$libresoc.v:42777$1009_Y + connect \$47 $not$libresoc.v:42778$1010_Y + connect \$49 $and$libresoc.v:42779$1011_Y + connect \$51 $not$libresoc.v:42780$1012_Y + connect \$5 $or$libresoc.v:42781$1013_Y + connect \$7 $not$libresoc.v:42782$1014_Y + connect \a_stall_i 1'0 + connect \f_stall_i 1'0 +end +attribute \src "libresoc.v:43024.1-45737.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag" +attribute \generator "nMigen" +module \jtag + attribute \src "libresoc.v:45169.3-45195.6" + wire $0\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:44817.3-44832.6" + wire $0\TAP_tdo[0:0] + attribute \src "libresoc.v:45330.3-45362.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$1482 + attribute \src "libresoc.v:44720.3-44721.41" + wire width 4 $0\dmi0__addr_i[3:0] + attribute \src "libresoc.v:45416.3-45442.6" + wire width 64 $0\dmi0__din$next[63:0]$1495 + attribute \src "libresoc.v:44716.3-44717.35" + wire width 64 $0\dmi0__din[63:0] + attribute \src "libresoc.v:45019.3-45035.6" + wire $0\dmi0_addrsr__oe$next[0:0]$1419 + attribute \src "libresoc.v:44748.3-44749.47" + wire $0\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:45036.3-45056.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$1423 + attribute \src "libresoc.v:44746.3-44747.47" + wire width 8 $0\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:45001.3-45009.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$1413 + attribute \src "libresoc.v:44752.3-44753.63" + wire $0\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:45010.3-45018.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$1416 + attribute \src "libresoc.v:44750.3-44751.73" + wire $0\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:45443.3-45463.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$1500 + attribute \src "libresoc.v:44714.3-44715.45" + wire width 64 $0\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:45075.3-45091.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$1434 + attribute \src "libresoc.v:44740.3-44741.47" + wire width 2 $0\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:45092.3-45112.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$1438 + attribute \src "libresoc.v:44738.3-44739.47" + wire width 64 $0\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:45057.3-45065.6" + wire $0\dmi0_datasr_update_core$next[0:0]$1428 + attribute \src "libresoc.v:44744.3-44745.63" + wire $0\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:45066.3-45074.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$1431 + attribute \src "libresoc.v:44742.3-44743.73" + wire $0\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:45363.3-45415.6" + wire width 3 $0\fsm_state$503$next[2:0]$1488 + attribute \src "libresoc.v:44718.3-44719.45" + wire width 3 $0\fsm_state$503[2:0]$1334 + attribute \src "libresoc.v:43670.13-43670.35" + wire width 3 $0\fsm_state$503[2:0]$1534 + attribute \src "libresoc.v:45229.3-45281.6" + wire width 3 $0\fsm_state$next[2:0]$1465 + attribute \src "libresoc.v:44726.3-44727.35" + wire width 3 $0\fsm_state[2:0] + attribute \src "libresoc.v:43025.7-43025.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:45511.3-45531.6" + wire width 154 $0\io_bd$next[153:0]$1517 + attribute \src "libresoc.v:44778.3-44779.27" + wire width 154 $0\io_bd[153:0] + attribute \src "libresoc.v:45493.3-45510.6" + wire width 154 $0\io_sr$next[153:0]$1513 + attribute \src "libresoc.v:44780.3-44781.27" + wire width 154 $0\io_sr[153:0] + attribute \src "libresoc.v:45196.3-45228.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$1459 + attribute \src "libresoc.v:44728.3-44729.41" + wire width 29 $0\jtag_wb__adr[28:0] + attribute \src "libresoc.v:45282.3-45308.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$1472 + attribute \src "libresoc.v:44724.3-44725.45" + wire width 64 $0\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:44907.3-44923.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$1389 + attribute \src "libresoc.v:44764.3-44765.53" + wire $0\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:44924.3-44944.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$1393 + attribute \src "libresoc.v:44762.3-44763.53" + wire width 29 $0\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:44889.3-44897.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$1383 + attribute \src "libresoc.v:44768.3-44769.69" + wire $0\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:44898.3-44906.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386 + attribute \src "libresoc.v:44766.3-44767.79" + wire $0\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:45309.3-45329.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$1477 + attribute \src "libresoc.v:44722.3-44723.51" + wire width 64 $0\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:44963.3-44979.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$1404 + attribute \src "libresoc.v:44756.3-44757.53" + wire width 2 $0\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:44980.3-45000.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$1408 + attribute \src "libresoc.v:44754.3-44755.53" + wire width 64 $0\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:44945.3-44953.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$1398 + attribute \src "libresoc.v:44760.3-44761.69" + wire $0\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:44954.3-44962.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401 + attribute \src "libresoc.v:44758.3-44759.79" + wire $0\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44851.3-44867.6" + wire $0\sr0__oe$next[0:0]$1374 + attribute \src "libresoc.v:44772.3-44773.31" + wire $0\sr0__oe[0:0] + attribute \src "libresoc.v:44868.3-44888.6" + wire width 3 $0\sr0_reg$next[2:0]$1378 + attribute \src "libresoc.v:44770.3-44771.31" + wire width 3 $0\sr0_reg[2:0] + attribute \src "libresoc.v:44833.3-44841.6" + wire $0\sr0_update_core$next[0:0]$1368 + attribute \src "libresoc.v:44776.3-44777.47" + wire $0\sr0_update_core[0:0] + attribute \src "libresoc.v:44842.3-44850.6" + wire $0\sr0_update_core_prev$next[0:0]$1371 + attribute \src "libresoc.v:44774.3-44775.57" + wire $0\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:45483.3-45492.6" + wire width 2 $0\sr5__i[1:0] + attribute \src "libresoc.v:45131.3-45147.6" + wire $0\sr5__oe$next[0:0]$1449 + attribute \src "libresoc.v:44732.3-44733.31" + wire $0\sr5__oe[0:0] + attribute \src "libresoc.v:45148.3-45168.6" + wire width 2 $0\sr5_reg$next[1:0]$1453 + attribute \src "libresoc.v:44730.3-44731.31" + wire width 2 $0\sr5_reg[1:0] + attribute \src "libresoc.v:45113.3-45121.6" + wire $0\sr5_update_core$next[0:0]$1443 + attribute \src "libresoc.v:44736.3-44737.47" + wire $0\sr5_update_core[0:0] + attribute \src "libresoc.v:45122.3-45130.6" + wire $0\sr5_update_core_prev$next[0:0]$1446 + attribute \src "libresoc.v:44734.3-44735.57" + wire $0\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:45464.3-45482.6" + wire $0\wb_dcache_en$next[0:0]$1505 + attribute \src "libresoc.v:44712.3-44713.41" + wire $0\wb_dcache_en[0:0] + attribute \src "libresoc.v:45464.3-45482.6" + wire $0\wb_icache_en$next[0:0]$1506 + attribute \src "libresoc.v:44710.3-44711.41" + wire $0\wb_icache_en[0:0] + attribute \src "libresoc.v:45169.3-45195.6" + wire $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:44817.3-44832.6" + wire $1\TAP_tdo[0:0] + attribute \src "libresoc.v:45330.3-45362.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$1483 + attribute \src "libresoc.v:43583.13-43583.32" + wire width 4 $1\dmi0__addr_i[3:0] + attribute \src "libresoc.v:45416.3-45442.6" + wire width 64 $1\dmi0__din$next[63:0]$1496 + attribute \src "libresoc.v:43588.14-43588.46" + wire width 64 $1\dmi0__din[63:0] + attribute \src "libresoc.v:45019.3-45035.6" + wire $1\dmi0_addrsr__oe$next[0:0]$1420 + attribute \src "libresoc.v:43602.7-43602.29" + wire $1\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:45036.3-45056.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$1424 + attribute \src "libresoc.v:43610.13-43610.36" + wire width 8 $1\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:45001.3-45009.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$1414 + attribute \src "libresoc.v:43618.7-43618.37" + wire $1\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:45010.3-45018.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 + attribute \src "libresoc.v:43622.7-43622.42" + wire $1\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:45443.3-45463.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$1501 + attribute \src "libresoc.v:43626.14-43626.51" + wire width 64 $1\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:45075.3-45091.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$1435 + attribute \src "libresoc.v:43632.13-43632.35" + wire width 2 $1\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:45092.3-45112.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$1439 + attribute \src "libresoc.v:43640.14-43640.52" + wire width 64 $1\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:45057.3-45065.6" + wire $1\dmi0_datasr_update_core$next[0:0]$1429 + attribute \src "libresoc.v:43648.7-43648.37" + wire $1\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:45066.3-45074.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$1432 + attribute \src "libresoc.v:43652.7-43652.42" + wire $1\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:45363.3-45415.6" + wire width 3 $1\fsm_state$503$next[2:0]$1489 + attribute \src "libresoc.v:45229.3-45281.6" + wire width 3 $1\fsm_state$next[2:0]$1466 + attribute \src "libresoc.v:43668.13-43668.29" + wire width 3 $1\fsm_state[2:0] + attribute \src "libresoc.v:45511.3-45531.6" + wire width 154 $1\io_bd$next[153:0]$1518 + attribute \src "libresoc.v:43868.15-43868.67" + wire width 154 $1\io_bd[153:0] + attribute \src "libresoc.v:45493.3-45510.6" + wire width 154 $1\io_sr$next[153:0]$1514 + attribute \src "libresoc.v:43880.15-43880.67" + wire width 154 $1\io_sr[153:0] + attribute \src "libresoc.v:45196.3-45228.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$1460 + attribute \src "libresoc.v:43889.14-43889.41" + wire width 29 $1\jtag_wb__adr[28:0] + attribute \src "libresoc.v:45282.3-45308.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$1473 + attribute \src "libresoc.v:43898.14-43898.51" + wire width 64 $1\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:44907.3-44923.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$1390 + attribute \src "libresoc.v:43912.7-43912.32" + wire $1\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:44924.3-44944.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$1394 + attribute \src "libresoc.v:43920.14-43920.47" + wire width 29 $1\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:44889.3-44897.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$1384 + attribute \src "libresoc.v:43928.7-43928.40" + wire $1\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:44898.3-44906.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 + attribute \src "libresoc.v:43932.7-43932.45" + wire $1\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:45309.3-45329.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$1478 + attribute \src "libresoc.v:43936.14-43936.54" + wire width 64 $1\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:44963.3-44979.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$1405 + attribute \src "libresoc.v:43942.13-43942.38" + wire width 2 $1\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:44980.3-45000.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$1409 + attribute \src "libresoc.v:43950.14-43950.55" + wire width 64 $1\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:44945.3-44953.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$1399 + attribute \src "libresoc.v:43958.7-43958.40" + wire $1\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:44954.3-44962.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 + attribute \src "libresoc.v:43962.7-43962.45" + wire $1\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44851.3-44867.6" + wire $1\sr0__oe$next[0:0]$1375 + attribute \src "libresoc.v:44392.7-44392.21" + wire $1\sr0__oe[0:0] + attribute \src "libresoc.v:44868.3-44888.6" + wire width 3 $1\sr0_reg$next[2:0]$1379 + attribute \src "libresoc.v:44400.13-44400.27" + wire width 3 $1\sr0_reg[2:0] + attribute \src "libresoc.v:44833.3-44841.6" + wire $1\sr0_update_core$next[0:0]$1369 + attribute \src "libresoc.v:44408.7-44408.29" + wire $1\sr0_update_core[0:0] + attribute \src "libresoc.v:44842.3-44850.6" + wire $1\sr0_update_core_prev$next[0:0]$1372 + attribute \src "libresoc.v:44412.7-44412.34" + wire $1\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:45483.3-45492.6" + wire width 2 $1\sr5__i[1:0] + attribute \src "libresoc.v:45131.3-45147.6" + wire $1\sr5__oe$next[0:0]$1450 + attribute \src "libresoc.v:44422.7-44422.21" + wire $1\sr5__oe[0:0] + attribute \src "libresoc.v:45148.3-45168.6" + wire width 2 $1\sr5_reg$next[1:0]$1454 + attribute \src "libresoc.v:44430.13-44430.27" + wire width 2 $1\sr5_reg[1:0] + attribute \src "libresoc.v:45113.3-45121.6" + wire $1\sr5_update_core$next[0:0]$1444 + attribute \src "libresoc.v:44438.7-44438.29" + wire $1\sr5_update_core[0:0] + attribute \src "libresoc.v:45122.3-45130.6" + wire $1\sr5_update_core_prev$next[0:0]$1447 + attribute \src "libresoc.v:44442.7-44442.34" + wire $1\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:45464.3-45482.6" + wire $1\wb_dcache_en$next[0:0]$1507 + attribute \src "libresoc.v:44446.7-44446.26" + wire $1\wb_dcache_en[0:0] + attribute \src "libresoc.v:45464.3-45482.6" + wire $1\wb_icache_en$next[0:0]$1508 + attribute \src "libresoc.v:44451.7-44451.26" + wire $1\wb_icache_en[0:0] + attribute \src "libresoc.v:45330.3-45362.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$1484 + attribute \src "libresoc.v:45416.3-45442.6" + wire width 64 $2\dmi0__din$next[63:0]$1497 + attribute \src "libresoc.v:45019.3-45035.6" + wire $2\dmi0_addrsr__oe$next[0:0]$1421 + attribute \src "libresoc.v:45036.3-45056.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$1425 + attribute \src "libresoc.v:45443.3-45463.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$1502 + attribute \src "libresoc.v:45075.3-45091.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$1436 + attribute \src "libresoc.v:45092.3-45112.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$1440 + attribute \src "libresoc.v:45363.3-45415.6" + wire width 3 $2\fsm_state$503$next[2:0]$1490 + attribute \src "libresoc.v:45229.3-45281.6" + wire width 3 $2\fsm_state$next[2:0]$1467 + attribute \src "libresoc.v:45511.3-45531.6" + wire width 154 $2\io_bd$next[153:0]$1519 + attribute \src "libresoc.v:45493.3-45510.6" + wire width 154 $2\io_sr$next[153:0]$1515 + attribute \src "libresoc.v:45196.3-45228.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$1461 + attribute \src "libresoc.v:45282.3-45308.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$1474 + attribute \src "libresoc.v:44907.3-44923.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$1391 + attribute \src "libresoc.v:44924.3-44944.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$1395 + attribute \src "libresoc.v:45309.3-45329.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$1479 + attribute \src "libresoc.v:44963.3-44979.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$1406 + attribute \src "libresoc.v:44980.3-45000.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$1410 + attribute \src "libresoc.v:44851.3-44867.6" + wire $2\sr0__oe$next[0:0]$1376 + attribute \src "libresoc.v:44868.3-44888.6" + wire width 3 $2\sr0_reg$next[2:0]$1380 + attribute \src "libresoc.v:45131.3-45147.6" + wire $2\sr5__oe$next[0:0]$1451 + attribute \src "libresoc.v:45148.3-45168.6" + wire width 2 $2\sr5_reg$next[1:0]$1455 + attribute \src "libresoc.v:45464.3-45482.6" + wire $2\wb_dcache_en$next[0:0]$1509 + attribute \src "libresoc.v:45464.3-45482.6" + wire $2\wb_icache_en$next[0:0]$1510 + attribute \src "libresoc.v:45330.3-45362.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$1485 + attribute \src "libresoc.v:45416.3-45442.6" + wire width 64 $3\dmi0__din$next[63:0]$1498 + attribute \src "libresoc.v:45036.3-45056.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$1426 + attribute \src "libresoc.v:45443.3-45463.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$1503 + attribute \src "libresoc.v:45092.3-45112.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$1441 + attribute \src "libresoc.v:45363.3-45415.6" + wire width 3 $3\fsm_state$503$next[2:0]$1491 + attribute \src "libresoc.v:45229.3-45281.6" + wire width 3 $3\fsm_state$next[2:0]$1468 + attribute \src "libresoc.v:45196.3-45228.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$1462 + attribute \src "libresoc.v:45282.3-45308.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$1475 + attribute \src "libresoc.v:44924.3-44944.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$1396 + attribute \src "libresoc.v:45309.3-45329.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$1480 + attribute \src "libresoc.v:44980.3-45000.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$1411 + attribute \src "libresoc.v:44868.3-44888.6" + wire width 3 $3\sr0_reg$next[2:0]$1381 + attribute \src "libresoc.v:45148.3-45168.6" + wire width 2 $3\sr5_reg$next[1:0]$1456 + attribute \src "libresoc.v:45330.3-45362.6" + wire width 4 $4\dmi0__addr_i$next[3:0]$1486 + attribute \src "libresoc.v:45363.3-45415.6" + wire width 3 $4\fsm_state$503$next[2:0]$1492 + attribute \src "libresoc.v:45229.3-45281.6" + wire width 3 $4\fsm_state$next[2:0]$1469 + attribute \src "libresoc.v:45196.3-45228.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$1463 + attribute \src "libresoc.v:45363.3-45415.6" + wire width 3 $5\fsm_state$503$next[2:0]$1493 + attribute \src "libresoc.v:45229.3-45281.6" + wire width 3 $5\fsm_state$next[2:0]$1470 + attribute \src "libresoc.v:44674.19-44674.112" + wire width 30 $add$libresoc.v:44674$1292_Y + attribute \src "libresoc.v:44676.19-44676.112" + wire width 30 $add$libresoc.v:44676$1294_Y + attribute \src "libresoc.v:44682.19-44682.112" + wire width 5 $add$libresoc.v:44682$1301_Y + attribute \src "libresoc.v:44683.19-44683.112" + wire width 5 $add$libresoc.v:44683$1302_Y + attribute \src "libresoc.v:44498.18-44498.112" + wire $and$libresoc.v:44498$1116_Y + attribute \src "libresoc.v:44565.18-44565.108" + wire $and$libresoc.v:44565$1183_Y + attribute \src "libresoc.v:44576.18-44576.110" + wire $and$libresoc.v:44576$1194_Y + attribute \src "libresoc.v:44604.19-44604.110" + wire $and$libresoc.v:44604$1222_Y + attribute \src "libresoc.v:44607.19-44607.114" + wire $and$libresoc.v:44607$1225_Y + attribute \src "libresoc.v:44610.19-44610.112" + wire $and$libresoc.v:44610$1228_Y + attribute \src "libresoc.v:44612.19-44612.113" + wire $and$libresoc.v:44612$1230_Y + attribute \src "libresoc.v:44614.19-44614.121" + wire $and$libresoc.v:44614$1232_Y + attribute \src "libresoc.v:44617.19-44617.114" + wire $and$libresoc.v:44617$1235_Y + attribute \src "libresoc.v:44619.19-44619.112" + wire $and$libresoc.v:44619$1237_Y + attribute \src "libresoc.v:44623.19-44623.113" + wire $and$libresoc.v:44623$1241_Y + attribute \src "libresoc.v:44625.19-44625.132" + wire $and$libresoc.v:44625$1243_Y + attribute \src "libresoc.v:44629.19-44629.114" + wire $and$libresoc.v:44629$1247_Y + attribute \src "libresoc.v:44631.19-44631.112" + wire $and$libresoc.v:44631$1249_Y + attribute \src "libresoc.v:44634.19-44634.113" + wire $and$libresoc.v:44634$1252_Y + attribute \src "libresoc.v:44636.19-44636.132" + wire $and$libresoc.v:44636$1254_Y + attribute \src "libresoc.v:44639.19-44639.114" + wire $and$libresoc.v:44639$1257_Y + attribute \src "libresoc.v:44641.19-44641.112" + wire $and$libresoc.v:44641$1259_Y + attribute \src "libresoc.v:44643.18-44643.108" + wire $and$libresoc.v:44643$1261_Y + attribute \src "libresoc.v:44644.19-44644.113" + wire $and$libresoc.v:44644$1262_Y + attribute \src "libresoc.v:44646.19-44646.129" + wire $and$libresoc.v:44646$1264_Y + attribute \src "libresoc.v:44650.19-44650.114" + wire $and$libresoc.v:44650$1268_Y + attribute \src "libresoc.v:44652.19-44652.112" + wire $and$libresoc.v:44652$1270_Y + attribute \src "libresoc.v:44654.18-44654.111" + wire $and$libresoc.v:44654$1272_Y + attribute \src "libresoc.v:44655.19-44655.113" + wire $and$libresoc.v:44655$1273_Y + attribute \src "libresoc.v:44657.19-44657.129" + wire $and$libresoc.v:44657$1275_Y + attribute \src "libresoc.v:44660.19-44660.114" + wire $and$libresoc.v:44660$1278_Y + attribute \src "libresoc.v:44662.19-44662.112" + wire $and$libresoc.v:44662$1280_Y + attribute \src "libresoc.v:44664.19-44664.113" + wire $and$libresoc.v:44664$1282_Y + attribute \src "libresoc.v:44667.19-44667.121" + wire $and$libresoc.v:44667$1285_Y + attribute \src "libresoc.v:44699.17-44699.106" + wire $and$libresoc.v:44699$1318_Y + attribute \src "libresoc.v:44454.17-44454.110" + wire $eq$libresoc.v:44454$1072_Y + attribute \src "libresoc.v:44465.18-44465.111" + wire $eq$libresoc.v:44465$1083_Y + attribute \src "libresoc.v:44476.18-44476.111" + wire $eq$libresoc.v:44476$1094_Y + attribute \src "libresoc.v:44509.17-44509.110" + wire $eq$libresoc.v:44509$1127_Y + attribute \src "libresoc.v:44510.18-44510.111" + wire $eq$libresoc.v:44510$1128_Y + attribute \src "libresoc.v:44521.18-44521.111" + wire $eq$libresoc.v:44521$1139_Y + attribute \src "libresoc.v:44543.18-44543.111" + wire $eq$libresoc.v:44543$1161_Y + attribute \src "libresoc.v:44587.18-44587.111" + wire $eq$libresoc.v:44587$1205_Y + attribute \src "libresoc.v:44598.18-44598.111" + wire $eq$libresoc.v:44598$1216_Y + attribute \src "libresoc.v:44599.19-44599.112" + wire $eq$libresoc.v:44599$1217_Y + attribute \src "libresoc.v:44600.19-44600.112" + wire $eq$libresoc.v:44600$1218_Y + attribute \src "libresoc.v:44602.19-44602.112" + wire $eq$libresoc.v:44602$1220_Y + attribute \src "libresoc.v:44605.19-44605.112" + wire $eq$libresoc.v:44605$1223_Y + attribute \src "libresoc.v:44615.19-44615.112" + wire $eq$libresoc.v:44615$1233_Y + attribute \src "libresoc.v:44620.17-44620.110" + wire $eq$libresoc.v:44620$1238_Y + attribute \src "libresoc.v:44621.18-44621.111" + wire $eq$libresoc.v:44621$1239_Y + attribute \src "libresoc.v:44626.19-44626.112" + wire $eq$libresoc.v:44626$1244_Y + attribute \src "libresoc.v:44627.19-44627.112" + wire $eq$libresoc.v:44627$1245_Y + attribute \src "libresoc.v:44637.19-44637.112" + wire $eq$libresoc.v:44637$1255_Y + attribute \src "libresoc.v:44647.19-44647.112" + wire $eq$libresoc.v:44647$1265_Y + attribute \src "libresoc.v:44648.19-44648.112" + wire $eq$libresoc.v:44648$1266_Y + attribute \src "libresoc.v:44658.19-44658.112" + wire $eq$libresoc.v:44658$1276_Y + attribute \src "libresoc.v:44665.18-44665.111" + wire $eq$libresoc.v:44665$1283_Y + attribute \src "libresoc.v:44668.19-44668.110" + wire $eq$libresoc.v:44668$1286_Y + attribute \src "libresoc.v:44670.19-44670.110" + wire $eq$libresoc.v:44670$1288_Y + attribute \src "libresoc.v:44671.19-44671.110" + wire $eq$libresoc.v:44671$1289_Y + attribute \src "libresoc.v:44673.19-44673.110" + wire $eq$libresoc.v:44673$1291_Y + attribute \src "libresoc.v:44675.18-44675.111" + wire $eq$libresoc.v:44675$1293_Y + attribute \src "libresoc.v:44678.19-44678.116" + wire $eq$libresoc.v:44678$1297_Y + attribute \src "libresoc.v:44679.19-44679.116" + wire $eq$libresoc.v:44679$1298_Y + attribute \src "libresoc.v:44681.19-44681.116" + wire $eq$libresoc.v:44681$1300_Y + attribute \src "libresoc.v:44677.19-44677.106" + wire width 8 $extend$libresoc.v:44677$1295_Y + attribute \src "libresoc.v:44606.19-44606.109" + wire $ne$libresoc.v:44606$1224_Y + attribute \src "libresoc.v:44608.19-44608.109" + wire $ne$libresoc.v:44608$1226_Y + attribute \src "libresoc.v:44611.19-44611.109" + wire $ne$libresoc.v:44611$1229_Y + attribute \src "libresoc.v:44616.19-44616.120" + wire $ne$libresoc.v:44616$1234_Y + attribute \src "libresoc.v:44618.19-44618.120" + wire $ne$libresoc.v:44618$1236_Y + attribute \src "libresoc.v:44622.19-44622.120" + wire $ne$libresoc.v:44622$1240_Y + attribute \src "libresoc.v:44628.19-44628.120" + wire $ne$libresoc.v:44628$1246_Y + attribute \src "libresoc.v:44630.19-44630.120" + wire $ne$libresoc.v:44630$1248_Y + attribute \src "libresoc.v:44633.19-44633.120" + wire $ne$libresoc.v:44633$1251_Y + attribute \src "libresoc.v:44638.19-44638.117" + wire $ne$libresoc.v:44638$1256_Y + attribute \src "libresoc.v:44640.19-44640.117" + wire $ne$libresoc.v:44640$1258_Y + attribute \src "libresoc.v:44642.19-44642.117" + wire $ne$libresoc.v:44642$1260_Y + attribute \src "libresoc.v:44649.19-44649.117" + wire $ne$libresoc.v:44649$1267_Y + attribute \src "libresoc.v:44651.19-44651.117" + wire $ne$libresoc.v:44651$1269_Y + attribute \src "libresoc.v:44653.19-44653.117" + wire $ne$libresoc.v:44653$1271_Y + attribute \src "libresoc.v:44659.19-44659.109" + wire $ne$libresoc.v:44659$1277_Y + attribute \src "libresoc.v:44661.19-44661.109" + wire $ne$libresoc.v:44661$1279_Y + attribute \src "libresoc.v:44663.19-44663.109" + wire $ne$libresoc.v:44663$1281_Y + attribute \src "libresoc.v:44613.19-44613.110" + wire $not$libresoc.v:44613$1231_Y + attribute \src "libresoc.v:44624.19-44624.121" + wire $not$libresoc.v:44624$1242_Y + attribute \src "libresoc.v:44635.19-44635.121" + wire $not$libresoc.v:44635$1253_Y + attribute \src "libresoc.v:44645.19-44645.118" + wire $not$libresoc.v:44645$1263_Y + attribute \src "libresoc.v:44656.19-44656.118" + wire $not$libresoc.v:44656$1274_Y + attribute \src "libresoc.v:44666.19-44666.110" + wire $not$libresoc.v:44666$1284_Y + attribute \src "libresoc.v:44669.19-44669.100" + wire $not$libresoc.v:44669$1287_Y + attribute \src "libresoc.v:44487.18-44487.104" + wire $or$libresoc.v:44487$1105_Y + attribute \src "libresoc.v:44532.18-44532.104" + wire $or$libresoc.v:44532$1150_Y + attribute \src "libresoc.v:44554.18-44554.104" + wire $or$libresoc.v:44554$1172_Y + attribute \src "libresoc.v:44601.19-44601.107" + wire $or$libresoc.v:44601$1219_Y + attribute \src "libresoc.v:44603.19-44603.107" + wire $or$libresoc.v:44603$1221_Y + attribute \src "libresoc.v:44609.18-44609.104" + wire $or$libresoc.v:44609$1227_Y + attribute \src "libresoc.v:44632.18-44632.104" + wire $or$libresoc.v:44632$1250_Y + attribute \src "libresoc.v:44672.19-44672.107" + wire $or$libresoc.v:44672$1290_Y + attribute \src "libresoc.v:44680.19-44680.107" + wire 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"/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$461 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$463 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$465 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$471 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$473 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$475 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$477 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$481 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$483 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$484 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$487 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$489 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$491 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" + wire \$493 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + wire width 30 \$495 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + wire width 30 \$496 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + wire width 30 \$498 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + wire width 30 \$499 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 8 \$501 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$504 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$506 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$508 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" + wire \$510 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + wire width 5 \$512 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + wire width 5 \$513 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + wire width 5 \$515 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + wire width 5 \$516 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 327 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 163 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 318 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 328 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" + wire \TAP_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \_fsm_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \_fsm_isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire \_fsm_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire \_fsm_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire \_fsm_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire \_idblock_TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire \_idblock_id_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire \_idblock_select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 \_irblock_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire \_irblock_tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 329 \clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire input 6 \dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 output 2 \dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \dmi0__addr_i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 output 5 \dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \dmi0__din$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 input 7 \dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 3 \dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 4 \dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \dmi0_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \dmi0_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 164 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 9 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 165 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 10 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 166 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 11 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 19 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 18 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 176 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 23 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 21 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 177 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 178 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 13 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 14 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 12 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 170 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 16 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 17 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 15 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 171 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 172 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s7__pad__oe + attribute \src "libresoc.v:43025.7-43025.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" + wire \io_bd2core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + wire \io_bd2io + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" + wire \io_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + wire \io_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" + wire \io_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 325 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 319 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 \jtag_wb__adr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 321 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 326 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 324 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 \jtag_wb__dat_w$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 320 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 322 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 323 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \jtag_wb_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \jtag_wb_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr0_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr0_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr0_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr0_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire width 2 \sr5__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__ie + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire width 2 \sr5__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr5_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr5_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 2 \sr5_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 2 \sr5_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr5_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr5_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire \wb_dcache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire \wb_dcache_en$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire output 8 \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \wb_icache_en$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + cell $add $add$libresoc.v:44674$1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:44674$1292_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + cell $add $add$libresoc.v:44676$1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:44676$1294_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + cell $add $add$libresoc.v:44682$1301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:44682$1301_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + cell $add $add$libresoc.v:44683$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:44683$1302_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" + cell $and $and$libresoc.v:44498$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:44498$1116_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:44565$1183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$27 + connect \Y $and$libresoc.v:44565$1183_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" + cell $and $and$libresoc.v:44576$1194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:44576$1194_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:44604$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$367 + connect \Y $and$libresoc.v:44604$1222_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:44607$1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$373 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:44607$1225_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:44610$1228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$377 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:44610$1228_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:44612$1230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$381 + connect \B \_fsm_update + connect \Y $and$libresoc.v:44612$1230_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:44614$1232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core_prev + connect \B \$385 + connect \Y $and$libresoc.v:44614$1232_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:44617$1235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$391 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:44617$1235_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:44619$1237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$395 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:44619$1237_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:44623$1241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$399 + connect \B \_fsm_update + connect \Y $and$libresoc.v:44623$1241_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:44625$1243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core_prev + connect \B \$403 + connect \Y $and$libresoc.v:44625$1243_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:44629$1247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$411 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:44629$1247_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:44631$1249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$415 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:44631$1249_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:44634$1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$419 + connect \B \_fsm_update + connect \Y $and$libresoc.v:44634$1252_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:44636$1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core_prev + connect \B \$423 + connect \Y $and$libresoc.v:44636$1254_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:44639$1257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$429 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:44639$1257_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:44641$1259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$433 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:44641$1259_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:44643$1261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$41 + connect \Y $and$libresoc.v:44643$1261_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:44644$1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$437 + connect \B \_fsm_update + connect \Y $and$libresoc.v:44644$1262_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:44646$1264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core_prev + connect \B \$441 + connect \Y $and$libresoc.v:44646$1264_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:44650$1268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$449 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:44650$1268_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:44652$1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$453 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:44652$1270_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + cell $and $and$libresoc.v:44654$1272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \_fsm_update + connect \Y $and$libresoc.v:44654$1272_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:44655$1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$457 + connect \B \_fsm_update + connect \Y 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$and$libresoc.v:44662$1280_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:44664$1282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$475 + connect \B \_fsm_update + connect \Y $and$libresoc.v:44664$1282_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:44667$1285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_update_core_prev + connect \B \$479 + connect \Y $and$libresoc.v:44667$1285_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $and $and$libresoc.v:44699$1318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$5 + connect \Y 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parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44661$1279_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:44663$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44663$1281_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44613$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core + connect \Y $not$libresoc.v:44613$1231_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44624$1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core + connect \Y $not$libresoc.v:44624$1242_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44635$1253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core + connect \Y $not$libresoc.v:44635$1253_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44645$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core + connect \Y $not$libresoc.v:44645$1263_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44656$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core + connect \Y $not$libresoc.v:44656$1274_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44666$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_update_core + connect \Y $not$libresoc.v:44666$1284_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + cell $not $not$libresoc.v:44669$1287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$484 + connect \Y $not$libresoc.v:44669$1287_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:44487$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \B \$13 + connect \Y $or$libresoc.v:44487$1105_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:44532$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \$21 + connect \Y $or$libresoc.v:44532$1150_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:44554$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:44554$1172_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:44601$1219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$359 + connect \B \$361 + connect \Y $or$libresoc.v:44601$1219_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:44603$1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$363 + connect \B \$365 + connect \Y $or$libresoc.v:44603$1221_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:44609$1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:44609$1227_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:44632$1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:44632$1250_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $or $or$libresoc.v:44672$1290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$487 + connect \B \$489 + connect \Y $or$libresoc.v:44672$1290_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $or $or$libresoc.v:44680$1299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$504 + connect \B \$506 + connect \Y $or$libresoc.v:44680$1299_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $or $or$libresoc.v:44688$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:44688$1307_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + cell $pos $pos$libresoc.v:44677$1296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:44677$1295_Y + connect \Y $pos$libresoc.v:44677$1296_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44455$1073 + parameter \WIDTH 1 + connect \A \gpio_e15__pad__i + connect \B \io_bd [24] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44455$1073_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44456$1074 + parameter \WIDTH 1 + connect \A \gpio_e15__core__o + connect \B \io_bd [25] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44456$1074_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44457$1075 + parameter \WIDTH 1 + connect \A \gpio_e15__core__oe + connect \B \io_bd [26] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44457$1075_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44458$1076 + parameter \WIDTH 1 + connect \A \gpio_s0__pad__i + connect \B \io_bd [27] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44458$1076_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44459$1077 + parameter \WIDTH 1 + connect \A \gpio_s0__core__o + connect \B \io_bd [28] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44459$1077_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44460$1078 + parameter \WIDTH 1 + connect \A \gpio_s0__core__oe + connect \B \io_bd [29] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44460$1078_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44461$1079 + parameter \WIDTH 1 + connect \A \gpio_s1__pad__i + connect \B \io_bd [30] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44461$1079_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44462$1080 + parameter \WIDTH 1 + connect \A \gpio_s1__core__o + connect \B \io_bd [31] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44462$1080_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44463$1081 + parameter \WIDTH 1 + connect \A \gpio_s1__core__oe + connect \B \io_bd [32] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44463$1081_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44464$1082 + parameter \WIDTH 1 + connect \A \gpio_s2__pad__i + connect \B \io_bd [33] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44464$1082_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44466$1084 + parameter \WIDTH 1 + connect \A \gpio_s2__core__o + connect \B \io_bd [34] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44466$1084_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44467$1085 + parameter \WIDTH 1 + connect \A \gpio_s2__core__oe + connect \B \io_bd [35] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44467$1085_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44468$1086 + parameter \WIDTH 1 + connect \A \gpio_s3__pad__i + connect \B \io_bd [36] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44468$1086_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44469$1087 + parameter \WIDTH 1 + connect \A \gpio_s3__core__o + connect \B \io_bd [37] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44469$1087_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44470$1088 + parameter \WIDTH 1 + connect \A \gpio_s3__core__oe + connect \B \io_bd [38] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44470$1088_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44471$1089 + parameter \WIDTH 1 + connect \A \gpio_s4__pad__i + connect \B \io_bd [39] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44471$1089_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44472$1090 + parameter \WIDTH 1 + connect \A \gpio_s4__core__o + connect \B \io_bd [40] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44472$1090_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44473$1091 + parameter \WIDTH 1 + connect \A \gpio_s4__core__oe + connect \B \io_bd [41] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44473$1091_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44474$1092 + parameter \WIDTH 1 + connect \A \gpio_s5__pad__i + connect \B \io_bd [42] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44474$1092_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44475$1093 + parameter \WIDTH 1 + connect \A \gpio_s5__core__o + connect \B \io_bd [43] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44475$1093_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44477$1095 + parameter \WIDTH 1 + connect \A \gpio_s5__core__oe + connect \B \io_bd [44] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44477$1095_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44478$1096 + parameter \WIDTH 1 + connect \A \gpio_s6__pad__i + connect \B \io_bd [45] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44478$1096_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44479$1097 + parameter \WIDTH 1 + connect \A \gpio_s6__core__o + connect \B \io_bd [46] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44479$1097_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44480$1098 + parameter \WIDTH 1 + connect \A \gpio_s6__core__oe + connect \B \io_bd [47] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44480$1098_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44481$1099 + parameter \WIDTH 1 + connect \A \gpio_s7__pad__i + connect \B \io_bd [48] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44481$1099_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44482$1100 + parameter \WIDTH 1 + connect \A \gpio_s7__core__o + connect \B \io_bd [49] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44482$1100_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44483$1101 + parameter \WIDTH 1 + connect \A \gpio_s7__core__oe + connect \B \io_bd [50] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44483$1101_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44484$1102 + parameter \WIDTH 1 + connect \A \mspi0_clk__core__o + connect \B \io_bd [51] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44484$1102_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44485$1103 + parameter \WIDTH 1 + connect \A \mspi0_cs_n__core__o + connect \B \io_bd [52] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44485$1103_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44486$1104 + parameter \WIDTH 1 + connect \A \mspi0_mosi__core__o + connect \B \io_bd [53] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44486$1104_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:44488$1106 + parameter \WIDTH 1 + connect \A \mspi0_miso__pad__i + connect \B \io_bd [54] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44488$1106_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44489$1107 + parameter \WIDTH 1 + connect \A \mspi1_clk__core__o + connect \B \io_bd [55] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44489$1107_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44490$1108 + parameter \WIDTH 1 + connect \A \mspi1_cs_n__core__o + connect \B \io_bd [56] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44490$1108_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44491$1109 + parameter \WIDTH 1 + connect \A \mspi1_mosi__core__o + connect \B \io_bd [57] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44491$1109_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:44492$1110 + parameter \WIDTH 1 + connect \A \mspi1_miso__pad__i + connect \B \io_bd [58] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44492$1110_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44493$1111 + parameter \WIDTH 1 + connect \A \mtwi_sda__pad__i + connect \B \io_bd [59] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44493$1111_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44494$1112 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__o + connect \B \io_bd [60] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44494$1112_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44495$1113 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__oe + connect \B \io_bd [61] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44495$1113_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44496$1114 + parameter \WIDTH 1 + connect \A \mtwi_scl__core__o + connect \B \io_bd [62] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44496$1114_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44497$1115 + parameter \WIDTH 1 + connect \A \pwm_0__core__o + connect \B \io_bd [63] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44497$1115_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44499$1117 + parameter \WIDTH 1 + connect \A \pwm_1__core__o + connect \B \io_bd [64] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44499$1117_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44500$1118 + parameter \WIDTH 1 + connect \A \sd0_cmd__pad__i + connect \B \io_bd [65] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44500$1118_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44501$1119 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__o + connect \B \io_bd [66] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44501$1119_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44502$1120 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__oe + connect \B \io_bd [67] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44502$1120_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44503$1121 + parameter \WIDTH 1 + connect \A \sd0_clk__core__o + connect \B \io_bd [68] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44503$1121_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44504$1122 + parameter \WIDTH 1 + connect \A \sd0_data0__pad__i + connect \B \io_bd [69] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44504$1122_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44505$1123 + parameter \WIDTH 1 + connect \A \sd0_data0__core__o + connect \B \io_bd [70] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44505$1123_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44506$1124 + parameter \WIDTH 1 + connect \A \sd0_data0__core__oe + connect \B \io_bd [71] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44506$1124_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44507$1125 + parameter \WIDTH 1 + connect \A \sd0_data1__pad__i + connect \B \io_bd [72] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44507$1125_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44508$1126 + parameter \WIDTH 1 + connect \A \sd0_data1__core__o + connect \B \io_bd [73] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44508$1126_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44511$1129 + parameter \WIDTH 1 + connect \A \sd0_data1__core__oe + connect \B \io_bd [74] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44511$1129_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44512$1130 + parameter \WIDTH 1 + connect \A \sd0_data2__pad__i + connect \B \io_bd [75] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44512$1130_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44513$1131 + parameter \WIDTH 1 + connect \A \sd0_data2__core__o + connect \B \io_bd [76] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44513$1131_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44514$1132 + parameter \WIDTH 1 + connect \A \sd0_data2__core__oe + connect \B \io_bd [77] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44514$1132_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44515$1133 + parameter \WIDTH 1 + connect \A \sd0_data3__pad__i + connect \B \io_bd [78] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44515$1133_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44516$1134 + parameter \WIDTH 1 + connect \A \sd0_data3__core__o + connect \B \io_bd [79] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44516$1134_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44517$1135 + parameter \WIDTH 1 + connect \A \sd0_data3__core__oe + connect \B \io_bd [80] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44517$1135_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44518$1136 + parameter \WIDTH 1 + connect \A \sdr_dm_0__core__o + connect \B \io_bd [81] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44518$1136_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44519$1137 + parameter \WIDTH 1 + connect \A \sdr_dq_0__pad__i + connect \B \io_bd [82] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44519$1137_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44520$1138 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__o + connect \B \io_bd [83] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44520$1138_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44522$1140 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__oe + connect \B \io_bd [84] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44522$1140_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44523$1141 + parameter \WIDTH 1 + connect \A \sdr_dq_1__pad__i + connect \B \io_bd [85] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44523$1141_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44524$1142 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__o + connect \B \io_bd [86] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44524$1142_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44525$1143 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__oe + connect \B \io_bd [87] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44525$1143_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44526$1144 + parameter \WIDTH 1 + connect \A \sdr_dq_2__pad__i + connect \B \io_bd [88] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44526$1144_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44527$1145 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__o + connect \B \io_bd [89] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44527$1145_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44528$1146 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__oe + connect \B \io_bd [90] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44528$1146_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44529$1147 + parameter \WIDTH 1 + connect \A \sdr_dq_3__pad__i + connect \B \io_bd [91] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44529$1147_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44530$1148 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__o + connect \B \io_bd [92] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44530$1148_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44531$1149 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__oe + connect \B \io_bd [93] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44531$1149_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44533$1151 + parameter \WIDTH 1 + connect \A \sdr_dq_4__pad__i + connect \B \io_bd [94] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44533$1151_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44534$1152 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__o + connect \B \io_bd [95] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44534$1152_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44535$1153 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__oe + connect \B \io_bd [96] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44535$1153_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44536$1154 + parameter \WIDTH 1 + connect \A \sdr_dq_5__pad__i + connect \B \io_bd [97] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44536$1154_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44537$1155 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__o + connect \B \io_bd [98] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44537$1155_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44538$1156 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__oe + connect \B \io_bd [99] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44538$1156_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44539$1157 + parameter \WIDTH 1 + connect \A \sdr_dq_6__pad__i + connect \B \io_bd [100] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44539$1157_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44540$1158 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__o + connect \B \io_bd [101] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44540$1158_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44541$1159 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__oe + connect \B \io_bd [102] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44541$1159_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44542$1160 + parameter \WIDTH 1 + connect \A \sdr_dq_7__pad__i + connect \B \io_bd [103] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44542$1160_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44544$1162 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__o + connect \B \io_bd [104] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44544$1162_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44545$1163 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__oe + connect \B \io_bd [105] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44545$1163_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44546$1164 + parameter \WIDTH 1 + connect \A \sdr_a_0__core__o + connect \B \io_bd [106] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44546$1164_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44547$1165 + parameter \WIDTH 1 + connect \A \sdr_a_1__core__o + connect \B \io_bd [107] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44547$1165_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44548$1166 + parameter \WIDTH 1 + connect \A \sdr_a_2__core__o + connect \B \io_bd [108] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44548$1166_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44549$1167 + parameter \WIDTH 1 + connect \A \sdr_a_3__core__o + connect \B \io_bd [109] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44549$1167_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44550$1168 + parameter \WIDTH 1 + connect \A \sdr_a_4__core__o + connect \B \io_bd [110] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44550$1168_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44551$1169 + parameter \WIDTH 1 + connect \A \sdr_a_5__core__o + connect \B \io_bd [111] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44551$1169_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44552$1170 + parameter \WIDTH 1 + connect \A \sdr_a_6__core__o + connect \B \io_bd [112] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44552$1170_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44553$1171 + parameter \WIDTH 1 + connect \A \sdr_a_7__core__o + connect \B \io_bd [113] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44553$1171_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44555$1173 + parameter \WIDTH 1 + connect \A \sdr_a_8__core__o + connect \B \io_bd [114] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44555$1173_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44556$1174 + parameter \WIDTH 1 + connect \A \sdr_a_9__core__o + connect \B \io_bd [115] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44556$1174_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44557$1175 + parameter \WIDTH 1 + connect \A \sdr_ba_0__core__o + connect \B \io_bd [116] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44557$1175_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44558$1176 + parameter \WIDTH 1 + connect \A \sdr_ba_1__core__o + connect \B \io_bd [117] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44558$1176_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44559$1177 + parameter \WIDTH 1 + connect \A \sdr_clock__core__o + connect \B \io_bd [118] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44559$1177_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44560$1178 + parameter \WIDTH 1 + connect \A \sdr_cke__core__o + connect \B \io_bd [119] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44560$1178_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44561$1179 + parameter \WIDTH 1 + connect \A \sdr_ras_n__core__o + connect \B \io_bd [120] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44561$1179_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44562$1180 + parameter \WIDTH 1 + connect \A \sdr_cas_n__core__o + connect \B \io_bd [121] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44562$1180_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44563$1181 + parameter \WIDTH 1 + connect \A \sdr_we_n__core__o + connect \B \io_bd [122] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44563$1181_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44564$1182 + parameter \WIDTH 1 + connect \A \sdr_cs_n__core__o + connect \B \io_bd [123] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44564$1182_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44566$1184 + parameter \WIDTH 1 + connect \A \sdr_a_10__core__o + connect \B \io_bd [124] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44566$1184_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44567$1185 + parameter \WIDTH 1 + connect \A \sdr_a_11__core__o + connect \B \io_bd [125] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44567$1185_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44568$1186 + parameter \WIDTH 1 + connect \A \sdr_a_12__core__o + connect \B \io_bd [126] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44568$1186_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44569$1187 + parameter \WIDTH 1 + connect \A \sdr_dm_1__pad__i + connect \B \io_bd [127] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44569$1187_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44570$1188 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__o + connect \B \io_bd [128] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44570$1188_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44571$1189 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__oe + connect \B \io_bd [129] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44571$1189_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44572$1190 + parameter \WIDTH 1 + connect \A \sdr_dq_8__pad__i + connect \B \io_bd [130] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44572$1190_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44573$1191 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__o + connect \B \io_bd [131] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44573$1191_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44574$1192 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__oe + connect \B \io_bd [132] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44574$1192_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44575$1193 + parameter \WIDTH 1 + connect \A \sdr_dq_9__pad__i + connect \B \io_bd [133] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44575$1193_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44577$1195 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__o + connect \B \io_bd [134] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44577$1195_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44578$1196 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__oe + connect \B \io_bd [135] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44578$1196_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44579$1197 + parameter \WIDTH 1 + connect \A \sdr_dq_10__pad__i + connect \B \io_bd [136] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44579$1197_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44580$1198 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__o + connect \B \io_bd [137] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44580$1198_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44581$1199 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__oe + connect \B \io_bd [138] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44581$1199_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44582$1200 + parameter \WIDTH 1 + connect \A \sdr_dq_11__pad__i + connect \B \io_bd [139] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44582$1200_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44583$1201 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__o + connect \B \io_bd [140] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44583$1201_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44584$1202 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__oe + connect \B \io_bd [141] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44584$1202_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44585$1203 + parameter \WIDTH 1 + connect \A \sdr_dq_12__pad__i + connect \B \io_bd [142] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44585$1203_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44586$1204 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__o + connect \B \io_bd [143] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44586$1204_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44588$1206 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__oe + connect \B \io_bd [144] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44588$1206_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44589$1207 + parameter \WIDTH 1 + connect \A \sdr_dq_13__pad__i + connect \B \io_bd [145] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44589$1207_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44590$1208 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__o + connect \B \io_bd [146] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44590$1208_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44591$1209 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__oe + connect \B \io_bd [147] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44591$1209_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44592$1210 + parameter \WIDTH 1 + connect \A \sdr_dq_14__pad__i + connect \B \io_bd [148] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44592$1210_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44593$1211 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__o + connect \B \io_bd [149] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44593$1211_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44594$1212 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__oe + connect \B \io_bd [150] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44594$1212_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44595$1213 + parameter \WIDTH 1 + connect \A \sdr_dq_15__pad__i + connect \B \io_bd [151] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44595$1213_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44596$1214 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__o + connect \B \io_bd [152] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44596$1214_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44597$1215 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__oe + connect \B \io_bd [153] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44597$1215_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:44684$1303 + parameter \WIDTH 1 + connect \A \eint_0__pad__i + connect \B \io_bd [0] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44684$1303_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:44685$1304 + parameter \WIDTH 1 + connect \A \eint_1__pad__i + connect \B \io_bd [1] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44685$1304_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:44686$1305 + parameter \WIDTH 1 + connect \A \eint_2__pad__i + connect \B \io_bd [2] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44686$1305_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44687$1306 + parameter \WIDTH 1 + connect \A \gpio_e8__pad__i + connect \B \io_bd [3] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44687$1306_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44689$1308 + parameter \WIDTH 1 + connect \A \gpio_e8__core__o + connect \B \io_bd [4] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44689$1308_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44690$1309 + parameter \WIDTH 1 + connect \A \gpio_e8__core__oe + connect \B \io_bd [5] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44690$1309_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44691$1310 + parameter \WIDTH 1 + connect \A \gpio_e9__pad__i + connect \B \io_bd [6] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44691$1310_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44692$1311 + parameter \WIDTH 1 + connect \A \gpio_e9__core__o + connect \B \io_bd [7] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44692$1311_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44693$1312 + parameter \WIDTH 1 + connect \A \gpio_e9__core__oe + connect \B \io_bd [8] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44693$1312_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44694$1313 + parameter \WIDTH 1 + connect \A \gpio_e10__pad__i + connect \B \io_bd [9] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44694$1313_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44695$1314 + parameter \WIDTH 1 + connect \A \gpio_e10__core__o + connect \B \io_bd [10] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44695$1314_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44696$1315 + parameter \WIDTH 1 + connect \A \gpio_e10__core__oe + connect \B \io_bd [11] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44696$1315_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44697$1316 + parameter \WIDTH 1 + connect \A \gpio_e11__pad__i + connect \B \io_bd [12] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44697$1316_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44698$1317 + parameter \WIDTH 1 + connect \A \gpio_e11__core__o + connect \B \io_bd [13] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44698$1317_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44700$1319 + parameter \WIDTH 1 + connect \A \gpio_e11__core__oe + connect \B \io_bd [14] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44700$1319_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44701$1320 + parameter \WIDTH 1 + connect \A \gpio_e12__pad__i + connect \B \io_bd [15] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44701$1320_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44702$1321 + parameter \WIDTH 1 + connect \A \gpio_e12__core__o + connect \B \io_bd [16] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44702$1321_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44703$1322 + parameter \WIDTH 1 + connect \A \gpio_e12__core__oe + connect \B \io_bd [17] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44703$1322_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44704$1323 + parameter \WIDTH 1 + connect \A \gpio_e13__pad__i + connect \B \io_bd [18] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44704$1323_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44705$1324 + parameter \WIDTH 1 + connect \A \gpio_e13__core__o + connect \B \io_bd [19] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44705$1324_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44706$1325 + parameter \WIDTH 1 + connect \A \gpio_e13__core__oe + connect \B \io_bd [20] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44706$1325_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44707$1326 + parameter \WIDTH 1 + connect \A \gpio_e14__pad__i + connect \B \io_bd [21] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44707$1326_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44708$1327 + parameter \WIDTH 1 + connect \A \gpio_e14__core__o + connect \B \io_bd [22] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44708$1327_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44709$1328 + parameter \WIDTH 1 + connect \A \gpio_e14__core__oe + connect \B \io_bd [23] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44709$1328_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:44782.8-44794.4" + cell \_fsm \_fsm + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tms \TAP_bus__tms + connect \capture \_fsm_capture + connect \isdr \_fsm_isdr + connect \isir \_fsm_isir + connect \negjtag_clk \negjtag_clk + connect \negjtag_rst \negjtag_rst + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:44795.12-44805.4" + cell \_idblock \_idblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_id_tdo \_idblock_TAP_id_tdo + connect \capture \_fsm_capture + connect \id_bypass \_idblock_id_bypass + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \select_id \_idblock_select_id + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:44806.12-44816.4" + cell \_irblock \_irblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isir \_fsm_isir + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \tdo \_irblock_tdo + connect \update \_fsm_update + end + attribute \src "libresoc.v:43025.7-43025.20" + process $proc$libresoc.v:43025$1520 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:43583.13-43583.32" + process $proc$libresoc.v:43583$1521 + assign { } { } + assign $1\dmi0__addr_i[3:0] 4'0000 + sync always + sync init + update \dmi0__addr_i $1\dmi0__addr_i[3:0] + end + attribute \src "libresoc.v:43588.14-43588.46" + process $proc$libresoc.v:43588$1522 + assign { } { } + assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0__din $1\dmi0__din[63:0] + end + attribute \src "libresoc.v:43602.7-43602.29" + process $proc$libresoc.v:43602$1523 + assign { } { } + assign $1\dmi0_addrsr__oe[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:43610.13-43610.36" + process $proc$libresoc.v:43610$1524 + assign { } { } + assign $1\dmi0_addrsr_reg[7:0] 8'00000000 + sync always + sync init + update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:43618.7-43618.37" + process $proc$libresoc.v:43618$1525 + assign { } { } + assign $1\dmi0_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:43622.7-43622.42" + process $proc$libresoc.v:43622$1526 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43626.14-43626.51" + process $proc$libresoc.v:43626$1527 + assign { } { } + assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:43632.13-43632.35" + process $proc$libresoc.v:43632$1528 + assign { } { } + assign $1\dmi0_datasr__oe[1:0] 2'00 + sync always + sync init + update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:43640.14-43640.52" + process $proc$libresoc.v:43640$1529 + assign { } { } + assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:43648.7-43648.37" + process $proc$libresoc.v:43648$1530 + assign { } { } + assign $1\dmi0_datasr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:43652.7-43652.42" + process $proc$libresoc.v:43652$1531 + assign { } { } + assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43668.13-43668.29" + process $proc$libresoc.v:43668$1532 + assign { } { } + assign $1\fsm_state[2:0] 3'000 + sync always + sync init + update \fsm_state $1\fsm_state[2:0] + end + attribute \src "libresoc.v:43670.13-43670.35" + process $proc$libresoc.v:43670$1533 + assign { } { } + assign $0\fsm_state$503[2:0]$1534 3'000 + sync always + sync init + update \fsm_state$503 $0\fsm_state$503[2:0]$1534 + end + attribute \src "libresoc.v:43868.15-43868.67" + process $proc$libresoc.v:43868$1535 + assign { } { } + assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_bd $1\io_bd[153:0] + end + attribute \src "libresoc.v:43880.15-43880.67" + process $proc$libresoc.v:43880$1536 + assign { } { } + assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_sr $1\io_sr[153:0] + end + attribute \src "libresoc.v:43889.14-43889.41" + process $proc$libresoc.v:43889$1537 + assign { } { } + assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb__adr $1\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:43898.14-43898.51" + process $proc$libresoc.v:43898$1538 + assign { } { } + assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:43912.7-43912.32" + process $proc$libresoc.v:43912$1539 + assign { } { } + assign $1\jtag_wb_addrsr__oe[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:43920.14-43920.47" + process $proc$libresoc.v:43920$1540 + assign { } { } + assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:43928.7-43928.40" + process $proc$libresoc.v:43928$1541 + assign { } { } + assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:43932.7-43932.45" + process $proc$libresoc.v:43932$1542 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43936.14-43936.54" + process $proc$libresoc.v:43936$1543 + assign { } { } + assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:43942.13-43942.38" + process $proc$libresoc.v:43942$1544 + assign { } { } + assign $1\jtag_wb_datasr__oe[1:0] 2'00 + sync always + sync init + update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:43950.14-43950.55" + process $proc$libresoc.v:43950$1545 + assign { } { } + assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:43958.7-43958.40" + process $proc$libresoc.v:43958$1546 + assign { } { } + assign $1\jtag_wb_datasr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:43962.7-43962.45" + process $proc$libresoc.v:43962$1547 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:44392.7-44392.21" + process $proc$libresoc.v:44392$1548 + assign { } { } + assign $1\sr0__oe[0:0] 1'0 + sync always + sync init + update \sr0__oe $1\sr0__oe[0:0] + end + attribute \src "libresoc.v:44400.13-44400.27" + process $proc$libresoc.v:44400$1549 + assign { } { } + assign $1\sr0_reg[2:0] 3'000 + sync always + sync init + update \sr0_reg $1\sr0_reg[2:0] + end + attribute \src "libresoc.v:44408.7-44408.29" + process $proc$libresoc.v:44408$1550 + assign { } { } + assign $1\sr0_update_core[0:0] 1'0 + sync always + sync init + update \sr0_update_core $1\sr0_update_core[0:0] + end + attribute \src "libresoc.v:44412.7-44412.34" + process $proc$libresoc.v:44412$1551 + assign { } { } + assign $1\sr0_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:44422.7-44422.21" + process $proc$libresoc.v:44422$1552 + assign { } { } + assign $1\sr5__oe[0:0] 1'0 + sync always + sync init + update \sr5__oe $1\sr5__oe[0:0] + end + attribute \src "libresoc.v:44430.13-44430.27" + process $proc$libresoc.v:44430$1553 + assign { } { } + assign $1\sr5_reg[1:0] 2'00 + sync always + sync init + update \sr5_reg $1\sr5_reg[1:0] + end + attribute \src "libresoc.v:44438.7-44438.29" + process $proc$libresoc.v:44438$1554 + assign { } { } + assign $1\sr5_update_core[0:0] 1'0 + sync always + sync init + update \sr5_update_core $1\sr5_update_core[0:0] + end + attribute \src "libresoc.v:44442.7-44442.34" + process $proc$libresoc.v:44442$1555 + assign { } { } + assign $1\sr5_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] + end + attribute \src "libresoc.v:44446.7-44446.26" + process $proc$libresoc.v:44446$1556 + assign { } { } + assign $1\wb_dcache_en[0:0] 1'1 + sync always + sync init + update \wb_dcache_en $1\wb_dcache_en[0:0] + end + attribute \src "libresoc.v:44451.7-44451.26" + process $proc$libresoc.v:44451$1557 + assign { } { } + assign $1\wb_icache_en[0:0] 1'1 + sync always + sync init + update \wb_icache_en $1\wb_icache_en[0:0] + end + attribute \src "libresoc.v:44710.3-44711.41" + process $proc$libresoc.v:44710$1329 + assign { } { } + assign $0\wb_icache_en[0:0] \wb_icache_en$next + sync posedge \clk + update \wb_icache_en $0\wb_icache_en[0:0] + end + attribute \src "libresoc.v:44712.3-44713.41" + process $proc$libresoc.v:44712$1330 + assign { } { } + assign $0\wb_dcache_en[0:0] \wb_dcache_en$next + sync posedge \clk + update \wb_dcache_en $0\wb_dcache_en[0:0] + end + attribute \src "libresoc.v:44714.3-44715.45" + process $proc$libresoc.v:44714$1331 + assign { } { } + assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next + sync posedge \clk + update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:44716.3-44717.35" + process $proc$libresoc.v:44716$1332 + assign { } { } + assign $0\dmi0__din[63:0] \dmi0__din$next + sync posedge \clk + update \dmi0__din $0\dmi0__din[63:0] + end + attribute \src "libresoc.v:44718.3-44719.45" + process $proc$libresoc.v:44718$1333 + assign { } { } + assign $0\fsm_state$503[2:0]$1334 \fsm_state$503$next + sync posedge \clk + update \fsm_state$503 $0\fsm_state$503[2:0]$1334 + end + attribute \src "libresoc.v:44720.3-44721.41" + process $proc$libresoc.v:44720$1335 + assign { } { } + assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next + sync posedge \clk + update \dmi0__addr_i $0\dmi0__addr_i[3:0] + end + attribute \src "libresoc.v:44722.3-44723.51" + process $proc$libresoc.v:44722$1336 + assign { } { } + assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next + sync posedge \clk + update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:44724.3-44725.45" + process $proc$libresoc.v:44724$1337 + assign { } { } + assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next + sync posedge \clk + update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:44726.3-44727.35" + process $proc$libresoc.v:44726$1338 + assign { } { } + assign $0\fsm_state[2:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[2:0] + end + attribute \src "libresoc.v:44728.3-44729.41" + process $proc$libresoc.v:44728$1339 + assign { } { } + assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next + sync posedge \clk + update \jtag_wb__adr $0\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:44730.3-44731.31" + process $proc$libresoc.v:44730$1340 + assign { } { } + assign $0\sr5_reg[1:0] \sr5_reg$next + sync posedge \posjtag_clk + update \sr5_reg $0\sr5_reg[1:0] + end + attribute \src "libresoc.v:44732.3-44733.31" + process $proc$libresoc.v:44732$1341 + assign { } { } + assign $0\sr5__oe[0:0] \sr5__oe$next + sync posedge \clk + update \sr5__oe $0\sr5__oe[0:0] + end + attribute \src "libresoc.v:44734.3-44735.57" + process $proc$libresoc.v:44734$1342 + assign { } { } + assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next + sync posedge \clk + update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] + end + attribute \src "libresoc.v:44736.3-44737.47" + process $proc$libresoc.v:44736$1343 + assign { } { } + assign $0\sr5_update_core[0:0] \sr5_update_core$next + sync posedge \clk + update \sr5_update_core $0\sr5_update_core[0:0] + end + attribute \src "libresoc.v:44738.3-44739.47" + process $proc$libresoc.v:44738$1344 + assign { } { } + assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next + sync posedge \posjtag_clk + update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:44740.3-44741.47" + process $proc$libresoc.v:44740$1345 + assign { } { } + assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next + sync posedge \clk + update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:44742.3-44743.73" + process $proc$libresoc.v:44742$1346 + assign { } { } + assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next + sync posedge \clk + update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:44744.3-44745.63" + process $proc$libresoc.v:44744$1347 + assign { } { } + assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next + sync posedge \clk + update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:44746.3-44747.47" + process $proc$libresoc.v:44746$1348 + assign { } { } + assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next + sync posedge \posjtag_clk + update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:44748.3-44749.47" + process $proc$libresoc.v:44748$1349 + assign { } { } + assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next + sync posedge \clk + update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:44750.3-44751.73" + process $proc$libresoc.v:44750$1350 + assign { } { } + assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next + sync posedge \clk + update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:44752.3-44753.63" + process $proc$libresoc.v:44752$1351 + assign { } { } + assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next + sync posedge \clk + update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:44754.3-44755.53" + process $proc$libresoc.v:44754$1352 + assign { } { } + assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:44756.3-44757.53" + process $proc$libresoc.v:44756$1353 + assign { } { } + assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next + sync posedge \clk + update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:44758.3-44759.79" + process $proc$libresoc.v:44758$1354 + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next + sync posedge \clk + update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:44760.3-44761.69" + process $proc$libresoc.v:44760$1355 + assign { } { } + assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next + sync posedge \clk + update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:44762.3-44763.53" + process $proc$libresoc.v:44762$1356 + assign { } { } + assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:44764.3-44765.53" + process $proc$libresoc.v:44764$1357 + assign { } { } + assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next + sync posedge \clk + update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:44766.3-44767.79" + process $proc$libresoc.v:44766$1358 + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next + sync posedge \clk + update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:44768.3-44769.69" + process $proc$libresoc.v:44768$1359 + assign { } { } + assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next + sync posedge \clk + update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:44770.3-44771.31" + process $proc$libresoc.v:44770$1360 + assign { } { } + assign $0\sr0_reg[2:0] \sr0_reg$next + sync posedge \posjtag_clk + update \sr0_reg $0\sr0_reg[2:0] + end + attribute \src "libresoc.v:44772.3-44773.31" + process $proc$libresoc.v:44772$1361 + assign { } { } + assign $0\sr0__oe[0:0] \sr0__oe$next + sync posedge \clk + update \sr0__oe $0\sr0__oe[0:0] + end + attribute \src "libresoc.v:44774.3-44775.57" + process $proc$libresoc.v:44774$1362 + assign { } { } + assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next + sync posedge \clk + update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:44776.3-44777.47" + process $proc$libresoc.v:44776$1363 + assign { } { } + assign $0\sr0_update_core[0:0] \sr0_update_core$next + sync posedge \clk + update \sr0_update_core $0\sr0_update_core[0:0] + end + attribute \src "libresoc.v:44778.3-44779.27" + process $proc$libresoc.v:44778$1364 + assign { } { } + assign $0\io_bd[153:0] \io_bd$next + sync negedge \negjtag_clk + update \io_bd $0\io_bd[153:0] + end + attribute \src "libresoc.v:44780.3-44781.27" + process $proc$libresoc.v:44780$1365 + assign { } { } + assign $0\io_sr[153:0] \io_sr$next + sync posedge \posjtag_clk + update \io_sr $0\io_sr[153:0] + end + attribute \src "libresoc.v:44817.3-44832.6" + process $proc$libresoc.v:44817$1366 + assign { } { } + assign { } { } + assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] + attribute \src "libresoc.v:44818.5-44818.29" + switch \initial + attribute \src "libresoc.v:44818.9-44818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" + switch { \$369 \_idblock_select_id \_fsm_isir } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\TAP_tdo[0:0] \_irblock_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\TAP_tdo[0:0] \io_sr [153] + case + assign $1\TAP_tdo[0:0] 1'0 + end + sync always + update \TAP_tdo $0\TAP_tdo[0:0] + end + attribute \src "libresoc.v:44833.3-44841.6" + process $proc$libresoc.v:44833$1367 + assign { } { } + assign { } { } + assign $0\sr0_update_core$next[0:0]$1368 $1\sr0_update_core$next[0:0]$1369 + attribute \src "libresoc.v:44834.5-44834.29" + switch \initial + attribute \src "libresoc.v:44834.9-44834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core$next[0:0]$1369 1'0 + case + assign $1\sr0_update_core$next[0:0]$1369 \sr0_update + end + sync always + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$1368 + end + attribute \src "libresoc.v:44842.3-44850.6" + process $proc$libresoc.v:44842$1370 + assign { } { } + assign { } { } + assign $0\sr0_update_core_prev$next[0:0]$1371 $1\sr0_update_core_prev$next[0:0]$1372 + attribute \src "libresoc.v:44843.5-44843.29" + switch \initial + attribute \src "libresoc.v:44843.9-44843.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core_prev$next[0:0]$1372 1'0 + case + assign $1\sr0_update_core_prev$next[0:0]$1372 \sr0_update_core + end + sync always + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$1371 + end + attribute \src "libresoc.v:44851.3-44867.6" + process $proc$libresoc.v:44851$1373 + assign { } { } + assign { } { } + assign $0\sr0__oe$next[0:0]$1374 $2\sr0__oe$next[0:0]$1376 + attribute \src "libresoc.v:44852.5-44852.29" + switch \initial + attribute \src "libresoc.v:44852.9-44852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$387 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0__oe$next[0:0]$1375 \sr0_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr0__oe$next[0:0]$1375 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0__oe$next[0:0]$1376 1'0 + case + assign $2\sr0__oe$next[0:0]$1376 $1\sr0__oe$next[0:0]$1375 + end + sync always + update \sr0__oe$next $0\sr0__oe$next[0:0]$1374 + end + attribute \src "libresoc.v:44868.3-44888.6" + process $proc$libresoc.v:44868$1377 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr0_reg$next[2:0]$1378 $3\sr0_reg$next[2:0]$1381 + attribute \src "libresoc.v:44869.5-44869.29" + switch \initial + attribute \src "libresoc.v:44869.9-44869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr0_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_reg$next[2:0]$1379 { \TAP_bus__tdi \sr0_reg [2:1] } + case + assign $1\sr0_reg$next[2:0]$1379 \sr0_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr0_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0_reg$next[2:0]$1380 \sr0__i + case + assign $2\sr0_reg$next[2:0]$1380 $1\sr0_reg$next[2:0]$1379 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr0_reg$next[2:0]$1381 3'000 + case + assign $3\sr0_reg$next[2:0]$1381 $2\sr0_reg$next[2:0]$1380 + end + sync always + update \sr0_reg$next $0\sr0_reg$next[2:0]$1378 + end + attribute \src "libresoc.v:44889.3-44897.6" + process $proc$libresoc.v:44889$1382 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core$next[0:0]$1383 $1\jtag_wb_addrsr_update_core$next[0:0]$1384 + attribute \src "libresoc.v:44890.5-44890.29" + switch \initial + attribute \src "libresoc.v:44890.9-44890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core$next[0:0]$1384 1'0 + case + assign $1\jtag_wb_addrsr_update_core$next[0:0]$1384 \jtag_wb_addrsr_update + end + sync always + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$1383 + end + attribute \src "libresoc.v:44898.3-44906.6" + process $proc$libresoc.v:44898$1385 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 + attribute \src "libresoc.v:44899.5-44899.29" + switch \initial + attribute \src "libresoc.v:44899.9-44899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 1'0 + case + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 \jtag_wb_addrsr_update_core + end + sync always + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386 + end + attribute \src "libresoc.v:44907.3-44923.6" + process $proc$libresoc.v:44907$1388 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr__oe$next[0:0]$1389 $2\jtag_wb_addrsr__oe$next[0:0]$1391 + attribute \src "libresoc.v:44908.5-44908.29" + switch \initial + attribute \src "libresoc.v:44908.9-44908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$405 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$1390 \jtag_wb_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$1390 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr__oe$next[0:0]$1391 1'0 + case + assign $2\jtag_wb_addrsr__oe$next[0:0]$1391 $1\jtag_wb_addrsr__oe$next[0:0]$1390 + end + sync always + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$1389 + end + attribute \src "libresoc.v:44924.3-44944.6" + process $proc$libresoc.v:44924$1392 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_reg$next[28:0]$1393 $3\jtag_wb_addrsr_reg$next[28:0]$1396 + attribute \src "libresoc.v:44925.5-44925.29" + switch \initial + attribute \src "libresoc.v:44925.9-44925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_reg$next[28:0]$1394 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + case + assign $1\jtag_wb_addrsr_reg$next[28:0]$1394 \jtag_wb_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr_reg$next[28:0]$1395 \jtag_wb_addrsr__i + case + assign $2\jtag_wb_addrsr_reg$next[28:0]$1395 $1\jtag_wb_addrsr_reg$next[28:0]$1394 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_addrsr_reg$next[28:0]$1396 29'00000000000000000000000000000 + case + assign $3\jtag_wb_addrsr_reg$next[28:0]$1396 $2\jtag_wb_addrsr_reg$next[28:0]$1395 + end + sync always + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$1393 + end + attribute \src "libresoc.v:44945.3-44953.6" + process $proc$libresoc.v:44945$1397 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core$next[0:0]$1398 $1\jtag_wb_datasr_update_core$next[0:0]$1399 + attribute \src "libresoc.v:44946.5-44946.29" + switch \initial + attribute \src "libresoc.v:44946.9-44946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core$next[0:0]$1399 1'0 + case + assign $1\jtag_wb_datasr_update_core$next[0:0]$1399 \jtag_wb_datasr_update + end + sync always + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$1398 + end + attribute \src "libresoc.v:44954.3-44962.6" + process $proc$libresoc.v:44954$1400 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401 $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 + attribute \src "libresoc.v:44955.5-44955.29" + switch \initial + attribute \src "libresoc.v:44955.9-44955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 1'0 + case + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 \jtag_wb_datasr_update_core + end + sync always + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401 + end + attribute \src "libresoc.v:44963.3-44979.6" + process $proc$libresoc.v:44963$1403 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__oe$next[1:0]$1404 $2\jtag_wb_datasr__oe$next[1:0]$1406 + attribute \src "libresoc.v:44964.5-44964.29" + switch \initial + attribute \src "libresoc.v:44964.9-44964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$425 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$1405 \jtag_wb_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$1405 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__oe$next[1:0]$1406 2'00 + case + assign $2\jtag_wb_datasr__oe$next[1:0]$1406 $1\jtag_wb_datasr__oe$next[1:0]$1405 + end + sync always + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$1404 + end + attribute \src "libresoc.v:44980.3-45000.6" + process $proc$libresoc.v:44980$1407 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_reg$next[63:0]$1408 $3\jtag_wb_datasr_reg$next[63:0]$1411 + attribute \src "libresoc.v:44981.5-44981.29" + switch \initial + attribute \src "libresoc.v:44981.9-44981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_reg$next[63:0]$1409 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + case + assign $1\jtag_wb_datasr_reg$next[63:0]$1409 \jtag_wb_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr_reg$next[63:0]$1410 \jtag_wb_datasr__i + case + assign $2\jtag_wb_datasr_reg$next[63:0]$1410 $1\jtag_wb_datasr_reg$next[63:0]$1409 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr_reg$next[63:0]$1411 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr_reg$next[63:0]$1411 $2\jtag_wb_datasr_reg$next[63:0]$1410 + end + sync always + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$1408 + end + attribute \src "libresoc.v:45001.3-45009.6" + process $proc$libresoc.v:45001$1412 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core$next[0:0]$1413 $1\dmi0_addrsr_update_core$next[0:0]$1414 + attribute \src "libresoc.v:45002.5-45002.29" + switch \initial + attribute \src "libresoc.v:45002.9-45002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core$next[0:0]$1414 1'0 + case + assign $1\dmi0_addrsr_update_core$next[0:0]$1414 \dmi0_addrsr_update + end + sync always + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$1413 + end + attribute \src "libresoc.v:45010.3-45018.6" + process $proc$libresoc.v:45010$1415 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$1416 $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 + attribute \src "libresoc.v:45011.5-45011.29" + switch \initial + attribute \src "libresoc.v:45011.9-45011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 1'0 + case + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 \dmi0_addrsr_update_core + end + sync always + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$1416 + end + attribute \src "libresoc.v:45019.3-45035.6" + process $proc$libresoc.v:45019$1418 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr__oe$next[0:0]$1419 $2\dmi0_addrsr__oe$next[0:0]$1421 + attribute \src "libresoc.v:45020.5-45020.29" + switch \initial + attribute \src "libresoc.v:45020.9-45020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$443 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$1420 \dmi0_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$1420 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr__oe$next[0:0]$1421 1'0 + case + assign $2\dmi0_addrsr__oe$next[0:0]$1421 $1\dmi0_addrsr__oe$next[0:0]$1420 + end + sync always + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$1419 + end + attribute \src "libresoc.v:45036.3-45056.6" + process $proc$libresoc.v:45036$1422 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_reg$next[7:0]$1423 $3\dmi0_addrsr_reg$next[7:0]$1426 + attribute \src "libresoc.v:45037.5-45037.29" + switch \initial + attribute \src "libresoc.v:45037.9-45037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_reg$next[7:0]$1424 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + case + assign $1\dmi0_addrsr_reg$next[7:0]$1424 \dmi0_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr_reg$next[7:0]$1425 \dmi0_addrsr__i + case + assign $2\dmi0_addrsr_reg$next[7:0]$1425 $1\dmi0_addrsr_reg$next[7:0]$1424 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_addrsr_reg$next[7:0]$1426 8'00000000 + case + assign $3\dmi0_addrsr_reg$next[7:0]$1426 $2\dmi0_addrsr_reg$next[7:0]$1425 + end + sync always + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$1423 + end + attribute \src "libresoc.v:45057.3-45065.6" + process $proc$libresoc.v:45057$1427 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core$next[0:0]$1428 $1\dmi0_datasr_update_core$next[0:0]$1429 + attribute \src "libresoc.v:45058.5-45058.29" + switch \initial + attribute \src "libresoc.v:45058.9-45058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core$next[0:0]$1429 1'0 + case + assign $1\dmi0_datasr_update_core$next[0:0]$1429 \dmi0_datasr_update + end + sync always + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$1428 + end + attribute \src "libresoc.v:45066.3-45074.6" + process $proc$libresoc.v:45066$1430 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core_prev$next[0:0]$1431 $1\dmi0_datasr_update_core_prev$next[0:0]$1432 + attribute \src "libresoc.v:45067.5-45067.29" + switch \initial + attribute \src "libresoc.v:45067.9-45067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core_prev$next[0:0]$1432 1'0 + case + assign $1\dmi0_datasr_update_core_prev$next[0:0]$1432 \dmi0_datasr_update_core + end + sync always + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$1431 + end + attribute \src "libresoc.v:45075.3-45091.6" + process $proc$libresoc.v:45075$1433 + assign { } { } + assign { } { } + assign $0\dmi0_datasr__oe$next[1:0]$1434 $2\dmi0_datasr__oe$next[1:0]$1436 + attribute \src "libresoc.v:45076.5-45076.29" + switch \initial + attribute \src "libresoc.v:45076.9-45076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$463 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$1435 \dmi0_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$1435 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__oe$next[1:0]$1436 2'00 + case + assign $2\dmi0_datasr__oe$next[1:0]$1436 $1\dmi0_datasr__oe$next[1:0]$1435 + end + sync always + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$1434 + end + attribute \src "libresoc.v:45092.3-45112.6" + process $proc$libresoc.v:45092$1437 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr_reg$next[63:0]$1438 $3\dmi0_datasr_reg$next[63:0]$1441 + attribute \src "libresoc.v:45093.5-45093.29" + switch \initial + attribute \src "libresoc.v:45093.9-45093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_reg$next[63:0]$1439 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + case + assign $1\dmi0_datasr_reg$next[63:0]$1439 \dmi0_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr_reg$next[63:0]$1440 \dmi0_datasr__i + case + assign $2\dmi0_datasr_reg$next[63:0]$1440 $1\dmi0_datasr_reg$next[63:0]$1439 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr_reg$next[63:0]$1441 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr_reg$next[63:0]$1441 $2\dmi0_datasr_reg$next[63:0]$1440 + end + sync always + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$1438 + end + attribute \src "libresoc.v:45113.3-45121.6" + process $proc$libresoc.v:45113$1442 + assign { } { } + assign { } { } + assign $0\sr5_update_core$next[0:0]$1443 $1\sr5_update_core$next[0:0]$1444 + attribute \src "libresoc.v:45114.5-45114.29" + switch \initial + attribute \src "libresoc.v:45114.9-45114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_update_core$next[0:0]$1444 1'0 + case + assign $1\sr5_update_core$next[0:0]$1444 \sr5_update + end + sync always + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$1443 + end + attribute \src "libresoc.v:45122.3-45130.6" + process $proc$libresoc.v:45122$1445 + assign { } { } + assign { } { } + assign $0\sr5_update_core_prev$next[0:0]$1446 $1\sr5_update_core_prev$next[0:0]$1447 + attribute \src "libresoc.v:45123.5-45123.29" + switch \initial + attribute \src "libresoc.v:45123.9-45123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_update_core_prev$next[0:0]$1447 1'0 + case + assign $1\sr5_update_core_prev$next[0:0]$1447 \sr5_update_core + end + sync always + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$1446 + end + attribute \src "libresoc.v:45131.3-45147.6" + process $proc$libresoc.v:45131$1448 + assign { } { } + assign { } { } + assign $0\sr5__oe$next[0:0]$1449 $2\sr5__oe$next[0:0]$1451 + attribute \src "libresoc.v:45132.5-45132.29" + switch \initial + attribute \src "libresoc.v:45132.9-45132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$481 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5__oe$next[0:0]$1450 \sr5_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr5__oe$next[0:0]$1450 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5__oe$next[0:0]$1451 1'0 + case + assign $2\sr5__oe$next[0:0]$1451 $1\sr5__oe$next[0:0]$1450 + end + sync always + update \sr5__oe$next $0\sr5__oe$next[0:0]$1449 + end + attribute \src "libresoc.v:45148.3-45168.6" + process $proc$libresoc.v:45148$1452 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr5_reg$next[1:0]$1453 $3\sr5_reg$next[1:0]$1456 + attribute \src "libresoc.v:45149.5-45149.29" + switch \initial + attribute \src "libresoc.v:45149.9-45149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr5_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_reg$next[1:0]$1454 { \TAP_bus__tdi \sr5_reg [1] } + case + assign $1\sr5_reg$next[1:0]$1454 \sr5_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr5_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5_reg$next[1:0]$1455 \sr5__i + case + assign $2\sr5_reg$next[1:0]$1455 $1\sr5_reg$next[1:0]$1454 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr5_reg$next[1:0]$1456 2'00 + case + assign $3\sr5_reg$next[1:0]$1456 $2\sr5_reg$next[1:0]$1455 + end + sync always + update \sr5_reg$next $0\sr5_reg$next[1:0]$1453 + end + attribute \src "libresoc.v:45169.3-45195.6" + process $proc$libresoc.v:45169$1457 + assign { } { } + assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:45170.5-45170.29" + switch \initial + attribute \src "libresoc.v:45170.9-45170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" + switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } + attribute \src "libresoc.v:0.0-0.0" + case 6'-----1 + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'----1- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'---1-- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'--1--- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'-1---- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'1----- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr5_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\TAP_bus__tdo[0:0] \TAP_tdo + end + sync always + update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] + end + attribute \src "libresoc.v:45196.3-45228.6" + process $proc$libresoc.v:45196$1458 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__adr$next[28:0]$1459 $4\jtag_wb__adr$next[28:0]$1463 + attribute \src "libresoc.v:45197.5-45197.29" + switch \initial + attribute \src "libresoc.v:45197.9-45197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$1460 $2\jtag_wb__adr$next[28:0]$1461 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$1461 \jtag_wb_addrsr__o + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$1461 \$495 [28:0] + case + assign $2\jtag_wb__adr$next[28:0]$1461 \jtag_wb__adr + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$1460 $3\jtag_wb__adr$next[28:0]$1462 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__adr$next[28:0]$1462 \$498 [28:0] + case + assign $3\jtag_wb__adr$next[28:0]$1462 \jtag_wb__adr + end + case + assign $1\jtag_wb__adr$next[28:0]$1460 \jtag_wb__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\jtag_wb__adr$next[28:0]$1463 29'00000000000000000000000000000 + case + assign $4\jtag_wb__adr$next[28:0]$1463 $1\jtag_wb__adr$next[28:0]$1460 + end + sync always + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$1459 + end + attribute \src "libresoc.v:45229.3-45281.6" + process $proc$libresoc.v:45229$1464 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[2:0]$1465 $5\fsm_state$next[2:0]$1470 + attribute \src "libresoc.v:45230.5-45230.29" + switch \initial + attribute \src "libresoc.v:45230.9-45230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$next[2:0]$1466 $2\fsm_state$next[2:0]$1467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$next[2:0]$1467 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$next[2:0]$1467 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$next[2:0]$1467 3'010 + case + assign $2\fsm_state$next[2:0]$1467 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$next[2:0]$1466 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$next[2:0]$1466 $3\fsm_state$next[2:0]$1468 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[2:0]$1468 3'000 + case + assign $3\fsm_state$next[2:0]$1468 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$next[2:0]$1466 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$next[2:0]$1466 $4\fsm_state$next[2:0]$1469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[2:0]$1469 3'001 + case + assign $4\fsm_state$next[2:0]$1469 \fsm_state + end + case + assign $1\fsm_state$next[2:0]$1466 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[2:0]$1470 3'000 + case + assign $5\fsm_state$next[2:0]$1470 $1\fsm_state$next[2:0]$1466 + end + sync always + update \fsm_state$next $0\fsm_state$next[2:0]$1465 + end + attribute \src "libresoc.v:45282.3-45308.6" + process $proc$libresoc.v:45282$1471 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__dat_w$next[63:0]$1472 $3\jtag_wb__dat_w$next[63:0]$1475 + attribute \src "libresoc.v:45283.5-45283.29" + switch \initial + attribute \src "libresoc.v:45283.9-45283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__dat_w$next[63:0]$1473 $2\jtag_wb__dat_w$next[63:0]$1474 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb_datasr__o + case + assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w + end + case + assign $1\jtag_wb__dat_w$next[63:0]$1473 \jtag_wb__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__dat_w$next[63:0]$1475 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb__dat_w$next[63:0]$1475 $1\jtag_wb__dat_w$next[63:0]$1473 + end + sync always + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$1472 + end + attribute \src "libresoc.v:45309.3-45329.6" + process $proc$libresoc.v:45309$1476 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__i$next[63:0]$1477 $3\jtag_wb_datasr__i$next[63:0]$1480 + attribute \src "libresoc.v:45310.5-45310.29" + switch \initial + attribute \src "libresoc.v:45310.9-45310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\jtag_wb_datasr__i$next[63:0]$1478 $2\jtag_wb_datasr__i$next[63:0]$1479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__i$next[63:0]$1479 \jtag_wb__dat_r + case + assign $2\jtag_wb_datasr__i$next[63:0]$1479 \jtag_wb_datasr__i + end + case + assign $1\jtag_wb_datasr__i$next[63:0]$1478 \jtag_wb_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr__i$next[63:0]$1480 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr__i$next[63:0]$1480 $1\jtag_wb_datasr__i$next[63:0]$1478 + end + sync always + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$1477 + end + attribute \src "libresoc.v:45330.3-45362.6" + process $proc$libresoc.v:45330$1481 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__addr_i$next[3:0]$1482 $4\dmi0__addr_i$next[3:0]$1486 + attribute \src "libresoc.v:45331.5-45331.29" + switch \initial + attribute \src "libresoc.v:45331.9-45331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$1483 $2\dmi0__addr_i$next[3:0]$1484 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$1484 \dmi0_addrsr__o [3:0] + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$1484 \$512 [3:0] + case + assign $2\dmi0__addr_i$next[3:0]$1484 \dmi0__addr_i + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$1483 $3\dmi0__addr_i$next[3:0]$1485 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__addr_i$next[3:0]$1485 \$515 [3:0] + case + assign $3\dmi0__addr_i$next[3:0]$1485 \dmi0__addr_i + end + case + assign $1\dmi0__addr_i$next[3:0]$1483 \dmi0__addr_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dmi0__addr_i$next[3:0]$1486 4'0000 + case + assign $4\dmi0__addr_i$next[3:0]$1486 $1\dmi0__addr_i$next[3:0]$1483 + end + sync always + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$1482 + end + attribute \src "libresoc.v:45363.3-45415.6" + process $proc$libresoc.v:45363$1487 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$503$next[2:0]$1488 $5\fsm_state$503$next[2:0]$1493 + attribute \src "libresoc.v:45364.5-45364.29" + switch \initial + attribute \src "libresoc.v:45364.9-45364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$503$next[2:0]$1489 $2\fsm_state$503$next[2:0]$1490 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$503$next[2:0]$1490 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$503$next[2:0]$1490 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$503$next[2:0]$1490 3'010 + case + assign $2\fsm_state$503$next[2:0]$1490 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$503$next[2:0]$1489 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$503$next[2:0]$1489 $3\fsm_state$503$next[2:0]$1491 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$503$next[2:0]$1491 3'000 + case + assign $3\fsm_state$503$next[2:0]$1491 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$503$next[2:0]$1489 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$503$next[2:0]$1489 $4\fsm_state$503$next[2:0]$1492 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$503$next[2:0]$1492 3'001 + case + assign $4\fsm_state$503$next[2:0]$1492 \fsm_state$503 + end + case + assign $1\fsm_state$503$next[2:0]$1489 \fsm_state$503 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$503$next[2:0]$1493 3'000 + case + assign $5\fsm_state$503$next[2:0]$1493 $1\fsm_state$503$next[2:0]$1489 + end + sync always + update \fsm_state$503$next $0\fsm_state$503$next[2:0]$1488 + end + attribute \src "libresoc.v:45416.3-45442.6" + process $proc$libresoc.v:45416$1494 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__din$next[63:0]$1495 $3\dmi0__din$next[63:0]$1498 + attribute \src "libresoc.v:45417.5-45417.29" + switch \initial + attribute \src "libresoc.v:45417.9-45417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__din$next[63:0]$1496 $2\dmi0__din$next[63:0]$1497 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\dmi0__din$next[63:0]$1497 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\dmi0__din$next[63:0]$1497 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\dmi0__din$next[63:0]$1497 \dmi0_datasr__o + case + assign $2\dmi0__din$next[63:0]$1497 \dmi0__din + end + case + assign $1\dmi0__din$next[63:0]$1496 \dmi0__din + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__din$next[63:0]$1498 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0__din$next[63:0]$1498 $1\dmi0__din$next[63:0]$1496 + end + sync always + update \dmi0__din$next $0\dmi0__din$next[63:0]$1495 + end + attribute \src "libresoc.v:45443.3-45463.6" + process $proc$libresoc.v:45443$1499 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr__i$next[63:0]$1500 $3\dmi0_datasr__i$next[63:0]$1503 + attribute \src "libresoc.v:45444.5-45444.29" + switch \initial + attribute \src "libresoc.v:45444.9-45444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\dmi0_datasr__i$next[63:0]$1501 $2\dmi0_datasr__i$next[63:0]$1502 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__i$next[63:0]$1502 \dmi0__dout + case + assign $2\dmi0_datasr__i$next[63:0]$1502 \dmi0_datasr__i + end + case + assign $1\dmi0_datasr__i$next[63:0]$1501 \dmi0_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr__i$next[63:0]$1503 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr__i$next[63:0]$1503 $1\dmi0_datasr__i$next[63:0]$1501 + end + sync always + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$1500 + end + attribute \src "libresoc.v:45464.3-45482.6" + process $proc$libresoc.v:45464$1504 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\wb_dcache_en$next[0:0]$1505 $2\wb_dcache_en$next[0:0]$1509 + assign $0\wb_icache_en$next[0:0]$1506 $2\wb_icache_en$next[0:0]$1510 + attribute \src "libresoc.v:45465.5-45465.29" + switch \initial + attribute \src "libresoc.v:45465.9-45465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:102" + switch \sr5__oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\wb_dcache_en$next[0:0]$1507 $1\wb_icache_en$next[0:0]$1508 } \sr5__o + case + assign $1\wb_dcache_en$next[0:0]$1507 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$1508 \wb_icache_en + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\wb_icache_en$next[0:0]$1510 1'1 + assign $2\wb_dcache_en$next[0:0]$1509 1'1 + case + assign $2\wb_dcache_en$next[0:0]$1509 $1\wb_dcache_en$next[0:0]$1507 + assign $2\wb_icache_en$next[0:0]$1510 $1\wb_icache_en$next[0:0]$1508 + end + sync always + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$1505 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$1506 + end + attribute \src "libresoc.v:45483.3-45492.6" + process $proc$libresoc.v:45483$1511 + assign { } { } + assign { } { } + assign $0\sr5__i[1:0] $1\sr5__i[1:0] + attribute \src "libresoc.v:45484.5-45484.29" + switch \initial + attribute \src "libresoc.v:45484.9-45484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:105" + switch \sr5__ie + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5__i[1:0] { \wb_dcache_en \wb_icache_en } + case + assign $1\sr5__i[1:0] 2'00 + end + sync always + update \sr5__i $0\sr5__i[1:0] + end + attribute \src "libresoc.v:45493.3-45510.6" + process $proc$libresoc.v:45493$1512 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_sr$next[153:0]$1513 $2\io_sr$next[153:0]$1515 + attribute \src "libresoc.v:45494.5-45494.29" + switch \initial + attribute \src "libresoc.v:45494.9-45494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\io_sr$next[153:0]$1514 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\io_sr$next[153:0]$1514 { \io_sr [152:0] \TAP_bus__tdi } + case + assign $1\io_sr$next[153:0]$1514 \io_sr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_sr$next[153:0]$1515 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_sr$next[153:0]$1515 $1\io_sr$next[153:0]$1514 + end + sync always + update \io_sr$next $0\io_sr$next[153:0]$1513 + end + attribute \src "libresoc.v:45511.3-45531.6" + process $proc$libresoc.v:45511$1516 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_bd$next[153:0]$1517 $2\io_bd$next[153:0]$1519 + attribute \src "libresoc.v:45512.5-45512.29" + switch \initial + attribute \src "libresoc.v:45512.9-45512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\io_bd$next[153:0]$1518 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\io_bd$next[153:0]$1518 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\io_bd$next[153:0]$1518 \io_sr + case + assign $1\io_bd$next[153:0]$1518 \io_bd + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \negjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_bd$next[153:0]$1519 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[153:0]$1519 $1\io_bd$next[153:0]$1518 + end + sync always + update \io_bd$next $0\io_bd$next[153:0]$1517 + end + connect \$9 $eq$libresoc.v:44454$1072_Y + connect \$99 $ternary$libresoc.v:44455$1073_Y + connect \$101 $ternary$libresoc.v:44456$1074_Y + connect \$103 $ternary$libresoc.v:44457$1075_Y + connect \$105 $ternary$libresoc.v:44458$1076_Y + connect \$107 $ternary$libresoc.v:44459$1077_Y + connect \$109 $ternary$libresoc.v:44460$1078_Y + connect \$111 $ternary$libresoc.v:44461$1079_Y + connect \$113 $ternary$libresoc.v:44462$1080_Y + connect \$115 $ternary$libresoc.v:44463$1081_Y + connect \$117 $ternary$libresoc.v:44464$1082_Y + connect \$11 $eq$libresoc.v:44465$1083_Y + connect \$119 $ternary$libresoc.v:44466$1084_Y + connect \$121 $ternary$libresoc.v:44467$1085_Y + connect \$123 $ternary$libresoc.v:44468$1086_Y + connect \$125 $ternary$libresoc.v:44469$1087_Y + connect \$127 $ternary$libresoc.v:44470$1088_Y + connect \$129 $ternary$libresoc.v:44471$1089_Y + connect \$131 $ternary$libresoc.v:44472$1090_Y + connect \$133 $ternary$libresoc.v:44473$1091_Y + connect \$135 $ternary$libresoc.v:44474$1092_Y + connect \$137 $ternary$libresoc.v:44475$1093_Y + connect \$13 $eq$libresoc.v:44476$1094_Y + connect \$139 $ternary$libresoc.v:44477$1095_Y + connect \$141 $ternary$libresoc.v:44478$1096_Y + connect \$143 $ternary$libresoc.v:44479$1097_Y + connect \$145 $ternary$libresoc.v:44480$1098_Y + connect \$147 $ternary$libresoc.v:44481$1099_Y + connect \$149 $ternary$libresoc.v:44482$1100_Y + connect \$151 $ternary$libresoc.v:44483$1101_Y + connect \$153 $ternary$libresoc.v:44484$1102_Y + connect \$155 $ternary$libresoc.v:44485$1103_Y + connect \$157 $ternary$libresoc.v:44486$1104_Y + connect \$15 $or$libresoc.v:44487$1105_Y + connect \$159 $ternary$libresoc.v:44488$1106_Y + connect \$161 $ternary$libresoc.v:44489$1107_Y + connect \$163 $ternary$libresoc.v:44490$1108_Y + connect \$165 $ternary$libresoc.v:44491$1109_Y + connect \$167 $ternary$libresoc.v:44492$1110_Y + connect \$169 $ternary$libresoc.v:44493$1111_Y + connect \$171 $ternary$libresoc.v:44494$1112_Y + connect \$173 $ternary$libresoc.v:44495$1113_Y + connect \$175 $ternary$libresoc.v:44496$1114_Y + connect \$177 $ternary$libresoc.v:44497$1115_Y + connect \$17 $and$libresoc.v:44498$1116_Y + connect \$179 $ternary$libresoc.v:44499$1117_Y + connect \$181 $ternary$libresoc.v:44500$1118_Y + connect \$183 $ternary$libresoc.v:44501$1119_Y + connect \$185 $ternary$libresoc.v:44502$1120_Y + connect \$187 $ternary$libresoc.v:44503$1121_Y + connect \$189 $ternary$libresoc.v:44504$1122_Y + connect \$191 $ternary$libresoc.v:44505$1123_Y + connect \$193 $ternary$libresoc.v:44506$1124_Y + connect \$195 $ternary$libresoc.v:44507$1125_Y + connect \$197 $ternary$libresoc.v:44508$1126_Y + connect \$1 $eq$libresoc.v:44509$1127_Y + connect \$19 $eq$libresoc.v:44510$1128_Y + connect \$199 $ternary$libresoc.v:44511$1129_Y + connect \$201 $ternary$libresoc.v:44512$1130_Y + connect \$203 $ternary$libresoc.v:44513$1131_Y + connect \$205 $ternary$libresoc.v:44514$1132_Y + connect \$207 $ternary$libresoc.v:44515$1133_Y + connect \$209 $ternary$libresoc.v:44516$1134_Y + connect \$211 $ternary$libresoc.v:44517$1135_Y + connect \$213 $ternary$libresoc.v:44518$1136_Y + connect \$215 $ternary$libresoc.v:44519$1137_Y + connect \$217 $ternary$libresoc.v:44520$1138_Y + connect \$21 $eq$libresoc.v:44521$1139_Y + connect \$219 $ternary$libresoc.v:44522$1140_Y + connect \$221 $ternary$libresoc.v:44523$1141_Y + connect \$223 $ternary$libresoc.v:44524$1142_Y + connect \$225 $ternary$libresoc.v:44525$1143_Y + connect \$227 $ternary$libresoc.v:44526$1144_Y + connect \$229 $ternary$libresoc.v:44527$1145_Y + connect \$231 $ternary$libresoc.v:44528$1146_Y + connect \$233 $ternary$libresoc.v:44529$1147_Y + connect \$235 $ternary$libresoc.v:44530$1148_Y + connect \$237 $ternary$libresoc.v:44531$1149_Y + connect \$23 $or$libresoc.v:44532$1150_Y + connect \$239 $ternary$libresoc.v:44533$1151_Y + connect \$241 $ternary$libresoc.v:44534$1152_Y + connect \$243 $ternary$libresoc.v:44535$1153_Y + connect \$245 $ternary$libresoc.v:44536$1154_Y + connect \$247 $ternary$libresoc.v:44537$1155_Y + connect \$249 $ternary$libresoc.v:44538$1156_Y + connect \$251 $ternary$libresoc.v:44539$1157_Y + connect \$253 $ternary$libresoc.v:44540$1158_Y + connect \$255 $ternary$libresoc.v:44541$1159_Y + connect \$257 $ternary$libresoc.v:44542$1160_Y + connect \$25 $eq$libresoc.v:44543$1161_Y + connect \$259 $ternary$libresoc.v:44544$1162_Y + connect \$261 $ternary$libresoc.v:44545$1163_Y + connect \$263 $ternary$libresoc.v:44546$1164_Y + connect \$265 $ternary$libresoc.v:44547$1165_Y + connect \$267 $ternary$libresoc.v:44548$1166_Y + connect \$269 $ternary$libresoc.v:44549$1167_Y + connect \$271 $ternary$libresoc.v:44550$1168_Y + connect \$273 $ternary$libresoc.v:44551$1169_Y + connect \$275 $ternary$libresoc.v:44552$1170_Y + connect \$277 $ternary$libresoc.v:44553$1171_Y + connect \$27 $or$libresoc.v:44554$1172_Y + connect \$279 $ternary$libresoc.v:44555$1173_Y + connect \$281 $ternary$libresoc.v:44556$1174_Y + connect \$283 $ternary$libresoc.v:44557$1175_Y + connect \$285 $ternary$libresoc.v:44558$1176_Y + connect \$287 $ternary$libresoc.v:44559$1177_Y + connect \$289 $ternary$libresoc.v:44560$1178_Y + connect \$291 $ternary$libresoc.v:44561$1179_Y + connect \$293 $ternary$libresoc.v:44562$1180_Y + connect \$295 $ternary$libresoc.v:44563$1181_Y + connect \$297 $ternary$libresoc.v:44564$1182_Y + connect \$29 $and$libresoc.v:44565$1183_Y + connect \$299 $ternary$libresoc.v:44566$1184_Y + connect \$301 $ternary$libresoc.v:44567$1185_Y + connect \$303 $ternary$libresoc.v:44568$1186_Y + connect \$305 $ternary$libresoc.v:44569$1187_Y + connect \$307 $ternary$libresoc.v:44570$1188_Y + connect \$309 $ternary$libresoc.v:44571$1189_Y + connect \$311 $ternary$libresoc.v:44572$1190_Y + connect \$313 $ternary$libresoc.v:44573$1191_Y + connect \$315 $ternary$libresoc.v:44574$1192_Y + connect \$317 $ternary$libresoc.v:44575$1193_Y + connect \$31 $and$libresoc.v:44576$1194_Y + connect \$319 $ternary$libresoc.v:44577$1195_Y + connect \$321 $ternary$libresoc.v:44578$1196_Y + connect \$323 $ternary$libresoc.v:44579$1197_Y + connect \$325 $ternary$libresoc.v:44580$1198_Y + connect \$327 $ternary$libresoc.v:44581$1199_Y + connect \$329 $ternary$libresoc.v:44582$1200_Y + connect \$331 $ternary$libresoc.v:44583$1201_Y + connect \$333 $ternary$libresoc.v:44584$1202_Y + connect \$335 $ternary$libresoc.v:44585$1203_Y + connect \$337 $ternary$libresoc.v:44586$1204_Y + connect \$33 $eq$libresoc.v:44587$1205_Y + connect \$339 $ternary$libresoc.v:44588$1206_Y + connect \$341 $ternary$libresoc.v:44589$1207_Y + connect \$343 $ternary$libresoc.v:44590$1208_Y + connect \$345 $ternary$libresoc.v:44591$1209_Y + connect \$347 $ternary$libresoc.v:44592$1210_Y + connect \$349 $ternary$libresoc.v:44593$1211_Y + connect \$351 $ternary$libresoc.v:44594$1212_Y + connect \$353 $ternary$libresoc.v:44595$1213_Y + connect \$355 $ternary$libresoc.v:44596$1214_Y + connect \$357 $ternary$libresoc.v:44597$1215_Y + connect \$35 $eq$libresoc.v:44598$1216_Y + connect \$359 $eq$libresoc.v:44599$1217_Y + connect \$361 $eq$libresoc.v:44600$1218_Y + connect \$363 $or$libresoc.v:44601$1219_Y + connect \$365 $eq$libresoc.v:44602$1220_Y + connect \$367 $or$libresoc.v:44603$1221_Y + connect \$369 $and$libresoc.v:44604$1222_Y + connect \$371 $eq$libresoc.v:44605$1223_Y + connect \$373 $ne$libresoc.v:44606$1224_Y + connect \$375 $and$libresoc.v:44607$1225_Y + connect \$377 $ne$libresoc.v:44608$1226_Y + connect \$37 $or$libresoc.v:44609$1227_Y + connect \$379 $and$libresoc.v:44610$1228_Y + connect \$381 $ne$libresoc.v:44611$1229_Y + connect \$383 $and$libresoc.v:44612$1230_Y + connect \$385 $not$libresoc.v:44613$1231_Y + connect \$387 $and$libresoc.v:44614$1232_Y + connect \$389 $eq$libresoc.v:44615$1233_Y + connect \$391 $ne$libresoc.v:44616$1234_Y + connect \$393 $and$libresoc.v:44617$1235_Y + connect \$395 $ne$libresoc.v:44618$1236_Y + connect \$397 $and$libresoc.v:44619$1237_Y + connect \$3 $eq$libresoc.v:44620$1238_Y + connect \$39 $eq$libresoc.v:44621$1239_Y + connect \$399 $ne$libresoc.v:44622$1240_Y + connect \$401 $and$libresoc.v:44623$1241_Y + connect \$403 $not$libresoc.v:44624$1242_Y + connect \$405 $and$libresoc.v:44625$1243_Y + connect \$407 $eq$libresoc.v:44626$1244_Y + connect \$409 $eq$libresoc.v:44627$1245_Y + connect \$411 $ne$libresoc.v:44628$1246_Y + connect \$413 $and$libresoc.v:44629$1247_Y + connect \$415 $ne$libresoc.v:44630$1248_Y + connect \$417 $and$libresoc.v:44631$1249_Y + connect \$41 $or$libresoc.v:44632$1250_Y + connect \$419 $ne$libresoc.v:44633$1251_Y + connect \$421 $and$libresoc.v:44634$1252_Y + connect \$423 $not$libresoc.v:44635$1253_Y + connect \$425 $and$libresoc.v:44636$1254_Y + connect \$427 $eq$libresoc.v:44637$1255_Y + connect \$429 $ne$libresoc.v:44638$1256_Y + connect \$431 $and$libresoc.v:44639$1257_Y + connect \$433 $ne$libresoc.v:44640$1258_Y + connect \$435 $and$libresoc.v:44641$1259_Y + connect \$437 $ne$libresoc.v:44642$1260_Y + connect \$43 $and$libresoc.v:44643$1261_Y + connect \$439 $and$libresoc.v:44644$1262_Y + connect \$441 $not$libresoc.v:44645$1263_Y + connect \$443 $and$libresoc.v:44646$1264_Y + connect \$445 $eq$libresoc.v:44647$1265_Y + connect \$447 $eq$libresoc.v:44648$1266_Y + connect \$449 $ne$libresoc.v:44649$1267_Y + connect \$451 $and$libresoc.v:44650$1268_Y + connect \$453 $ne$libresoc.v:44651$1269_Y + connect \$455 $and$libresoc.v:44652$1270_Y + connect \$457 $ne$libresoc.v:44653$1271_Y + connect \$45 $and$libresoc.v:44654$1272_Y + connect \$459 $and$libresoc.v:44655$1273_Y + connect \$461 $not$libresoc.v:44656$1274_Y + connect \$463 $and$libresoc.v:44657$1275_Y + connect \$465 $eq$libresoc.v:44658$1276_Y + connect \$467 $ne$libresoc.v:44659$1277_Y + connect \$469 $and$libresoc.v:44660$1278_Y + connect \$471 $ne$libresoc.v:44661$1279_Y + connect \$473 $and$libresoc.v:44662$1280_Y + connect \$475 $ne$libresoc.v:44663$1281_Y + connect \$477 $and$libresoc.v:44664$1282_Y + connect \$47 $eq$libresoc.v:44665$1283_Y + connect \$479 $not$libresoc.v:44666$1284_Y + connect \$481 $and$libresoc.v:44667$1285_Y + connect \$484 $eq$libresoc.v:44668$1286_Y + connect \$483 $not$libresoc.v:44669$1287_Y + connect \$487 $eq$libresoc.v:44670$1288_Y + connect \$489 $eq$libresoc.v:44671$1289_Y + connect \$491 $or$libresoc.v:44672$1290_Y + connect \$493 $eq$libresoc.v:44673$1291_Y + connect \$496 $add$libresoc.v:44674$1292_Y + connect \$49 $eq$libresoc.v:44675$1293_Y + connect \$499 $add$libresoc.v:44676$1294_Y + connect \$501 $pos$libresoc.v:44677$1296_Y + connect \$504 $eq$libresoc.v:44678$1297_Y + connect \$506 $eq$libresoc.v:44679$1298_Y + connect \$508 $or$libresoc.v:44680$1299_Y + connect \$510 $eq$libresoc.v:44681$1300_Y + connect \$513 $add$libresoc.v:44682$1301_Y + connect \$516 $add$libresoc.v:44683$1302_Y + connect \$51 $ternary$libresoc.v:44684$1303_Y + connect \$53 $ternary$libresoc.v:44685$1304_Y + connect \$55 $ternary$libresoc.v:44686$1305_Y + connect \$57 $ternary$libresoc.v:44687$1306_Y + connect \$5 $or$libresoc.v:44688$1307_Y + connect \$59 $ternary$libresoc.v:44689$1308_Y + connect \$61 $ternary$libresoc.v:44690$1309_Y + connect \$63 $ternary$libresoc.v:44691$1310_Y + connect \$65 $ternary$libresoc.v:44692$1311_Y + connect \$67 $ternary$libresoc.v:44693$1312_Y + connect \$69 $ternary$libresoc.v:44694$1313_Y + connect \$71 $ternary$libresoc.v:44695$1314_Y + connect \$73 $ternary$libresoc.v:44696$1315_Y + connect \$75 $ternary$libresoc.v:44697$1316_Y + connect \$77 $ternary$libresoc.v:44698$1317_Y + connect \$7 $and$libresoc.v:44699$1318_Y + connect \$79 $ternary$libresoc.v:44700$1319_Y + connect \$81 $ternary$libresoc.v:44701$1320_Y + connect \$83 $ternary$libresoc.v:44702$1321_Y + connect \$85 $ternary$libresoc.v:44703$1322_Y + connect \$87 $ternary$libresoc.v:44704$1323_Y + connect \$89 $ternary$libresoc.v:44705$1324_Y + connect \$91 $ternary$libresoc.v:44706$1325_Y + connect \$93 $ternary$libresoc.v:44707$1326_Y + connect \$95 $ternary$libresoc.v:44708$1327_Y + connect \$97 $ternary$libresoc.v:44709$1328_Y + connect \$495 \$496 + connect \$498 \$499 + connect \$512 \$513 + connect \$515 \$516 + connect \sr5__ie 1'0 + connect \sr0__i \sr0__o + connect \dmi0__we_i \$510 + connect \dmi0__req_i \$508 + connect \dmi0_addrsr__i \$501 + connect \jtag_wb__we \$493 + connect \jtag_wb__stb \$491 + connect \jtag_wb__cyc \$483 + connect \jtag_wb__sel 1'1 + connect \jtag_wb_addrsr__i \jtag_wb__adr + connect \sr5_update \$477 + connect \sr5_shift \$473 + connect \sr5_capture \$469 + connect \sr5_isir \$465 + connect \sr5__o \sr5_reg + connect \dmi0_datasr_update \$459 + connect \dmi0_datasr_shift \$455 + connect \dmi0_datasr_capture \$451 + connect \dmi0_datasr_isir { \$447 \$445 } + connect \dmi0_datasr__o \dmi0_datasr_reg + connect \dmi0_addrsr_update \$439 + connect \dmi0_addrsr_shift \$435 + connect \dmi0_addrsr_capture \$431 + connect \dmi0_addrsr_isir \$427 + connect \dmi0_addrsr__o \dmi0_addrsr_reg + connect \jtag_wb_datasr_update \$421 + connect \jtag_wb_datasr_shift \$417 + connect \jtag_wb_datasr_capture \$413 + connect \jtag_wb_datasr_isir { \$409 \$407 } + connect \jtag_wb_datasr__o \jtag_wb_datasr_reg + connect \jtag_wb_addrsr_update \$401 + connect \jtag_wb_addrsr_shift \$397 + connect \jtag_wb_addrsr_capture \$393 + connect \jtag_wb_addrsr_isir \$389 + connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg + connect \sr0_update \$383 + connect \sr0_shift \$379 + connect \sr0_capture \$375 + connect \sr0_isir \$371 + connect \sr0__o \sr0_reg + connect \sdr_dq_15__pad__oe \$357 + connect \sdr_dq_15__pad__o \$355 + connect \sdr_dq_15__core__i \$353 + connect \sdr_dq_14__pad__oe \$351 + connect \sdr_dq_14__pad__o \$349 + connect \sdr_dq_14__core__i \$347 + connect \sdr_dq_13__pad__oe \$345 + connect \sdr_dq_13__pad__o \$343 + connect \sdr_dq_13__core__i \$341 + connect \sdr_dq_12__pad__oe \$339 + connect \sdr_dq_12__pad__o \$337 + connect \sdr_dq_12__core__i \$335 + connect \sdr_dq_11__pad__oe \$333 + connect \sdr_dq_11__pad__o \$331 + connect \sdr_dq_11__core__i \$329 + connect \sdr_dq_10__pad__oe \$327 + connect \sdr_dq_10__pad__o \$325 + connect \sdr_dq_10__core__i \$323 + connect \sdr_dq_9__pad__oe \$321 + connect \sdr_dq_9__pad__o \$319 + connect \sdr_dq_9__core__i \$317 + connect \sdr_dq_8__pad__oe \$315 + connect \sdr_dq_8__pad__o \$313 + connect \sdr_dq_8__core__i \$311 + connect \sdr_dm_1__pad__oe \$309 + connect \sdr_dm_1__pad__o \$307 + connect \sdr_dm_1__core__i \$305 + connect \sdr_a_12__pad__o \$303 + connect \sdr_a_11__pad__o \$301 + connect \sdr_a_10__pad__o \$299 + connect \sdr_cs_n__pad__o \$297 + connect \sdr_we_n__pad__o \$295 + connect \sdr_cas_n__pad__o \$293 + connect \sdr_ras_n__pad__o \$291 + connect \sdr_cke__pad__o \$289 + connect \sdr_clock__pad__o \$287 + connect \sdr_ba_1__pad__o \$285 + connect \sdr_ba_0__pad__o \$283 + connect \sdr_a_9__pad__o \$281 + connect \sdr_a_8__pad__o \$279 + connect \sdr_a_7__pad__o \$277 + connect \sdr_a_6__pad__o \$275 + connect \sdr_a_5__pad__o \$273 + connect \sdr_a_4__pad__o \$271 + connect \sdr_a_3__pad__o \$269 + connect \sdr_a_2__pad__o \$267 + connect \sdr_a_1__pad__o \$265 + connect \sdr_a_0__pad__o \$263 + connect \sdr_dq_7__pad__oe \$261 + connect \sdr_dq_7__pad__o \$259 + connect \sdr_dq_7__core__i \$257 + connect \sdr_dq_6__pad__oe \$255 + connect \sdr_dq_6__pad__o \$253 + connect \sdr_dq_6__core__i \$251 + connect \sdr_dq_5__pad__oe \$249 + connect \sdr_dq_5__pad__o \$247 + connect \sdr_dq_5__core__i \$245 + connect \sdr_dq_4__pad__oe \$243 + connect \sdr_dq_4__pad__o \$241 + connect \sdr_dq_4__core__i \$239 + connect \sdr_dq_3__pad__oe \$237 + connect \sdr_dq_3__pad__o \$235 + connect \sdr_dq_3__core__i \$233 + connect \sdr_dq_2__pad__oe \$231 + connect \sdr_dq_2__pad__o \$229 + connect \sdr_dq_2__core__i \$227 + connect \sdr_dq_1__pad__oe \$225 + connect \sdr_dq_1__pad__o \$223 + connect \sdr_dq_1__core__i \$221 + connect \sdr_dq_0__pad__oe \$219 + connect \sdr_dq_0__pad__o \$217 + connect \sdr_dq_0__core__i \$215 + connect \sdr_dm_0__pad__o \$213 + connect \sd0_data3__pad__oe \$211 + connect \sd0_data3__pad__o \$209 + connect \sd0_data3__core__i \$207 + connect \sd0_data2__pad__oe \$205 + connect \sd0_data2__pad__o \$203 + connect \sd0_data2__core__i \$201 + connect \sd0_data1__pad__oe \$199 + connect \sd0_data1__pad__o \$197 + connect \sd0_data1__core__i \$195 + connect \sd0_data0__pad__oe \$193 + connect \sd0_data0__pad__o \$191 + connect \sd0_data0__core__i \$189 + connect \sd0_clk__pad__o \$187 + connect \sd0_cmd__pad__oe \$185 + connect \sd0_cmd__pad__o \$183 + connect \sd0_cmd__core__i \$181 + connect \pwm_1__pad__o \$179 + connect \pwm_0__pad__o \$177 + connect \mtwi_scl__pad__o \$175 + connect \mtwi_sda__pad__oe \$173 + connect \mtwi_sda__pad__o \$171 + connect \mtwi_sda__core__i \$169 + connect \mspi1_miso__core__i \$167 + connect \mspi1_mosi__pad__o \$165 + connect \mspi1_cs_n__pad__o \$163 + connect \mspi1_clk__pad__o \$161 + connect \mspi0_miso__core__i \$159 + connect \mspi0_mosi__pad__o \$157 + connect \mspi0_cs_n__pad__o \$155 + connect \mspi0_clk__pad__o \$153 + connect \gpio_s7__pad__oe \$151 + connect \gpio_s7__pad__o \$149 + connect \gpio_s7__core__i \$147 + connect \gpio_s6__pad__oe \$145 + connect \gpio_s6__pad__o \$143 + connect \gpio_s6__core__i \$141 + connect \gpio_s5__pad__oe \$139 + connect \gpio_s5__pad__o \$137 + connect \gpio_s5__core__i \$135 + connect \gpio_s4__pad__oe \$133 + connect \gpio_s4__pad__o \$131 + connect \gpio_s4__core__i \$129 + connect \gpio_s3__pad__oe \$127 + connect \gpio_s3__pad__o \$125 + connect \gpio_s3__core__i \$123 + connect \gpio_s2__pad__oe \$121 + connect \gpio_s2__pad__o \$119 + connect \gpio_s2__core__i \$117 + connect \gpio_s1__pad__oe \$115 + connect \gpio_s1__pad__o \$113 + connect \gpio_s1__core__i \$111 + connect \gpio_s0__pad__oe \$109 + connect \gpio_s0__pad__o \$107 + connect \gpio_s0__core__i \$105 + connect \gpio_e15__pad__oe \$103 + connect \gpio_e15__pad__o \$101 + connect \gpio_e15__core__i \$99 + connect \gpio_e14__pad__oe \$97 + connect \gpio_e14__pad__o \$95 + connect \gpio_e14__core__i \$93 + connect \gpio_e13__pad__oe \$91 + connect \gpio_e13__pad__o \$89 + connect \gpio_e13__core__i \$87 + connect \gpio_e12__pad__oe \$85 + connect \gpio_e12__pad__o \$83 + connect \gpio_e12__core__i \$81 + connect \gpio_e11__pad__oe \$79 + connect \gpio_e11__pad__o \$77 + connect \gpio_e11__core__i \$75 + connect \gpio_e10__pad__oe \$73 + connect \gpio_e10__pad__o \$71 + connect \gpio_e10__core__i \$69 + connect \gpio_e9__pad__oe \$67 + connect \gpio_e9__pad__o \$65 + connect \gpio_e9__core__i \$63 + connect \gpio_e8__pad__oe \$61 + connect \gpio_e8__pad__o \$59 + connect \gpio_e8__core__i \$57 + connect \eint_2__core__i \$55 + connect \eint_1__core__i \$53 + connect \eint_0__core__i \$51 + connect \io_bd2core \$49 + connect \io_bd2io \$47 + connect \io_update \$45 + connect \io_shift \$31 + connect \io_capture \$17 + connect \_idblock_id_bypass \$9 + connect \_idblock_select_id \$7 +end +attribute \src "ls180.v:4.1-10555.10" +attribute \cells_not_processed 1 +module \ls180 + attribute \src "ls180.v:10043.1-10053.4" + wire width 7 $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 + attribute \src "ls180.v:10043.1-10053.4" + wire width 32 $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 + attribute \src "ls180.v:10043.1-10053.4" + wire width 32 $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 + attribute \src "ls180.v:10043.1-10053.4" + wire width 7 $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 + attribute \src "ls180.v:10043.1-10053.4" + wire width 32 $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 + attribute \src "ls180.v:10043.1-10053.4" + wire width 32 $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 + attribute \src "ls180.v:10043.1-10053.4" + wire width 7 $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 + attribute \src "ls180.v:10043.1-10053.4" + wire width 32 $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 + attribute \src "ls180.v:10043.1-10053.4" + wire width 32 $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 + attribute \src "ls180.v:10043.1-10053.4" + wire width 7 $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 + attribute \src "ls180.v:10043.1-10053.4" + wire width 32 $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 + attribute \src "ls180.v:10043.1-10053.4" + wire width 32 $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 + attribute \src "ls180.v:10063.1-10067.4" + wire width 3 $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 + attribute \src "ls180.v:10063.1-10067.4" + wire width 25 $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 + attribute \src "ls180.v:10063.1-10067.4" + wire width 25 $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 + attribute \src "ls180.v:10077.1-10081.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 + attribute \src "ls180.v:10077.1-10081.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 + attribute \src "ls180.v:10077.1-10081.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 + attribute \src "ls180.v:10091.1-10095.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 + attribute \src "ls180.v:10091.1-10095.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 + attribute \src "ls180.v:10091.1-10095.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 + attribute \src "ls180.v:10105.1-10109.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 + attribute \src "ls180.v:10105.1-10109.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 + attribute \src "ls180.v:10105.1-10109.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 + attribute \src "ls180.v:10120.1-10124.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 + attribute \src "ls180.v:10120.1-10124.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 + attribute \src "ls180.v:10120.1-10124.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 + attribute \src "ls180.v:10137.1-10141.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 + attribute \src "ls180.v:10137.1-10141.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 + attribute \src "ls180.v:10137.1-10141.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 + attribute \src "ls180.v:10153.1-10157.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 + attribute \src "ls180.v:10153.1-10157.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 + attribute \src "ls180.v:10153.1-10157.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 + attribute \src "ls180.v:10167.1-10171.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 + attribute \src "ls180.v:10167.1-10171.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 + attribute \src "ls180.v:10167.1-10171.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 + attribute \src "ls180.v:3222.1-3315.4" + wire width 3 $0\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:3379.1-3472.4" + wire width 3 $0\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:3536.1-3629.4" + wire width 3 $0\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:3693.1-3786.4" + wire width 3 $0\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:6516.1-6532.4" + wire $0\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:6737.1-6753.4" + wire $0\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:6754.1-6770.4" + wire $0\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:6822.1-6829.4" + wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:6830.1-6837.4" + wire $0\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:6838.1-6845.4" + wire $0\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:6846.1-6853.4" + wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:6854.1-6861.4" + wire $0\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:6862.1-6869.4" + wire $0\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:6870.1-6877.4" + wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:6878.1-6885.4" + wire $0\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:6533.1-6549.4" + wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:6886.1-6893.4" + wire $0\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:6894.1-6901.4" + wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:6902.1-6909.4" + wire $0\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:6910.1-6917.4" + wire $0\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:6918.1-6937.4" + wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:6938.1-6957.4" + wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] + attribute \src "ls180.v:6958.1-6977.4" + wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] + attribute \src "ls180.v:6978.1-6997.4" + wire $0\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:6998.1-7017.4" + wire $0\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:7018.1-7037.4" + wire $0\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:6550.1-6566.4" + wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:7038.1-7057.4" + wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:7058.1-7077.4" + wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:6567.1-6583.4" + wire $0\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:6584.1-6600.4" + wire $0\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:6601.1-6617.4" + wire $0\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:6669.1-6685.4" + wire $0\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:6686.1-6702.4" + wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:6703.1-6719.4" + wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:6720.1-6736.4" + wire $0\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:6618.1-6634.4" + wire $0\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:6635.1-6651.4" + wire $0\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:6652.1-6668.4" + wire $0\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:6771.1-6787.4" + wire $0\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:6788.1-6804.4" + wire $0\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:6805.1-6821.4" + wire $0\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:2786.1-2832.4" + wire $0\builder_converter0_next_state[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_converter0_state[0:0] + attribute \src "ls180.v:2846.1-2892.4" + wire $0\builder_converter1_next_state[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_converter1_state[0:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\builder_converter2_next_state[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_converter2_state[0:0] + attribute \src "ls180.v:4039.1-4085.4" + wire $0\builder_converter_next_state[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_converter_state[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 20 $0\builder_count[19:0] + attribute \src "ls180.v:5756.1-5767.4" + wire $0\builder_error[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\builder_grant[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 14 $0\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:5645.1-5681.4" + wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:5645.1-5681.4" + wire $0\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:5645.1-5681.4" + wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:5645.1-5681.4" + wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_libresocsim_we[0:0] + attribute \src "ls180.v:5645.1-5681.4" + wire $0\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:5645.1-5681.4" + wire $0\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:5645.1-5681.4" + wire $0\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:5645.1-5681.4" + wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1877.5-1877.44" + wire $0\builder_libresocsim_wishbone_err[0:0] + attribute \src "ls180.v:1766.5-1766.27" + wire $0\builder_locked0[0:0] + attribute \src "ls180.v:1767.5-1767.27" + wire $0\builder_locked1[0:0] + attribute \src "ls180.v:1768.5-1768.27" + wire $0\builder_locked2[0:0] + attribute \src "ls180.v:1769.5-1769.27" + wire $0\builder_locked3[0:0] + attribute \src "ls180.v:3911.1-3983.4" + wire width 3 $0\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\builder_multiplexer_state[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:5645.1-5681.4" + wire width 2 $0\builder_next_state[1:0] + attribute \src "ls180.v:3128.1-3158.4" + wire width 2 $0\builder_refresher_next_state[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\builder_refresher_state[1:0] + attribute \src "ls180.v:5455.1-5494.4" + wire width 2 $0\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:5022.1-5101.4" + wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire width 3 $0\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:5514.1-5551.4" + wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:5552.1-5588.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:4697.1-4769.4" + wire width 3 $0\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:4542.1-4635.4" + wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:4432.1-4508.4" + wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:4669.1-4696.4" + wire $0\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:4803.1-4904.4" + wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:4398.1-4431.4" + wire $0\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:5756.1-5767.4" + wire $0\builder_shared_ack[0:0] + attribute \src "ls180.v:5756.1-5767.4" + wire width 32 $0\builder_shared_dat_r[31:0] + attribute \src "ls180.v:5706.1-5713.4" + wire width 5 $0\builder_slave_sel[4:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 5 $0\builder_slave_sel_r[4:0] + attribute \src "ls180.v:4229.1-4277.4" + wire width 2 $0\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\builder_spimaster0_state[1:0] + attribute \src "ls180.v:4288.1-4336.4" + wire width 2 $0\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\builder_spimaster1_state[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\builder_state[1:0] + attribute \src "ls180.v:7197.1-7225.4" + wire $0\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:7226.1-7254.4" + wire $0\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:7078.1-7094.4" + wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:7095.1-7111.4" + wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:7112.1-7128.4" + wire $0\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:7129.1-7145.4" + wire $0\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:7146.1-7162.4" + wire $0\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:7163.1-7179.4" + wire $0\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:7180.1-7196.4" + wire $0\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_cmd_consumed[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_converter_counter[0:0] + attribute \src "ls180.v:4039.1-4085.4" + wire $0\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:4039.1-4085.4" + wire $0\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_converter_dat_r[31:0] + attribute \src "ls180.v:4039.1-4085.4" + wire $0\main_converter_skip[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire width 16 $0\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 24 $0\main_dummy[23:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_gpio_oe_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_gpio_oe_storage[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_gpio_out_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_gpio_out_storage[15:0] + attribute \src "ls180.v:7312.1-7330.4" + wire width 16 $0\main_gpio_status[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_i2c_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_i2c_storage[2:0] + attribute \src "ls180.v:7351.1-7353.4" + wire $0\main_int_rst[0:0] + attribute \src "ls180.v:1554.11-1554.41" + wire width 2 $0\main_interface0_bus_bte[1:0] + attribute \src "ls180.v:1553.11-1553.41" + wire width 3 $0\main_interface0_bus_cti[2:0] + attribute \src "ls180.v:5514.1-5551.4" + wire width 32 $0\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1645.11-1645.41" + wire width 2 $0\main_interface1_bus_bte[1:0] + attribute \src "ls180.v:1644.11-1644.41" + wire width 3 $0\main_interface1_bus_cti[2:0] + attribute \src "ls180.v:5514.1-5551.4" + wire $0\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1637.12-1637.45" + wire width 32 $0\main_interface1_bus_dat_w[31:0] + attribute \src "ls180.v:5514.1-5551.4" + wire width 4 $0\main_interface1_bus_sel[3:0] + attribute \src "ls180.v:5514.1-5551.4" + wire $0\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:5514.1-5551.4" + wire $0\main_interface1_bus_we[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:2786.1-2832.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:2786.1-2832.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:2786.1-2832.4" + wire $0\main_libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:2846.1-2892.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:2846.1-2892.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:2846.1-2892.4" + wire $0\main_libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:2786.1-2832.4" + wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:167.11-167.69" + wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] + attribute \src "ls180.v:166.11-166.69" + wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] + attribute \src "ls180.v:2786.1-2832.4" + wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:2774.1-2784.4" + wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2786.1-2832.4" + wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:2786.1-2832.4" + wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:2786.1-2832.4" + wire $0\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:2846.1-2892.4" + wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:182.11-182.69" + wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] + attribute \src "ls180.v:181.11-181.69" + wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] + attribute \src "ls180.v:2846.1-2892.4" + wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:2834.1-2844.4" + wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2846.1-2892.4" + wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:2846.1-2892.4" + wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:2846.1-2892.4" + wire $0\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:2906.1-2952.4" + wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:197.11-197.69" + wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] + attribute \src "ls180.v:196.11-196.69" + wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:2894.1-2904.4" + wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2906.1-2952.4" + wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:2846.1-2892.4" + wire $0\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:74.5-74.46" + wire $0\main_libresocsim_libresoc_dbus_err[0:0] + attribute \src "ls180.v:2786.1-2832.4" + wire $0\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:83.5-83.46" + wire $0\main_libresocsim_libresoc_ibus_err[0:0] + attribute \src "ls180.v:2767.1-2772.4" + wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:2906.1-2952.4" + wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:114.5-114.49" + wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:213.5-213.40" + wire $0\main_libresocsim_ram_bus_err[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_libresocsim_value[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:2955.1-2961.4" + wire width 4 $0\main_libresocsim_we[3:0] + attribute \src "ls180.v:2967.1-2972.4" + wire $0\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:4039.1-4085.4" + wire width 30 $0\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:4039.1-4085.4" + wire $0\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:4027.1-4037.4" + wire width 16 $0\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:4039.1-4085.4" + wire width 2 $0\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:4039.1-4085.4" + wire $0\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:4039.1-4085.4" + wire $0\main_litedram_wb_we[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_pwm0_counter[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_pwm0_period_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_pwm0_width_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_pwm1_counter[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_pwm1_period_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_pwm1_width_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_rddata_en[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\main_sdblock2mem_converter_demux[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 6 $0\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1578.5-1578.41" + wire $0\main_sdblock2mem_fifo_replace[0:0] + attribute \src "ls180.v:5422.1-5429.4" + wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:5455.1-5494.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:5455.1-5494.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "ls180.v:5455.1-5494.4" + wire $0\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:5455.1-5494.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:5455.1-5494.4" + wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:5455.1-5494.4" + wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:5455.1-5494.4" + wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 10 $0\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:5204.1-5394.4" + wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 128 $0\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:5204.1-5394.4" + wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1387.5-1387.34" + wire $0\main_sdcore_cmd_send_w[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:5110.1-5117.4" + wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:5166.1-5173.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:5120.1-5127.4" + wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:5176.1-5183.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:5130.1-5137.4" + wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:5186.1-5193.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:5140.1-5147.4" + wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:5196.1-5203.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:5155.1-5162.4" + wire $0\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1493.5-1493.50" + wire $0\main_sdcore_crc16_checker_source_first[0:0] + attribute \src "ls180.v:5149.1-5154.4" + wire $0\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:5102.1-5107.4" + wire $0\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:5022.1-5101.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:5022.1-5101.4" + wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:4984.1-4991.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:4994.1-5001.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:5004.1-5011.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:5014.1-5021.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:5022.1-5101.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:5022.1-5101.4" + wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:5022.1-5101.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:5022.1-5101.4" + wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:5022.1-5101.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:5022.1-5101.4" + wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:5022.1-5101.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:5022.1-5101.4" + wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:5022.1-5101.4" + wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1450.5-1450.51" + wire $0\main_sdcore_crc16_inserter_source_first[0:0] + attribute \src "ls180.v:5022.1-5101.4" + wire $0\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:5022.1-5101.4" + wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:5022.1-5101.4" + wire $0\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:4962.1-4969.4" + wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdcore_data_count[31:0] + attribute \src "ls180.v:5204.1-5394.4" + wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdcore_data_done[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdcore_data_error[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\main_sdmem2block_converter_mux[1:0] + attribute \src "ls180.v:5600.1-5616.4" + wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdmem2block_dma_data[31:0] + attribute \src "ls180.v:5514.1-5551.4" + wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "ls180.v:5514.1-5551.4" + wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:5552.1-5588.4" + wire $0\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:5552.1-5588.4" + wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:5552.1-5588.4" + wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:5552.1-5588.4" + wire $0\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:5552.1-5588.4" + wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:5514.1-5551.4" + wire $0\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:5552.1-5588.4" + wire $0\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1658.5-1658.45" + wire $0\main_sdmem2block_dma_source_first[0:0] + attribute \src "ls180.v:5514.1-5551.4" + wire $0\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:5514.1-5551.4" + wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] + attribute \src "ls180.v:5514.1-5551.4" + wire $0\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 5 $0\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 6 $0\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 5 $0\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1714.5-1714.41" + wire $0\main_sdmem2block_fifo_replace[0:0] + attribute \src "ls180.v:5630.1-5637.4" + wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:4368.1-4396.4" + wire $0\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 9 $0\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 9 $0\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1179.5-1179.53" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + attribute \src "ls180.v:1180.5-1180.52" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1160.5-1160.46" + wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:4542.1-4635.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:4542.1-4635.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:4542.1-4635.4" + wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:4542.1-4635.4" + wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:4542.1-4635.4" + wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1133.5-1133.49" + wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1134.5-1134.48" + wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1135.5-1135.55" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1137.5-1137.57" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1138.5-1138.58" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1140.11-1140.64" + wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1141.5-1141.59" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4542.1-4635.4" + wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4542.1-4635.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4542.1-4635.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1146.11-1146.57" + wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1147.5-1147.52" + wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:4542.1-4635.4" + wire $0\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:4542.1-4635.4" + wire $0\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:4542.1-4635.4" + wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:4542.1-4635.4" + wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:4542.1-4635.4" + wire $0\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:4542.1-4635.4" + wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:4542.1-4635.4" + wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:4432.1-4508.4" + wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:4432.1-4508.4" + wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:4432.1-4508.4" + wire $0\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:4432.1-4508.4" + wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4432.1-4508.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4432.1-4508.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1123.11-1123.57" + wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1124.5-1124.52" + wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:4432.1-4508.4" + wire $0\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 10 $0\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:4803.1-4904.4" + wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:4803.1-4904.4" + wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1335.5-1335.55" + wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] + attribute \src "ls180.v:1336.5-1336.54" + wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1316.5-1316.48" + wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:4803.1-4904.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:4803.1-4904.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:4803.1-4904.4" + wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1287.5-1287.50" + wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1288.5-1288.49" + wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1289.5-1289.56" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1291.5-1291.58" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1292.5-1292.59" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1294.11-1294.65" + wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1295.5-1295.60" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4803.1-4904.4" + wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1298.5-1298.51" + wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1299.5-1299.52" + wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1300.11-1300.58" + wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1301.5-1301.53" + wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:4803.1-4904.4" + wire $0\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1308.5-1308.41" + wire $0\main_sdphy_datar_source_first[0:0] + attribute \src "ls180.v:4803.1-4904.4" + wire $0\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:4803.1-4904.4" + wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:4803.1-4904.4" + wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:4803.1-4904.4" + wire $0\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:4803.1-4904.4" + wire $0\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:4803.1-4904.4" + wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:4803.1-4904.4" + wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:4697.1-4769.4" + wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:4697.1-4769.4" + wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1257.5-1257.54" + wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + attribute \src "ls180.v:1258.5-1258.53" + wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1238.5-1238.47" + wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:4669.1-4696.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:4669.1-4696.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:4669.1-4696.4" + wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:4669.1-4696.4" + wire $0\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1225.5-1225.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1226.5-1226.49" + wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1227.5-1227.56" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1228.5-1228.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + attribute \src "ls180.v:1229.5-1229.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1230.5-1230.59" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1231.11-1231.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + attribute \src "ls180.v:1232.11-1232.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1233.5-1233.60" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:1223.5-1223.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + attribute \src "ls180.v:4697.1-4769.4" + wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1212.5-1212.51" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1213.5-1213.52" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4697.1-4769.4" + wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4697.1-4769.4" + wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:4697.1-4769.4" + wire $0\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:5204.1-5394.4" + wire $0\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:4697.1-4769.4" + wire $0\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:4697.1-4769.4" + wire $0\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:4669.1-4696.4" + wire $0\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_sdphy_init_count[7:0] + attribute \src "ls180.v:4398.1-4431.4" + wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:4398.1-4431.4" + wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1105.5-1105.40" + wire $0\main_sdphy_init_initialize_w[0:0] + attribute \src "ls180.v:4398.1-4431.4" + wire $0\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4398.1-4431.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4398.1-4431.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4398.1-4431.4" + wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4398.1-4431.4" + wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire width 4 $0\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_address_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 13 $0\main_sdram_address_storage[12:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:3184.1-3191.4" + wire $0\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:445.5-445.64" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:428.5-428.67" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:429.5-429.66" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3206.1-3213.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3173.1-3180.4" + wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:3871.1-3879.4" + wire $0\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 13 $0\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3222.1-3315.4" + wire $0\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:487.32-487.76" + wire $0\main_sdram_bankmachine0_trascon_ready[0:0] + attribute \src "ls180.v:485.32-485.75" + wire $0\main_sdram_bankmachine0_trccon_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:3341.1-3348.4" + wire $0\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:527.5-527.64" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:510.5-510.67" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:511.5-511.66" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3363.1-3370.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3330.1-3337.4" + wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:3880.1-3888.4" + wire $0\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 13 $0\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3379.1-3472.4" + wire $0\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:569.32-569.76" + wire $0\main_sdram_bankmachine1_trascon_ready[0:0] + attribute \src "ls180.v:567.32-567.75" + wire $0\main_sdram_bankmachine1_trccon_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:3498.1-3505.4" + wire $0\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:609.5-609.64" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:592.5-592.67" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:593.5-593.66" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3520.1-3527.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3487.1-3494.4" + wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:3889.1-3897.4" + wire $0\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 13 $0\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3536.1-3629.4" + wire $0\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:651.32-651.76" + wire $0\main_sdram_bankmachine2_trascon_ready[0:0] + attribute \src "ls180.v:649.32-649.75" + wire $0\main_sdram_bankmachine2_trccon_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:3655.1-3662.4" + wire $0\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:691.5-691.64" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:674.5-674.67" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:675.5-675.66" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3677.1-3684.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3644.1-3651.4" + wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:3898.1-3906.4" + wire $0\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 13 $0\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3693.1-3786.4" + wire $0\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:733.32-733.76" + wire $0\main_sdram_bankmachine3_trascon_ready[0:0] + attribute \src "ls180.v:731.32-731.75" + wire $0\main_sdram_bankmachine3_trccon_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:3820.1-3825.4" + wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:3826.1-3831.4" + wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:3832.1-3837.4" + wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:741.5-741.43" + wire $0\main_sdram_choose_cmd_cmd_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:3806.1-3812.4" + wire width 4 $0\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:739.5-739.48" + wire $0\main_sdram_choose_cmd_want_activates[0:0] + attribute \src "ls180.v:738.5-738.43" + wire $0\main_sdram_choose_cmd_want_cmds[0:0] + attribute \src "ls180.v:736.5-736.44" + wire $0\main_sdram_choose_cmd_want_reads[0:0] + attribute \src "ls180.v:737.5-737.45" + wire $0\main_sdram_choose_cmd_want_writes[0:0] + attribute \src "ls180.v:3853.1-3858.4" + wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:3859.1-3864.4" + wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:3865.1-3870.4" + wire $0\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:3911.1-3983.4" + wire $0\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:3839.1-3845.4" + wire width 4 $0\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:3911.1-3983.4" + wire $0\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:3911.1-3983.4" + wire $0\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:3911.1-3983.4" + wire $0\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:3128.1-3158.4" + wire $0\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 13 $0\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:389.5-389.42" + wire $0\main_sdram_cmd_payload_is_read[0:0] + attribute \src "ls180.v:390.5-390.43" + wire $0\main_sdram_cmd_payload_is_write[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:3911.1-3983.4" + wire $0\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:3128.1-3158.4" + wire $0\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:325.5-325.38" + wire $0\main_sdram_command_issue_w[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_command_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 6 $0\main_sdram_command_storage[5:0] + attribute \src "ls180.v:374.5-374.35" + wire $0\main_sdram_dfi_p0_act_n[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 13 $0\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:3911.1-3983.4" + wire $0\main_sdram_en0[0:0] + attribute \src "ls180.v:3911.1-3983.4" + wire $0\main_sdram_en1[0:0] + attribute \src "ls180.v:4007.1-4020.4" + wire width 16 $0\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:4007.1-4020.4" + wire width 2 $0\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:275.5-275.36" + wire $0\main_sdram_inti_p0_act_n[0:0] + attribute \src "ls180.v:3069.1-3085.4" + wire $0\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:3069.1-3085.4" + wire $0\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:3069.1-3085.4" + wire $0\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire width 16 $0\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:3069.1-3085.4" + wire $0\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire width 13 $0\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:3011.1-3065.4" + wire width 2 $0\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire width 16 $0\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:772.12-772.36" + wire width 13 $0\main_sdram_nop_a[12:0] + attribute \src "ls180.v:773.11-773.35" + wire width 2 $0\main_sdram_nop_ba[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:3128.1-3158.4" + wire $0\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:3011.1-3065.4" + wire width 16 $0\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:3011.1-3065.4" + wire $0\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdram_status[15:0] + attribute \src "ls180.v:775.5-775.31" + wire $0\main_sdram_steerer0[0:0] + attribute \src "ls180.v:776.5-776.31" + wire $0\main_sdram_steerer1[0:0] + attribute \src "ls180.v:3911.1-3983.4" + wire width 2 $0\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_sdram_storage[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:780.32-780.63" + wire $0\main_sdram_tfawcon_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 5 $0\main_sdram_time0[4:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_sdram_time1[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 10 $0\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:778.32-778.63" + wire $0\main_sdram_trrdcon_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_spimaster11_storage[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spimaster12_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_spimaster16_storage[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spimaster17_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spimaster1_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_spimaster1_storage[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spimaster21_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spimaster22_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spimaster23_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spimaster24_re[0:0] + attribute \src "ls180.v:4229.1-4277.4" + wire $0\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:4229.1-4277.4" + wire $0\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_spimaster27_count[2:0] + attribute \src "ls180.v:4229.1-4277.4" + wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:4229.1-4277.4" + wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:4229.1-4277.4" + wire $0\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:4229.1-4277.4" + wire $0\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:4229.1-4277.4" + wire $0\main_spimaster2_done[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:4229.1-4277.4" + wire $0\main_spimaster3_irq[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_spimaster5_miso[7:0] + attribute \src "ls180.v:996.12-996.47" + wire width 16 $0\main_spimaster8_clk_divider[15:0] + attribute \src "ls180.v:6281.1-6286.4" + wire $0\main_spimaster9_start[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:4288.1-4336.4" + wire $0\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 16 $0\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_spisdcard_count[2:0] + attribute \src "ls180.v:4288.1-4336.4" + wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:4288.1-4336.4" + wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:4288.1-4336.4" + wire $0\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:4288.1-4336.4" + wire $0\main_spisdcard_done0[0:0] + attribute \src "ls180.v:4288.1-4336.4" + wire $0\main_spisdcard_irq[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_spisdcard_miso[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:4288.1-4336.4" + wire $0\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:4288.1-4336.4" + wire $0\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 3 $0\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:6327.1-6332.4" + wire $0\main_spisdcard_start1[0:0] + attribute \src "ls180.v:4147.1-4151.4" + wire width 2 $0\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:4136.1-4140.4" + wire width 2 $0\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_phy_re[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:851.5-851.38" + wire $0\main_uart_phy_source_first[0:0] + attribute \src "ls180.v:852.5-852.37" + wire $0\main_uart_phy_source_last[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 32 $0\main_uart_phy_storage[31:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 8 $0\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:978.5-978.27" + wire $0\main_uart_reset[0:0] + attribute \src "ls180.v:4141.1-4146.4" + wire $0\main_uart_rx_clear[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 5 $0\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:960.5-960.37" + wire $0\main_uart_rx_fifo_replace[0:0] + attribute \src "ls180.v:4199.1-4206.4" + wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_rx_pending[0:0] + attribute \src "ls180.v:4130.1-4135.4" + wire $0\main_uart_tx_clear[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 5 $0\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 4 $0\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:923.5-923.37" + wire $0\main_uart_tx_fifo_replace[0:0] + attribute \src "ls180.v:906.5-906.40" + wire $0\main_uart_tx_fifo_sink_first[0:0] + attribute \src "ls180.v:907.5-907.39" + wire $0\main_uart_tx_fifo_sink_last[0:0] + attribute \src "ls180.v:4169.1-4176.4" + wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_uart_tx_pending[0:0] + attribute \src "ls180.v:4039.1-4085.4" + wire $0\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:819.5-819.29" + wire $0\main_wb_sdram_err[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\main_wdata_consumed[0:0] + attribute \src "ls180.v:10043.1-10053.4" + wire width 7 $0\memadr[6:0] + attribute \src "ls180.v:10063.1-10067.4" + wire width 25 $0\memdat[24:0] + attribute \src "ls180.v:10077.1-10081.4" + wire width 25 $0\memdat_1[24:0] + attribute \src "ls180.v:10091.1-10095.4" + wire width 25 $0\memdat_2[24:0] + attribute \src "ls180.v:10105.1-10109.4" + wire width 25 $0\memdat_3[24:0] + attribute \src "ls180.v:10120.1-10124.4" + wire width 10 $0\memdat_4[9:0] + attribute \src "ls180.v:10126.1-10129.4" + wire width 10 $0\memdat_5[9:0] + attribute \src "ls180.v:10137.1-10141.4" + wire width 10 $0\memdat_6[9:0] + attribute \src "ls180.v:10143.1-10146.4" + wire width 10 $0\memdat_7[9:0] + attribute \src "ls180.v:10153.1-10157.4" + wire width 10 $0\memdat_8[9:0] + attribute \src "ls180.v:10167.1-10171.4" + wire width 10 $0\memdat_9[9:0] + attribute \src "ls180.v:7427.1-10039.4" + wire width 2 $0\pwm[1:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\sdcard_clk[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\sdcard_cmd_o[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\sdcard_cmd_oe[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire width 4 $0\sdcard_data_o[3:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\sdcard_data_oe[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire width 13 $0\sdram_a[12:0] + attribute \src "ls180.v:7355.1-7425.4" + wire width 2 $0\sdram_ba[1:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\sdram_cas_n[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\sdram_cke[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\sdram_clock[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\sdram_cs_n[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire width 2 $0\sdram_dm[1:0] + attribute \src "ls180.v:7355.1-7425.4" + wire width 16 $0\sdram_dq_o[15:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\sdram_dq_oe[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\sdram_ras_n[0:0] + attribute \src "ls180.v:7355.1-7425.4" + wire $0\sdram_we_n[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\spimaster_clk[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\spimaster_cs_n[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\spimaster_mosi[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\spisdcard_clk[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\spisdcard_cs_n[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\spisdcard_mosi[0:0] + attribute \src "ls180.v:7427.1-10039.4" + wire $0\uart_tx[0:0] + attribute \src "ls180.v:1745.11-1745.49" + wire width 3 $1\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:1744.11-1744.44" + wire width 3 $1\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:1747.11-1747.49" + wire width 3 $1\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:1746.11-1746.44" + wire width 3 $1\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:1749.11-1749.49" + wire width 3 $1\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:1748.11-1748.44" + wire width 3 $1\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:1751.11-1751.49" + wire width 3 $1\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:1750.11-1750.44" + wire width 3 $1\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:2596.5-2596.41" + wire $1\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:2609.5-2609.42" + wire $1\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:2610.5-2610.42" + wire $1\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:2614.12-2614.50" + wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:2615.5-2615.42" + wire $1\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:2616.5-2616.42" + wire $1\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:2617.12-2617.50" + wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:2618.5-2618.42" + wire $1\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:2619.5-2619.42" + wire $1\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:2620.12-2620.50" + wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:2621.5-2621.42" + wire $1\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:2597.12-2597.49" + wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2622.5-2622.42" + wire $1\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:2623.12-2623.50" + wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:2624.5-2624.42" + wire $1\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:2625.5-2625.42" + wire $1\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:2626.12-2626.50" + wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:2627.12-2627.50" + wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] + attribute \src "ls180.v:2628.11-2628.48" + wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] + attribute \src "ls180.v:2629.5-2629.42" + wire $1\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:2630.5-2630.42" + wire $1\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:2631.5-2631.42" + wire $1\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:2598.11-2598.47" + wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:2632.11-2632.48" + wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:2633.11-2633.48" + wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:2599.5-2599.41" + wire $1\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2600.5-2600.41" + wire $1\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2601.5-2601.41" + wire $1\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2605.5-2605.41" + wire $1\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:2606.12-2606.49" + wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:2607.11-2607.47" + wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:2608.5-2608.41" + wire $1\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:2602.5-2602.39" + wire $1\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:2603.5-2603.39" + wire $1\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:2604.5-2604.39" + wire $1\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:2611.5-2611.39" + wire $1\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:2612.5-2612.39" + wire $1\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:2613.5-2613.39" + wire $1\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:1731.5-1731.41" + wire $1\builder_converter0_next_state[0:0] + attribute \src "ls180.v:1730.5-1730.36" + wire $1\builder_converter0_state[0:0] + attribute \src "ls180.v:1735.5-1735.41" + wire $1\builder_converter1_next_state[0:0] + attribute \src "ls180.v:1734.5-1734.36" + wire $1\builder_converter1_state[0:0] + attribute \src "ls180.v:1739.5-1739.41" + wire $1\builder_converter2_next_state[0:0] + attribute \src "ls180.v:1738.5-1738.36" + wire $1\builder_converter2_state[0:0] + attribute \src "ls180.v:1776.5-1776.40" + wire $1\builder_converter_next_state[0:0] + attribute \src "ls180.v:1775.5-1775.35" + wire $1\builder_converter_state[0:0] + attribute \src "ls180.v:1896.12-1896.39" + wire width 20 $1\builder_count[19:0] + attribute \src "ls180.v:1893.5-1893.25" + wire $1\builder_error[0:0] + attribute \src "ls180.v:1890.11-1890.31" + wire width 3 $1\builder_grant[2:0] + attribute \src "ls180.v:1900.11-1900.51" + wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2402.11-2402.52" + wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2435.11-2435.52" + wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2476.11-2476.52" + wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2541.11-2541.52" + wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2566.11-2566.52" + wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1941.11-1941.51" + wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1970.11-1970.51" + wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1983.11-1983.51" + wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2024.11-2024.51" + wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2065.11-2065.51" + wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2130.11-2130.51" + wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2263.11-2263.51" + wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2344.11-2344.51" + wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2361.11-2361.51" + wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1863.12-1863.43" + wire width 14 $1\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:2592.12-2592.55" + wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:2593.5-2593.50" + wire $1\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:1865.11-1865.43" + wire width 8 $1\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:2590.11-2590.55" + wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:2591.5-2591.52" + wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:1864.5-1864.34" + wire $1\builder_libresocsim_we[0:0] + attribute \src "ls180.v:2594.5-2594.46" + wire $1\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:2595.5-2595.49" + wire $1\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:1873.5-1873.44" + wire $1\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1869.12-1869.54" + wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1753.11-1753.48" + wire width 3 $1\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:1752.11-1752.43" + wire width 3 $1\builder_multiplexer_state[2:0] + attribute \src "ls180.v:2699.32-2699.66" + wire $1\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:2700.32-2700.66" + wire $1\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:2719.32-2719.67" + wire $1\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:2720.32-2720.67" + wire $1\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:2721.32-2721.67" + wire $1\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:2722.32-2722.67" + wire $1\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:2723.32-2723.67" + wire $1\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:2724.32-2724.67" + wire $1\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:2725.32-2725.67" + wire $1\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:2726.32-2726.67" + wire $1\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:2727.32-2727.67" + wire $1\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:2728.32-2728.67" + wire $1\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:2729.32-2729.67" + wire $1\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:2730.32-2730.67" + wire $1\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:2731.32-2731.67" + wire $1\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:2732.32-2732.67" + wire $1\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:2701.32-2701.66" + wire $1\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:2702.32-2702.66" + wire $1\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:2703.32-2703.66" + wire $1\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:2704.32-2704.66" + wire $1\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:2705.32-2705.66" + wire $1\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:2706.32-2706.66" + wire $1\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:2707.32-2707.66" + wire $1\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:2708.32-2708.66" + wire $1\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:2709.32-2709.66" + wire $1\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:2710.32-2710.66" + wire $1\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:2711.32-2711.66" + wire $1\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:2712.32-2712.66" + wire $1\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:2713.32-2713.66" + wire $1\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:2714.32-2714.66" + wire $1\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:2715.32-2715.66" + wire $1\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:2716.32-2716.66" + wire $1\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:2717.32-2717.66" + wire $1\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:2718.32-2718.66" + wire $1\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:1771.5-1771.43" + wire $1\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:1772.5-1772.43" + wire $1\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:1773.5-1773.43" + wire $1\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:1774.5-1774.43" + wire $1\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:1770.5-1770.42" + wire $1\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:2589.11-2589.36" + wire width 2 $1\builder_next_state[1:0] + attribute \src "ls180.v:1743.11-1743.46" + wire width 2 $1\builder_refresher_next_state[1:0] + attribute \src "ls180.v:1742.11-1742.41" + wire width 2 $1\builder_refresher_state[1:0] + attribute \src "ls180.v:1852.11-1852.51" + wire width 2 $1\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:1851.11-1851.46" + wire width 2 $1\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:1820.5-1820.57" + wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:1819.5-1819.52" + wire $1\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:1832.11-1832.47" + wire width 3 $1\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:1831.11-1831.42" + wire width 3 $1\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:1856.5-1856.49" + wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:1855.5-1855.44" + wire $1\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:1860.11-1860.65" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:1859.11-1859.60" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:1808.11-1808.46" + wire width 3 $1\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:1807.11-1807.41" + wire width 3 $1\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:1796.11-1796.52" + wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:1795.11-1795.47" + wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:1792.11-1792.52" + wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:1791.11-1791.47" + wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:1804.5-1804.46" + wire $1\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:1803.5-1803.41" + wire $1\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:1812.11-1812.53" + wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:1811.11-1811.48" + wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:1788.5-1788.46" + wire $1\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:1787.5-1787.41" + wire $1\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:1884.5-1884.30" + wire $1\builder_shared_ack[0:0] + attribute \src "ls180.v:1880.12-1880.40" + wire width 32 $1\builder_shared_dat_r[31:0] + attribute \src "ls180.v:1891.11-1891.35" + wire width 5 $1\builder_slave_sel[4:0] + attribute \src "ls180.v:1892.11-1892.37" + wire width 5 $1\builder_slave_sel_r[4:0] + attribute \src "ls180.v:1780.11-1780.47" + wire width 2 $1\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:1779.11-1779.42" + wire width 2 $1\builder_spimaster0_state[1:0] + attribute \src "ls180.v:1784.11-1784.47" + wire width 2 $1\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:1783.11-1783.42" + wire width 2 $1\builder_spimaster1_state[1:0] + attribute \src "ls180.v:2588.11-2588.31" + wire width 2 $1\builder_state[1:0] + attribute \src "ls180.v:2641.5-2641.39" + wire $1\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:2642.5-2642.39" + wire $1\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:2634.11-2634.47" + wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:2635.12-2635.49" + wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2636.5-2636.41" + wire $1\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:2637.5-2637.41" + wire $1\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2638.5-2638.41" + wire $1\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2639.5-2639.41" + wire $1\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2640.5-2640.41" + wire $1\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:832.5-832.29" + wire $1\main_cmd_consumed[0:0] + attribute \src "ls180.v:829.5-829.34" + wire $1\main_converter_counter[0:0] + attribute \src "ls180.v:1777.5-1777.55" + wire $1\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:1778.5-1778.58" + wire $1\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:831.12-831.40" + wire width 32 $1\main_converter_dat_r[31:0] + attribute \src "ls180.v:828.5-828.31" + wire $1\main_converter_skip[0:0] + attribute \src "ls180.v:263.12-263.38" + wire width 16 $1\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:264.5-264.36" + wire $1\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:1063.12-1063.30" + wire width 24 $1\main_dummy[23:0] + attribute \src "ls180.v:980.5-980.27" + wire $1\main_gpio_oe_re[0:0] + attribute \src "ls180.v:979.12-979.40" + wire width 16 $1\main_gpio_oe_storage[15:0] + attribute \src "ls180.v:984.5-984.28" + wire $1\main_gpio_out_re[0:0] + attribute \src "ls180.v:983.12-983.41" + wire width 16 $1\main_gpio_out_storage[15:0] + attribute \src "ls180.v:981.12-981.36" + wire width 16 $1\main_gpio_status[15:0] + attribute \src "ls180.v:1088.5-1088.23" + wire $1\main_i2c_re[0:0] + attribute \src "ls180.v:1087.11-1087.34" + wire width 3 $1\main_i2c_storage[2:0] + attribute \src "ls180.v:248.5-248.24" + wire $1\main_int_rst[0:0] + attribute \src "ls180.v:1636.12-1636.43" + wire width 32 $1\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1640.5-1640.35" + wire $1\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1639.11-1639.41" + wire width 4 $1\main_interface1_bus_sel[3:0] + attribute \src "ls180.v:1641.5-1641.35" + wire $1\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:1643.5-1643.34" + wire $1\main_interface1_bus_we[0:0] + attribute \src "ls180.v:63.12-63.47" + wire width 32 $1\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:170.5-170.47" + wire $1\main_libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:1732.5-1732.69" + wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:1733.5-1733.72" + wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:172.12-172.53" + wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:169.5-169.44" + wire $1\main_libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:185.5-185.47" + wire $1\main_libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:1736.5-1736.69" + wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:1737.5-1737.72" + wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:187.12-187.53" + wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:184.5-184.44" + wire $1\main_libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:200.5-200.47" + wire $1\main_libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:1740.5-1740.69" + wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + attribute \src "ls180.v:1741.5-1741.72" + wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:202.12-202.53" + wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:199.5-199.44" + wire $1\main_libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:223.5-223.34" + wire $1\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:222.5-222.39" + wire $1\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:243.5-243.44" + wire $1\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:242.5-242.49" + wire $1\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:158.12-158.71" + wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:162.5-162.63" + wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:159.12-159.73" + wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:161.11-161.69" + wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:163.5-163.63" + wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:165.5-165.62" + wire $1\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:173.12-173.71" + wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:177.5-177.63" + wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:174.12-174.73" + wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:176.11-176.69" + wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:178.5-178.63" + wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:180.5-180.62" + wire $1\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:188.12-188.71" + wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:192.5-192.63" + wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:189.12-189.73" + wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:191.11-191.69" + wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:193.5-193.63" + wire $1\main_libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:195.5-195.62" + wire $1\main_libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:72.5-72.46" + wire $1\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:81.5-81.46" + wire $1\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:65.12-65.55" + wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:112.5-112.49" + wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:219.5-219.36" + wire $1\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:218.12-218.49" + wire width 32 $1\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:209.5-209.40" + wire $1\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:221.5-221.38" + wire $1\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:220.12-220.51" + wire width 32 $1\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:56.5-56.37" + wire $1\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:55.5-55.42" + wire $1\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:58.5-58.39" + wire $1\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:57.12-57.60" + wire width 32 $1\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:225.5-225.44" + wire $1\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:224.5-224.49" + wire $1\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:244.12-244.42" + wire width 32 $1\main_libresocsim_value[31:0] + attribute \src "ls180.v:226.12-226.49" + wire width 32 $1\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:216.11-216.37" + wire width 4 $1\main_libresocsim_we[3:0] + attribute \src "ls180.v:232.5-232.39" + wire $1\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:233.5-233.45" + wire $1\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:230.5-230.41" + wire $1\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:820.12-820.40" + wire width 30 $1\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:824.5-824.32" + wire $1\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:821.12-821.42" + wire width 16 $1\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:823.11-823.38" + wire width 2 $1\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:825.5-825.32" + wire $1\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:827.5-827.31" + wire $1\main_litedram_wb_we[0:0] + attribute \src "ls180.v:1067.12-1067.37" + wire width 32 $1\main_pwm0_counter[31:0] + attribute \src "ls180.v:1069.5-1069.31" + wire $1\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:1068.5-1068.36" + wire $1\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:1073.5-1073.31" + wire $1\main_pwm0_period_re[0:0] + attribute \src "ls180.v:1072.12-1072.44" + wire width 32 $1\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:1071.5-1071.30" + wire $1\main_pwm0_width_re[0:0] + attribute \src "ls180.v:1070.12-1070.43" + wire width 32 $1\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:1077.12-1077.37" + wire width 32 $1\main_pwm1_counter[31:0] + attribute \src "ls180.v:1079.5-1079.31" + wire $1\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:1078.5-1078.36" + wire $1\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:1083.5-1083.31" + wire $1\main_pwm1_period_re[0:0] + attribute \src "ls180.v:1082.12-1082.44" + wire width 32 $1\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:1081.5-1081.30" + wire $1\main_pwm1_width_re[0:0] + attribute \src "ls180.v:1080.12-1080.43" + wire width 32 $1\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:265.11-265.32" + wire width 3 $1\main_rddata_en[2:0] + attribute \src "ls180.v:1605.11-1605.50" + wire width 2 $1\main_sdblock2mem_converter_demux[1:0] + attribute \src "ls180.v:1601.5-1601.51" + wire $1\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:1602.5-1602.50" + wire $1\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:1603.12-1603.66" + wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "ls180.v:1604.11-1604.77" + wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "ls180.v:1607.5-1607.49" + wire $1\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:1580.11-1580.47" + wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:1577.11-1577.45" + wire width 6 $1\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:1579.11-1579.47" + wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1581.11-1581.50" + wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1615.12-1615.62" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:1616.12-1616.60" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "ls180.v:1613.5-1613.45" + wire $1\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:1623.5-1623.54" + wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:1622.12-1622.67" + wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:1627.5-1627.56" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:1626.5-1626.61" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:1625.5-1625.56" + wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:1624.12-1624.69" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:1631.5-1631.54" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:1630.5-1630.59" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:1633.12-1633.61" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:1853.12-1853.87" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:1854.5-1854.82" + wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:1618.5-1618.57" + wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:1628.5-1628.53" + wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:1397.5-1397.38" + wire $1\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:1396.12-1396.51" + wire width 32 $1\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:1395.5-1395.39" + wire $1\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:1394.11-1394.51" + wire width 10 $1\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:1381.5-1381.39" + wire $1\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:1380.12-1380.52" + wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:1383.5-1383.38" + wire $1\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:1382.12-1382.51" + wire width 32 $1\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:1536.11-1536.39" + wire width 3 $1\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:1837.11-1837.62" + wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:1838.5-1838.59" + wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:1537.5-1537.32" + wire $1\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:1833.5-1833.55" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:1834.5-1834.58" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:1538.5-1538.33" + wire $1\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:1841.5-1841.56" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:1842.5-1842.59" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:1388.13-1388.53" + wire width 128 $1\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:1849.13-1849.76" + wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:1850.5-1850.69" + wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1539.5-1539.35" + wire $1\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:1843.5-1843.58" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:1844.5-1844.61" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:1497.11-1497.47" + wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:1503.5-1503.46" + wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:1502.12-1502.54" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:1498.12-1498.58" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:1510.5-1510.46" + wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:1509.12-1509.54" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:1505.12-1505.58" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:1517.5-1517.46" + wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:1516.12-1516.54" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:1512.12-1512.58" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:1524.5-1524.46" + wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:1523.12-1523.54" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:1519.12-1519.58" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:1526.12-1526.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:1527.12-1527.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:1528.12-1528.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:1529.12-1529.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:1531.12-1531.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:1532.12-1532.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:1533.12-1533.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:1534.12-1534.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:1488.5-1488.48" + wire $1\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:1489.5-1489.47" + wire $1\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:1490.11-1490.61" + wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:1487.5-1487.48" + wire $1\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:1486.5-1486.48" + wire $1\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1491.5-1491.50" + wire $1\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:1496.11-1496.47" + wire width 8 $1\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:1530.5-1530.43" + wire $1\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:1453.11-1453.48" + wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:1829.11-1829.87" + wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:1830.5-1830.84" + wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:1458.12-1458.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:1454.12-1454.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:1465.12-1465.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:1461.12-1461.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:1472.12-1472.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:1468.12-1468.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:1479.12-1479.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:1475.12-1475.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:1482.12-1482.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:1821.12-1821.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:1822.5-1822.88" + wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:1483.12-1483.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:1823.12-1823.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:1824.5-1824.88" + wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:1484.12-1484.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:1825.12-1825.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:1826.5-1826.88" + wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:1485.12-1485.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:1827.12-1827.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:1828.5-1828.88" + wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:1444.5-1444.49" + wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1451.5-1451.50" + wire $1\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:1452.11-1452.64" + wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:1449.5-1449.51" + wire $1\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:1448.5-1448.51" + wire $1\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:1440.11-1440.47" + wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:1398.11-1398.51" + wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:1541.12-1541.42" + wire width 32 $1\main_sdcore_data_count[31:0] + attribute \src "ls180.v:1839.12-1839.65" + wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:1840.5-1840.60" + wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:1542.5-1542.33" + wire $1\main_sdcore_data_done[0:0] + attribute \src "ls180.v:1835.5-1835.56" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:1836.5-1836.59" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:1543.5-1543.34" + wire $1\main_sdcore_data_error[0:0] + attribute \src "ls180.v:1845.5-1845.57" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:1846.5-1846.60" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:1544.5-1544.36" + wire $1\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:1847.5-1847.59" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:1848.5-1848.62" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:1689.11-1689.48" + wire width 2 $1\main_sdmem2block_converter_mux[1:0] + attribute \src "ls180.v:1687.11-1687.64" + wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:1663.5-1663.40" + wire $1\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:1662.12-1662.53" + wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:1661.12-1661.45" + wire width 32 $1\main_sdmem2block_dma_data[31:0] + attribute \src "ls180.v:1857.12-1857.75" + wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "ls180.v:1858.5-1858.70" + wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1668.5-1668.44" + wire $1\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:1667.5-1667.42" + wire $1\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:1666.5-1666.47" + wire $1\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:1665.5-1665.42" + wire $1\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:1664.12-1664.55" + wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:1671.5-1671.40" + wire $1\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:1670.5-1670.45" + wire $1\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:1675.12-1675.47" + wire width 32 $1\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:1861.12-1861.87" + wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:1862.5-1862.82" + wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:1654.5-1654.42" + wire $1\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:1655.12-1655.61" + wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:1653.5-1653.43" + wire $1\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:1652.5-1652.43" + wire $1\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1659.5-1659.44" + wire $1\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:1660.12-1660.60" + wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] + attribute \src "ls180.v:1656.5-1656.45" + wire $1\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:1716.11-1716.47" + wire width 5 $1\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:1713.11-1713.45" + wire width 6 $1\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:1715.11-1715.47" + wire width 5 $1\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1717.11-1717.50" + wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1097.5-1097.35" + wire $1\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:1100.5-1100.35" + wire $1\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:1101.5-1101.36" + wire $1\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:1099.11-1099.41" + wire width 9 $1\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:1095.5-1095.33" + wire $1\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:1094.11-1094.46" + wire width 9 $1\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:1203.5-1203.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:1204.5-1204.48" + wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:1205.11-1205.62" + wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1201.5-1201.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:1188.11-1188.54" + wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1184.5-1184.55" + wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:1185.5-1185.54" + wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:1186.11-1186.68" + wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1187.11-1187.81" + wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1190.5-1190.53" + wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1206.5-1206.38" + wire $1\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:1801.5-1801.66" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:1802.5-1802.69" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:1176.5-1176.36" + wire $1\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:1171.5-1171.53" + wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:1158.11-1158.39" + wire width 8 $1\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:1797.11-1797.67" + wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:1798.5-1798.64" + wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1143.5-1143.48" + wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1144.5-1144.50" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1145.5-1145.51" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1150.5-1150.37" + wire $1\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:1151.11-1151.53" + wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:1149.5-1149.38" + wire $1\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:1148.5-1148.38" + wire $1\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:1154.5-1154.39" + wire $1\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:1155.11-1155.53" + wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:1156.11-1156.55" + wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:1153.5-1153.40" + wire $1\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:1152.5-1152.40" + wire $1\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:1157.12-1157.48" + wire width 32 $1\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:1799.12-1799.71" + wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:1800.5-1800.66" + wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:1130.11-1130.39" + wire width 8 $1\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:1793.11-1793.66" + wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:1794.5-1794.63" + wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:1129.5-1129.32" + wire $1\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:1120.5-1120.48" + wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1121.5-1121.50" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1122.5-1122.51" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1127.5-1127.37" + wire $1\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:1128.11-1128.51" + wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:1126.5-1126.38" + wire $1\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:1125.5-1125.38" + wire $1\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:1314.11-1314.41" + wire width 10 $1\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:1813.11-1813.70" + wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:1814.5-1814.66" + wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:1359.5-1359.51" + wire $1\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:1360.5-1360.50" + wire $1\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:1361.11-1361.64" + wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:1357.5-1357.51" + wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:1344.5-1344.50" + wire $1\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1340.5-1340.57" + wire $1\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:1341.5-1341.56" + wire $1\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:1342.11-1342.70" + wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:1343.11-1343.83" + wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:1346.5-1346.55" + wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1362.5-1362.40" + wire $1\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:1817.5-1817.69" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:1818.5-1818.72" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:1332.5-1332.38" + wire $1\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:1327.5-1327.55" + wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1297.5-1297.49" + wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1304.5-1304.38" + wire $1\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:1305.11-1305.61" + wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:1303.5-1303.39" + wire $1\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:1302.5-1302.39" + wire $1\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1309.5-1309.40" + wire $1\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:1310.11-1310.54" + wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:1311.11-1311.56" + wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:1307.5-1307.41" + wire $1\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:1306.5-1306.41" + wire $1\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:1312.5-1312.33" + wire $1\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:1313.12-1313.49" + wire width 32 $1\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:1815.12-1815.73" + wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:1816.5-1816.68" + wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:1222.11-1222.40" + wire width 8 $1\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:1809.11-1809.61" + wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:1810.5-1810.58" + wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1281.5-1281.50" + wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:1282.5-1282.49" + wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:1283.11-1283.63" + wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1279.5-1279.50" + wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:1266.11-1266.55" + wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1262.5-1262.56" + wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:1263.5-1263.55" + wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:1264.11-1264.69" + wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1265.11-1265.82" + wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1268.5-1268.54" + wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1284.5-1284.39" + wire $1\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:1805.5-1805.66" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:1806.5-1806.69" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:1254.5-1254.37" + wire $1\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:1249.5-1249.54" + wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:1236.5-1236.34" + wire $1\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1211.5-1211.49" + wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1214.11-1214.58" + wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1215.5-1215.53" + wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1218.5-1218.39" + wire $1\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:1219.5-1219.38" + wire $1\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:1220.11-1220.52" + wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:1217.5-1217.39" + wire $1\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:1216.5-1216.39" + wire $1\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:1234.5-1234.34" + wire $1\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:1221.5-1221.33" + wire $1\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:1235.5-1235.34" + wire $1\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:1115.11-1115.39" + wire width 8 $1\main_sdphy_init_count[7:0] + attribute \src "ls180.v:1789.11-1789.66" + wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:1790.5-1790.63" + wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1110.5-1110.48" + wire $1\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1111.5-1111.50" + wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1112.5-1112.51" + wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1113.11-1113.57" + wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1114.5-1114.52" + wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1364.5-1364.35" + wire $1\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:1367.11-1367.42" + wire width 4 $1\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:327.5-327.33" + wire $1\main_sdram_address_re[0:0] + attribute \src "ls180.v:326.12-326.46" + wire width 13 $1\main_sdram_address_storage[12:0] + attribute \src "ls180.v:329.5-329.34" + wire $1\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:328.11-328.45" + wire width 2 $1\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:425.5-425.50" + wire $1\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:447.11-447.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:444.11-444.68" + wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:446.11-446.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:448.11-448.73" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:471.5-471.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:472.5-472.58" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:474.12-474.74" + wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:473.5-473.64" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:469.5-469.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:417.12-417.57" + wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:419.5-419.51" + wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:422.5-422.54" + wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:423.5-423.55" + wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:424.5-424.56" + wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:420.5-420.51" + wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:421.5-421.50" + wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:416.5-416.45" + wire $1\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:415.5-415.45" + wire $1\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:414.5-414.47" + wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:412.5-412.51" + wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:411.5-411.51" + wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:475.12-475.47" + wire width 13 $1\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:479.5-479.45" + wire $1\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:480.5-480.54" + wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:478.5-478.44" + wire $1\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:476.5-476.46" + wire $1\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:483.11-483.55" + wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:482.32-482.76" + wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:507.5-507.50" + wire $1\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:529.11-529.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:526.11-526.68" + wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:528.11-528.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:530.11-530.73" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:553.5-553.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:554.5-554.58" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:556.12-556.74" + wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:555.5-555.64" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:551.5-551.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:499.12-499.57" + wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:501.5-501.51" + wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:504.5-504.54" + wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:505.5-505.55" + wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:506.5-506.56" + wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:502.5-502.51" + wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:503.5-503.50" + wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:498.5-498.45" + wire $1\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:497.5-497.45" + wire $1\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:496.5-496.47" + wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:494.5-494.51" + wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:493.5-493.51" + wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:557.12-557.47" + wire width 13 $1\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:561.5-561.45" + wire $1\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:562.5-562.54" + wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:560.5-560.44" + wire $1\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:558.5-558.46" + wire $1\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:565.11-565.55" + wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:564.32-564.76" + wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:589.5-589.50" + wire $1\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:611.11-611.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:608.11-608.68" + wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:610.11-610.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:612.11-612.73" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:635.5-635.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:636.5-636.58" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:638.12-638.74" + wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:637.5-637.64" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:633.5-633.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:581.12-581.57" + wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:583.5-583.51" + wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:586.5-586.54" + wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:587.5-587.55" + wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:588.5-588.56" + wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:584.5-584.51" + wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:585.5-585.50" + wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:580.5-580.45" + wire $1\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:579.5-579.45" + wire $1\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:578.5-578.47" + wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:576.5-576.51" + wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:575.5-575.51" + wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:639.12-639.47" + wire width 13 $1\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:643.5-643.45" + wire $1\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:644.5-644.54" + wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:642.5-642.44" + wire $1\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:640.5-640.46" + wire $1\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:647.11-647.55" + wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:646.32-646.76" + wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:671.5-671.50" + wire $1\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:693.11-693.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:690.11-690.68" + wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:692.11-692.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:694.11-694.73" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:717.5-717.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:718.5-718.58" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:720.12-720.74" + wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:719.5-719.64" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:715.5-715.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:663.12-663.57" + wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:665.5-665.51" + wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:668.5-668.54" + wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:669.5-669.55" + wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:670.5-670.56" + wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:666.5-666.51" + wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:667.5-667.50" + wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:662.5-662.45" + wire $1\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:661.5-661.45" + wire $1\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:660.5-660.47" + wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:658.5-658.51" + wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:657.5-657.51" + wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:721.12-721.47" + wire width 13 $1\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:725.5-725.45" + wire $1\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:726.5-726.54" + wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:724.5-724.44" + wire $1\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:722.5-722.46" + wire $1\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:729.11-729.55" + wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:728.32-728.76" + wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:744.5-744.49" + wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:745.5-745.49" + wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:746.5-746.48" + wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:752.11-752.45" + wire width 2 $1\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:750.11-750.46" + wire width 4 $1\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:762.5-762.49" + wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:763.5-763.49" + wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:764.5-764.48" + wire $1\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:759.5-759.43" + wire $1\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:770.11-770.45" + wire width 2 $1\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:768.11-768.46" + wire width 4 $1\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:757.5-757.48" + wire $1\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:754.5-754.44" + wire $1\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:755.5-755.45" + wire $1\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:383.5-383.31" + wire $1\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:384.12-384.44" + wire width 13 $1\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:385.11-385.43" + wire width 2 $1\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:386.5-386.38" + wire $1\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:387.5-387.38" + wire $1\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:388.5-388.37" + wire $1\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:382.5-382.32" + wire $1\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:381.5-381.32" + wire $1\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:321.5-321.33" + wire $1\main_sdram_command_re[0:0] + attribute \src "ls180.v:320.11-320.44" + wire width 6 $1\main_sdram_command_storage[5:0] + attribute \src "ls180.v:365.12-365.45" + wire width 13 $1\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:366.11-366.40" + wire width 2 $1\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:367.5-367.35" + wire $1\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:368.5-368.34" + wire $1\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:369.5-369.35" + wire $1\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:378.5-378.39" + wire $1\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:370.5-370.34" + wire $1\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:376.5-376.39" + wire $1\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:789.5-789.26" + wire $1\main_sdram_en0[0:0] + attribute \src "ls180.v:792.5-792.26" + wire $1\main_sdram_en1[0:0] + attribute \src "ls180.v:362.12-362.46" + wire width 16 $1\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:363.11-363.47" + wire width 2 $1\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:268.5-268.36" + wire $1\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:269.5-269.35" + wire $1\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:270.5-270.36" + wire $1\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:280.12-280.45" + wire width 16 $1\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:281.5-281.43" + wire $1\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:271.5-271.35" + wire $1\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:307.5-307.38" + wire $1\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:298.12-298.48" + wire width 13 $1\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:299.11-299.43" + wire width 2 $1\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:300.5-300.38" + wire $1\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:304.5-304.36" + wire $1\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:301.5-301.37" + wire $1\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:305.5-305.36" + wire $1\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:302.5-302.38" + wire $1\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:311.5-311.42" + wire $1\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:306.5-306.40" + wire $1\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:303.5-303.37" + wire $1\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:308.12-308.47" + wire width 16 $1\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:309.5-309.42" + wire $1\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:310.11-310.50" + wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:399.5-399.38" + wire $1\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:398.5-398.38" + wire $1\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:319.5-319.25" + wire $1\main_sdram_re[0:0] + attribute \src "ls180.v:405.5-405.38" + wire $1\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:404.11-404.46" + wire width 4 $1\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:403.5-403.38" + wire $1\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:400.5-400.39" + wire $1\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:296.12-296.46" + wire width 16 $1\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:297.5-297.44" + wire $1\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:332.12-332.37" + wire width 16 $1\main_sdram_status[15:0] + attribute \src "ls180.v:774.11-774.40" + wire width 2 $1\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:318.11-318.36" + wire width 4 $1\main_sdram_storage[3:0] + attribute \src "ls180.v:783.5-783.36" + wire $1\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:782.32-782.63" + wire $1\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:791.11-791.34" + wire width 5 $1\main_sdram_time0[4:0] + attribute \src "ls180.v:794.11-794.34" + wire width 4 $1\main_sdram_time1[3:0] + attribute \src "ls180.v:396.11-396.44" + wire width 10 $1\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:786.11-786.42" + wire width 3 $1\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:785.32-785.63" + wire $1\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:331.5-331.32" + wire $1\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:330.12-330.45" + wire width 16 $1\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:999.12-999.44" + wire width 16 $1\main_spimaster11_storage[15:0] + attribute \src "ls180.v:1000.5-1000.31" + wire $1\main_spimaster12_re[0:0] + attribute \src "ls180.v:1004.11-1004.42" + wire width 8 $1\main_spimaster16_storage[7:0] + attribute \src "ls180.v:1005.5-1005.31" + wire $1\main_spimaster17_re[0:0] + attribute \src "ls180.v:1061.5-1061.30" + wire $1\main_spimaster1_re[0:0] + attribute \src "ls180.v:1060.12-1060.45" + wire width 16 $1\main_spimaster1_storage[15:0] + attribute \src "ls180.v:1009.5-1009.36" + wire $1\main_spimaster21_storage[0:0] + attribute \src "ls180.v:1010.5-1010.31" + wire $1\main_spimaster22_re[0:0] + attribute \src "ls180.v:1011.5-1011.36" + wire $1\main_spimaster23_storage[0:0] + attribute \src "ls180.v:1012.5-1012.31" + wire $1\main_spimaster24_re[0:0] + attribute \src "ls180.v:1013.5-1013.39" + wire $1\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:1014.5-1014.38" + wire $1\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:1015.11-1015.40" + wire width 3 $1\main_spimaster27_count[2:0] + attribute \src "ls180.v:1781.11-1781.62" + wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:1782.5-1782.59" + wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:1016.5-1016.39" + wire $1\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:1017.5-1017.39" + wire $1\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:990.5-990.32" + wire $1\main_spimaster2_done[0:0] + attribute \src "ls180.v:1018.12-1018.48" + wire width 16 $1\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:1021.11-1021.44" + wire width 8 $1\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:1022.11-1022.43" + wire width 3 $1\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:1023.11-1023.44" + wire width 8 $1\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:991.5-991.31" + wire $1\main_spimaster3_irq[0:0] + attribute \src "ls180.v:993.11-993.38" + wire width 8 $1\main_spimaster5_miso[7:0] + attribute \src "ls180.v:997.5-997.33" + wire $1\main_spimaster9_start[0:0] + attribute \src "ls180.v:1054.12-1054.47" + wire width 16 $1\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:1049.5-1049.37" + wire $1\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:1036.5-1036.37" + wire $1\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:1035.12-1035.50" + wire width 16 $1\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:1051.11-1051.38" + wire width 3 $1\main_spisdcard_count[2:0] + attribute \src "ls180.v:1785.11-1785.60" + wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:1786.5-1786.57" + wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:1050.5-1050.36" + wire $1\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:1046.5-1046.32" + wire $1\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:1045.5-1045.37" + wire $1\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:1026.5-1026.32" + wire $1\main_spisdcard_done0[0:0] + attribute \src "ls180.v:1027.5-1027.30" + wire $1\main_spisdcard_irq[0:0] + attribute \src "ls180.v:1048.5-1048.38" + wire $1\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:1047.5-1047.43" + wire $1\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:1029.11-1029.37" + wire width 8 $1\main_spisdcard_miso[7:0] + attribute \src "ls180.v:1059.11-1059.42" + wire width 8 $1\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:1053.5-1053.37" + wire $1\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:1057.11-1057.42" + wire width 8 $1\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:1052.5-1052.37" + wire $1\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:1041.5-1041.34" + wire $1\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:1058.11-1058.41" + wire width 3 $1\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:1040.11-1040.45" + wire width 8 $1\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:1033.5-1033.33" + wire $1\main_spisdcard_start1[0:0] + attribute \src "ls180.v:887.11-887.50" + wire width 2 $1\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:889.5-889.37" + wire $1\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:883.11-883.49" + wire width 2 $1\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:888.11-888.48" + wire width 2 $1\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:855.12-855.54" + wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:845.12-845.54" + wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:838.5-838.28" + wire $1\main_uart_phy_re[0:0] + attribute \src "ls180.v:859.11-859.43" + wire width 4 $1\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:860.5-860.33" + wire $1\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:857.5-857.30" + wire $1\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:858.11-858.38" + wire width 8 $1\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:840.5-840.36" + wire $1\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:853.11-853.51" + wire width 8 $1\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:849.5-849.38" + wire $1\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:837.12-837.47" + wire width 32 $1\main_uart_phy_storage[31:0] + attribute \src "ls180.v:847.11-847.43" + wire width 4 $1\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:848.5-848.33" + wire $1\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:846.11-846.38" + wire width 8 $1\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:854.5-854.39" + wire $1\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:844.5-844.39" + wire $1\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:878.5-878.30" + wire $1\main_uart_rx_clear[0:0] + attribute \src "ls180.v:962.11-962.43" + wire width 4 $1\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:959.11-959.42" + wire width 5 $1\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:961.11-961.43" + wire width 4 $1\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:952.5-952.38" + wire $1\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:963.11-963.46" + wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:879.5-879.36" + wire $1\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:876.5-876.32" + wire $1\main_uart_rx_pending[0:0] + attribute \src "ls180.v:873.5-873.30" + wire $1\main_uart_tx_clear[0:0] + attribute \src "ls180.v:925.11-925.43" + wire width 4 $1\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:922.11-922.42" + wire width 5 $1\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:924.11-924.43" + wire width 4 $1\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:915.5-915.38" + wire $1\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:926.11-926.46" + wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:874.5-874.36" + wire $1\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:871.5-871.32" + wire $1\main_uart_tx_pending[0:0] + attribute \src "ls180.v:815.5-815.29" + wire $1\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:833.5-833.31" + wire $1\main_wdata_consumed[0:0] + attribute \src "ls180.v:2815.68-2815.110" + wire $add$ls180.v:2815$22_Y + attribute \src "ls180.v:2875.68-2875.110" + wire $add$ls180.v:2875$33_Y + attribute \src "ls180.v:2935.68-2935.110" + wire $add$ls180.v:2935$44_Y + attribute \src "ls180.v:4068.54-4068.83" + wire $add$ls180.v:4068$537_Y + attribute \src "ls180.v:4168.36-4168.89" + wire width 5 $add$ls180.v:4168$583_Y + attribute \src "ls180.v:4198.36-4198.89" + wire width 5 $add$ls180.v:4198$594_Y + attribute \src "ls180.v:4253.54-4253.83" + wire width 3 $add$ls180.v:4253$607_Y + attribute \src "ls180.v:4312.52-4312.79" + wire width 3 $add$ls180.v:4312$615_Y + attribute \src "ls180.v:4416.58-4416.86" + wire width 8 $add$ls180.v:4416$643_Y + attribute \src "ls180.v:4473.58-4473.86" + wire width 8 $add$ls180.v:4473$646_Y + attribute \src "ls180.v:4490.58-4490.86" + wire width 8 $add$ls180.v:4490$648_Y + attribute \src "ls180.v:4583.59-4583.87" + wire width 8 $add$ls180.v:4583$665_Y + attribute \src "ls180.v:4608.59-4608.87" + wire width 8 $add$ls180.v:4608$668_Y + attribute \src "ls180.v:4730.53-4730.82" + wire width 8 $add$ls180.v:4730$685_Y + attribute \src "ls180.v:4841.65-4841.114" + wire width 10 $add$ls180.v:4841$699_Y + attribute \src "ls180.v:4846.62-4846.91" + wire width 10 $add$ls180.v:4846$702_Y + attribute \src "ls180.v:4872.61-4872.90" + wire width 10 $add$ls180.v:4872$705_Y + attribute \src "ls180.v:5076.80-5076.117" + wire width 3 $add$ls180.v:5076$890_Y + attribute \src "ls180.v:5270.54-5270.82" + wire width 3 $add$ls180.v:5270$965_Y + attribute \src "ls180.v:5322.55-5322.84" + wire width 32 $add$ls180.v:5322$975_Y + attribute \src "ls180.v:5348.57-5348.86" + wire width 32 $add$ls180.v:5348$983_Y + attribute \src "ls180.v:5469.51-5469.134" + wire width 32 $add$ls180.v:5469$999_Y + attribute \src "ls180.v:5472.77-5472.125" + wire width 32 $add$ls180.v:5472$1001_Y + attribute \src "ls180.v:5565.50-5565.105" + wire width 32 $add$ls180.v:5565$1010_Y + attribute \src "ls180.v:5567.77-5567.111" + wire width 32 $add$ls180.v:5567$1011_Y + attribute \src "ls180.v:7487.36-7487.70" + wire width 32 $add$ls180.v:7487$2403_Y + attribute \src "ls180.v:7572.37-7572.72" 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$eq$ls180.v:5921$1332_Y + attribute \src "ls180.v:5923.100-5923.144" + wire $eq$ls180.v:5923$1334_Y + attribute \src "ls180.v:5924.103-5924.147" + wire $eq$ls180.v:5924$1338_Y + attribute \src "ls180.v:5926.100-5926.144" + wire $eq$ls180.v:5926$1341_Y + attribute \src "ls180.v:5927.103-5927.147" + wire $eq$ls180.v:5927$1345_Y + attribute \src "ls180.v:5929.100-5929.144" + wire $eq$ls180.v:5929$1348_Y + attribute \src "ls180.v:5930.103-5930.147" + wire $eq$ls180.v:5930$1352_Y + attribute \src "ls180.v:5932.100-5932.144" + wire $eq$ls180.v:5932$1355_Y + attribute \src "ls180.v:5933.103-5933.147" + wire $eq$ls180.v:5933$1359_Y + attribute \src "ls180.v:5935.100-5935.144" + wire $eq$ls180.v:5935$1362_Y + attribute \src "ls180.v:5936.103-5936.147" + wire $eq$ls180.v:5936$1366_Y + attribute \src "ls180.v:5938.100-5938.144" + wire $eq$ls180.v:5938$1369_Y + attribute \src "ls180.v:5939.103-5939.147" + wire $eq$ls180.v:5939$1373_Y + attribute \src "ls180.v:5941.100-5941.144" + wire $eq$ls180.v:5941$1376_Y + attribute \src "ls180.v:5942.103-5942.147" + wire $eq$ls180.v:5942$1380_Y + attribute \src "ls180.v:5944.100-5944.144" + wire $eq$ls180.v:5944$1383_Y + attribute \src "ls180.v:5945.103-5945.147" + wire $eq$ls180.v:5945$1387_Y + attribute \src "ls180.v:5947.102-5947.146" + wire $eq$ls180.v:5947$1390_Y + attribute \src "ls180.v:5948.105-5948.149" + wire $eq$ls180.v:5948$1394_Y + attribute \src "ls180.v:5950.102-5950.146" + wire $eq$ls180.v:5950$1397_Y + attribute \src "ls180.v:5951.105-5951.149" + wire $eq$ls180.v:5951$1401_Y + attribute \src "ls180.v:5953.102-5953.147" + wire $eq$ls180.v:5953$1404_Y + attribute \src "ls180.v:5954.105-5954.150" + wire $eq$ls180.v:5954$1408_Y + attribute \src "ls180.v:5956.102-5956.147" + wire $eq$ls180.v:5956$1411_Y + attribute \src "ls180.v:5957.105-5957.150" + wire $eq$ls180.v:5957$1415_Y + attribute \src "ls180.v:5959.102-5959.147" + wire $eq$ls180.v:5959$1418_Y + attribute \src "ls180.v:5960.105-5960.150" + wire $eq$ls180.v:5960$1422_Y + attribute \src "ls180.v:5962.99-5962.144" + wire $eq$ls180.v:5962$1425_Y + attribute \src "ls180.v:5963.102-5963.147" + wire $eq$ls180.v:5963$1429_Y + attribute \src "ls180.v:5965.100-5965.145" + wire $eq$ls180.v:5965$1432_Y + attribute \src "ls180.v:5966.103-5966.148" + wire $eq$ls180.v:5966$1436_Y + attribute \src "ls180.v:5983.32-5983.78" + wire $eq$ls180.v:5983$1438_Y + attribute \src "ls180.v:5985.104-5985.148" + wire $eq$ls180.v:5985$1440_Y + attribute \src "ls180.v:5986.107-5986.151" + wire $eq$ls180.v:5986$1444_Y + attribute \src "ls180.v:5988.104-5988.148" + wire $eq$ls180.v:5988$1447_Y + attribute \src "ls180.v:5989.107-5989.151" + wire $eq$ls180.v:5989$1451_Y + attribute \src "ls180.v:5991.104-5991.148" + wire $eq$ls180.v:5991$1454_Y + attribute \src "ls180.v:5992.107-5992.151" + wire $eq$ls180.v:5992$1458_Y + attribute \src "ls180.v:5994.104-5994.148" + wire $eq$ls180.v:5994$1461_Y + attribute \src "ls180.v:5995.107-5995.151" + wire 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$eq$ls180.v:6015$1510_Y + attribute \src "ls180.v:6016.108-6016.153" + wire $eq$ls180.v:6016$1514_Y + attribute \src "ls180.v:6018.105-6018.150" + wire $eq$ls180.v:6018$1517_Y + attribute \src "ls180.v:6019.108-6019.153" + wire $eq$ls180.v:6019$1521_Y + attribute \src "ls180.v:6021.105-6021.150" + wire $eq$ls180.v:6021$1524_Y + attribute \src "ls180.v:6022.108-6022.153" + wire $eq$ls180.v:6022$1528_Y + attribute \src "ls180.v:6024.105-6024.150" + wire $eq$ls180.v:6024$1531_Y + attribute \src "ls180.v:6025.108-6025.153" + wire $eq$ls180.v:6025$1535_Y + attribute \src "ls180.v:6027.105-6027.150" + wire $eq$ls180.v:6027$1538_Y + attribute \src "ls180.v:6028.108-6028.153" + wire $eq$ls180.v:6028$1542_Y + attribute \src "ls180.v:6030.104-6030.149" + wire $eq$ls180.v:6030$1545_Y + attribute \src "ls180.v:6031.107-6031.152" + wire $eq$ls180.v:6031$1549_Y + attribute \src "ls180.v:6033.104-6033.149" + wire $eq$ls180.v:6033$1552_Y + attribute \src "ls180.v:6034.107-6034.152" + wire $eq$ls180.v:6034$1556_Y + attribute \src "ls180.v:6036.104-6036.149" + wire $eq$ls180.v:6036$1559_Y + attribute \src "ls180.v:6037.107-6037.152" + wire $eq$ls180.v:6037$1563_Y + attribute \src "ls180.v:6039.104-6039.149" + wire $eq$ls180.v:6039$1566_Y + attribute \src "ls180.v:6040.107-6040.152" + wire $eq$ls180.v:6040$1570_Y + attribute \src "ls180.v:6042.104-6042.149" + wire $eq$ls180.v:6042$1573_Y + attribute \src "ls180.v:6043.107-6043.152" + wire $eq$ls180.v:6043$1577_Y + attribute \src "ls180.v:6045.104-6045.149" + wire $eq$ls180.v:6045$1580_Y + attribute \src "ls180.v:6046.107-6046.152" + wire $eq$ls180.v:6046$1584_Y + attribute \src "ls180.v:6048.104-6048.149" + wire $eq$ls180.v:6048$1587_Y + attribute \src "ls180.v:6049.107-6049.152" + wire $eq$ls180.v:6049$1591_Y + attribute \src "ls180.v:6051.104-6051.149" + wire $eq$ls180.v:6051$1594_Y + attribute \src "ls180.v:6052.107-6052.152" + wire $eq$ls180.v:6052$1598_Y + attribute \src "ls180.v:6054.104-6054.149" + wire $eq$ls180.v:6054$1601_Y + attribute \src "ls180.v:6055.107-6055.152" + wire $eq$ls180.v:6055$1605_Y + attribute \src "ls180.v:6057.104-6057.149" + wire $eq$ls180.v:6057$1608_Y + attribute \src "ls180.v:6058.107-6058.152" + wire $eq$ls180.v:6058$1612_Y + attribute \src "ls180.v:6060.100-6060.145" + wire $eq$ls180.v:6060$1615_Y + attribute \src "ls180.v:6061.103-6061.148" + wire $eq$ls180.v:6061$1619_Y + attribute \src "ls180.v:6063.101-6063.146" + wire $eq$ls180.v:6063$1622_Y + attribute \src "ls180.v:6064.104-6064.149" + wire $eq$ls180.v:6064$1626_Y + attribute \src "ls180.v:6066.104-6066.149" + wire $eq$ls180.v:6066$1629_Y + attribute \src "ls180.v:6067.107-6067.152" + wire $eq$ls180.v:6067$1633_Y + attribute \src "ls180.v:6069.104-6069.149" + wire $eq$ls180.v:6069$1636_Y + attribute \src "ls180.v:6070.107-6070.152" + wire $eq$ls180.v:6070$1640_Y + attribute \src "ls180.v:6072.103-6072.148" + wire $eq$ls180.v:6072$1643_Y + attribute \src "ls180.v:6073.106-6073.151" + wire $eq$ls180.v:6073$1647_Y + attribute \src "ls180.v:6075.103-6075.148" + wire $eq$ls180.v:6075$1650_Y + attribute \src "ls180.v:6076.106-6076.151" + wire $eq$ls180.v:6076$1654_Y + attribute \src "ls180.v:6078.103-6078.148" + wire $eq$ls180.v:6078$1657_Y + attribute \src "ls180.v:6079.106-6079.151" + wire $eq$ls180.v:6079$1661_Y + attribute \src "ls180.v:6081.103-6081.148" + wire $eq$ls180.v:6081$1664_Y + attribute \src "ls180.v:6082.106-6082.151" + wire $eq$ls180.v:6082$1668_Y + attribute \src "ls180.v:6118.32-6118.78" + wire $eq$ls180.v:6118$1670_Y + attribute \src "ls180.v:6120.100-6120.144" + wire $eq$ls180.v:6120$1672_Y + attribute \src "ls180.v:6121.103-6121.147" + wire $eq$ls180.v:6121$1676_Y + attribute \src "ls180.v:6123.100-6123.144" + wire $eq$ls180.v:6123$1679_Y + attribute \src "ls180.v:6124.103-6124.147" + wire $eq$ls180.v:6124$1683_Y + attribute \src "ls180.v:6126.100-6126.144" + wire $eq$ls180.v:6126$1686_Y + attribute \src "ls180.v:6127.103-6127.147" + wire $eq$ls180.v:6127$1690_Y + attribute \src "ls180.v:6129.100-6129.144" + wire $eq$ls180.v:6129$1693_Y + attribute \src "ls180.v:6130.103-6130.147" + wire $eq$ls180.v:6130$1697_Y + attribute \src "ls180.v:6132.100-6132.144" + wire $eq$ls180.v:6132$1700_Y + attribute \src "ls180.v:6133.103-6133.147" + wire $eq$ls180.v:6133$1704_Y + attribute \src "ls180.v:6135.100-6135.144" + wire $eq$ls180.v:6135$1707_Y + attribute \src "ls180.v:6136.103-6136.147" + wire $eq$ls180.v:6136$1711_Y + attribute \src "ls180.v:6138.100-6138.144" + wire $eq$ls180.v:6138$1714_Y + attribute \src "ls180.v:6139.103-6139.147" + wire $eq$ls180.v:6139$1718_Y + attribute \src "ls180.v:6141.100-6141.144" + wire $eq$ls180.v:6141$1721_Y + attribute \src "ls180.v:6142.103-6142.147" + wire $eq$ls180.v:6142$1725_Y + attribute \src "ls180.v:6144.102-6144.146" + wire $eq$ls180.v:6144$1728_Y + attribute \src "ls180.v:6145.105-6145.149" + wire $eq$ls180.v:6145$1732_Y + attribute \src "ls180.v:6147.102-6147.146" + wire $eq$ls180.v:6147$1735_Y + attribute \src "ls180.v:6148.105-6148.149" + wire $eq$ls180.v:6148$1739_Y + attribute \src "ls180.v:6150.102-6150.147" + wire $eq$ls180.v:6150$1742_Y + attribute \src "ls180.v:6151.105-6151.150" + wire $eq$ls180.v:6151$1746_Y + attribute \src "ls180.v:6153.102-6153.147" + wire $eq$ls180.v:6153$1749_Y + attribute \src "ls180.v:6154.105-6154.150" + wire $eq$ls180.v:6154$1753_Y + attribute \src "ls180.v:6156.102-6156.147" + wire $eq$ls180.v:6156$1756_Y + attribute \src "ls180.v:6157.105-6157.150" + wire $eq$ls180.v:6157$1760_Y + attribute \src "ls180.v:6159.99-6159.144" + wire $eq$ls180.v:6159$1763_Y + attribute \src "ls180.v:6160.102-6160.147" + wire $eq$ls180.v:6160$1767_Y + attribute \src "ls180.v:6162.100-6162.145" + wire $eq$ls180.v:6162$1770_Y + attribute \src "ls180.v:6163.103-6163.148" + wire $eq$ls180.v:6163$1774_Y + attribute \src "ls180.v:6165.102-6165.147" + wire $eq$ls180.v:6165$1777_Y + attribute \src "ls180.v:6166.105-6166.150" + wire $eq$ls180.v:6166$1781_Y + attribute \src "ls180.v:6168.102-6168.147" + wire $eq$ls180.v:6168$1784_Y + attribute \src "ls180.v:6169.105-6169.150" + wire $eq$ls180.v:6169$1788_Y + attribute \src "ls180.v:6171.102-6171.147" + wire $eq$ls180.v:6171$1791_Y + attribute \src "ls180.v:6172.105-6172.150" + wire $eq$ls180.v:6172$1795_Y + attribute \src "ls180.v:6174.102-6174.147" + wire $eq$ls180.v:6174$1798_Y + attribute \src "ls180.v:6175.105-6175.150" + wire $eq$ls180.v:6175$1802_Y + attribute \src "ls180.v:6197.32-6197.78" + wire $eq$ls180.v:6197$1804_Y + attribute \src "ls180.v:6199.102-6199.146" + wire $eq$ls180.v:6199$1806_Y + attribute \src "ls180.v:6200.105-6200.149" + wire $eq$ls180.v:6200$1810_Y + attribute \src "ls180.v:6202.107-6202.151" + wire $eq$ls180.v:6202$1813_Y + attribute \src "ls180.v:6203.110-6203.154" + wire $eq$ls180.v:6203$1817_Y + attribute \src "ls180.v:6205.107-6205.151" + wire $eq$ls180.v:6205$1820_Y + attribute \src "ls180.v:6206.110-6206.154" + wire $eq$ls180.v:6206$1824_Y + attribute \src "ls180.v:6208.100-6208.144" + wire $eq$ls180.v:6208$1827_Y + attribute \src "ls180.v:6209.103-6209.147" + wire $eq$ls180.v:6209$1831_Y + attribute \src "ls180.v:6214.32-6214.77" + wire $eq$ls180.v:6214$1833_Y + attribute \src "ls180.v:6216.104-6216.148" + wire $eq$ls180.v:6216$1835_Y + attribute \src "ls180.v:6217.107-6217.151" + wire $eq$ls180.v:6217$1839_Y + attribute \src "ls180.v:6219.108-6219.152" + wire $eq$ls180.v:6219$1842_Y + attribute \src "ls180.v:6220.111-6220.155" + wire $eq$ls180.v:6220$1846_Y + attribute \src "ls180.v:6222.98-6222.142" + wire $eq$ls180.v:6222$1849_Y + attribute \src "ls180.v:6223.101-6223.145" + wire $eq$ls180.v:6223$1853_Y + attribute \src "ls180.v:6225.108-6225.152" + wire $eq$ls180.v:6225$1856_Y + attribute \src "ls180.v:6226.111-6226.155" + wire $eq$ls180.v:6226$1860_Y + attribute \src "ls180.v:6228.108-6228.152" + wire $eq$ls180.v:6228$1863_Y + attribute \src "ls180.v:6229.111-6229.155" + wire $eq$ls180.v:6229$1867_Y + attribute \src "ls180.v:6231.109-6231.153" + wire $eq$ls180.v:6231$1870_Y + attribute \src "ls180.v:6232.112-6232.156" + wire $eq$ls180.v:6232$1874_Y + attribute \src "ls180.v:6234.107-6234.151" + wire $eq$ls180.v:6234$1877_Y + attribute \src "ls180.v:6235.110-6235.154" + wire $eq$ls180.v:6235$1881_Y + attribute \src "ls180.v:6237.107-6237.151" + wire $eq$ls180.v:6237$1884_Y + attribute \src "ls180.v:6238.110-6238.154" + wire $eq$ls180.v:6238$1888_Y + attribute \src "ls180.v:6240.107-6240.151" + wire $eq$ls180.v:6240$1891_Y + attribute \src "ls180.v:6241.110-6241.154" + wire $eq$ls180.v:6241$1895_Y + attribute \src "ls180.v:6243.107-6243.151" + wire $eq$ls180.v:6243$1898_Y + attribute \src "ls180.v:6244.110-6244.154" + wire $eq$ls180.v:6244$1902_Y + attribute \src "ls180.v:6259.33-6259.79" + wire $eq$ls180.v:6259$1904_Y + attribute \src "ls180.v:6261.102-6261.147" + wire $eq$ls180.v:6261$1906_Y + attribute \src "ls180.v:6262.105-6262.150" + wire $eq$ls180.v:6262$1910_Y + attribute \src "ls180.v:6264.102-6264.147" + wire $eq$ls180.v:6264$1913_Y + attribute \src "ls180.v:6265.105-6265.150" + wire $eq$ls180.v:6265$1917_Y + attribute \src "ls180.v:6267.100-6267.145" + wire $eq$ls180.v:6267$1920_Y + attribute \src "ls180.v:6268.103-6268.148" + wire $eq$ls180.v:6268$1924_Y + attribute \src "ls180.v:6270.99-6270.144" + wire $eq$ls180.v:6270$1927_Y + attribute \src "ls180.v:6271.102-6271.147" + wire $eq$ls180.v:6271$1931_Y + attribute \src "ls180.v:6273.98-6273.143" + wire $eq$ls180.v:6273$1934_Y + attribute \src "ls180.v:6274.101-6274.146" + wire $eq$ls180.v:6274$1938_Y + attribute \src "ls180.v:6276.97-6276.142" + wire $eq$ls180.v:6276$1941_Y + attribute \src "ls180.v:6277.100-6277.145" + wire $eq$ls180.v:6277$1945_Y + attribute \src "ls180.v:6279.103-6279.148" + wire $eq$ls180.v:6279$1948_Y + attribute \src "ls180.v:6280.106-6280.151" + wire $eq$ls180.v:6280$1952_Y + attribute \src "ls180.v:6299.33-6299.79" + wire $eq$ls180.v:6299$1955_Y + attribute \src "ls180.v:6301.102-6301.147" + wire $eq$ls180.v:6301$1957_Y + attribute \src "ls180.v:6302.105-6302.150" + wire $eq$ls180.v:6302$1961_Y + attribute \src "ls180.v:6304.102-6304.147" + wire $eq$ls180.v:6304$1964_Y + attribute \src "ls180.v:6305.105-6305.150" + wire $eq$ls180.v:6305$1968_Y + attribute \src "ls180.v:6307.100-6307.145" + wire $eq$ls180.v:6307$1971_Y + attribute \src "ls180.v:6308.103-6308.148" + wire $eq$ls180.v:6308$1975_Y + attribute \src "ls180.v:6310.99-6310.144" + wire $eq$ls180.v:6310$1978_Y + attribute \src "ls180.v:6311.102-6311.147" + wire $eq$ls180.v:6311$1982_Y + attribute \src "ls180.v:6313.98-6313.143" + wire $eq$ls180.v:6313$1985_Y + attribute \src "ls180.v:6314.101-6314.146" + wire $eq$ls180.v:6314$1989_Y + attribute \src "ls180.v:6316.97-6316.142" + wire $eq$ls180.v:6316$1992_Y + attribute \src "ls180.v:6317.100-6317.145" + wire $eq$ls180.v:6317$1996_Y + attribute \src "ls180.v:6319.103-6319.148" + wire $eq$ls180.v:6319$1999_Y + attribute \src "ls180.v:6320.106-6320.151" + wire $eq$ls180.v:6320$2003_Y + attribute \src "ls180.v:6322.106-6322.151" + wire $eq$ls180.v:6322$2006_Y + attribute \src "ls180.v:6323.109-6323.154" + wire $eq$ls180.v:6323$2010_Y + attribute \src "ls180.v:6325.106-6325.151" + wire $eq$ls180.v:6325$2013_Y + attribute \src "ls180.v:6326.109-6326.154" + wire $eq$ls180.v:6326$2017_Y + attribute \src "ls180.v:6347.33-6347.79" + wire $eq$ls180.v:6347$2020_Y + attribute \src "ls180.v:6349.99-6349.144" + wire $eq$ls180.v:6349$2022_Y + attribute \src "ls180.v:6350.102-6350.147" + wire $eq$ls180.v:6350$2026_Y + attribute \src "ls180.v:6352.99-6352.144" + wire $eq$ls180.v:6352$2029_Y + attribute \src "ls180.v:6353.102-6353.147" + wire $eq$ls180.v:6353$2033_Y + attribute \src "ls180.v:6355.99-6355.144" + wire $eq$ls180.v:6355$2036_Y + attribute \src "ls180.v:6356.102-6356.147" + wire $eq$ls180.v:6356$2040_Y + attribute \src "ls180.v:6358.99-6358.144" + wire $eq$ls180.v:6358$2043_Y + attribute \src "ls180.v:6359.102-6359.147" + wire $eq$ls180.v:6359$2047_Y + attribute \src "ls180.v:6361.101-6361.146" + wire $eq$ls180.v:6361$2050_Y + attribute \src "ls180.v:6362.104-6362.149" + wire $eq$ls180.v:6362$2054_Y + attribute \src "ls180.v:6364.101-6364.146" + wire $eq$ls180.v:6364$2057_Y + attribute \src "ls180.v:6365.104-6365.149" + wire $eq$ls180.v:6365$2061_Y + attribute \src "ls180.v:6367.101-6367.146" + wire $eq$ls180.v:6367$2064_Y + attribute \src "ls180.v:6368.104-6368.149" + wire $eq$ls180.v:6368$2068_Y + attribute \src "ls180.v:6370.101-6370.146" + wire $eq$ls180.v:6370$2071_Y + attribute \src "ls180.v:6371.104-6371.149" + wire $eq$ls180.v:6371$2075_Y + attribute \src "ls180.v:6373.97-6373.142" + wire $eq$ls180.v:6373$2078_Y + attribute \src "ls180.v:6374.100-6374.145" + wire $eq$ls180.v:6374$2082_Y + attribute \src "ls180.v:6376.107-6376.152" + wire $eq$ls180.v:6376$2085_Y + attribute \src "ls180.v:6377.110-6377.155" + wire $eq$ls180.v:6377$2089_Y + attribute \src "ls180.v:6379.100-6379.146" + wire $eq$ls180.v:6379$2092_Y + attribute \src "ls180.v:6380.103-6380.149" + wire $eq$ls180.v:6380$2096_Y + attribute \src "ls180.v:6382.100-6382.146" + wire $eq$ls180.v:6382$2099_Y + attribute \src "ls180.v:6383.103-6383.149" + wire $eq$ls180.v:6383$2103_Y + attribute \src "ls180.v:6385.100-6385.146" + wire $eq$ls180.v:6385$2106_Y + attribute \src "ls180.v:6386.103-6386.149" + wire $eq$ls180.v:6386$2110_Y + attribute \src "ls180.v:6388.100-6388.146" + wire $eq$ls180.v:6388$2113_Y + attribute \src "ls180.v:6389.103-6389.149" + wire $eq$ls180.v:6389$2117_Y + attribute \src "ls180.v:6391.112-6391.158" + wire $eq$ls180.v:6391$2120_Y + attribute \src "ls180.v:6392.115-6392.161" + wire $eq$ls180.v:6392$2124_Y + attribute \src "ls180.v:6394.113-6394.159" + wire $eq$ls180.v:6394$2127_Y + attribute \src "ls180.v:6395.116-6395.162" + wire $eq$ls180.v:6395$2131_Y + attribute \src "ls180.v:6397.104-6397.150" + wire $eq$ls180.v:6397$2134_Y + attribute \src "ls180.v:6398.107-6398.153" + wire $eq$ls180.v:6398$2138_Y + attribute \src "ls180.v:6415.33-6415.79" + wire $eq$ls180.v:6415$2140_Y + attribute \src "ls180.v:6417.90-6417.135" + wire $eq$ls180.v:6417$2142_Y + attribute \src "ls180.v:6418.93-6418.138" + wire $eq$ls180.v:6418$2146_Y + attribute \src "ls180.v:6420.100-6420.145" + wire $eq$ls180.v:6420$2149_Y + attribute \src "ls180.v:6421.103-6421.148" + wire $eq$ls180.v:6421$2153_Y + attribute \src "ls180.v:6423.101-6423.146" + wire $eq$ls180.v:6423$2156_Y + attribute \src "ls180.v:6424.104-6424.149" + wire $eq$ls180.v:6424$2160_Y + attribute \src "ls180.v:6426.105-6426.150" + wire $eq$ls180.v:6426$2163_Y + attribute \src "ls180.v:6427.108-6427.153" + wire $eq$ls180.v:6427$2167_Y + attribute \src "ls180.v:6429.106-6429.151" + wire $eq$ls180.v:6429$2170_Y + attribute \src "ls180.v:6430.109-6430.154" + wire $eq$ls180.v:6430$2174_Y + attribute \src "ls180.v:6432.104-6432.149" + wire $eq$ls180.v:6432$2177_Y + attribute \src "ls180.v:6433.107-6433.152" + wire $eq$ls180.v:6433$2181_Y + attribute \src "ls180.v:6435.101-6435.146" + wire $eq$ls180.v:6435$2184_Y + attribute \src "ls180.v:6436.104-6436.149" + wire $eq$ls180.v:6436$2188_Y + attribute \src "ls180.v:6438.100-6438.145" + wire $eq$ls180.v:6438$2191_Y + attribute \src "ls180.v:6439.103-6439.148" + wire $eq$ls180.v:6439$2195_Y + attribute \src "ls180.v:6449.33-6449.79" + wire $eq$ls180.v:6449$2197_Y + attribute \src "ls180.v:6451.106-6451.151" + wire $eq$ls180.v:6451$2199_Y + attribute \src "ls180.v:6452.109-6452.154" + wire $eq$ls180.v:6452$2203_Y + attribute \src "ls180.v:6454.106-6454.151" + wire $eq$ls180.v:6454$2206_Y + attribute \src "ls180.v:6455.109-6455.154" + wire $eq$ls180.v:6455$2210_Y + attribute \src "ls180.v:6457.106-6457.151" + wire $eq$ls180.v:6457$2213_Y + attribute \src "ls180.v:6458.109-6458.154" + wire $eq$ls180.v:6458$2217_Y + attribute \src "ls180.v:6460.106-6460.151" + wire $eq$ls180.v:6460$2220_Y + attribute \src "ls180.v:6461.109-6461.154" + wire $eq$ls180.v:6461$2224_Y + attribute \src "ls180.v:6842.41-6842.81" + wire $eq$ls180.v:6842$2261_Y + attribute \src "ls180.v:6842.144-6842.177" + wire $eq$ls180.v:6842$2262_Y + attribute \src "ls180.v:6842.219-6842.252" + wire $eq$ls180.v:6842$2265_Y + attribute \src "ls180.v:6842.294-6842.327" + wire $eq$ls180.v:6842$2268_Y + attribute \src "ls180.v:6866.41-6866.81" + wire $eq$ls180.v:6866$2277_Y + attribute \src "ls180.v:6866.144-6866.177" + wire $eq$ls180.v:6866$2278_Y + attribute \src "ls180.v:6866.219-6866.252" + wire $eq$ls180.v:6866$2281_Y + attribute \src "ls180.v:6866.294-6866.327" + wire $eq$ls180.v:6866$2284_Y + attribute \src "ls180.v:6890.41-6890.81" + wire $eq$ls180.v:6890$2293_Y + attribute \src "ls180.v:6890.144-6890.177" + wire $eq$ls180.v:6890$2294_Y + attribute \src "ls180.v:6890.219-6890.252" + wire $eq$ls180.v:6890$2297_Y + attribute \src "ls180.v:6890.294-6890.327" + wire $eq$ls180.v:6890$2300_Y + attribute \src "ls180.v:6914.41-6914.81" + wire $eq$ls180.v:6914$2309_Y + attribute \src "ls180.v:6914.144-6914.177" + wire $eq$ls180.v:6914$2310_Y + attribute \src "ls180.v:6914.219-6914.252" + wire $eq$ls180.v:6914$2313_Y + attribute \src "ls180.v:6914.294-6914.327" + wire $eq$ls180.v:6914$2316_Y + attribute \src "ls180.v:7495.8-7495.38" + wire $eq$ls180.v:7495$2407_Y + attribute \src "ls180.v:7526.8-7526.42" + wire $eq$ls180.v:7526$2415_Y + attribute \src "ls180.v:7546.38-7546.74" + wire $eq$ls180.v:7546$2418_Y + attribute \src "ls180.v:7553.7-7553.43" + wire $eq$ls180.v:7553$2420_Y + attribute \src "ls180.v:7560.7-7560.43" + wire $eq$ls180.v:7560$2421_Y + attribute \src "ls180.v:7568.7-7568.43" + wire $eq$ls180.v:7568$2422_Y + attribute \src "ls180.v:7620.9-7620.54" + wire $eq$ls180.v:7620$2440_Y + attribute \src "ls180.v:7666.9-7666.54" + wire $eq$ls180.v:7666$2456_Y + attribute \src "ls180.v:7712.9-7712.54" + wire $eq$ls180.v:7712$2472_Y + attribute \src "ls180.v:7758.9-7758.54" + wire $eq$ls180.v:7758$2488_Y + attribute \src "ls180.v:7908.9-7908.41" + wire $eq$ls180.v:7908$2500_Y + attribute \src "ls180.v:7923.9-7923.41" + wire $eq$ls180.v:7923$2503_Y + attribute \src "ls180.v:7929.49-7929.82" + wire $eq$ls180.v:7929$2504_Y + attribute \src "ls180.v:7929.131-7929.164" + wire $eq$ls180.v:7929$2507_Y + attribute \src "ls180.v:7929.213-7929.246" + wire $eq$ls180.v:7929$2510_Y + attribute \src "ls180.v:7929.295-7929.328" + wire $eq$ls180.v:7929$2513_Y + attribute \src "ls180.v:7930.50-7930.83" + wire $eq$ls180.v:7930$2516_Y + attribute \src "ls180.v:7930.132-7930.165" + wire $eq$ls180.v:7930$2519_Y + attribute \src "ls180.v:7930.214-7930.247" + wire $eq$ls180.v:7930$2522_Y + attribute \src "ls180.v:7930.296-7930.329" + wire $eq$ls180.v:7930$2525_Y + attribute \src "ls180.v:7965.9-7965.42" + wire $eq$ls180.v:7965$2537_Y + attribute \src "ls180.v:7968.10-7968.43" + wire $eq$ls180.v:7968$2538_Y + attribute \src "ls180.v:7994.9-7994.42" + wire $eq$ls180.v:7994$2544_Y + attribute \src "ls180.v:7999.10-7999.43" + wire $eq$ls180.v:7999$2545_Y + attribute \src "ls180.v:8206.9-8206.53" + wire $eq$ls180.v:8206$2594_Y + attribute \src "ls180.v:8287.9-8287.54" + wire $eq$ls180.v:8287$2606_Y + attribute \src "ls180.v:8366.9-8366.55" + wire $eq$ls180.v:8366$2618_Y + attribute \src "ls180.v:8589.9-8589.49" + wire $eq$ls180.v:8589$2651_Y + attribute \src "ls180.v:8165.8-8165.54" + wire $ge$ls180.v:8165$2586_Y + attribute \src "ls180.v:8179.8-8179.54" + wire $ge$ls180.v:8179$2590_Y + attribute \src "ls180.v:5151.47-5151.83" + wire $gt$ls180.v:5151$914_Y + attribute \src "ls180.v:5157.7-5157.43" + wire $lt$ls180.v:5157$917_Y + attribute \src "ls180.v:8160.8-8160.43" + wire $lt$ls180.v:8160$2584_Y + attribute \src "ls180.v:8174.8-8174.43" + wire $lt$ls180.v:8174$2588_Y + attribute \src "ls180.v:10055.33-10055.36" + wire width 32 $memrd$\mem$ls180.v:10055$2693_DATA + attribute \src "ls180.v:10066.12-10066.19" + wire width 25 $memrd$\storage$ls180.v:10066$2698_DATA + attribute \src "ls180.v:10073.68-10073.75" + wire width 25 $memrd$\storage$ls180.v:10073$2700_DATA + attribute \src "ls180.v:10080.14-10080.23" + wire width 25 $memrd$\storage_1$ls180.v:10080$2705_DATA + attribute \src "ls180.v:10087.68-10087.77" + wire width 25 $memrd$\storage_1$ls180.v:10087$2707_DATA + attribute \src "ls180.v:10094.14-10094.23" + wire width 25 $memrd$\storage_2$ls180.v:10094$2712_DATA + attribute \src "ls180.v:10101.68-10101.77" + wire width 25 $memrd$\storage_2$ls180.v:10101$2714_DATA + attribute \src "ls180.v:10108.14-10108.23" + wire width 25 $memrd$\storage_3$ls180.v:10108$2719_DATA + attribute \src "ls180.v:10115.68-10115.77" + wire width 25 $memrd$\storage_3$ls180.v:10115$2721_DATA + attribute \src "ls180.v:10123.14-10123.23" + wire width 10 $memrd$\storage_4$ls180.v:10123$2726_DATA + attribute \src "ls180.v:10128.15-10128.24" + wire width 10 $memrd$\storage_4$ls180.v:10128$2728_DATA + attribute \src "ls180.v:10140.14-10140.23" + wire width 10 $memrd$\storage_5$ls180.v:10140$2733_DATA + attribute \src "ls180.v:10145.15-10145.24" + wire width 10 $memrd$\storage_5$ls180.v:10145$2735_DATA + attribute \src "ls180.v:10156.14-10156.23" + wire width 10 $memrd$\storage_6$ls180.v:10156$2740_DATA + attribute \src "ls180.v:10163.45-10163.54" + wire width 10 $memrd$\storage_6$ls180.v:10163$2742_DATA + attribute \src "ls180.v:10170.14-10170.23" + wire width 10 $memrd$\storage_7$ls180.v:10170$2747_DATA + attribute \src "ls180.v:10177.45-10177.54" + wire width 10 $memrd$\storage_7$ls180.v:10177$2749_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10045$1_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10045$1_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10045$1_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10047$2_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10047$2_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10047$2_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10049$3_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10049$3_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10049$3_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10051$4_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10051$4_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10051$4_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage$ls180.v:10065$5_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10065$5_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10065$5_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_1$ls180.v:10079$6_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10079$6_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10079$6_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_2$ls180.v:10093$7_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10093$7_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10093$7_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_3$ls180.v:10107$8_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10107$8_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10107$8_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_4$ls180.v:10122$9_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10122$9_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10122$9_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 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$xor$ls180.v:4960$825_Y + attribute \src "ls180.v:4960.164-4960.278" + wire $xor$ls180.v:4960$826_Y + attribute \src "ls180.v:4961.360-4961.432" + wire $xor$ls180.v:4961$827_Y + attribute \src "ls180.v:4961.205-4961.277" + wire $xor$ls180.v:4961$828_Y + attribute \src "ls180.v:4961.164-4961.278" + wire $xor$ls180.v:4961$829_Y + attribute \src "ls180.v:4982.899-4982.983" + wire $xor$ls180.v:4982$843_Y + attribute \src "ls180.v:4982.634-4982.718" + wire $xor$ls180.v:4982$844_Y + attribute \src "ls180.v:4982.588-4982.719" + wire $xor$ls180.v:4982$845_Y + attribute \src "ls180.v:4982.234-4982.318" + wire $xor$ls180.v:4982$846_Y + attribute \src "ls180.v:4982.187-4982.319" + wire $xor$ls180.v:4982$847_Y + attribute \src "ls180.v:4983.899-4983.983" + wire $xor$ls180.v:4983$848_Y + attribute \src "ls180.v:4983.634-4983.718" + wire $xor$ls180.v:4983$849_Y + attribute \src "ls180.v:4983.588-4983.719" + wire $xor$ls180.v:4983$850_Y + attribute \src "ls180.v:4983.234-4983.318" + wire $xor$ls180.v:4983$851_Y + attribute \src "ls180.v:4983.187-4983.319" + wire $xor$ls180.v:4983$852_Y + attribute \src "ls180.v:4992.899-4992.983" + wire $xor$ls180.v:4992$854_Y + attribute \src "ls180.v:4992.634-4992.718" + wire $xor$ls180.v:4992$855_Y + attribute \src "ls180.v:4992.588-4992.719" + wire $xor$ls180.v:4992$856_Y + attribute \src "ls180.v:4992.234-4992.318" + wire $xor$ls180.v:4992$857_Y + attribute \src "ls180.v:4992.187-4992.319" + wire $xor$ls180.v:4992$858_Y + attribute \src "ls180.v:4993.899-4993.983" + wire $xor$ls180.v:4993$859_Y + attribute \src "ls180.v:4993.634-4993.718" + wire $xor$ls180.v:4993$860_Y + attribute \src "ls180.v:4993.588-4993.719" + wire $xor$ls180.v:4993$861_Y + attribute \src "ls180.v:4993.234-4993.318" + wire $xor$ls180.v:4993$862_Y + attribute \src "ls180.v:4993.187-4993.319" + wire $xor$ls180.v:4993$863_Y + attribute \src "ls180.v:5002.899-5002.983" + wire $xor$ls180.v:5002$865_Y + attribute \src "ls180.v:5002.634-5002.718" + wire $xor$ls180.v:5002$866_Y + attribute \src "ls180.v:5002.588-5002.719" + wire $xor$ls180.v:5002$867_Y + attribute \src "ls180.v:5002.234-5002.318" + wire $xor$ls180.v:5002$868_Y + attribute \src "ls180.v:5002.187-5002.319" + wire $xor$ls180.v:5002$869_Y + attribute \src "ls180.v:5003.899-5003.983" + wire $xor$ls180.v:5003$870_Y + attribute \src "ls180.v:5003.634-5003.718" + wire $xor$ls180.v:5003$871_Y + attribute \src "ls180.v:5003.588-5003.719" + wire $xor$ls180.v:5003$872_Y + attribute \src "ls180.v:5003.234-5003.318" + wire $xor$ls180.v:5003$873_Y + attribute \src "ls180.v:5003.187-5003.319" + wire $xor$ls180.v:5003$874_Y + attribute \src "ls180.v:5012.899-5012.983" + wire $xor$ls180.v:5012$876_Y + attribute \src "ls180.v:5012.634-5012.718" + wire $xor$ls180.v:5012$877_Y + attribute \src "ls180.v:5012.588-5012.719" + wire $xor$ls180.v:5012$878_Y + attribute \src "ls180.v:5012.234-5012.318" + wire $xor$ls180.v:5012$879_Y + attribute \src "ls180.v:5012.187-5012.319" + wire $xor$ls180.v:5012$880_Y + attribute \src "ls180.v:5013.899-5013.983" + wire $xor$ls180.v:5013$881_Y + attribute \src "ls180.v:5013.634-5013.718" + wire $xor$ls180.v:5013$882_Y + attribute \src "ls180.v:5013.588-5013.719" + wire $xor$ls180.v:5013$883_Y + attribute \src "ls180.v:5013.234-5013.318" + wire $xor$ls180.v:5013$884_Y + attribute \src "ls180.v:5013.187-5013.319" + wire $xor$ls180.v:5013$885_Y + attribute \src "ls180.v:5164.879-5164.961" + wire $xor$ls180.v:5164$918_Y + attribute \src "ls180.v:5164.620-5164.702" + wire $xor$ls180.v:5164$919_Y + attribute \src "ls180.v:5164.575-5164.703" + wire $xor$ls180.v:5164$920_Y + attribute \src "ls180.v:5164.229-5164.311" + wire $xor$ls180.v:5164$921_Y + attribute \src "ls180.v:5164.183-5164.312" + wire $xor$ls180.v:5164$922_Y + attribute \src "ls180.v:5165.879-5165.961" + wire $xor$ls180.v:5165$923_Y + attribute \src "ls180.v:5165.620-5165.702" + wire $xor$ls180.v:5165$924_Y + attribute \src "ls180.v:5165.575-5165.703" + wire $xor$ls180.v:5165$925_Y + attribute \src "ls180.v:5165.229-5165.311" + wire $xor$ls180.v:5165$926_Y + attribute \src "ls180.v:5165.183-5165.312" + wire $xor$ls180.v:5165$927_Y + attribute \src "ls180.v:5174.879-5174.961" + wire $xor$ls180.v:5174$929_Y + attribute \src "ls180.v:5174.620-5174.702" + wire $xor$ls180.v:5174$930_Y + attribute \src "ls180.v:5174.575-5174.703" + wire $xor$ls180.v:5174$931_Y + attribute \src "ls180.v:5174.229-5174.311" + wire $xor$ls180.v:5174$932_Y + attribute \src "ls180.v:5174.183-5174.312" + wire $xor$ls180.v:5174$933_Y + attribute \src "ls180.v:5175.879-5175.961" + wire $xor$ls180.v:5175$934_Y + attribute \src "ls180.v:5175.620-5175.702" + wire $xor$ls180.v:5175$935_Y + attribute \src "ls180.v:5175.575-5175.703" + wire $xor$ls180.v:5175$936_Y + attribute \src "ls180.v:5175.229-5175.311" + wire $xor$ls180.v:5175$937_Y + attribute \src "ls180.v:5175.183-5175.312" + wire $xor$ls180.v:5175$938_Y + attribute \src "ls180.v:5184.879-5184.961" + wire $xor$ls180.v:5184$940_Y + attribute \src "ls180.v:5184.620-5184.702" + wire $xor$ls180.v:5184$941_Y + attribute \src "ls180.v:5184.575-5184.703" + wire $xor$ls180.v:5184$942_Y + attribute \src "ls180.v:5184.229-5184.311" + wire $xor$ls180.v:5184$943_Y + attribute \src "ls180.v:5184.183-5184.312" + wire $xor$ls180.v:5184$944_Y + attribute \src "ls180.v:5185.879-5185.961" + wire $xor$ls180.v:5185$945_Y + attribute \src "ls180.v:5185.620-5185.702" + wire $xor$ls180.v:5185$946_Y + attribute \src "ls180.v:5185.575-5185.703" + wire $xor$ls180.v:5185$947_Y + attribute \src "ls180.v:5185.229-5185.311" + wire $xor$ls180.v:5185$948_Y + attribute \src "ls180.v:5185.183-5185.312" + wire $xor$ls180.v:5185$949_Y + attribute \src "ls180.v:5194.879-5194.961" + wire $xor$ls180.v:5194$951_Y + attribute \src "ls180.v:5194.620-5194.702" + wire $xor$ls180.v:5194$952_Y + attribute \src "ls180.v:5194.575-5194.703" + wire $xor$ls180.v:5194$953_Y + attribute \src "ls180.v:5194.229-5194.311" + wire $xor$ls180.v:5194$954_Y + attribute \src "ls180.v:5194.183-5194.312" + wire $xor$ls180.v:5194$955_Y + attribute \src "ls180.v:5195.879-5195.961" + wire $xor$ls180.v:5195$956_Y + attribute \src "ls180.v:5195.620-5195.702" + wire $xor$ls180.v:5195$957_Y + attribute \src "ls180.v:5195.575-5195.703" + wire $xor$ls180.v:5195$958_Y + attribute \src "ls180.v:5195.229-5195.311" + wire $xor$ls180.v:5195$959_Y + attribute \src "ls180.v:5195.183-5195.312" + wire $xor$ls180.v:5195$960_Y + attribute \src "ls180.v:1745.11-1745.42" + wire width 3 \builder_bankmachine0_next_state + attribute \src "ls180.v:1744.11-1744.37" + wire width 3 \builder_bankmachine0_state + attribute \src "ls180.v:1747.11-1747.42" + wire width 3 \builder_bankmachine1_next_state + attribute \src "ls180.v:1746.11-1746.37" + wire width 3 \builder_bankmachine1_state + attribute \src "ls180.v:1749.11-1749.42" + wire width 3 \builder_bankmachine2_next_state + attribute \src "ls180.v:1748.11-1748.37" + wire width 3 \builder_bankmachine2_state + attribute \src "ls180.v:1751.11-1751.42" + wire width 3 \builder_bankmachine3_next_state + attribute \src "ls180.v:1750.11-1750.37" + wire width 3 \builder_bankmachine3_state + attribute \src "ls180.v:2596.5-2596.34" + wire \builder_comb_rhs_array_muxed0 + attribute \src "ls180.v:2597.12-2597.41" + wire width 13 \builder_comb_rhs_array_muxed1 + attribute \src "ls180.v:2609.5-2609.35" + wire \builder_comb_rhs_array_muxed10 + attribute \src "ls180.v:2610.5-2610.35" + wire \builder_comb_rhs_array_muxed11 + attribute \src "ls180.v:2614.12-2614.42" + wire width 22 \builder_comb_rhs_array_muxed12 + attribute \src "ls180.v:2615.5-2615.35" + wire \builder_comb_rhs_array_muxed13 + attribute \src "ls180.v:2616.5-2616.35" + wire \builder_comb_rhs_array_muxed14 + attribute \src "ls180.v:2617.12-2617.42" + wire width 22 \builder_comb_rhs_array_muxed15 + attribute \src "ls180.v:2618.5-2618.35" + wire \builder_comb_rhs_array_muxed16 + attribute \src "ls180.v:2619.5-2619.35" + wire \builder_comb_rhs_array_muxed17 + attribute \src "ls180.v:2620.12-2620.42" + wire width 22 \builder_comb_rhs_array_muxed18 + attribute \src "ls180.v:2621.5-2621.35" + wire \builder_comb_rhs_array_muxed19 + attribute \src "ls180.v:2598.11-2598.40" + wire width 2 \builder_comb_rhs_array_muxed2 + attribute \src "ls180.v:2622.5-2622.35" + wire \builder_comb_rhs_array_muxed20 + attribute \src "ls180.v:2623.12-2623.42" + wire width 22 \builder_comb_rhs_array_muxed21 + attribute \src "ls180.v:2624.5-2624.35" + wire \builder_comb_rhs_array_muxed22 + attribute \src "ls180.v:2625.5-2625.35" + wire \builder_comb_rhs_array_muxed23 + attribute \src "ls180.v:2626.12-2626.42" + wire width 32 \builder_comb_rhs_array_muxed24 + attribute \src "ls180.v:2627.12-2627.42" + wire width 32 \builder_comb_rhs_array_muxed25 + attribute \src "ls180.v:2628.11-2628.41" + wire width 4 \builder_comb_rhs_array_muxed26 + attribute \src "ls180.v:2629.5-2629.35" + wire \builder_comb_rhs_array_muxed27 + attribute \src "ls180.v:2630.5-2630.35" + wire \builder_comb_rhs_array_muxed28 + attribute \src "ls180.v:2631.5-2631.35" + wire \builder_comb_rhs_array_muxed29 + attribute \src "ls180.v:2599.5-2599.34" + wire \builder_comb_rhs_array_muxed3 + attribute \src "ls180.v:2632.11-2632.41" + wire width 3 \builder_comb_rhs_array_muxed30 + attribute \src "ls180.v:2633.11-2633.41" + wire width 2 \builder_comb_rhs_array_muxed31 + attribute \src "ls180.v:2600.5-2600.34" + wire \builder_comb_rhs_array_muxed4 + attribute \src "ls180.v:2601.5-2601.34" + wire \builder_comb_rhs_array_muxed5 + attribute \src "ls180.v:2605.5-2605.34" + wire \builder_comb_rhs_array_muxed6 + attribute \src "ls180.v:2606.12-2606.41" + wire width 13 \builder_comb_rhs_array_muxed7 + attribute \src "ls180.v:2607.11-2607.40" + wire width 2 \builder_comb_rhs_array_muxed8 + attribute \src "ls180.v:2608.5-2608.34" + wire \builder_comb_rhs_array_muxed9 + attribute \src "ls180.v:2602.5-2602.32" + wire \builder_comb_t_array_muxed0 + attribute \src "ls180.v:2603.5-2603.32" + wire \builder_comb_t_array_muxed1 + attribute \src "ls180.v:2604.5-2604.32" + wire \builder_comb_t_array_muxed2 + attribute \src "ls180.v:2611.5-2611.32" + wire \builder_comb_t_array_muxed3 + attribute \src "ls180.v:2612.5-2612.32" + wire \builder_comb_t_array_muxed4 + attribute \src "ls180.v:2613.5-2613.32" + wire \builder_comb_t_array_muxed5 + attribute \src "ls180.v:1731.5-1731.34" + wire \builder_converter0_next_state + attribute \src "ls180.v:1730.5-1730.29" + wire \builder_converter0_state + attribute \src "ls180.v:1735.5-1735.34" + wire \builder_converter1_next_state + attribute \src "ls180.v:1734.5-1734.29" + wire \builder_converter1_state + attribute \src "ls180.v:1739.5-1739.34" + wire \builder_converter2_next_state + attribute \src "ls180.v:1738.5-1738.29" + wire \builder_converter2_state + attribute \src "ls180.v:1776.5-1776.33" + wire \builder_converter_next_state + attribute \src "ls180.v:1775.5-1775.28" + wire \builder_converter_state + attribute \src "ls180.v:1896.12-1896.25" + wire width 20 \builder_count + attribute \src "ls180.v:2584.13-2584.41" + wire width 14 \builder_csr_interconnect_adr + attribute \src "ls180.v:2587.12-2587.42" + wire width 8 \builder_csr_interconnect_dat_r + attribute \src "ls180.v:2586.12-2586.42" + wire width 8 \builder_csr_interconnect_dat_w + attribute \src "ls180.v:2585.6-2585.33" + wire \builder_csr_interconnect_we + attribute \src "ls180.v:1934.12-1934.42" + wire width 8 \builder_csrbank0_bus_errors0_r + attribute \src "ls180.v:1933.6-1933.37" + wire \builder_csrbank0_bus_errors0_re + attribute \src "ls180.v:1936.12-1936.42" + wire width 8 \builder_csrbank0_bus_errors0_w + attribute \src "ls180.v:1935.6-1935.37" + wire \builder_csrbank0_bus_errors0_we + attribute \src "ls180.v:1930.12-1930.42" + wire width 8 \builder_csrbank0_bus_errors1_r + attribute \src "ls180.v:1929.6-1929.37" + wire \builder_csrbank0_bus_errors1_re + attribute \src "ls180.v:1932.12-1932.42" + wire width 8 \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:1931.6-1931.37" + wire \builder_csrbank0_bus_errors1_we + attribute \src "ls180.v:1926.12-1926.42" + wire width 8 \builder_csrbank0_bus_errors2_r + attribute \src "ls180.v:1925.6-1925.37" + wire \builder_csrbank0_bus_errors2_re + attribute \src "ls180.v:1928.12-1928.42" + wire width 8 \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:1927.6-1927.37" + wire \builder_csrbank0_bus_errors2_we + attribute \src "ls180.v:1922.12-1922.42" + wire width 8 \builder_csrbank0_bus_errors3_r + attribute \src "ls180.v:1921.6-1921.37" + wire \builder_csrbank0_bus_errors3_re + attribute \src "ls180.v:1924.12-1924.42" + wire width 8 \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:1923.6-1923.37" + wire \builder_csrbank0_bus_errors3_we + attribute \src "ls180.v:1902.6-1902.31" + wire \builder_csrbank0_reset0_r + attribute \src "ls180.v:1901.6-1901.32" + wire \builder_csrbank0_reset0_re + attribute \src "ls180.v:1904.6-1904.31" + wire \builder_csrbank0_reset0_w + attribute \src "ls180.v:1903.6-1903.32" + wire \builder_csrbank0_reset0_we + attribute \src "ls180.v:1918.12-1918.39" + wire width 8 \builder_csrbank0_scratch0_r + attribute \src "ls180.v:1917.6-1917.34" + wire \builder_csrbank0_scratch0_re + attribute \src "ls180.v:1920.12-1920.39" + wire width 8 \builder_csrbank0_scratch0_w + attribute \src "ls180.v:1919.6-1919.34" + wire \builder_csrbank0_scratch0_we + attribute \src "ls180.v:1914.12-1914.39" + wire width 8 \builder_csrbank0_scratch1_r + attribute \src "ls180.v:1913.6-1913.34" + wire \builder_csrbank0_scratch1_re + attribute \src "ls180.v:1916.12-1916.39" + wire width 8 \builder_csrbank0_scratch1_w + attribute \src "ls180.v:1915.6-1915.34" + wire \builder_csrbank0_scratch1_we + attribute \src "ls180.v:1910.12-1910.39" + wire width 8 \builder_csrbank0_scratch2_r + attribute \src "ls180.v:1909.6-1909.34" + wire \builder_csrbank0_scratch2_re + attribute \src "ls180.v:1912.12-1912.39" + wire width 8 \builder_csrbank0_scratch2_w + attribute \src "ls180.v:1911.6-1911.34" + wire \builder_csrbank0_scratch2_we + attribute \src "ls180.v:1906.12-1906.39" + wire width 8 \builder_csrbank0_scratch3_r + attribute \src "ls180.v:1905.6-1905.34" + wire \builder_csrbank0_scratch3_re + attribute \src "ls180.v:1908.12-1908.39" + wire width 8 \builder_csrbank0_scratch3_w + attribute \src "ls180.v:1907.6-1907.34" + wire \builder_csrbank0_scratch3_we + attribute \src "ls180.v:1937.6-1937.26" + wire \builder_csrbank0_sel + attribute \src "ls180.v:2408.12-2408.40" + wire width 8 \builder_csrbank10_control0_r + attribute \src "ls180.v:2407.6-2407.35" + wire \builder_csrbank10_control0_re + attribute \src "ls180.v:2410.12-2410.40" + wire width 8 \builder_csrbank10_control0_w + attribute \src "ls180.v:2409.6-2409.35" + wire \builder_csrbank10_control0_we + attribute \src "ls180.v:2404.12-2404.40" + wire width 8 \builder_csrbank10_control1_r + attribute \src "ls180.v:2403.6-2403.35" + wire \builder_csrbank10_control1_re + attribute \src "ls180.v:2406.12-2406.40" + wire width 8 \builder_csrbank10_control1_w + attribute \src "ls180.v:2405.6-2405.35" + wire \builder_csrbank10_control1_we + attribute \src "ls180.v:2424.6-2424.29" + wire \builder_csrbank10_cs0_r + attribute \src "ls180.v:2423.6-2423.30" + wire \builder_csrbank10_cs0_re + attribute \src "ls180.v:2426.6-2426.29" + wire \builder_csrbank10_cs0_w + attribute \src "ls180.v:2425.6-2425.30" + wire \builder_csrbank10_cs0_we + attribute \src "ls180.v:2428.6-2428.35" + wire \builder_csrbank10_loopback0_r + attribute \src "ls180.v:2427.6-2427.36" + wire \builder_csrbank10_loopback0_re + attribute \src "ls180.v:2430.6-2430.35" + wire \builder_csrbank10_loopback0_w + attribute \src "ls180.v:2429.6-2429.36" + wire \builder_csrbank10_loopback0_we + attribute \src "ls180.v:2420.12-2420.36" + wire width 8 \builder_csrbank10_miso_r + attribute \src "ls180.v:2419.6-2419.31" + wire \builder_csrbank10_miso_re + attribute \src "ls180.v:2422.12-2422.36" + wire width 8 \builder_csrbank10_miso_w + attribute \src "ls180.v:2421.6-2421.31" + wire \builder_csrbank10_miso_we + attribute \src "ls180.v:2416.12-2416.37" + wire width 8 \builder_csrbank10_mosi0_r + attribute \src "ls180.v:2415.6-2415.32" + wire \builder_csrbank10_mosi0_re + attribute \src "ls180.v:2418.12-2418.37" + wire width 8 \builder_csrbank10_mosi0_w + attribute \src "ls180.v:2417.6-2417.32" + wire \builder_csrbank10_mosi0_we + attribute \src "ls180.v:2431.6-2431.27" + wire \builder_csrbank10_sel + attribute \src "ls180.v:2412.6-2412.32" + wire \builder_csrbank10_status_r + attribute \src "ls180.v:2411.6-2411.33" + wire \builder_csrbank10_status_re + attribute \src "ls180.v:2414.6-2414.32" + wire \builder_csrbank10_status_w + attribute \src "ls180.v:2413.6-2413.33" + wire \builder_csrbank10_status_we + attribute \src "ls180.v:2469.12-2469.44" + wire width 8 \builder_csrbank11_clk_divider0_r + attribute \src "ls180.v:2468.6-2468.39" + wire \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:2471.12-2471.44" + wire width 8 \builder_csrbank11_clk_divider0_w + attribute \src "ls180.v:2470.6-2470.39" + wire \builder_csrbank11_clk_divider0_we + attribute \src "ls180.v:2465.12-2465.44" + wire width 8 \builder_csrbank11_clk_divider1_r + attribute \src "ls180.v:2464.6-2464.39" + wire \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:2467.12-2467.44" + wire width 8 \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:2466.6-2466.39" + wire \builder_csrbank11_clk_divider1_we + attribute \src "ls180.v:2441.12-2441.40" + wire width 8 \builder_csrbank11_control0_r + attribute \src "ls180.v:2440.6-2440.35" + wire \builder_csrbank11_control0_re + attribute \src "ls180.v:2443.12-2443.40" + wire width 8 \builder_csrbank11_control0_w + attribute \src "ls180.v:2442.6-2442.35" + wire \builder_csrbank11_control0_we + attribute \src "ls180.v:2437.12-2437.40" + wire width 8 \builder_csrbank11_control1_r + attribute \src "ls180.v:2436.6-2436.35" + wire \builder_csrbank11_control1_re + attribute \src "ls180.v:2439.12-2439.40" + wire width 8 \builder_csrbank11_control1_w + attribute \src "ls180.v:2438.6-2438.35" + wire \builder_csrbank11_control1_we + attribute \src "ls180.v:2457.6-2457.29" + wire \builder_csrbank11_cs0_r + attribute \src "ls180.v:2456.6-2456.30" + wire \builder_csrbank11_cs0_re + attribute \src "ls180.v:2459.6-2459.29" + wire \builder_csrbank11_cs0_w + attribute \src "ls180.v:2458.6-2458.30" + wire \builder_csrbank11_cs0_we + attribute \src "ls180.v:2461.6-2461.35" + wire \builder_csrbank11_loopback0_r + attribute \src "ls180.v:2460.6-2460.36" + wire \builder_csrbank11_loopback0_re + attribute \src "ls180.v:2463.6-2463.35" + wire \builder_csrbank11_loopback0_w + attribute \src "ls180.v:2462.6-2462.36" + wire \builder_csrbank11_loopback0_we + attribute \src "ls180.v:2453.12-2453.36" + wire width 8 \builder_csrbank11_miso_r + attribute \src "ls180.v:2452.6-2452.31" + wire \builder_csrbank11_miso_re + attribute \src "ls180.v:2455.12-2455.36" + wire width 8 \builder_csrbank11_miso_w + attribute \src "ls180.v:2454.6-2454.31" + wire \builder_csrbank11_miso_we + attribute \src "ls180.v:2449.12-2449.37" + wire width 8 \builder_csrbank11_mosi0_r + attribute \src "ls180.v:2448.6-2448.32" + wire \builder_csrbank11_mosi0_re + attribute \src "ls180.v:2451.12-2451.37" + wire width 8 \builder_csrbank11_mosi0_w + attribute \src "ls180.v:2450.6-2450.32" + wire \builder_csrbank11_mosi0_we + attribute \src "ls180.v:2472.6-2472.27" + wire \builder_csrbank11_sel + attribute \src "ls180.v:2445.6-2445.32" + wire \builder_csrbank11_status_r + attribute \src "ls180.v:2444.6-2444.33" + wire \builder_csrbank11_status_re + attribute \src "ls180.v:2447.6-2447.32" + wire \builder_csrbank11_status_w + attribute \src "ls180.v:2446.6-2446.33" + wire \builder_csrbank11_status_we + attribute \src "ls180.v:2510.6-2510.29" + wire \builder_csrbank12_en0_r + attribute \src "ls180.v:2509.6-2509.30" + wire \builder_csrbank12_en0_re + attribute \src "ls180.v:2512.6-2512.29" + wire \builder_csrbank12_en0_w + attribute \src "ls180.v:2511.6-2511.30" + wire \builder_csrbank12_en0_we + attribute \src "ls180.v:2534.6-2534.36" + wire \builder_csrbank12_ev_enable0_r + attribute \src "ls180.v:2533.6-2533.37" + wire \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:2536.6-2536.36" + wire \builder_csrbank12_ev_enable0_w + attribute \src "ls180.v:2535.6-2535.37" + wire \builder_csrbank12_ev_enable0_we + attribute \src "ls180.v:2490.12-2490.37" + wire width 8 \builder_csrbank12_load0_r + attribute \src "ls180.v:2489.6-2489.32" + wire \builder_csrbank12_load0_re + attribute \src "ls180.v:2492.12-2492.37" + wire width 8 \builder_csrbank12_load0_w + attribute \src "ls180.v:2491.6-2491.32" + wire \builder_csrbank12_load0_we + attribute \src "ls180.v:2486.12-2486.37" + wire width 8 \builder_csrbank12_load1_r + attribute \src "ls180.v:2485.6-2485.32" + wire \builder_csrbank12_load1_re + attribute \src "ls180.v:2488.12-2488.37" + wire width 8 \builder_csrbank12_load1_w + attribute \src "ls180.v:2487.6-2487.32" + wire \builder_csrbank12_load1_we + attribute \src "ls180.v:2482.12-2482.37" + wire width 8 \builder_csrbank12_load2_r + attribute \src "ls180.v:2481.6-2481.32" + wire \builder_csrbank12_load2_re + attribute \src "ls180.v:2484.12-2484.37" + wire width 8 \builder_csrbank12_load2_w + attribute \src "ls180.v:2483.6-2483.32" + wire \builder_csrbank12_load2_we + attribute \src "ls180.v:2478.12-2478.37" + wire width 8 \builder_csrbank12_load3_r + attribute \src "ls180.v:2477.6-2477.32" + wire \builder_csrbank12_load3_re + attribute \src "ls180.v:2480.12-2480.37" + wire width 8 \builder_csrbank12_load3_w + attribute \src "ls180.v:2479.6-2479.32" + wire \builder_csrbank12_load3_we + attribute \src "ls180.v:2506.12-2506.39" + wire width 8 \builder_csrbank12_reload0_r + attribute \src "ls180.v:2505.6-2505.34" + wire \builder_csrbank12_reload0_re + attribute \src "ls180.v:2508.12-2508.39" + wire width 8 \builder_csrbank12_reload0_w + attribute \src "ls180.v:2507.6-2507.34" + wire \builder_csrbank12_reload0_we + attribute \src "ls180.v:2502.12-2502.39" + wire width 8 \builder_csrbank12_reload1_r + attribute \src "ls180.v:2501.6-2501.34" + wire \builder_csrbank12_reload1_re + attribute \src "ls180.v:2504.12-2504.39" + wire width 8 \builder_csrbank12_reload1_w + attribute \src "ls180.v:2503.6-2503.34" + wire \builder_csrbank12_reload1_we + attribute \src "ls180.v:2498.12-2498.39" + wire width 8 \builder_csrbank12_reload2_r + attribute \src "ls180.v:2497.6-2497.34" + wire \builder_csrbank12_reload2_re + attribute \src "ls180.v:2500.12-2500.39" + wire width 8 \builder_csrbank12_reload2_w + attribute \src "ls180.v:2499.6-2499.34" + wire \builder_csrbank12_reload2_we + attribute \src "ls180.v:2494.12-2494.39" + wire width 8 \builder_csrbank12_reload3_r + attribute \src "ls180.v:2493.6-2493.34" + wire \builder_csrbank12_reload3_re + attribute \src "ls180.v:2496.12-2496.39" + wire width 8 \builder_csrbank12_reload3_w + attribute \src "ls180.v:2495.6-2495.34" + wire \builder_csrbank12_reload3_we + attribute \src "ls180.v:2537.6-2537.27" + wire \builder_csrbank12_sel + attribute \src "ls180.v:2514.6-2514.39" + wire \builder_csrbank12_update_value0_r + attribute \src "ls180.v:2513.6-2513.40" + wire \builder_csrbank12_update_value0_re + attribute \src "ls180.v:2516.6-2516.39" + wire \builder_csrbank12_update_value0_w + attribute \src "ls180.v:2515.6-2515.40" + wire \builder_csrbank12_update_value0_we + attribute \src "ls180.v:2530.12-2530.38" + wire width 8 \builder_csrbank12_value0_r + attribute \src "ls180.v:2529.6-2529.33" + wire \builder_csrbank12_value0_re + attribute \src "ls180.v:2532.12-2532.38" + wire width 8 \builder_csrbank12_value0_w + attribute \src "ls180.v:2531.6-2531.33" + wire \builder_csrbank12_value0_we + attribute \src "ls180.v:2526.12-2526.38" + wire width 8 \builder_csrbank12_value1_r + attribute \src "ls180.v:2525.6-2525.33" + wire \builder_csrbank12_value1_re + attribute \src "ls180.v:2528.12-2528.38" + wire width 8 \builder_csrbank12_value1_w + attribute \src "ls180.v:2527.6-2527.33" + wire \builder_csrbank12_value1_we + attribute \src "ls180.v:2522.12-2522.38" + wire width 8 \builder_csrbank12_value2_r + attribute \src "ls180.v:2521.6-2521.33" + wire \builder_csrbank12_value2_re + attribute \src "ls180.v:2524.12-2524.38" + wire width 8 \builder_csrbank12_value2_w + attribute \src "ls180.v:2523.6-2523.33" + wire \builder_csrbank12_value2_we + attribute \src "ls180.v:2518.12-2518.38" + wire width 8 \builder_csrbank12_value3_r + attribute \src "ls180.v:2517.6-2517.33" + wire \builder_csrbank12_value3_re + attribute \src "ls180.v:2520.12-2520.38" + wire width 8 \builder_csrbank12_value3_w + attribute \src "ls180.v:2519.6-2519.33" + wire \builder_csrbank12_value3_we + attribute \src "ls180.v:2551.12-2551.42" + wire width 2 \builder_csrbank13_ev_enable0_r + attribute \src "ls180.v:2550.6-2550.37" + wire \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:2553.12-2553.42" + wire width 2 \builder_csrbank13_ev_enable0_w + attribute \src "ls180.v:2552.6-2552.37" + wire \builder_csrbank13_ev_enable0_we + attribute \src "ls180.v:2547.6-2547.33" + wire \builder_csrbank13_rxempty_r + attribute \src "ls180.v:2546.6-2546.34" + wire \builder_csrbank13_rxempty_re + attribute \src "ls180.v:2549.6-2549.33" + wire \builder_csrbank13_rxempty_w + attribute \src "ls180.v:2548.6-2548.34" + wire \builder_csrbank13_rxempty_we + attribute \src "ls180.v:2559.6-2559.32" + wire \builder_csrbank13_rxfull_r + attribute \src "ls180.v:2558.6-2558.33" + wire \builder_csrbank13_rxfull_re + attribute \src "ls180.v:2561.6-2561.32" + wire \builder_csrbank13_rxfull_w + attribute \src "ls180.v:2560.6-2560.33" + wire \builder_csrbank13_rxfull_we + attribute \src "ls180.v:2562.6-2562.27" + wire \builder_csrbank13_sel + attribute \src "ls180.v:2555.6-2555.33" + wire \builder_csrbank13_txempty_r + attribute \src "ls180.v:2554.6-2554.34" + wire \builder_csrbank13_txempty_re + attribute \src "ls180.v:2557.6-2557.33" + wire \builder_csrbank13_txempty_w + attribute \src "ls180.v:2556.6-2556.34" + wire \builder_csrbank13_txempty_we + attribute \src "ls180.v:2543.6-2543.32" + wire \builder_csrbank13_txfull_r + attribute \src "ls180.v:2542.6-2542.33" + wire \builder_csrbank13_txfull_re + attribute \src "ls180.v:2545.6-2545.32" + wire \builder_csrbank13_txfull_w + attribute \src "ls180.v:2544.6-2544.33" + wire \builder_csrbank13_txfull_we + attribute \src "ls180.v:2583.6-2583.27" + wire \builder_csrbank14_sel + attribute \src "ls180.v:2580.12-2580.44" + wire width 8 \builder_csrbank14_tuning_word0_r + attribute \src "ls180.v:2579.6-2579.39" + wire \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:2582.12-2582.44" + wire width 8 \builder_csrbank14_tuning_word0_w + attribute \src "ls180.v:2581.6-2581.39" + wire \builder_csrbank14_tuning_word0_we + attribute \src "ls180.v:2576.12-2576.44" + wire width 8 \builder_csrbank14_tuning_word1_r + attribute \src "ls180.v:2575.6-2575.39" + wire \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:2578.12-2578.44" + wire width 8 \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:2577.6-2577.39" + wire \builder_csrbank14_tuning_word1_we + attribute \src "ls180.v:2572.12-2572.44" + wire width 8 \builder_csrbank14_tuning_word2_r + attribute \src "ls180.v:2571.6-2571.39" + wire \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:2574.12-2574.44" + wire width 8 \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:2573.6-2573.39" + wire \builder_csrbank14_tuning_word2_we + attribute \src "ls180.v:2568.12-2568.44" + wire width 8 \builder_csrbank14_tuning_word3_r + attribute \src "ls180.v:2567.6-2567.39" + wire \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:2570.12-2570.44" + wire width 8 \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:2569.6-2569.39" + wire \builder_csrbank14_tuning_word3_we + attribute \src "ls180.v:1955.12-1955.34" + wire width 8 \builder_csrbank1_in0_r + attribute \src "ls180.v:1954.6-1954.29" + wire \builder_csrbank1_in0_re + attribute \src "ls180.v:1957.12-1957.34" + wire width 8 \builder_csrbank1_in0_w + attribute \src "ls180.v:1956.6-1956.29" + wire \builder_csrbank1_in0_we + attribute \src "ls180.v:1951.12-1951.34" + wire width 8 \builder_csrbank1_in1_r + attribute \src "ls180.v:1950.6-1950.29" + wire \builder_csrbank1_in1_re + attribute \src "ls180.v:1953.12-1953.34" + wire width 8 \builder_csrbank1_in1_w + attribute \src "ls180.v:1952.6-1952.29" + wire \builder_csrbank1_in1_we + attribute \src "ls180.v:1947.12-1947.34" + wire width 8 \builder_csrbank1_oe0_r + attribute \src "ls180.v:1946.6-1946.29" + wire \builder_csrbank1_oe0_re + attribute \src "ls180.v:1949.12-1949.34" + wire width 8 \builder_csrbank1_oe0_w + attribute \src "ls180.v:1948.6-1948.29" + wire \builder_csrbank1_oe0_we + attribute \src "ls180.v:1943.12-1943.34" + wire width 8 \builder_csrbank1_oe1_r + attribute \src "ls180.v:1942.6-1942.29" + wire \builder_csrbank1_oe1_re + attribute \src "ls180.v:1945.12-1945.34" + wire width 8 \builder_csrbank1_oe1_w + attribute \src "ls180.v:1944.6-1944.29" + wire \builder_csrbank1_oe1_we + attribute \src "ls180.v:1963.12-1963.35" + wire width 8 \builder_csrbank1_out0_r + attribute \src "ls180.v:1962.6-1962.30" + wire \builder_csrbank1_out0_re + attribute \src "ls180.v:1965.12-1965.35" + wire width 8 \builder_csrbank1_out0_w + attribute \src "ls180.v:1964.6-1964.30" + wire \builder_csrbank1_out0_we + attribute \src "ls180.v:1959.12-1959.35" + wire width 8 \builder_csrbank1_out1_r + attribute \src "ls180.v:1958.6-1958.30" + wire \builder_csrbank1_out1_re + attribute \src "ls180.v:1961.12-1961.35" + wire width 8 \builder_csrbank1_out1_w + attribute \src "ls180.v:1960.6-1960.30" + wire \builder_csrbank1_out1_we + attribute \src "ls180.v:1966.6-1966.26" + wire \builder_csrbank1_sel + attribute \src "ls180.v:1976.6-1976.26" + wire \builder_csrbank2_r_r + attribute \src "ls180.v:1975.6-1975.27" + wire \builder_csrbank2_r_re + attribute \src "ls180.v:1978.6-1978.26" + wire \builder_csrbank2_r_w + attribute \src "ls180.v:1977.6-1977.27" + wire \builder_csrbank2_r_we + attribute \src "ls180.v:1979.6-1979.26" + wire \builder_csrbank2_sel + attribute \src "ls180.v:1972.12-1972.33" + wire width 3 \builder_csrbank2_w0_r + attribute \src "ls180.v:1971.6-1971.28" + wire \builder_csrbank2_w0_re + attribute \src "ls180.v:1974.12-1974.33" + wire width 3 \builder_csrbank2_w0_w + attribute \src "ls180.v:1973.6-1973.28" + wire \builder_csrbank2_w0_we + attribute \src "ls180.v:1985.6-1985.32" + wire \builder_csrbank3_enable0_r + attribute \src "ls180.v:1984.6-1984.33" + wire \builder_csrbank3_enable0_re + attribute \src "ls180.v:1987.6-1987.32" + wire \builder_csrbank3_enable0_w + attribute \src "ls180.v:1986.6-1986.33" + wire \builder_csrbank3_enable0_we + attribute \src "ls180.v:2017.12-2017.38" + wire width 8 \builder_csrbank3_period0_r + attribute \src "ls180.v:2016.6-2016.33" + wire \builder_csrbank3_period0_re + attribute \src "ls180.v:2019.12-2019.38" + wire width 8 \builder_csrbank3_period0_w + attribute \src "ls180.v:2018.6-2018.33" + wire \builder_csrbank3_period0_we + attribute \src "ls180.v:2013.12-2013.38" + wire width 8 \builder_csrbank3_period1_r + attribute \src "ls180.v:2012.6-2012.33" + wire \builder_csrbank3_period1_re + attribute \src "ls180.v:2015.12-2015.38" + wire width 8 \builder_csrbank3_period1_w + attribute \src "ls180.v:2014.6-2014.33" + wire \builder_csrbank3_period1_we + attribute \src "ls180.v:2009.12-2009.38" + wire width 8 \builder_csrbank3_period2_r + attribute \src "ls180.v:2008.6-2008.33" + wire \builder_csrbank3_period2_re + attribute \src "ls180.v:2011.12-2011.38" + wire width 8 \builder_csrbank3_period2_w + attribute \src "ls180.v:2010.6-2010.33" + wire \builder_csrbank3_period2_we + attribute \src "ls180.v:2005.12-2005.38" + wire width 8 \builder_csrbank3_period3_r + attribute \src "ls180.v:2004.6-2004.33" + wire \builder_csrbank3_period3_re + attribute \src "ls180.v:2007.12-2007.38" + wire width 8 \builder_csrbank3_period3_w + attribute \src "ls180.v:2006.6-2006.33" + wire \builder_csrbank3_period3_we + attribute \src "ls180.v:2020.6-2020.26" + wire \builder_csrbank3_sel + attribute \src "ls180.v:2001.12-2001.37" + wire width 8 \builder_csrbank3_width0_r + attribute \src "ls180.v:2000.6-2000.32" + wire \builder_csrbank3_width0_re + attribute \src "ls180.v:2003.12-2003.37" + wire width 8 \builder_csrbank3_width0_w + attribute \src "ls180.v:2002.6-2002.32" + wire \builder_csrbank3_width0_we + attribute \src "ls180.v:1997.12-1997.37" + wire width 8 \builder_csrbank3_width1_r + attribute \src "ls180.v:1996.6-1996.32" + wire \builder_csrbank3_width1_re + attribute \src "ls180.v:1999.12-1999.37" + wire width 8 \builder_csrbank3_width1_w + attribute \src "ls180.v:1998.6-1998.32" + wire \builder_csrbank3_width1_we + attribute \src "ls180.v:1993.12-1993.37" + wire width 8 \builder_csrbank3_width2_r + attribute \src "ls180.v:1992.6-1992.32" + wire \builder_csrbank3_width2_re + attribute \src "ls180.v:1995.12-1995.37" + wire width 8 \builder_csrbank3_width2_w + attribute \src "ls180.v:1994.6-1994.32" + wire \builder_csrbank3_width2_we + attribute \src "ls180.v:1989.12-1989.37" + wire width 8 \builder_csrbank3_width3_r + attribute \src "ls180.v:1988.6-1988.32" + wire \builder_csrbank3_width3_re + attribute \src "ls180.v:1991.12-1991.37" + wire width 8 \builder_csrbank3_width3_w + attribute \src "ls180.v:1990.6-1990.32" + wire \builder_csrbank3_width3_we + attribute \src "ls180.v:2026.6-2026.32" + wire \builder_csrbank4_enable0_r + attribute \src "ls180.v:2025.6-2025.33" + wire \builder_csrbank4_enable0_re + attribute \src "ls180.v:2028.6-2028.32" + wire \builder_csrbank4_enable0_w + attribute \src "ls180.v:2027.6-2027.33" + wire \builder_csrbank4_enable0_we + attribute \src "ls180.v:2058.12-2058.38" + wire width 8 \builder_csrbank4_period0_r + attribute \src "ls180.v:2057.6-2057.33" + wire \builder_csrbank4_period0_re + attribute \src "ls180.v:2060.12-2060.38" + wire width 8 \builder_csrbank4_period0_w + attribute \src "ls180.v:2059.6-2059.33" + wire \builder_csrbank4_period0_we + attribute \src "ls180.v:2054.12-2054.38" + wire width 8 \builder_csrbank4_period1_r + attribute \src "ls180.v:2053.6-2053.33" + wire \builder_csrbank4_period1_re + attribute \src "ls180.v:2056.12-2056.38" + wire width 8 \builder_csrbank4_period1_w + attribute \src "ls180.v:2055.6-2055.33" + wire \builder_csrbank4_period1_we + attribute \src "ls180.v:2050.12-2050.38" + wire width 8 \builder_csrbank4_period2_r + attribute \src "ls180.v:2049.6-2049.33" + wire \builder_csrbank4_period2_re + attribute \src "ls180.v:2052.12-2052.38" + wire width 8 \builder_csrbank4_period2_w + attribute \src "ls180.v:2051.6-2051.33" + wire \builder_csrbank4_period2_we + attribute \src "ls180.v:2046.12-2046.38" + wire width 8 \builder_csrbank4_period3_r + attribute \src "ls180.v:2045.6-2045.33" + wire \builder_csrbank4_period3_re + attribute \src "ls180.v:2048.12-2048.38" + wire width 8 \builder_csrbank4_period3_w + attribute \src "ls180.v:2047.6-2047.33" + wire \builder_csrbank4_period3_we + attribute \src "ls180.v:2061.6-2061.26" + wire \builder_csrbank4_sel + attribute \src "ls180.v:2042.12-2042.37" + wire width 8 \builder_csrbank4_width0_r + attribute \src "ls180.v:2041.6-2041.32" + wire \builder_csrbank4_width0_re + attribute \src "ls180.v:2044.12-2044.37" + wire width 8 \builder_csrbank4_width0_w + attribute \src "ls180.v:2043.6-2043.32" + wire \builder_csrbank4_width0_we + attribute \src "ls180.v:2038.12-2038.37" + wire width 8 \builder_csrbank4_width1_r + attribute \src "ls180.v:2037.6-2037.32" + wire \builder_csrbank4_width1_re + attribute \src "ls180.v:2040.12-2040.37" + wire width 8 \builder_csrbank4_width1_w + attribute \src "ls180.v:2039.6-2039.32" + wire \builder_csrbank4_width1_we + attribute \src "ls180.v:2034.12-2034.37" + wire width 8 \builder_csrbank4_width2_r + attribute \src "ls180.v:2033.6-2033.32" + wire \builder_csrbank4_width2_re + attribute \src "ls180.v:2036.12-2036.37" + wire width 8 \builder_csrbank4_width2_w + attribute \src "ls180.v:2035.6-2035.32" + wire \builder_csrbank4_width2_we + attribute \src "ls180.v:2030.12-2030.37" + wire width 8 \builder_csrbank4_width3_r + attribute \src "ls180.v:2029.6-2029.32" + wire \builder_csrbank4_width3_re + attribute \src "ls180.v:2032.12-2032.37" + wire width 8 \builder_csrbank4_width3_w + attribute \src "ls180.v:2031.6-2031.32" + wire \builder_csrbank4_width3_we + attribute \src "ls180.v:2095.12-2095.40" + wire width 8 \builder_csrbank5_dma_base0_r + attribute \src "ls180.v:2094.6-2094.35" + wire \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:2097.12-2097.40" + wire width 8 \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:2096.6-2096.35" + wire \builder_csrbank5_dma_base0_we + attribute \src "ls180.v:2091.12-2091.40" + wire width 8 \builder_csrbank5_dma_base1_r + attribute \src "ls180.v:2090.6-2090.35" + wire \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:2093.12-2093.40" + wire width 8 \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:2092.6-2092.35" + wire \builder_csrbank5_dma_base1_we + attribute \src "ls180.v:2087.12-2087.40" + wire width 8 \builder_csrbank5_dma_base2_r + attribute \src "ls180.v:2086.6-2086.35" + wire \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:2089.12-2089.40" + wire width 8 \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:2088.6-2088.35" + wire \builder_csrbank5_dma_base2_we + attribute \src "ls180.v:2083.12-2083.40" + wire width 8 \builder_csrbank5_dma_base3_r + attribute \src "ls180.v:2082.6-2082.35" + wire \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:2085.12-2085.40" + wire width 8 \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:2084.6-2084.35" + wire \builder_csrbank5_dma_base3_we + attribute \src "ls180.v:2079.12-2079.40" + wire width 8 \builder_csrbank5_dma_base4_r + attribute \src "ls180.v:2078.6-2078.35" + wire \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:2081.12-2081.40" + wire width 8 \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:2080.6-2080.35" + wire \builder_csrbank5_dma_base4_we + attribute \src "ls180.v:2075.12-2075.40" + wire width 8 \builder_csrbank5_dma_base5_r + attribute \src "ls180.v:2074.6-2074.35" + wire \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:2077.12-2077.40" + wire width 8 \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:2076.6-2076.35" + wire \builder_csrbank5_dma_base5_we + attribute \src "ls180.v:2071.12-2071.40" + wire width 8 \builder_csrbank5_dma_base6_r + attribute \src "ls180.v:2070.6-2070.35" + wire \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:2073.12-2073.40" + wire width 8 \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:2072.6-2072.35" + wire \builder_csrbank5_dma_base6_we + attribute \src "ls180.v:2067.12-2067.40" + wire width 8 \builder_csrbank5_dma_base7_r + attribute \src "ls180.v:2066.6-2066.35" + wire \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:2069.12-2069.40" + wire width 8 \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:2068.6-2068.35" + wire \builder_csrbank5_dma_base7_we + attribute \src "ls180.v:2119.6-2119.33" + wire \builder_csrbank5_dma_done_r + attribute \src "ls180.v:2118.6-2118.34" + wire \builder_csrbank5_dma_done_re + attribute \src "ls180.v:2121.6-2121.33" + wire \builder_csrbank5_dma_done_w + attribute \src "ls180.v:2120.6-2120.34" + wire \builder_csrbank5_dma_done_we + attribute \src "ls180.v:2115.6-2115.36" + wire \builder_csrbank5_dma_enable0_r + attribute \src "ls180.v:2114.6-2114.37" + wire \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:2117.6-2117.36" + wire \builder_csrbank5_dma_enable0_w + attribute \src "ls180.v:2116.6-2116.37" + wire \builder_csrbank5_dma_enable0_we + attribute \src "ls180.v:2111.12-2111.42" + wire width 8 \builder_csrbank5_dma_length0_r + attribute \src "ls180.v:2110.6-2110.37" + wire \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:2113.12-2113.42" + wire width 8 \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:2112.6-2112.37" + wire \builder_csrbank5_dma_length0_we + attribute \src "ls180.v:2107.12-2107.42" + wire width 8 \builder_csrbank5_dma_length1_r + attribute \src "ls180.v:2106.6-2106.37" + wire \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:2109.12-2109.42" + wire width 8 \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:2108.6-2108.37" + wire \builder_csrbank5_dma_length1_we + attribute \src "ls180.v:2103.12-2103.42" + wire width 8 \builder_csrbank5_dma_length2_r + attribute \src "ls180.v:2102.6-2102.37" + wire \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:2105.12-2105.42" + wire width 8 \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:2104.6-2104.37" + wire \builder_csrbank5_dma_length2_we + attribute \src "ls180.v:2099.12-2099.42" + wire width 8 \builder_csrbank5_dma_length3_r + attribute \src "ls180.v:2098.6-2098.37" + wire \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:2101.12-2101.42" + wire width 8 \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:2100.6-2100.37" + wire \builder_csrbank5_dma_length3_we + attribute \src "ls180.v:2123.6-2123.34" + wire \builder_csrbank5_dma_loop0_r + attribute \src "ls180.v:2122.6-2122.35" + wire \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:2125.6-2125.34" + wire \builder_csrbank5_dma_loop0_w + attribute \src "ls180.v:2124.6-2124.35" + wire \builder_csrbank5_dma_loop0_we + attribute \src "ls180.v:2126.6-2126.26" + wire \builder_csrbank5_sel + attribute \src "ls180.v:2256.12-2256.43" + wire width 8 \builder_csrbank6_block_count0_r + attribute \src "ls180.v:2255.6-2255.38" + wire \builder_csrbank6_block_count0_re + attribute \src "ls180.v:2258.12-2258.43" + wire width 8 \builder_csrbank6_block_count0_w + attribute \src "ls180.v:2257.6-2257.38" + wire \builder_csrbank6_block_count0_we + attribute \src "ls180.v:2252.12-2252.43" + wire width 8 \builder_csrbank6_block_count1_r + attribute \src "ls180.v:2251.6-2251.38" + wire \builder_csrbank6_block_count1_re + attribute \src "ls180.v:2254.12-2254.43" + wire width 8 \builder_csrbank6_block_count1_w + attribute \src "ls180.v:2253.6-2253.38" + wire \builder_csrbank6_block_count1_we + attribute \src "ls180.v:2248.12-2248.43" + wire width 8 \builder_csrbank6_block_count2_r + attribute \src "ls180.v:2247.6-2247.38" + wire \builder_csrbank6_block_count2_re + attribute \src "ls180.v:2250.12-2250.43" + wire width 8 \builder_csrbank6_block_count2_w + attribute \src "ls180.v:2249.6-2249.38" + wire \builder_csrbank6_block_count2_we + attribute \src "ls180.v:2244.12-2244.43" + wire width 8 \builder_csrbank6_block_count3_r + attribute \src "ls180.v:2243.6-2243.38" + wire \builder_csrbank6_block_count3_re + attribute \src "ls180.v:2246.12-2246.43" + wire width 8 \builder_csrbank6_block_count3_w + attribute \src "ls180.v:2245.6-2245.38" + wire \builder_csrbank6_block_count3_we + attribute \src "ls180.v:2240.12-2240.44" + wire width 8 \builder_csrbank6_block_length0_r + attribute \src "ls180.v:2239.6-2239.39" + wire \builder_csrbank6_block_length0_re + attribute \src "ls180.v:2242.12-2242.44" + wire width 8 \builder_csrbank6_block_length0_w + attribute \src "ls180.v:2241.6-2241.39" + wire \builder_csrbank6_block_length0_we + attribute \src "ls180.v:2236.12-2236.44" + wire width 2 \builder_csrbank6_block_length1_r + attribute \src "ls180.v:2235.6-2235.39" + wire \builder_csrbank6_block_length1_re + attribute \src "ls180.v:2238.12-2238.44" + wire width 2 \builder_csrbank6_block_length1_w + attribute \src "ls180.v:2237.6-2237.39" + wire \builder_csrbank6_block_length1_we + attribute \src "ls180.v:2144.12-2144.44" + wire width 8 \builder_csrbank6_cmd_argument0_r + attribute \src "ls180.v:2143.6-2143.39" + wire \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:2146.12-2146.44" + wire width 8 \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:2145.6-2145.39" + wire \builder_csrbank6_cmd_argument0_we + attribute \src "ls180.v:2140.12-2140.44" + wire width 8 \builder_csrbank6_cmd_argument1_r + attribute \src "ls180.v:2139.6-2139.39" + wire \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:2142.12-2142.44" + wire width 8 \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:2141.6-2141.39" + wire \builder_csrbank6_cmd_argument1_we + attribute \src "ls180.v:2136.12-2136.44" + wire width 8 \builder_csrbank6_cmd_argument2_r + attribute \src "ls180.v:2135.6-2135.39" + wire \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:2138.12-2138.44" + wire width 8 \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:2137.6-2137.39" + wire \builder_csrbank6_cmd_argument2_we + attribute \src "ls180.v:2132.12-2132.44" + wire width 8 \builder_csrbank6_cmd_argument3_r + attribute \src "ls180.v:2131.6-2131.39" + wire \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:2134.12-2134.44" + wire width 8 \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:2133.6-2133.39" + wire \builder_csrbank6_cmd_argument3_we + attribute \src "ls180.v:2160.12-2160.43" + wire width 8 \builder_csrbank6_cmd_command0_r + attribute \src "ls180.v:2159.6-2159.38" + wire \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:2162.12-2162.43" + wire width 8 \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:2161.6-2161.38" + wire \builder_csrbank6_cmd_command0_we + attribute \src "ls180.v:2156.12-2156.43" + wire width 8 \builder_csrbank6_cmd_command1_r + attribute \src "ls180.v:2155.6-2155.38" + wire \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:2158.12-2158.43" + wire width 8 \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:2157.6-2157.38" + wire \builder_csrbank6_cmd_command1_we + attribute \src "ls180.v:2152.12-2152.43" + wire width 8 \builder_csrbank6_cmd_command2_r + attribute \src "ls180.v:2151.6-2151.38" + wire \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:2154.12-2154.43" + wire width 8 \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:2153.6-2153.38" + wire \builder_csrbank6_cmd_command2_we + attribute \src "ls180.v:2148.12-2148.43" + wire width 8 \builder_csrbank6_cmd_command3_r + attribute \src "ls180.v:2147.6-2147.38" + wire \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:2150.12-2150.43" + wire width 8 \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:2149.6-2149.38" + wire \builder_csrbank6_cmd_command3_we + attribute \src "ls180.v:2228.12-2228.40" + wire width 4 \builder_csrbank6_cmd_event_r + attribute \src "ls180.v:2227.6-2227.35" + wire \builder_csrbank6_cmd_event_re + attribute \src "ls180.v:2230.12-2230.40" + wire width 4 \builder_csrbank6_cmd_event_w + attribute \src "ls180.v:2229.6-2229.35" + wire \builder_csrbank6_cmd_event_we + attribute \src "ls180.v:2224.12-2224.44" + wire width 8 \builder_csrbank6_cmd_response0_r + attribute \src "ls180.v:2223.6-2223.39" + wire \builder_csrbank6_cmd_response0_re + attribute \src "ls180.v:2226.12-2226.44" + wire width 8 \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:2225.6-2225.39" + wire \builder_csrbank6_cmd_response0_we + attribute \src "ls180.v:2184.12-2184.45" + wire width 8 \builder_csrbank6_cmd_response10_r + attribute \src "ls180.v:2183.6-2183.40" + wire \builder_csrbank6_cmd_response10_re + attribute \src "ls180.v:2186.12-2186.45" + wire width 8 \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:2185.6-2185.40" + wire \builder_csrbank6_cmd_response10_we + attribute \src "ls180.v:2180.12-2180.45" + wire width 8 \builder_csrbank6_cmd_response11_r + attribute \src "ls180.v:2179.6-2179.40" + wire \builder_csrbank6_cmd_response11_re + attribute \src "ls180.v:2182.12-2182.45" + wire width 8 \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:2181.6-2181.40" + wire \builder_csrbank6_cmd_response11_we + attribute \src "ls180.v:2176.12-2176.45" + wire width 8 \builder_csrbank6_cmd_response12_r + attribute \src "ls180.v:2175.6-2175.40" + wire \builder_csrbank6_cmd_response12_re + attribute \src "ls180.v:2178.12-2178.45" + wire width 8 \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:2177.6-2177.40" + wire \builder_csrbank6_cmd_response12_we + attribute \src "ls180.v:2172.12-2172.45" + wire width 8 \builder_csrbank6_cmd_response13_r + attribute \src "ls180.v:2171.6-2171.40" + wire \builder_csrbank6_cmd_response13_re + attribute \src "ls180.v:2174.12-2174.45" + wire width 8 \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:2173.6-2173.40" + wire \builder_csrbank6_cmd_response13_we + attribute \src "ls180.v:2168.12-2168.45" + wire width 8 \builder_csrbank6_cmd_response14_r + attribute \src "ls180.v:2167.6-2167.40" + wire \builder_csrbank6_cmd_response14_re + attribute \src "ls180.v:2170.12-2170.45" + wire width 8 \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:2169.6-2169.40" + wire \builder_csrbank6_cmd_response14_we + attribute \src "ls180.v:2164.12-2164.45" + wire width 8 \builder_csrbank6_cmd_response15_r + attribute \src "ls180.v:2163.6-2163.40" + wire \builder_csrbank6_cmd_response15_re + attribute \src "ls180.v:2166.12-2166.45" + wire width 8 \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:2165.6-2165.40" + wire \builder_csrbank6_cmd_response15_we + attribute \src "ls180.v:2220.12-2220.44" + wire width 8 \builder_csrbank6_cmd_response1_r + attribute \src "ls180.v:2219.6-2219.39" + wire \builder_csrbank6_cmd_response1_re + attribute \src "ls180.v:2222.12-2222.44" + wire width 8 \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:2221.6-2221.39" + wire \builder_csrbank6_cmd_response1_we + attribute \src "ls180.v:2216.12-2216.44" + wire width 8 \builder_csrbank6_cmd_response2_r + attribute \src "ls180.v:2215.6-2215.39" + wire \builder_csrbank6_cmd_response2_re + attribute \src "ls180.v:2218.12-2218.44" + wire width 8 \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:2217.6-2217.39" + wire \builder_csrbank6_cmd_response2_we + attribute \src "ls180.v:2212.12-2212.44" + wire width 8 \builder_csrbank6_cmd_response3_r + attribute \src "ls180.v:2211.6-2211.39" + wire \builder_csrbank6_cmd_response3_re + attribute \src "ls180.v:2214.12-2214.44" + wire width 8 \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:2213.6-2213.39" + wire \builder_csrbank6_cmd_response3_we + attribute \src "ls180.v:2208.12-2208.44" + wire width 8 \builder_csrbank6_cmd_response4_r + attribute \src "ls180.v:2207.6-2207.39" + wire \builder_csrbank6_cmd_response4_re + attribute \src "ls180.v:2210.12-2210.44" + wire width 8 \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:2209.6-2209.39" + wire \builder_csrbank6_cmd_response4_we + attribute \src "ls180.v:2204.12-2204.44" + wire width 8 \builder_csrbank6_cmd_response5_r + attribute \src "ls180.v:2203.6-2203.39" + wire \builder_csrbank6_cmd_response5_re + attribute \src "ls180.v:2206.12-2206.44" + wire width 8 \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:2205.6-2205.39" + wire \builder_csrbank6_cmd_response5_we + attribute \src "ls180.v:2200.12-2200.44" + wire width 8 \builder_csrbank6_cmd_response6_r + attribute \src "ls180.v:2199.6-2199.39" + wire \builder_csrbank6_cmd_response6_re + attribute \src "ls180.v:2202.12-2202.44" + wire width 8 \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:2201.6-2201.39" + wire \builder_csrbank6_cmd_response6_we + attribute \src "ls180.v:2196.12-2196.44" + wire width 8 \builder_csrbank6_cmd_response7_r + attribute \src "ls180.v:2195.6-2195.39" + wire \builder_csrbank6_cmd_response7_re + attribute \src "ls180.v:2198.12-2198.44" + wire width 8 \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:2197.6-2197.39" + wire \builder_csrbank6_cmd_response7_we + attribute \src "ls180.v:2192.12-2192.44" + wire width 8 \builder_csrbank6_cmd_response8_r + attribute \src "ls180.v:2191.6-2191.39" + wire \builder_csrbank6_cmd_response8_re + attribute \src "ls180.v:2194.12-2194.44" + wire width 8 \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:2193.6-2193.39" + wire \builder_csrbank6_cmd_response8_we + attribute \src "ls180.v:2188.12-2188.44" + wire width 8 \builder_csrbank6_cmd_response9_r + attribute \src "ls180.v:2187.6-2187.39" + wire \builder_csrbank6_cmd_response9_re + attribute \src "ls180.v:2190.12-2190.44" + wire width 8 \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:2189.6-2189.39" + wire \builder_csrbank6_cmd_response9_we + attribute \src "ls180.v:2232.12-2232.41" + wire width 4 \builder_csrbank6_data_event_r + attribute \src "ls180.v:2231.6-2231.36" + wire \builder_csrbank6_data_event_re + attribute \src "ls180.v:2234.12-2234.41" + wire width 4 \builder_csrbank6_data_event_w + attribute \src "ls180.v:2233.6-2233.36" + wire \builder_csrbank6_data_event_we + attribute \src "ls180.v:2259.6-2259.26" + wire \builder_csrbank6_sel + attribute \src "ls180.v:2293.12-2293.40" + wire width 8 \builder_csrbank7_dma_base0_r + attribute \src "ls180.v:2292.6-2292.35" + wire \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:2295.12-2295.40" + wire width 8 \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:2294.6-2294.35" + wire \builder_csrbank7_dma_base0_we + attribute \src "ls180.v:2289.12-2289.40" + wire width 8 \builder_csrbank7_dma_base1_r + attribute \src "ls180.v:2288.6-2288.35" + wire \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:2291.12-2291.40" + wire width 8 \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:2290.6-2290.35" + wire \builder_csrbank7_dma_base1_we + attribute \src "ls180.v:2285.12-2285.40" + wire width 8 \builder_csrbank7_dma_base2_r + attribute \src "ls180.v:2284.6-2284.35" + wire \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:2287.12-2287.40" + wire width 8 \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:2286.6-2286.35" + wire \builder_csrbank7_dma_base2_we + attribute \src "ls180.v:2281.12-2281.40" + wire width 8 \builder_csrbank7_dma_base3_r + attribute \src "ls180.v:2280.6-2280.35" + wire \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:2283.12-2283.40" + wire width 8 \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:2282.6-2282.35" + wire \builder_csrbank7_dma_base3_we + attribute \src "ls180.v:2277.12-2277.40" + wire width 8 \builder_csrbank7_dma_base4_r + attribute \src "ls180.v:2276.6-2276.35" + wire \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:2279.12-2279.40" + wire width 8 \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:2278.6-2278.35" + wire \builder_csrbank7_dma_base4_we + attribute \src "ls180.v:2273.12-2273.40" + wire width 8 \builder_csrbank7_dma_base5_r + attribute \src "ls180.v:2272.6-2272.35" + wire \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:2275.12-2275.40" + wire width 8 \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:2274.6-2274.35" + wire \builder_csrbank7_dma_base5_we + attribute \src "ls180.v:2269.12-2269.40" + wire width 8 \builder_csrbank7_dma_base6_r + attribute \src "ls180.v:2268.6-2268.35" + wire \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:2271.12-2271.40" + wire width 8 \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:2270.6-2270.35" + wire \builder_csrbank7_dma_base6_we + attribute \src "ls180.v:2265.12-2265.40" + wire width 8 \builder_csrbank7_dma_base7_r + attribute \src "ls180.v:2264.6-2264.35" + wire \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:2267.12-2267.40" + wire width 8 \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:2266.6-2266.35" + wire \builder_csrbank7_dma_base7_we + attribute \src "ls180.v:2317.6-2317.33" + wire \builder_csrbank7_dma_done_r + attribute \src "ls180.v:2316.6-2316.34" + wire \builder_csrbank7_dma_done_re + attribute \src "ls180.v:2319.6-2319.33" + wire \builder_csrbank7_dma_done_w + attribute \src "ls180.v:2318.6-2318.34" + wire \builder_csrbank7_dma_done_we + attribute \src "ls180.v:2313.6-2313.36" + wire \builder_csrbank7_dma_enable0_r + attribute \src "ls180.v:2312.6-2312.37" + wire \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:2315.6-2315.36" + wire \builder_csrbank7_dma_enable0_w + attribute \src "ls180.v:2314.6-2314.37" + wire \builder_csrbank7_dma_enable0_we + attribute \src "ls180.v:2309.12-2309.42" + wire width 8 \builder_csrbank7_dma_length0_r + attribute \src "ls180.v:2308.6-2308.37" + wire \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:2311.12-2311.42" + wire width 8 \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:2310.6-2310.37" + wire \builder_csrbank7_dma_length0_we + attribute \src "ls180.v:2305.12-2305.42" + wire width 8 \builder_csrbank7_dma_length1_r + attribute \src "ls180.v:2304.6-2304.37" + wire \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:2307.12-2307.42" + wire width 8 \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:2306.6-2306.37" + wire \builder_csrbank7_dma_length1_we + attribute \src "ls180.v:2301.12-2301.42" + wire width 8 \builder_csrbank7_dma_length2_r + attribute \src "ls180.v:2300.6-2300.37" + wire \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:2303.12-2303.42" + wire width 8 \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:2302.6-2302.37" + wire \builder_csrbank7_dma_length2_we + attribute \src "ls180.v:2297.12-2297.42" + wire width 8 \builder_csrbank7_dma_length3_r + attribute \src "ls180.v:2296.6-2296.37" + wire \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:2299.12-2299.42" + wire width 8 \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:2298.6-2298.37" + wire \builder_csrbank7_dma_length3_we + attribute \src "ls180.v:2321.6-2321.34" + wire \builder_csrbank7_dma_loop0_r + attribute \src "ls180.v:2320.6-2320.35" + wire \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:2323.6-2323.34" + wire \builder_csrbank7_dma_loop0_w + attribute \src "ls180.v:2322.6-2322.35" + wire \builder_csrbank7_dma_loop0_we + attribute \src "ls180.v:2337.12-2337.42" + wire width 8 \builder_csrbank7_dma_offset0_r + attribute \src "ls180.v:2336.6-2336.37" + wire \builder_csrbank7_dma_offset0_re + attribute \src "ls180.v:2339.12-2339.42" + wire width 8 \builder_csrbank7_dma_offset0_w + attribute \src "ls180.v:2338.6-2338.37" + wire \builder_csrbank7_dma_offset0_we + attribute \src "ls180.v:2333.12-2333.42" + wire width 8 \builder_csrbank7_dma_offset1_r + attribute \src "ls180.v:2332.6-2332.37" + wire \builder_csrbank7_dma_offset1_re + attribute \src "ls180.v:2335.12-2335.42" + wire width 8 \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:2334.6-2334.37" + wire \builder_csrbank7_dma_offset1_we + attribute \src "ls180.v:2329.12-2329.42" + wire width 8 \builder_csrbank7_dma_offset2_r + attribute \src "ls180.v:2328.6-2328.37" + wire \builder_csrbank7_dma_offset2_re + attribute \src "ls180.v:2331.12-2331.42" + wire width 8 \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:2330.6-2330.37" + wire \builder_csrbank7_dma_offset2_we + attribute \src "ls180.v:2325.12-2325.42" + wire width 8 \builder_csrbank7_dma_offset3_r + attribute \src "ls180.v:2324.6-2324.37" + wire \builder_csrbank7_dma_offset3_re + attribute \src "ls180.v:2327.12-2327.42" + wire width 8 \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:2326.6-2326.37" + wire \builder_csrbank7_dma_offset3_we + attribute \src "ls180.v:2340.6-2340.26" + wire \builder_csrbank7_sel + attribute \src "ls180.v:2346.6-2346.36" + wire \builder_csrbank8_card_detect_r + attribute \src "ls180.v:2345.6-2345.37" + wire \builder_csrbank8_card_detect_re + attribute \src "ls180.v:2348.6-2348.36" + wire \builder_csrbank8_card_detect_w + attribute \src "ls180.v:2347.6-2347.37" + wire \builder_csrbank8_card_detect_we + attribute \src "ls180.v:2354.12-2354.47" + wire width 8 \builder_csrbank8_clocker_divider0_r + attribute \src "ls180.v:2353.6-2353.42" + wire \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:2356.12-2356.47" + wire width 8 \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:2355.6-2355.42" + wire \builder_csrbank8_clocker_divider0_we + attribute \src "ls180.v:2350.6-2350.41" + wire \builder_csrbank8_clocker_divider1_r + attribute \src "ls180.v:2349.6-2349.42" + wire \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:2352.6-2352.41" + wire \builder_csrbank8_clocker_divider1_w + attribute \src "ls180.v:2351.6-2351.42" + wire \builder_csrbank8_clocker_divider1_we + attribute \src "ls180.v:2357.6-2357.26" + wire \builder_csrbank8_sel + attribute \src "ls180.v:2363.12-2363.44" + wire width 4 \builder_csrbank9_dfii_control0_r + attribute \src "ls180.v:2362.6-2362.39" + wire \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:2365.12-2365.44" + wire width 4 \builder_csrbank9_dfii_control0_w + attribute \src "ls180.v:2364.6-2364.39" + wire \builder_csrbank9_dfii_control0_we + attribute \src "ls180.v:2375.12-2375.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_r + attribute \src "ls180.v:2374.6-2374.43" + wire \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:2377.12-2377.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:2376.6-2376.43" + wire \builder_csrbank9_dfii_pi0_address0_we + attribute \src "ls180.v:2371.12-2371.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_r + attribute \src "ls180.v:2370.6-2370.43" + wire \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:2373.12-2373.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_w + attribute \src "ls180.v:2372.6-2372.43" + wire \builder_csrbank9_dfii_pi0_address1_we + attribute \src "ls180.v:2379.12-2379.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r + attribute \src "ls180.v:2378.6-2378.44" + wire \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:2381.12-2381.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w + attribute \src "ls180.v:2380.6-2380.44" + wire \builder_csrbank9_dfii_pi0_baddress0_we + attribute \src "ls180.v:2367.12-2367.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_r + attribute \src "ls180.v:2366.6-2366.43" + wire \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:2369.12-2369.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_w + attribute \src "ls180.v:2368.6-2368.43" + wire \builder_csrbank9_dfii_pi0_command0_we + attribute \src "ls180.v:2395.12-2395.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r + attribute \src "ls180.v:2394.6-2394.42" + wire \builder_csrbank9_dfii_pi0_rddata0_re + attribute \src "ls180.v:2397.12-2397.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w + attribute \src "ls180.v:2396.6-2396.42" + wire \builder_csrbank9_dfii_pi0_rddata0_we + attribute \src "ls180.v:2391.12-2391.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r + attribute \src "ls180.v:2390.6-2390.42" + wire \builder_csrbank9_dfii_pi0_rddata1_re + attribute \src "ls180.v:2393.12-2393.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:2392.6-2392.42" + wire \builder_csrbank9_dfii_pi0_rddata1_we + attribute \src "ls180.v:2387.12-2387.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r + attribute \src "ls180.v:2386.6-2386.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:2389.12-2389.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:2388.6-2388.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_we + attribute \src "ls180.v:2383.12-2383.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r + attribute \src "ls180.v:2382.6-2382.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:2385.12-2385.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:2384.6-2384.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_we + attribute \src "ls180.v:2398.6-2398.26" + wire \builder_csrbank9_sel + attribute \src "ls180.v:1895.6-1895.18" + wire \builder_done + attribute \src "ls180.v:1893.5-1893.18" + wire \builder_error + attribute \src "ls180.v:1890.11-1890.24" + wire width 3 \builder_grant + attribute \src "ls180.v:1897.13-1897.44" + wire width 14 \builder_interface0_bank_bus_adr + attribute \src "ls180.v:1900.11-1900.44" + wire width 8 \builder_interface0_bank_bus_dat_r + attribute \src "ls180.v:1899.12-1899.45" + wire width 8 \builder_interface0_bank_bus_dat_w + attribute \src "ls180.v:1898.6-1898.36" + wire \builder_interface0_bank_bus_we + attribute \src "ls180.v:2399.13-2399.45" + wire width 14 \builder_interface10_bank_bus_adr + attribute \src "ls180.v:2402.11-2402.45" + wire width 8 \builder_interface10_bank_bus_dat_r + attribute \src "ls180.v:2401.12-2401.46" + wire width 8 \builder_interface10_bank_bus_dat_w + attribute \src "ls180.v:2400.6-2400.37" + wire \builder_interface10_bank_bus_we + attribute \src "ls180.v:2432.13-2432.45" + wire width 14 \builder_interface11_bank_bus_adr + attribute \src "ls180.v:2435.11-2435.45" + wire width 8 \builder_interface11_bank_bus_dat_r + attribute \src "ls180.v:2434.12-2434.46" + wire width 8 \builder_interface11_bank_bus_dat_w + attribute \src "ls180.v:2433.6-2433.37" + wire \builder_interface11_bank_bus_we + attribute \src "ls180.v:2473.13-2473.45" + wire width 14 \builder_interface12_bank_bus_adr + attribute \src "ls180.v:2476.11-2476.45" + wire width 8 \builder_interface12_bank_bus_dat_r + attribute \src "ls180.v:2475.12-2475.46" + wire width 8 \builder_interface12_bank_bus_dat_w + attribute \src "ls180.v:2474.6-2474.37" + wire \builder_interface12_bank_bus_we + attribute \src "ls180.v:2538.13-2538.45" + wire width 14 \builder_interface13_bank_bus_adr + attribute \src "ls180.v:2541.11-2541.45" + wire width 8 \builder_interface13_bank_bus_dat_r + attribute \src "ls180.v:2540.12-2540.46" + wire width 8 \builder_interface13_bank_bus_dat_w + attribute \src "ls180.v:2539.6-2539.37" + wire \builder_interface13_bank_bus_we + attribute \src "ls180.v:2563.13-2563.45" + wire width 14 \builder_interface14_bank_bus_adr + attribute \src "ls180.v:2566.11-2566.45" + wire width 8 \builder_interface14_bank_bus_dat_r + attribute \src "ls180.v:2565.12-2565.46" + wire width 8 \builder_interface14_bank_bus_dat_w + attribute \src "ls180.v:2564.6-2564.37" + wire \builder_interface14_bank_bus_we + attribute \src "ls180.v:1938.13-1938.44" + wire width 14 \builder_interface1_bank_bus_adr + attribute \src "ls180.v:1941.11-1941.44" + wire width 8 \builder_interface1_bank_bus_dat_r + attribute \src "ls180.v:1940.12-1940.45" + wire width 8 \builder_interface1_bank_bus_dat_w + attribute \src "ls180.v:1939.6-1939.36" + wire \builder_interface1_bank_bus_we + attribute \src "ls180.v:1967.13-1967.44" + wire width 14 \builder_interface2_bank_bus_adr + attribute \src "ls180.v:1970.11-1970.44" + wire width 8 \builder_interface2_bank_bus_dat_r + attribute \src "ls180.v:1969.12-1969.45" + wire width 8 \builder_interface2_bank_bus_dat_w + attribute \src "ls180.v:1968.6-1968.36" + wire \builder_interface2_bank_bus_we + attribute \src "ls180.v:1980.13-1980.44" + wire width 14 \builder_interface3_bank_bus_adr + attribute \src "ls180.v:1983.11-1983.44" + wire width 8 \builder_interface3_bank_bus_dat_r + attribute \src "ls180.v:1982.12-1982.45" + wire width 8 \builder_interface3_bank_bus_dat_w + attribute \src "ls180.v:1981.6-1981.36" + wire \builder_interface3_bank_bus_we + attribute \src "ls180.v:2021.13-2021.44" + wire width 14 \builder_interface4_bank_bus_adr + attribute \src "ls180.v:2024.11-2024.44" + wire width 8 \builder_interface4_bank_bus_dat_r + attribute \src "ls180.v:2023.12-2023.45" + wire width 8 \builder_interface4_bank_bus_dat_w + attribute \src "ls180.v:2022.6-2022.36" + wire \builder_interface4_bank_bus_we + attribute \src "ls180.v:2062.13-2062.44" + wire width 14 \builder_interface5_bank_bus_adr + attribute \src "ls180.v:2065.11-2065.44" + wire width 8 \builder_interface5_bank_bus_dat_r + attribute \src "ls180.v:2064.12-2064.45" + wire width 8 \builder_interface5_bank_bus_dat_w + attribute \src "ls180.v:2063.6-2063.36" + wire \builder_interface5_bank_bus_we + attribute \src "ls180.v:2127.13-2127.44" + wire width 14 \builder_interface6_bank_bus_adr + attribute \src "ls180.v:2130.11-2130.44" + wire width 8 \builder_interface6_bank_bus_dat_r + attribute \src "ls180.v:2129.12-2129.45" + wire width 8 \builder_interface6_bank_bus_dat_w + attribute \src "ls180.v:2128.6-2128.36" + wire \builder_interface6_bank_bus_we + attribute \src "ls180.v:2260.13-2260.44" + wire width 14 \builder_interface7_bank_bus_adr + attribute \src "ls180.v:2263.11-2263.44" + wire width 8 \builder_interface7_bank_bus_dat_r + attribute \src "ls180.v:2262.12-2262.45" + wire width 8 \builder_interface7_bank_bus_dat_w + attribute \src "ls180.v:2261.6-2261.36" + wire \builder_interface7_bank_bus_we + attribute \src "ls180.v:2341.13-2341.44" + wire width 14 \builder_interface8_bank_bus_adr + attribute \src "ls180.v:2344.11-2344.44" + wire width 8 \builder_interface8_bank_bus_dat_r + attribute \src "ls180.v:2343.12-2343.45" + wire width 8 \builder_interface8_bank_bus_dat_w + attribute \src "ls180.v:2342.6-2342.36" + wire \builder_interface8_bank_bus_we + attribute \src "ls180.v:2358.13-2358.44" + wire width 14 \builder_interface9_bank_bus_adr + attribute \src "ls180.v:2361.11-2361.44" + wire width 8 \builder_interface9_bank_bus_dat_r + attribute \src "ls180.v:2360.12-2360.45" + wire width 8 \builder_interface9_bank_bus_dat_w + attribute \src "ls180.v:2359.6-2359.36" + wire \builder_interface9_bank_bus_we + attribute \src "ls180.v:1863.12-1863.35" + wire width 14 \builder_libresocsim_adr + attribute \src "ls180.v:2592.12-2592.47" + wire width 14 \builder_libresocsim_adr_next_value1 + attribute \src "ls180.v:2593.5-2593.43" + wire \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:1866.12-1866.37" + wire width 8 \builder_libresocsim_dat_r + attribute \src "ls180.v:1865.11-1865.36" + wire width 8 \builder_libresocsim_dat_w + attribute \src "ls180.v:2590.11-2590.48" + wire width 8 \builder_libresocsim_dat_w_next_value0 + attribute \src "ls180.v:2591.5-2591.45" + wire \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:1864.5-1864.27" + wire \builder_libresocsim_we + attribute \src "ls180.v:2594.5-2594.39" + wire \builder_libresocsim_we_next_value2 + attribute \src "ls180.v:2595.5-2595.42" + wire \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:1873.5-1873.37" + wire \builder_libresocsim_wishbone_ack + attribute \src "ls180.v:1867.13-1867.45" + wire width 30 \builder_libresocsim_wishbone_adr + attribute \src "ls180.v:1876.12-1876.44" + wire width 2 \builder_libresocsim_wishbone_bte + attribute \src "ls180.v:1875.12-1875.44" + wire width 3 \builder_libresocsim_wishbone_cti + attribute \src "ls180.v:1871.6-1871.38" + wire \builder_libresocsim_wishbone_cyc + attribute \src "ls180.v:1869.12-1869.46" + wire width 32 \builder_libresocsim_wishbone_dat_r + attribute \src "ls180.v:1868.13-1868.47" + wire width 32 \builder_libresocsim_wishbone_dat_w + attribute \src "ls180.v:1877.5-1877.37" + wire \builder_libresocsim_wishbone_err + attribute \src "ls180.v:1870.12-1870.44" + wire width 4 \builder_libresocsim_wishbone_sel + attribute \src "ls180.v:1872.6-1872.38" + wire \builder_libresocsim_wishbone_stb + attribute \src "ls180.v:1874.6-1874.37" + wire \builder_libresocsim_wishbone_we + attribute \src "ls180.v:1766.5-1766.20" + wire \builder_locked0 + attribute \src "ls180.v:1767.5-1767.20" + wire \builder_locked1 + attribute \src "ls180.v:1768.5-1768.20" + wire \builder_locked2 + attribute \src "ls180.v:1769.5-1769.20" + wire \builder_locked3 + attribute \src "ls180.v:1753.11-1753.41" + wire width 3 \builder_multiplexer_next_state + attribute \src "ls180.v:1752.11-1752.36" + wire width 3 \builder_multiplexer_state + attribute \no_retiming "true" + attribute \src "ls180.v:2699.32-2699.59" + wire \builder_multiregimpl0_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2700.32-2700.59" + wire \builder_multiregimpl0_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2719.32-2719.60" + wire \builder_multiregimpl10_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2720.32-2720.60" + wire \builder_multiregimpl10_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2721.32-2721.60" + wire \builder_multiregimpl11_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2722.32-2722.60" + wire \builder_multiregimpl11_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2723.32-2723.60" + wire \builder_multiregimpl12_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2724.32-2724.60" + wire \builder_multiregimpl12_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2725.32-2725.60" + wire \builder_multiregimpl13_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2726.32-2726.60" + wire \builder_multiregimpl13_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2727.32-2727.60" + wire \builder_multiregimpl14_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2728.32-2728.60" + wire \builder_multiregimpl14_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2729.32-2729.60" + wire \builder_multiregimpl15_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2730.32-2730.60" + wire \builder_multiregimpl15_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2731.32-2731.60" + wire \builder_multiregimpl16_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2732.32-2732.60" + wire \builder_multiregimpl16_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2701.32-2701.59" + wire \builder_multiregimpl1_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2702.32-2702.59" + wire \builder_multiregimpl1_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2703.32-2703.59" + wire \builder_multiregimpl2_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2704.32-2704.59" + wire \builder_multiregimpl2_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2705.32-2705.59" + wire \builder_multiregimpl3_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2706.32-2706.59" + wire \builder_multiregimpl3_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2707.32-2707.59" + wire \builder_multiregimpl4_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2708.32-2708.59" + wire \builder_multiregimpl4_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2709.32-2709.59" + wire \builder_multiregimpl5_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2710.32-2710.59" + wire \builder_multiregimpl5_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2711.32-2711.59" + wire \builder_multiregimpl6_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2712.32-2712.59" + wire \builder_multiregimpl6_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2713.32-2713.59" + wire \builder_multiregimpl7_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2714.32-2714.59" + wire \builder_multiregimpl7_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2715.32-2715.59" + wire \builder_multiregimpl8_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2716.32-2716.59" + wire \builder_multiregimpl8_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2717.32-2717.59" + wire \builder_multiregimpl9_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2718.32-2718.59" + wire \builder_multiregimpl9_regs1 + attribute \src "ls180.v:1771.5-1771.36" + wire \builder_new_master_rdata_valid0 + attribute \src "ls180.v:1772.5-1772.36" + wire \builder_new_master_rdata_valid1 + attribute \src "ls180.v:1773.5-1773.36" + wire \builder_new_master_rdata_valid2 + attribute \src "ls180.v:1774.5-1774.36" + wire \builder_new_master_rdata_valid3 + attribute \src "ls180.v:1770.5-1770.35" + wire \builder_new_master_wdata_ready + attribute \src "ls180.v:2589.11-2589.29" + wire width 2 \builder_next_state + attribute \src "ls180.v:1743.11-1743.39" + wire width 2 \builder_refresher_next_state + attribute \src "ls180.v:1742.11-1742.34" + wire width 2 \builder_refresher_state + attribute \src "ls180.v:1889.12-1889.27" + wire width 5 \builder_request + attribute \src "ls180.v:1756.6-1756.28" + wire \builder_roundrobin0_ce + attribute \src "ls180.v:1755.6-1755.31" + wire \builder_roundrobin0_grant + attribute \src "ls180.v:1754.6-1754.33" + wire \builder_roundrobin0_request + attribute \src "ls180.v:1759.6-1759.28" + wire \builder_roundrobin1_ce + attribute \src "ls180.v:1758.6-1758.31" + wire \builder_roundrobin1_grant + attribute \src "ls180.v:1757.6-1757.33" + wire \builder_roundrobin1_request + attribute \src "ls180.v:1762.6-1762.28" + wire \builder_roundrobin2_ce + attribute \src "ls180.v:1761.6-1761.31" + wire \builder_roundrobin2_grant + attribute \src "ls180.v:1760.6-1760.33" + wire \builder_roundrobin2_request + attribute \src "ls180.v:1765.6-1765.28" + wire \builder_roundrobin3_ce + attribute \src "ls180.v:1764.6-1764.31" + wire \builder_roundrobin3_grant + attribute \src "ls180.v:1763.6-1763.33" + wire \builder_roundrobin3_request + attribute \src "ls180.v:1852.11-1852.44" + wire width 2 \builder_sdblock2memdma_next_state + attribute \src "ls180.v:1851.11-1851.39" + wire width 2 \builder_sdblock2memdma_state + attribute \src "ls180.v:1820.5-1820.50" + wire \builder_sdcore_crcupstreaminserter_next_state + attribute \src "ls180.v:1819.5-1819.45" + wire \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:1832.11-1832.40" + wire width 3 \builder_sdcore_fsm_next_state + attribute \src "ls180.v:1831.11-1831.35" + wire width 3 \builder_sdcore_fsm_state + attribute \src "ls180.v:1856.5-1856.42" + wire \builder_sdmem2blockdma_fsm_next_state + attribute \src "ls180.v:1855.5-1855.37" + wire \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:1860.11-1860.58" + wire width 2 \builder_sdmem2blockdma_resetinserter_next_state + attribute \src "ls180.v:1859.11-1859.53" + wire width 2 \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:1808.11-1808.39" + wire width 3 \builder_sdphy_fsm_next_state + attribute \src "ls180.v:1807.11-1807.34" + wire width 3 \builder_sdphy_fsm_state + attribute \src "ls180.v:1796.11-1796.45" + wire width 3 \builder_sdphy_sdphycmdr_next_state + attribute \src "ls180.v:1795.11-1795.40" + wire width 3 \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:1792.11-1792.45" + wire width 2 \builder_sdphy_sdphycmdw_next_state + attribute \src "ls180.v:1791.11-1791.40" + wire width 2 \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:1804.5-1804.39" + wire \builder_sdphy_sdphycrcr_next_state + attribute \src "ls180.v:1803.5-1803.34" + wire \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:1812.11-1812.46" + wire width 3 \builder_sdphy_sdphydatar_next_state + attribute \src "ls180.v:1811.11-1811.41" + wire width 3 \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:1788.5-1788.39" + wire \builder_sdphy_sdphyinit_next_state + attribute \src "ls180.v:1787.5-1787.34" + wire \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:1884.5-1884.23" + wire \builder_shared_ack + attribute \src "ls180.v:1878.13-1878.31" + wire width 30 \builder_shared_adr + attribute \src "ls180.v:1887.12-1887.30" + wire width 2 \builder_shared_bte + attribute \src "ls180.v:1886.12-1886.30" + wire width 3 \builder_shared_cti + attribute \src "ls180.v:1882.6-1882.24" + wire \builder_shared_cyc + attribute \src "ls180.v:1880.12-1880.32" + wire width 32 \builder_shared_dat_r + attribute \src "ls180.v:1879.13-1879.33" + wire width 32 \builder_shared_dat_w + attribute \src "ls180.v:1888.6-1888.24" + wire \builder_shared_err + attribute \src "ls180.v:1881.12-1881.30" + wire width 4 \builder_shared_sel + attribute \src "ls180.v:1883.6-1883.24" + wire \builder_shared_stb + attribute \src "ls180.v:1885.6-1885.23" + wire \builder_shared_we + attribute \src "ls180.v:1891.11-1891.28" + wire width 5 \builder_slave_sel + attribute \src "ls180.v:1892.11-1892.30" + wire width 5 \builder_slave_sel_r + attribute \src "ls180.v:1780.11-1780.40" + wire width 2 \builder_spimaster0_next_state + attribute \src "ls180.v:1779.11-1779.35" + wire width 2 \builder_spimaster0_state + attribute \src "ls180.v:1784.11-1784.40" + wire width 2 \builder_spimaster1_next_state + attribute \src "ls180.v:1783.11-1783.35" + wire width 2 \builder_spimaster1_state + attribute \src "ls180.v:2588.11-2588.24" + wire width 2 \builder_state + attribute \src "ls180.v:2641.5-2641.32" + wire \builder_sync_f_array_muxed0 + attribute \src "ls180.v:2642.5-2642.32" + wire \builder_sync_f_array_muxed1 + attribute \src "ls180.v:2634.11-2634.40" + wire width 2 \builder_sync_rhs_array_muxed0 + attribute \src "ls180.v:2635.12-2635.41" + wire width 13 \builder_sync_rhs_array_muxed1 + attribute \src "ls180.v:2636.5-2636.34" + wire \builder_sync_rhs_array_muxed2 + attribute \src "ls180.v:2637.5-2637.34" + wire \builder_sync_rhs_array_muxed3 + attribute \src "ls180.v:2638.5-2638.34" + wire \builder_sync_rhs_array_muxed4 + attribute \src "ls180.v:2639.5-2639.34" + wire \builder_sync_rhs_array_muxed5 + attribute \src "ls180.v:2640.5-2640.34" + wire \builder_sync_rhs_array_muxed6 + attribute \src "ls180.v:1894.6-1894.18" + wire \builder_wait + attribute \src "ls180.v:42.19-42.23" + wire width 3 input 38 \eint + attribute \src "ls180.v:157.12-157.18" + wire width 3 \eint_1 + attribute \src "ls180.v:28.20-28.26" + wire width 16 input 24 \gpio_i + attribute \src "ls180.v:29.21-29.27" + wire width 16 output 25 \gpio_o + attribute \src "ls180.v:30.21-30.28" + wire width 16 output 26 \gpio_oe + attribute \src "ls180.v:35.14-35.21" + wire output 31 \i2c_scl + attribute \src "ls180.v:36.13-36.22" + wire input 32 \i2c_sda_i + attribute \src "ls180.v:37.14-37.23" + wire output 33 \i2c_sda_o + attribute \src "ls180.v:38.14-38.24" + wire output 34 \i2c_sda_oe + attribute \src "ls180.v:49.13-49.21" + wire input 45 \jtag_tck + attribute \src "ls180.v:50.13-50.21" + wire input 46 \jtag_tdi + attribute \src "ls180.v:51.14-51.22" + wire output 47 \jtag_tdo + attribute \src "ls180.v:48.13-48.21" + wire input 44 \jtag_tms + attribute \src "ls180.v:834.6-834.18" + wire \main_ack_cmd + attribute \src "ls180.v:836.6-836.20" + wire \main_ack_rdata + attribute \src "ls180.v:835.6-835.20" + wire \main_ack_wdata + attribute \src "ls180.v:832.5-832.22" + wire \main_cmd_consumed + attribute \src "ls180.v:829.5-829.27" + wire \main_converter_counter + attribute \src "ls180.v:1777.5-1777.48" + wire \main_converter_counter_converter_next_value + attribute \src "ls180.v:1778.5-1778.51" + wire \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:831.12-831.32" + wire width 32 \main_converter_dat_r + attribute \src "ls180.v:830.6-830.26" + wire \main_converter_reset + attribute \src "ls180.v:828.5-828.24" + wire \main_converter_skip + attribute \src "ls180.v:258.6-258.23" + wire \main_dfi_p0_act_n + attribute \src "ls180.v:249.13-249.32" + wire width 13 \main_dfi_p0_address + attribute \src "ls180.v:250.12-250.28" + wire width 2 \main_dfi_p0_bank + attribute \src "ls180.v:251.6-251.23" + wire \main_dfi_p0_cas_n + attribute \src "ls180.v:255.6-255.21" + wire \main_dfi_p0_cke + attribute \src "ls180.v:252.6-252.22" + wire \main_dfi_p0_cs_n + attribute \src "ls180.v:256.6-256.21" + wire \main_dfi_p0_odt + attribute \src "ls180.v:253.6-253.23" + wire \main_dfi_p0_ras_n + attribute \src "ls180.v:263.12-263.30" + wire width 16 \main_dfi_p0_rddata + attribute \src "ls180.v:262.6-262.27" + wire \main_dfi_p0_rddata_en + attribute \src "ls180.v:264.5-264.29" + wire \main_dfi_p0_rddata_valid + attribute \src "ls180.v:257.6-257.25" + wire \main_dfi_p0_reset_n + attribute \src "ls180.v:254.6-254.22" + wire \main_dfi_p0_we_n + attribute \src "ls180.v:259.13-259.31" + wire width 16 \main_dfi_p0_wrdata + attribute \src "ls180.v:260.6-260.27" + wire \main_dfi_p0_wrdata_en + attribute \src "ls180.v:261.12-261.35" + wire width 2 \main_dfi_p0_wrdata_mask + attribute \src "ls180.v:1063.12-1063.22" + wire width 24 \main_dummy + attribute \src "ls180.v:980.5-980.20" + wire \main_gpio_oe_re + attribute \src "ls180.v:979.12-979.32" + wire width 16 \main_gpio_oe_storage + attribute \src "ls180.v:984.5-984.21" + wire \main_gpio_out_re + attribute \src "ls180.v:983.12-983.33" + wire width 16 \main_gpio_out_storage + attribute \src "ls180.v:985.13-985.29" + wire width 16 \main_gpio_pads_i + attribute \src "ls180.v:986.13-986.29" + wire width 16 \main_gpio_pads_o + attribute \src "ls180.v:987.13-987.30" + wire width 16 \main_gpio_pads_oe + attribute \src "ls180.v:981.12-981.28" + wire width 16 \main_gpio_status + attribute \src "ls180.v:982.6-982.18" + wire \main_gpio_we + attribute \src "ls180.v:1085.6-1085.17" + wire \main_i2c_oe + attribute \src "ls180.v:1088.5-1088.16" + wire \main_i2c_re + attribute \src "ls180.v:1084.6-1084.18" + wire \main_i2c_scl + attribute \src "ls180.v:1086.6-1086.19" + wire \main_i2c_sda0 + attribute \src "ls180.v:1089.6-1089.19" + wire \main_i2c_sda1 + attribute \src "ls180.v:1090.6-1090.21" + wire \main_i2c_status + attribute \src "ls180.v:1087.11-1087.27" + wire width 3 \main_i2c_storage + attribute \src "ls180.v:1091.6-1091.17" + wire \main_i2c_we + attribute \src "ls180.v:248.5-248.17" + wire \main_int_rst + attribute \src "ls180.v:1551.6-1551.29" + wire \main_interface0_bus_ack + attribute \src "ls180.v:1545.13-1545.36" + wire width 32 \main_interface0_bus_adr + attribute \src "ls180.v:1554.11-1554.34" + wire width 2 \main_interface0_bus_bte + attribute \src "ls180.v:1553.11-1553.34" + wire width 3 \main_interface0_bus_cti + attribute \src "ls180.v:1549.6-1549.29" + wire \main_interface0_bus_cyc + attribute \src "ls180.v:1547.13-1547.38" + wire width 32 \main_interface0_bus_dat_r + attribute \src "ls180.v:1546.13-1546.38" + wire width 32 \main_interface0_bus_dat_w + attribute \src "ls180.v:1555.6-1555.29" + wire \main_interface0_bus_err + attribute \src "ls180.v:1548.12-1548.35" + wire width 4 \main_interface0_bus_sel + attribute \src "ls180.v:1550.6-1550.29" + wire \main_interface0_bus_stb + attribute \src "ls180.v:1552.6-1552.28" + wire \main_interface0_bus_we + attribute \src "ls180.v:1642.6-1642.29" + wire \main_interface1_bus_ack + attribute \src "ls180.v:1636.12-1636.35" + wire width 32 \main_interface1_bus_adr + attribute \src "ls180.v:1645.11-1645.34" + wire width 2 \main_interface1_bus_bte + attribute \src "ls180.v:1644.11-1644.34" + wire width 3 \main_interface1_bus_cti + attribute \src "ls180.v:1640.5-1640.28" + wire \main_interface1_bus_cyc + attribute \src "ls180.v:1638.13-1638.38" + wire width 32 \main_interface1_bus_dat_r + attribute \src "ls180.v:1637.12-1637.37" + wire width 32 \main_interface1_bus_dat_w + attribute \src "ls180.v:1646.6-1646.29" + wire \main_interface1_bus_err + attribute \src "ls180.v:1639.11-1639.34" + wire width 4 \main_interface1_bus_sel + attribute \src "ls180.v:1641.5-1641.28" + wire \main_interface1_bus_stb + attribute \src "ls180.v:1643.5-1643.27" + wire \main_interface1_bus_we + attribute \src "ls180.v:214.12-214.32" + wire width 7 \main_libresocsim_adr + attribute \src "ls180.v:62.6-62.32" + wire \main_libresocsim_bus_error + attribute \src "ls180.v:63.12-63.39" + wire width 32 \main_libresocsim_bus_errors + attribute \src "ls180.v:59.13-59.47" + wire width 32 \main_libresocsim_bus_errors_status + attribute \src "ls180.v:60.6-60.36" + wire \main_libresocsim_bus_errors_we + attribute \src "ls180.v:170.5-170.40" + wire \main_libresocsim_converter0_counter + attribute \src "ls180.v:1732.5-1732.62" + wire \main_libresocsim_converter0_counter_converter0_next_value + attribute \src "ls180.v:1733.5-1733.65" + wire \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:172.12-172.45" + wire width 64 \main_libresocsim_converter0_dat_r + attribute \src "ls180.v:171.6-171.39" + wire \main_libresocsim_converter0_reset + attribute \src "ls180.v:169.5-169.37" + wire \main_libresocsim_converter0_skip + attribute \src "ls180.v:185.5-185.40" + wire \main_libresocsim_converter1_counter + attribute \src "ls180.v:1736.5-1736.62" + wire \main_libresocsim_converter1_counter_converter1_next_value + attribute \src "ls180.v:1737.5-1737.65" + wire \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:187.12-187.45" + wire width 64 \main_libresocsim_converter1_dat_r + attribute \src "ls180.v:186.6-186.39" + wire \main_libresocsim_converter1_reset + attribute \src "ls180.v:184.5-184.37" + wire \main_libresocsim_converter1_skip + attribute \src "ls180.v:200.5-200.40" + wire \main_libresocsim_converter2_counter + attribute \src "ls180.v:1740.5-1740.62" + wire \main_libresocsim_converter2_counter_converter2_next_value + attribute \src "ls180.v:1741.5-1741.65" + wire \main_libresocsim_converter2_counter_converter2_next_value_ce + attribute \src "ls180.v:202.12-202.45" + wire width 64 \main_libresocsim_converter2_dat_r + attribute \src "ls180.v:201.6-201.39" + wire \main_libresocsim_converter2_reset + attribute \src "ls180.v:199.5-199.37" + wire \main_libresocsim_converter2_skip + attribute \src "ls180.v:215.13-215.35" + wire width 32 \main_libresocsim_dat_r + attribute \src "ls180.v:217.13-217.35" + wire width 32 \main_libresocsim_dat_w + attribute \src "ls180.v:223.5-223.27" + wire \main_libresocsim_en_re + attribute \src "ls180.v:222.5-222.32" + wire \main_libresocsim_en_storage + attribute \src "ls180.v:239.6-239.45" + wire \main_libresocsim_eventmanager_pending_r + attribute \src "ls180.v:238.6-238.46" + wire \main_libresocsim_eventmanager_pending_re + attribute \src "ls180.v:241.6-241.45" + wire \main_libresocsim_eventmanager_pending_w + attribute \src "ls180.v:240.6-240.46" + wire \main_libresocsim_eventmanager_pending_we + attribute \src "ls180.v:243.5-243.37" + wire \main_libresocsim_eventmanager_re + attribute \src "ls180.v:235.6-235.44" + wire \main_libresocsim_eventmanager_status_r + attribute \src "ls180.v:234.6-234.45" + wire \main_libresocsim_eventmanager_status_re + attribute \src "ls180.v:237.6-237.44" + wire \main_libresocsim_eventmanager_status_w + attribute \src "ls180.v:236.6-236.45" + wire \main_libresocsim_eventmanager_status_we + attribute \src "ls180.v:242.5-242.42" + wire \main_libresocsim_eventmanager_storage + attribute \src "ls180.v:164.6-164.57" + wire \main_libresocsim_interface0_converted_interface_ack + attribute \src "ls180.v:158.12-158.63" + wire width 30 \main_libresocsim_interface0_converted_interface_adr + attribute \src "ls180.v:167.11-167.62" + wire width 2 \main_libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:166.11-166.62" + wire width 3 \main_libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:162.5-162.56" + wire \main_libresocsim_interface0_converted_interface_cyc + attribute \src "ls180.v:160.13-160.66" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_r + attribute \src "ls180.v:159.12-159.65" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "ls180.v:168.6-168.57" + wire \main_libresocsim_interface0_converted_interface_err + attribute \src "ls180.v:161.11-161.62" + wire width 4 \main_libresocsim_interface0_converted_interface_sel + attribute \src "ls180.v:163.5-163.56" + wire \main_libresocsim_interface0_converted_interface_stb + attribute \src "ls180.v:165.5-165.55" + wire \main_libresocsim_interface0_converted_interface_we + attribute \src "ls180.v:179.6-179.57" + wire \main_libresocsim_interface1_converted_interface_ack + attribute \src "ls180.v:173.12-173.63" + wire width 30 \main_libresocsim_interface1_converted_interface_adr + attribute \src "ls180.v:182.11-182.62" + wire width 2 \main_libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:181.11-181.62" + wire width 3 \main_libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:177.5-177.56" + wire \main_libresocsim_interface1_converted_interface_cyc + attribute \src "ls180.v:175.13-175.66" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_r + attribute \src "ls180.v:174.12-174.65" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "ls180.v:183.6-183.57" + wire \main_libresocsim_interface1_converted_interface_err + attribute \src "ls180.v:176.11-176.62" + wire width 4 \main_libresocsim_interface1_converted_interface_sel + attribute \src "ls180.v:178.5-178.56" + wire \main_libresocsim_interface1_converted_interface_stb + attribute \src "ls180.v:180.5-180.55" + wire \main_libresocsim_interface1_converted_interface_we + attribute \src "ls180.v:194.6-194.57" + wire \main_libresocsim_interface2_converted_interface_ack + attribute \src "ls180.v:188.12-188.63" + wire width 30 \main_libresocsim_interface2_converted_interface_adr + attribute \src "ls180.v:197.11-197.62" + wire width 2 \main_libresocsim_interface2_converted_interface_bte + attribute \src "ls180.v:196.11-196.62" + wire width 3 \main_libresocsim_interface2_converted_interface_cti + attribute \src "ls180.v:192.5-192.56" + wire \main_libresocsim_interface2_converted_interface_cyc + attribute \src "ls180.v:190.13-190.66" + wire width 32 \main_libresocsim_interface2_converted_interface_dat_r + attribute \src "ls180.v:189.12-189.65" + wire width 32 \main_libresocsim_interface2_converted_interface_dat_w + attribute \src "ls180.v:198.6-198.57" + wire \main_libresocsim_interface2_converted_interface_err + attribute \src "ls180.v:191.11-191.62" + wire width 4 \main_libresocsim_interface2_converted_interface_sel + attribute \src "ls180.v:193.5-193.56" + wire \main_libresocsim_interface2_converted_interface_stb + attribute \src "ls180.v:195.5-195.55" + wire \main_libresocsim_interface2_converted_interface_we + attribute \src "ls180.v:228.6-228.26" + wire \main_libresocsim_irq + attribute \src "ls180.v:119.6-119.32" + wire \main_libresocsim_libresoc0 + attribute \src "ls180.v:120.6-120.32" + wire \main_libresocsim_libresoc1 + attribute \src "ls180.v:121.13-121.39" + wire width 64 \main_libresocsim_libresoc2 + attribute \src "ls180.v:123.12-123.45" + wire width 2 \main_libresocsim_libresoc_clk_sel + attribute \src "ls180.v:145.13-145.67" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i + attribute \src "ls180.v:146.13-146.67" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o + attribute \src "ls180.v:147.13-147.68" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe + attribute \src "ls180.v:152.6-152.61" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + attribute \src "ls180.v:153.6-153.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + attribute \src "ls180.v:154.6-154.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + attribute \src "ls180.v:155.6-155.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + attribute \src "ls180.v:125.6-125.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + attribute \src "ls180.v:126.6-126.66" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + attribute \src "ls180.v:127.6-127.66" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + attribute \src "ls180.v:128.6-128.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + attribute \src "ls180.v:133.13-133.68" + wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a + attribute \src "ls180.v:142.12-142.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba + attribute \src "ls180.v:139.6-139.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + attribute \src "ls180.v:141.6-141.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + attribute \src "ls180.v:140.6-140.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + attribute \src "ls180.v:143.12-143.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm + attribute \src "ls180.v:134.13-134.71" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i + attribute \src "ls180.v:135.13-135.71" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o + attribute \src "ls180.v:136.6-136.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + attribute \src "ls180.v:138.6-138.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + attribute \src "ls180.v:137.6-137.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + attribute \src "ls180.v:129.6-129.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + attribute \src "ls180.v:131.6-131.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + attribute \src "ls180.v:132.6-132.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + attribute \src "ls180.v:130.6-130.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + attribute \src "ls180.v:148.6-148.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + attribute \src "ls180.v:150.6-150.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + attribute \src "ls180.v:151.6-151.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + attribute \src "ls180.v:149.6-149.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + attribute \src "ls180.v:72.5-72.39" + wire \main_libresocsim_libresoc_dbus_ack + attribute \src "ls180.v:66.13-66.47" + wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:70.6-70.40" + wire \main_libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:68.13-68.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_r + attribute \src "ls180.v:67.13-67.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:74.5-74.39" + wire \main_libresocsim_libresoc_dbus_err + attribute \src "ls180.v:69.12-69.46" + wire width 8 \main_libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:71.6-71.40" + wire \main_libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:73.6-73.39" + wire \main_libresocsim_libresoc_dbus_we + attribute \src "ls180.v:81.5-81.39" + wire \main_libresocsim_libresoc_ibus_ack + attribute \src "ls180.v:75.13-75.47" + wire width 29 \main_libresocsim_libresoc_ibus_adr + attribute \src "ls180.v:79.6-79.40" + wire \main_libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:77.13-77.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_r + attribute \src "ls180.v:76.13-76.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:83.5-83.39" + wire \main_libresocsim_libresoc_ibus_err + attribute \src "ls180.v:78.12-78.46" + wire width 8 \main_libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:80.6-80.40" + wire \main_libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:82.6-82.39" + wire \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:65.12-65.47" + wire width 16 \main_libresocsim_libresoc_interrupt + attribute \src "ls180.v:115.6-115.40" + wire \main_libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:117.6-117.40" + wire \main_libresocsim_libresoc_jtag_tdi + attribute \src "ls180.v:118.6-118.40" + wire \main_libresocsim_libresoc_jtag_tdo + attribute \src "ls180.v:116.6-116.40" + wire \main_libresocsim_libresoc_jtag_tms + attribute \src "ls180.v:112.5-112.42" + wire \main_libresocsim_libresoc_jtag_wb_ack + attribute \src "ls180.v:106.13-106.50" + wire width 29 \main_libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:110.6-110.43" + wire \main_libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:108.13-108.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r + attribute \src "ls180.v:107.13-107.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:114.5-114.42" + wire \main_libresocsim_libresoc_jtag_wb_err + attribute \src "ls180.v:109.12-109.49" + wire width 8 \main_libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:111.6-111.43" + wire \main_libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:113.6-113.42" + wire \main_libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:122.6-122.40" + wire \main_libresocsim_libresoc_pll_18_o + attribute \src "ls180.v:124.6-124.41" + wire \main_libresocsim_libresoc_pll_lck_o + attribute \src "ls180.v:64.6-64.37" + wire \main_libresocsim_libresoc_reset + attribute \src "ls180.v:90.6-90.44" + wire \main_libresocsim_libresoc_xics_icp_ack + attribute \src "ls180.v:84.13-84.51" + wire width 30 \main_libresocsim_libresoc_xics_icp_adr + attribute \src "ls180.v:93.12-93.50" + wire width 2 \main_libresocsim_libresoc_xics_icp_bte + attribute \src "ls180.v:92.12-92.50" + wire width 3 \main_libresocsim_libresoc_xics_icp_cti + attribute \src "ls180.v:88.6-88.44" + wire \main_libresocsim_libresoc_xics_icp_cyc + attribute \src "ls180.v:86.13-86.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r + attribute \src "ls180.v:85.13-85.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w + attribute \src "ls180.v:94.6-94.44" + wire \main_libresocsim_libresoc_xics_icp_err + attribute \src "ls180.v:87.12-87.50" + wire width 4 \main_libresocsim_libresoc_xics_icp_sel + attribute \src "ls180.v:89.6-89.44" + wire \main_libresocsim_libresoc_xics_icp_stb + attribute \src "ls180.v:91.6-91.43" + wire \main_libresocsim_libresoc_xics_icp_we + attribute \src "ls180.v:101.6-101.44" + wire \main_libresocsim_libresoc_xics_ics_ack + attribute \src "ls180.v:95.13-95.51" + wire width 30 \main_libresocsim_libresoc_xics_ics_adr + attribute \src "ls180.v:104.12-104.50" + wire width 2 \main_libresocsim_libresoc_xics_ics_bte + attribute \src "ls180.v:103.12-103.50" + wire width 3 \main_libresocsim_libresoc_xics_ics_cti + attribute \src "ls180.v:99.6-99.44" + wire \main_libresocsim_libresoc_xics_ics_cyc + attribute \src "ls180.v:97.13-97.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r + attribute \src "ls180.v:96.13-96.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w + attribute \src "ls180.v:105.6-105.44" + wire \main_libresocsim_libresoc_xics_ics_err + attribute \src "ls180.v:98.12-98.50" + wire width 4 \main_libresocsim_libresoc_xics_ics_sel + attribute \src "ls180.v:100.6-100.44" + wire \main_libresocsim_libresoc_xics_ics_stb + attribute \src "ls180.v:102.6-102.43" + wire \main_libresocsim_libresoc_xics_ics_we + attribute \src "ls180.v:219.5-219.29" + wire \main_libresocsim_load_re + attribute \src "ls180.v:218.12-218.41" + wire width 32 \main_libresocsim_load_storage + attribute \src "ls180.v:209.5-209.33" + wire \main_libresocsim_ram_bus_ack + attribute \src "ls180.v:203.13-203.41" + wire width 30 \main_libresocsim_ram_bus_adr + attribute \src "ls180.v:212.12-212.40" + wire width 2 \main_libresocsim_ram_bus_bte + attribute \src "ls180.v:211.12-211.40" + wire width 3 \main_libresocsim_ram_bus_cti + attribute \src "ls180.v:207.6-207.34" + wire \main_libresocsim_ram_bus_cyc + attribute \src "ls180.v:205.13-205.43" + wire width 32 \main_libresocsim_ram_bus_dat_r + attribute \src "ls180.v:204.13-204.43" + wire width 32 \main_libresocsim_ram_bus_dat_w + attribute \src "ls180.v:213.5-213.33" + wire \main_libresocsim_ram_bus_err + attribute \src "ls180.v:206.12-206.40" + wire width 4 \main_libresocsim_ram_bus_sel + attribute \src "ls180.v:208.6-208.34" + wire \main_libresocsim_ram_bus_stb + attribute \src "ls180.v:210.6-210.33" + wire \main_libresocsim_ram_bus_we + attribute \src "ls180.v:221.5-221.31" + wire \main_libresocsim_reload_re + attribute \src "ls180.v:220.12-220.43" + wire width 32 \main_libresocsim_reload_storage + attribute \src "ls180.v:61.6-61.28" + wire \main_libresocsim_reset + attribute \src "ls180.v:56.5-56.30" + wire \main_libresocsim_reset_re + attribute \src "ls180.v:55.5-55.35" + wire \main_libresocsim_reset_storage + attribute \src "ls180.v:58.5-58.32" + wire \main_libresocsim_scratch_re + attribute \src "ls180.v:57.12-57.44" + wire width 32 \main_libresocsim_scratch_storage + attribute \src "ls180.v:225.5-225.37" + wire \main_libresocsim_update_value_re + attribute \src "ls180.v:224.5-224.42" + wire \main_libresocsim_update_value_storage + attribute \src "ls180.v:244.12-244.34" + wire width 32 \main_libresocsim_value + attribute \src "ls180.v:226.12-226.41" + wire width 32 \main_libresocsim_value_status + attribute \src "ls180.v:227.6-227.31" + wire \main_libresocsim_value_we + attribute \src "ls180.v:216.11-216.30" + wire width 4 \main_libresocsim_we + attribute \src "ls180.v:232.5-232.32" + wire \main_libresocsim_zero_clear + attribute \src "ls180.v:233.5-233.38" + wire \main_libresocsim_zero_old_trigger + attribute \src "ls180.v:230.5-230.34" + wire \main_libresocsim_zero_pending + attribute \src "ls180.v:229.6-229.34" + wire \main_libresocsim_zero_status + attribute \src "ls180.v:231.6-231.35" + wire \main_libresocsim_zero_trigger + attribute \src "ls180.v:826.6-826.26" + wire \main_litedram_wb_ack + attribute \src "ls180.v:820.12-820.32" + wire width 30 \main_litedram_wb_adr + attribute \src "ls180.v:824.5-824.25" + wire \main_litedram_wb_cyc + attribute \src "ls180.v:822.13-822.35" + wire width 16 \main_litedram_wb_dat_r + attribute \src "ls180.v:821.12-821.34" + wire width 16 \main_litedram_wb_dat_w + attribute \src "ls180.v:823.11-823.31" + wire width 2 \main_litedram_wb_sel + attribute \src "ls180.v:825.5-825.25" + wire \main_litedram_wb_stb + attribute \src "ls180.v:827.5-827.24" + wire \main_litedram_wb_we + attribute \src "ls180.v:1062.13-1062.20" + wire width 24 \main_nc + attribute \src "ls180.v:799.6-799.24" + wire \main_port_cmd_last + attribute \src "ls180.v:801.13-801.39" + wire width 24 \main_port_cmd_payload_addr + attribute \src "ls180.v:800.6-800.30" + wire \main_port_cmd_payload_we + attribute \src "ls180.v:798.6-798.25" + wire \main_port_cmd_ready + attribute \src "ls180.v:797.6-797.25" + wire \main_port_cmd_valid + attribute \src "ls180.v:796.6-796.21" + wire \main_port_flush + attribute \src "ls180.v:808.13-808.41" + wire width 16 \main_port_rdata_payload_data + attribute \src "ls180.v:807.6-807.27" + wire \main_port_rdata_ready + attribute \src "ls180.v:806.6-806.27" + wire \main_port_rdata_valid + attribute \src "ls180.v:804.13-804.41" + wire width 16 \main_port_wdata_payload_data + attribute \src "ls180.v:805.12-805.38" + wire width 2 \main_port_wdata_payload_we + attribute \src "ls180.v:803.6-803.27" + wire \main_port_wdata_ready + attribute \src "ls180.v:802.6-802.27" + wire \main_port_wdata_valid + attribute \src "ls180.v:1067.12-1067.29" + wire width 32 \main_pwm0_counter + attribute \src "ls180.v:1064.6-1064.22" + wire \main_pwm0_enable + attribute \src "ls180.v:1069.5-1069.24" + wire \main_pwm0_enable_re + attribute \src "ls180.v:1068.5-1068.29" + wire \main_pwm0_enable_storage + attribute \src "ls180.v:1066.13-1066.29" + wire width 32 \main_pwm0_period + attribute \src "ls180.v:1073.5-1073.24" + wire \main_pwm0_period_re + attribute \src "ls180.v:1072.12-1072.36" + wire width 32 \main_pwm0_period_storage + attribute \src "ls180.v:1065.13-1065.28" + wire width 32 \main_pwm0_width + attribute \src "ls180.v:1071.5-1071.23" + wire \main_pwm0_width_re + attribute \src "ls180.v:1070.12-1070.35" + wire width 32 \main_pwm0_width_storage + attribute \src "ls180.v:1077.12-1077.29" + wire width 32 \main_pwm1_counter + attribute \src "ls180.v:1074.6-1074.22" + wire \main_pwm1_enable + attribute \src "ls180.v:1079.5-1079.24" + wire \main_pwm1_enable_re + attribute \src "ls180.v:1078.5-1078.29" + wire \main_pwm1_enable_storage + attribute \src "ls180.v:1076.13-1076.29" + wire width 32 \main_pwm1_period + attribute \src "ls180.v:1083.5-1083.24" + wire \main_pwm1_period_re + attribute \src "ls180.v:1082.12-1082.36" + wire width 32 \main_pwm1_period_storage + attribute \src "ls180.v:1075.13-1075.28" + wire width 32 \main_pwm1_width + attribute \src "ls180.v:1081.5-1081.23" + wire \main_pwm1_width_re + attribute \src "ls180.v:1080.12-1080.35" + wire width 32 \main_pwm1_width_storage + attribute \src "ls180.v:265.11-265.25" + wire width 3 \main_rddata_en + attribute \src "ls180.v:1605.11-1605.43" + wire width 2 \main_sdblock2mem_converter_demux + attribute \src "ls180.v:1606.6-1606.42" + wire \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:1596.6-1596.43" + wire \main_sdblock2mem_converter_sink_first + attribute \src "ls180.v:1597.6-1597.42" + wire \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:1598.12-1598.56" + wire width 8 \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:1595.6-1595.43" + wire \main_sdblock2mem_converter_sink_ready + attribute \src "ls180.v:1594.6-1594.43" + wire \main_sdblock2mem_converter_sink_valid + attribute \src "ls180.v:1601.5-1601.44" + wire \main_sdblock2mem_converter_source_first + attribute \src "ls180.v:1602.5-1602.43" + wire \main_sdblock2mem_converter_source_last + attribute \src "ls180.v:1603.12-1603.58" + wire width 32 \main_sdblock2mem_converter_source_payload_data + attribute \src "ls180.v:1604.11-1604.70" + wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "ls180.v:1600.6-1600.45" + wire \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:1599.6-1599.45" + wire \main_sdblock2mem_converter_source_valid + attribute \src "ls180.v:1607.5-1607.42" + wire \main_sdblock2mem_converter_strobe_all + attribute \src "ls180.v:1580.11-1580.40" + wire width 5 \main_sdblock2mem_fifo_consume + attribute \src "ls180.v:1585.6-1585.35" + wire \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:1589.6-1589.41" + wire \main_sdblock2mem_fifo_fifo_in_first + attribute \src "ls180.v:1590.6-1590.40" + wire \main_sdblock2mem_fifo_fifo_in_last + attribute \src "ls180.v:1588.12-1588.54" + wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data + attribute \src "ls180.v:1592.6-1592.42" + wire \main_sdblock2mem_fifo_fifo_out_first + attribute \src "ls180.v:1593.6-1593.41" + wire \main_sdblock2mem_fifo_fifo_out_last + attribute \src "ls180.v:1591.12-1591.55" + wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data + attribute \src "ls180.v:1577.11-1577.38" + wire width 6 \main_sdblock2mem_fifo_level + attribute \src "ls180.v:1579.11-1579.40" + wire width 5 \main_sdblock2mem_fifo_produce + attribute \src "ls180.v:1586.12-1586.44" + wire width 5 \main_sdblock2mem_fifo_rdport_adr + attribute \src "ls180.v:1587.12-1587.46" + wire width 10 \main_sdblock2mem_fifo_rdport_dat_r + attribute \src "ls180.v:1578.5-1578.34" + wire \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:1563.6-1563.38" + wire \main_sdblock2mem_fifo_sink_first + attribute \src "ls180.v:1564.6-1564.37" + wire \main_sdblock2mem_fifo_sink_last + attribute \src "ls180.v:1565.12-1565.51" + wire width 8 \main_sdblock2mem_fifo_sink_payload_data + attribute \src "ls180.v:1562.6-1562.38" + wire \main_sdblock2mem_fifo_sink_ready + attribute \src "ls180.v:1561.6-1561.38" + wire \main_sdblock2mem_fifo_sink_valid + attribute \src "ls180.v:1568.6-1568.40" + wire \main_sdblock2mem_fifo_source_first + attribute \src "ls180.v:1569.6-1569.39" + wire \main_sdblock2mem_fifo_source_last + attribute \src "ls180.v:1570.12-1570.53" + wire width 8 \main_sdblock2mem_fifo_source_payload_data + attribute \src "ls180.v:1567.6-1567.40" + wire \main_sdblock2mem_fifo_source_ready + attribute \src "ls180.v:1566.6-1566.40" + wire \main_sdblock2mem_fifo_source_valid + attribute \src "ls180.v:1575.12-1575.46" + wire width 10 \main_sdblock2mem_fifo_syncfifo_din + attribute \src "ls180.v:1576.12-1576.47" + wire width 10 \main_sdblock2mem_fifo_syncfifo_dout + attribute \src "ls180.v:1573.6-1573.39" + wire \main_sdblock2mem_fifo_syncfifo_re + attribute \src "ls180.v:1574.6-1574.45" + wire \main_sdblock2mem_fifo_syncfifo_readable + attribute \src "ls180.v:1571.6-1571.39" + wire \main_sdblock2mem_fifo_syncfifo_we + attribute \src "ls180.v:1572.6-1572.45" + wire \main_sdblock2mem_fifo_syncfifo_writable + attribute \src "ls180.v:1581.11-1581.43" + wire width 5 \main_sdblock2mem_fifo_wrport_adr + attribute \src "ls180.v:1582.12-1582.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_r + attribute \src "ls180.v:1584.12-1584.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_w + attribute \src "ls180.v:1583.6-1583.37" + wire \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:1558.6-1558.38" + wire \main_sdblock2mem_sink_sink_first + attribute \src "ls180.v:1559.6-1559.37" + wire \main_sdblock2mem_sink_sink_last + attribute \src "ls180.v:1615.12-1615.54" + wire width 32 \main_sdblock2mem_sink_sink_payload_address + attribute \src "ls180.v:1560.12-1560.52" + wire width 8 \main_sdblock2mem_sink_sink_payload_data0 + attribute \src "ls180.v:1616.12-1616.52" + wire width 32 \main_sdblock2mem_sink_sink_payload_data1 + attribute \src "ls180.v:1557.6-1557.39" + wire \main_sdblock2mem_sink_sink_ready0 + attribute \src "ls180.v:1614.6-1614.39" + wire \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:1556.6-1556.39" + wire \main_sdblock2mem_sink_sink_valid0 + attribute \src "ls180.v:1613.5-1613.38" + wire \main_sdblock2mem_sink_sink_valid1 + attribute \src "ls180.v:1610.6-1610.42" + wire \main_sdblock2mem_source_source_first + attribute \src "ls180.v:1611.6-1611.41" + wire \main_sdblock2mem_source_source_last + attribute \src "ls180.v:1612.13-1612.56" + wire width 32 \main_sdblock2mem_source_source_payload_data + attribute \src "ls180.v:1609.6-1609.42" + wire \main_sdblock2mem_source_source_ready + attribute \src "ls180.v:1608.6-1608.42" + wire \main_sdblock2mem_source_source_valid + attribute \src "ls180.v:1632.13-1632.52" + wire width 32 \main_sdblock2mem_wishbonedmawriter_base + attribute \src "ls180.v:1623.5-1623.47" + wire \main_sdblock2mem_wishbonedmawriter_base_re + attribute \src "ls180.v:1622.12-1622.59" + wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage + attribute \src "ls180.v:1627.5-1627.49" + wire \main_sdblock2mem_wishbonedmawriter_enable_re + attribute \src "ls180.v:1626.5-1626.54" + wire \main_sdblock2mem_wishbonedmawriter_enable_storage + attribute \src "ls180.v:1634.13-1634.54" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length + attribute \src "ls180.v:1625.5-1625.49" + wire \main_sdblock2mem_wishbonedmawriter_length_re + attribute \src "ls180.v:1624.12-1624.61" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage + attribute \src "ls180.v:1631.5-1631.47" + wire \main_sdblock2mem_wishbonedmawriter_loop_re + attribute \src "ls180.v:1630.5-1630.52" + wire \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:1633.12-1633.53" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset + attribute \src "ls180.v:1853.12-1853.79" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + attribute \src "ls180.v:1854.5-1854.75" + wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:1635.6-1635.46" + wire \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:1619.6-1619.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_first + attribute \src "ls180.v:1620.6-1620.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_last + attribute \src "ls180.v:1621.13-1621.65" + wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "ls180.v:1618.5-1618.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_ready + attribute \src "ls180.v:1617.6-1617.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_valid + attribute \src "ls180.v:1628.5-1628.46" + wire \main_sdblock2mem_wishbonedmawriter_status + attribute \src "ls180.v:1629.6-1629.43" + wire \main_sdblock2mem_wishbonedmawriter_we + attribute \src "ls180.v:1397.5-1397.31" + wire \main_sdcore_block_count_re + attribute \src "ls180.v:1396.12-1396.43" + wire width 32 \main_sdcore_block_count_storage + attribute \src "ls180.v:1395.5-1395.32" + wire \main_sdcore_block_length_re + attribute \src "ls180.v:1394.11-1394.43" + wire width 10 \main_sdcore_block_length_storage + attribute \src "ls180.v:1381.5-1381.32" + wire \main_sdcore_cmd_argument_re + attribute \src "ls180.v:1380.12-1380.44" + wire width 32 \main_sdcore_cmd_argument_storage + attribute \src "ls180.v:1383.5-1383.31" + wire \main_sdcore_cmd_command_re + attribute \src "ls180.v:1382.12-1382.43" + wire width 32 \main_sdcore_cmd_command_storage + attribute \src "ls180.v:1536.11-1536.32" + wire width 3 \main_sdcore_cmd_count + attribute \src "ls180.v:1837.11-1837.55" + wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 + attribute \src "ls180.v:1838.5-1838.52" + wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:1537.5-1537.25" + wire \main_sdcore_cmd_done + attribute \src "ls180.v:1833.5-1833.48" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 + attribute \src "ls180.v:1834.5-1834.51" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:1538.5-1538.26" + wire \main_sdcore_cmd_error + attribute \src "ls180.v:1841.5-1841.49" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 + attribute \src "ls180.v:1842.5-1842.52" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:1390.12-1390.40" + wire width 4 \main_sdcore_cmd_event_status + attribute \src "ls180.v:1391.6-1391.30" + wire \main_sdcore_cmd_event_we + attribute \src "ls180.v:1388.13-1388.44" + wire width 128 \main_sdcore_cmd_response_status + attribute \src "ls180.v:1849.13-1849.67" + wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + attribute \src "ls180.v:1850.5-1850.62" + wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:1389.6-1389.33" + wire \main_sdcore_cmd_response_we + attribute \src "ls180.v:1385.6-1385.28" + wire \main_sdcore_cmd_send_r + attribute \src "ls180.v:1384.6-1384.29" + wire \main_sdcore_cmd_send_re + attribute \src "ls180.v:1387.5-1387.27" + wire \main_sdcore_cmd_send_w + attribute \src "ls180.v:1386.6-1386.29" + wire \main_sdcore_cmd_send_we + attribute \src "ls180.v:1539.5-1539.28" + wire \main_sdcore_cmd_timeout + attribute \src "ls180.v:1843.5-1843.51" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + attribute \src "ls180.v:1844.5-1844.54" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:1535.12-1535.32" + wire width 2 \main_sdcore_cmd_type + attribute \src "ls180.v:1497.11-1497.40" + wire width 4 \main_sdcore_crc16_checker_cnt + attribute \src "ls180.v:1503.5-1503.39" + wire \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:1502.12-1502.46" + wire width 16 \main_sdcore_crc16_checker_crc0_crc + attribute \src "ls180.v:1498.12-1498.50" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 + attribute \src "ls180.v:1499.13-1499.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 + attribute \src "ls180.v:1500.13-1500.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:1504.6-1504.43" + wire \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:1501.12-1501.46" + wire width 2 \main_sdcore_crc16_checker_crc0_val + attribute \src "ls180.v:1510.5-1510.39" + wire \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:1509.12-1509.46" + wire width 16 \main_sdcore_crc16_checker_crc1_crc + attribute \src "ls180.v:1505.12-1505.50" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 + attribute \src "ls180.v:1506.13-1506.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 + attribute \src "ls180.v:1507.13-1507.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:1511.6-1511.43" + wire \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:1508.12-1508.46" + wire width 2 \main_sdcore_crc16_checker_crc1_val + attribute \src "ls180.v:1517.5-1517.39" + wire \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:1516.12-1516.46" + wire width 16 \main_sdcore_crc16_checker_crc2_crc + attribute \src "ls180.v:1512.12-1512.50" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 + attribute \src "ls180.v:1513.13-1513.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 + attribute \src "ls180.v:1514.13-1514.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:1518.6-1518.43" + wire \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:1515.12-1515.46" + wire width 2 \main_sdcore_crc16_checker_crc2_val + attribute \src "ls180.v:1524.5-1524.39" + wire \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:1523.12-1523.46" + wire width 16 \main_sdcore_crc16_checker_crc3_crc + attribute \src "ls180.v:1519.12-1519.50" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 + attribute \src "ls180.v:1520.13-1520.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 + attribute \src "ls180.v:1521.13-1521.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:1525.6-1525.43" + wire \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:1522.12-1522.46" + wire width 2 \main_sdcore_crc16_checker_crc3_val + attribute \src "ls180.v:1526.12-1526.45" + wire width 16 \main_sdcore_crc16_checker_crctmp0 + attribute \src "ls180.v:1527.12-1527.45" + wire width 16 \main_sdcore_crc16_checker_crctmp1 + attribute \src "ls180.v:1528.12-1528.45" + wire width 16 \main_sdcore_crc16_checker_crctmp2 + attribute \src "ls180.v:1529.12-1529.45" + wire width 16 \main_sdcore_crc16_checker_crctmp3 + attribute \src "ls180.v:1531.12-1531.43" + wire width 16 \main_sdcore_crc16_checker_fifo0 + attribute \src "ls180.v:1532.12-1532.43" + wire width 16 \main_sdcore_crc16_checker_fifo1 + attribute \src "ls180.v:1533.12-1533.43" + wire width 16 \main_sdcore_crc16_checker_fifo2 + attribute \src "ls180.v:1534.12-1534.43" + wire width 16 \main_sdcore_crc16_checker_fifo3 + attribute \src "ls180.v:1488.5-1488.41" + wire \main_sdcore_crc16_checker_sink_first + attribute \src "ls180.v:1489.5-1489.40" + wire \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:1490.11-1490.54" + wire width 8 \main_sdcore_crc16_checker_sink_payload_data + attribute \src "ls180.v:1487.5-1487.41" + wire \main_sdcore_crc16_checker_sink_ready + attribute \src "ls180.v:1486.5-1486.41" + wire \main_sdcore_crc16_checker_sink_valid + attribute \src "ls180.v:1493.5-1493.43" + wire \main_sdcore_crc16_checker_source_first + attribute \src "ls180.v:1494.6-1494.43" + wire \main_sdcore_crc16_checker_source_last + attribute \src "ls180.v:1495.12-1495.57" + wire width 8 \main_sdcore_crc16_checker_source_payload_data + attribute \src "ls180.v:1492.6-1492.44" + wire \main_sdcore_crc16_checker_source_ready + attribute \src "ls180.v:1491.5-1491.43" + wire \main_sdcore_crc16_checker_source_valid + attribute \src "ls180.v:1496.11-1496.40" + wire width 8 \main_sdcore_crc16_checker_val + attribute \src "ls180.v:1530.5-1530.36" + wire \main_sdcore_crc16_checker_valid + attribute \src "ls180.v:1453.11-1453.41" + wire width 3 \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:1829.11-1829.80" + wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + attribute \src "ls180.v:1830.5-1830.77" + wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:1459.6-1459.41" + wire \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:1458.12-1458.47" + wire width 16 \main_sdcore_crc16_inserter_crc0_crc + attribute \src "ls180.v:1454.12-1454.51" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 + attribute \src "ls180.v:1455.13-1455.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 + attribute \src "ls180.v:1456.13-1456.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:1460.6-1460.44" + wire \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:1457.12-1457.47" + wire width 2 \main_sdcore_crc16_inserter_crc0_val + attribute \src "ls180.v:1466.6-1466.41" + wire \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:1465.12-1465.47" + wire width 16 \main_sdcore_crc16_inserter_crc1_crc + attribute \src "ls180.v:1461.12-1461.51" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 + attribute \src "ls180.v:1462.13-1462.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 + attribute \src "ls180.v:1463.13-1463.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:1467.6-1467.44" + wire \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:1464.12-1464.47" + wire width 2 \main_sdcore_crc16_inserter_crc1_val + attribute \src "ls180.v:1473.6-1473.41" + wire \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:1472.12-1472.47" + wire width 16 \main_sdcore_crc16_inserter_crc2_crc + attribute \src "ls180.v:1468.12-1468.51" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 + attribute \src "ls180.v:1469.13-1469.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 + attribute \src "ls180.v:1470.13-1470.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:1474.6-1474.44" + wire \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:1471.12-1471.47" + wire width 2 \main_sdcore_crc16_inserter_crc2_val + attribute \src "ls180.v:1480.6-1480.41" + wire \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:1479.12-1479.47" + wire width 16 \main_sdcore_crc16_inserter_crc3_crc + attribute \src "ls180.v:1475.12-1475.51" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 + attribute \src "ls180.v:1476.13-1476.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 + attribute \src "ls180.v:1477.13-1477.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:1481.6-1481.44" + wire \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:1478.12-1478.47" + wire width 2 \main_sdcore_crc16_inserter_crc3_val + attribute \src "ls180.v:1482.12-1482.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp0 + attribute \src "ls180.v:1821.12-1821.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + attribute \src "ls180.v:1822.5-1822.81" + wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:1483.12-1483.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp1 + attribute \src "ls180.v:1823.12-1823.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + attribute \src "ls180.v:1824.5-1824.81" + wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:1484.12-1484.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp2 + attribute \src "ls180.v:1825.12-1825.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + attribute \src "ls180.v:1826.5-1826.81" + wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:1485.12-1485.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp3 + attribute \src "ls180.v:1827.12-1827.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + attribute \src "ls180.v:1828.5-1828.81" + wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:1445.6-1445.43" + wire \main_sdcore_crc16_inserter_sink_first + attribute \src "ls180.v:1446.6-1446.42" + wire \main_sdcore_crc16_inserter_sink_last + attribute \src "ls180.v:1447.12-1447.56" + wire width 8 \main_sdcore_crc16_inserter_sink_payload_data + attribute \src "ls180.v:1444.5-1444.42" + wire \main_sdcore_crc16_inserter_sink_ready + attribute \src "ls180.v:1443.6-1443.43" + wire \main_sdcore_crc16_inserter_sink_valid + attribute \src "ls180.v:1450.5-1450.44" + wire \main_sdcore_crc16_inserter_source_first + attribute \src "ls180.v:1451.5-1451.43" + wire \main_sdcore_crc16_inserter_source_last + attribute \src "ls180.v:1452.11-1452.57" + wire width 8 \main_sdcore_crc16_inserter_source_payload_data + attribute \src "ls180.v:1449.5-1449.44" + wire \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:1448.5-1448.44" + wire \main_sdcore_crc16_inserter_source_valid + attribute \src "ls180.v:1441.6-1441.35" + wire \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:1440.11-1440.40" + wire width 7 \main_sdcore_crc7_inserter_crc + attribute \src "ls180.v:1398.11-1398.44" + wire width 7 \main_sdcore_crc7_inserter_crcreg0 + attribute \src "ls180.v:1399.12-1399.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg1 + attribute \src "ls180.v:1408.12-1408.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg10 + attribute \src "ls180.v:1409.12-1409.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg11 + attribute \src "ls180.v:1410.12-1410.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg12 + attribute \src "ls180.v:1411.12-1411.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg13 + attribute \src "ls180.v:1412.12-1412.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg14 + attribute \src "ls180.v:1413.12-1413.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg15 + attribute \src "ls180.v:1414.12-1414.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg16 + attribute \src "ls180.v:1415.12-1415.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg17 + attribute \src "ls180.v:1416.12-1416.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg18 + attribute \src "ls180.v:1417.12-1417.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg19 + attribute \src "ls180.v:1400.12-1400.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg2 + attribute \src "ls180.v:1418.12-1418.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg20 + attribute \src "ls180.v:1419.12-1419.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg21 + attribute \src "ls180.v:1420.12-1420.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg22 + attribute \src "ls180.v:1421.12-1421.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg23 + attribute \src "ls180.v:1422.12-1422.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg24 + attribute \src "ls180.v:1423.12-1423.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg25 + attribute \src "ls180.v:1424.12-1424.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg26 + attribute \src "ls180.v:1425.12-1425.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg27 + attribute \src "ls180.v:1426.12-1426.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg28 + attribute \src "ls180.v:1427.12-1427.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg29 + attribute \src "ls180.v:1401.12-1401.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg3 + attribute \src "ls180.v:1428.12-1428.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg30 + attribute \src "ls180.v:1429.12-1429.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg31 + attribute \src "ls180.v:1430.12-1430.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg32 + attribute \src "ls180.v:1431.12-1431.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg33 + attribute \src "ls180.v:1432.12-1432.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg34 + attribute \src "ls180.v:1433.12-1433.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg35 + attribute \src "ls180.v:1434.12-1434.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg36 + attribute \src "ls180.v:1435.12-1435.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg37 + attribute \src "ls180.v:1436.12-1436.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg38 + attribute \src "ls180.v:1437.12-1437.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg39 + attribute \src "ls180.v:1402.12-1402.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg4 + attribute \src "ls180.v:1438.12-1438.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:1403.12-1403.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg5 + attribute \src "ls180.v:1404.12-1404.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg6 + attribute \src "ls180.v:1405.12-1405.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg7 + attribute \src "ls180.v:1406.12-1406.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg8 + attribute \src "ls180.v:1407.12-1407.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg9 + attribute \src "ls180.v:1442.6-1442.38" + wire \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:1439.13-1439.42" + wire width 40 \main_sdcore_crc7_inserter_val + attribute \src "ls180.v:1541.12-1541.34" + wire width 32 \main_sdcore_data_count + attribute \src "ls180.v:1839.12-1839.57" + wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 + attribute \src "ls180.v:1840.5-1840.53" + wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:1542.5-1542.26" + wire \main_sdcore_data_done + attribute \src "ls180.v:1835.5-1835.49" + wire \main_sdcore_data_done_sdcore_fsm_next_value1 + attribute \src "ls180.v:1836.5-1836.52" + wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:1543.5-1543.27" + wire \main_sdcore_data_error + attribute \src "ls180.v:1845.5-1845.50" + wire \main_sdcore_data_error_sdcore_fsm_next_value6 + attribute \src "ls180.v:1846.5-1846.53" + wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:1392.12-1392.41" + wire width 4 \main_sdcore_data_event_status + attribute \src "ls180.v:1393.6-1393.31" + wire \main_sdcore_data_event_we + attribute \src "ls180.v:1544.5-1544.29" + wire \main_sdcore_data_timeout + attribute \src "ls180.v:1847.5-1847.52" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 + attribute \src "ls180.v:1848.5-1848.55" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:1540.12-1540.33" + wire width 2 \main_sdcore_data_type + attribute \src "ls180.v:1372.6-1372.33" + wire \main_sdcore_sink_sink_first + attribute \src "ls180.v:1373.6-1373.32" + wire \main_sdcore_sink_sink_last + attribute \src "ls180.v:1374.12-1374.46" + wire width 8 \main_sdcore_sink_sink_payload_data + attribute \src "ls180.v:1371.6-1371.33" + wire \main_sdcore_sink_sink_ready + attribute \src "ls180.v:1370.6-1370.33" + wire \main_sdcore_sink_sink_valid + attribute \src "ls180.v:1377.6-1377.37" + wire \main_sdcore_source_source_first + attribute \src "ls180.v:1378.6-1378.36" + wire \main_sdcore_source_source_last + attribute \src "ls180.v:1379.12-1379.50" + wire width 8 \main_sdcore_source_source_payload_data + attribute \src "ls180.v:1376.6-1376.37" + wire \main_sdcore_source_source_ready + attribute \src "ls180.v:1375.6-1375.37" + wire \main_sdcore_source_source_valid + attribute \src "ls180.v:1690.6-1690.38" + wire \main_sdmem2block_converter_first + attribute \src "ls180.v:1691.6-1691.37" + wire \main_sdmem2block_converter_last + attribute \src "ls180.v:1689.11-1689.41" + wire width 2 \main_sdmem2block_converter_mux + attribute \src "ls180.v:1680.6-1680.43" + wire \main_sdmem2block_converter_sink_first + attribute \src "ls180.v:1681.6-1681.42" + wire \main_sdmem2block_converter_sink_last + attribute \src "ls180.v:1682.13-1682.57" + wire width 32 \main_sdmem2block_converter_sink_payload_data + attribute \src "ls180.v:1679.6-1679.43" + wire \main_sdmem2block_converter_sink_ready + attribute \src "ls180.v:1678.6-1678.43" + wire \main_sdmem2block_converter_sink_valid + attribute \src "ls180.v:1685.6-1685.45" + wire \main_sdmem2block_converter_source_first + attribute \src "ls180.v:1686.6-1686.44" + wire \main_sdmem2block_converter_source_last + attribute \src "ls180.v:1687.11-1687.57" + wire width 8 \main_sdmem2block_converter_source_payload_data + attribute \src "ls180.v:1688.6-1688.65" + wire \main_sdmem2block_converter_source_payload_valid_token_count + attribute \src "ls180.v:1684.6-1684.45" + wire \main_sdmem2block_converter_source_ready + attribute \src "ls180.v:1683.6-1683.45" + wire \main_sdmem2block_converter_source_valid + attribute \src "ls180.v:1674.13-1674.38" + wire width 32 \main_sdmem2block_dma_base + attribute \src "ls180.v:1663.5-1663.33" + wire \main_sdmem2block_dma_base_re + attribute \src "ls180.v:1662.12-1662.45" + wire width 64 \main_sdmem2block_dma_base_storage + attribute \src "ls180.v:1661.12-1661.37" + wire width 32 \main_sdmem2block_dma_data + attribute \src "ls180.v:1857.12-1857.67" + wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "ls180.v:1858.5-1858.63" + wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:1668.5-1668.37" + wire \main_sdmem2block_dma_done_status + attribute \src "ls180.v:1669.6-1669.34" + wire \main_sdmem2block_dma_done_we + attribute \src "ls180.v:1667.5-1667.35" + wire \main_sdmem2block_dma_enable_re + attribute \src "ls180.v:1666.5-1666.40" + wire \main_sdmem2block_dma_enable_storage + attribute \src "ls180.v:1676.13-1676.40" + wire width 32 \main_sdmem2block_dma_length + attribute \src "ls180.v:1665.5-1665.35" + wire \main_sdmem2block_dma_length_re + attribute \src "ls180.v:1664.12-1664.47" + wire width 32 \main_sdmem2block_dma_length_storage + attribute \src "ls180.v:1671.5-1671.33" + wire \main_sdmem2block_dma_loop_re + attribute \src "ls180.v:1670.5-1670.38" + wire \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:1675.12-1675.39" + wire width 32 \main_sdmem2block_dma_offset + attribute \src "ls180.v:1861.12-1861.79" + wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + attribute \src "ls180.v:1862.5-1862.75" + wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:1672.13-1672.47" + wire width 32 \main_sdmem2block_dma_offset_status + attribute \src "ls180.v:1673.6-1673.36" + wire \main_sdmem2block_dma_offset_we + attribute \src "ls180.v:1677.6-1677.32" + wire \main_sdmem2block_dma_reset + attribute \src "ls180.v:1654.5-1654.35" + wire \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:1655.12-1655.53" + wire width 32 \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:1653.5-1653.36" + wire \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:1652.5-1652.36" + wire \main_sdmem2block_dma_sink_valid + attribute \src "ls180.v:1658.5-1658.38" + wire \main_sdmem2block_dma_source_first + attribute \src "ls180.v:1659.5-1659.37" + wire \main_sdmem2block_dma_source_last + attribute \src "ls180.v:1660.12-1660.52" + wire width 32 \main_sdmem2block_dma_source_payload_data + attribute \src "ls180.v:1657.6-1657.39" + wire \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:1656.5-1656.38" + wire \main_sdmem2block_dma_source_valid + attribute \src "ls180.v:1716.11-1716.40" + wire width 5 \main_sdmem2block_fifo_consume + attribute \src "ls180.v:1721.6-1721.35" + wire \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:1725.6-1725.41" + wire \main_sdmem2block_fifo_fifo_in_first + attribute \src "ls180.v:1726.6-1726.40" + wire \main_sdmem2block_fifo_fifo_in_last + attribute \src "ls180.v:1724.12-1724.54" + wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data + attribute \src "ls180.v:1728.6-1728.42" + wire \main_sdmem2block_fifo_fifo_out_first + attribute \src "ls180.v:1729.6-1729.41" + wire \main_sdmem2block_fifo_fifo_out_last + attribute \src "ls180.v:1727.12-1727.55" + wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data + attribute \src "ls180.v:1713.11-1713.38" + wire width 6 \main_sdmem2block_fifo_level + attribute \src "ls180.v:1715.11-1715.40" + wire width 5 \main_sdmem2block_fifo_produce + attribute \src "ls180.v:1722.12-1722.44" + wire width 5 \main_sdmem2block_fifo_rdport_adr + attribute \src "ls180.v:1723.12-1723.46" + wire width 10 \main_sdmem2block_fifo_rdport_dat_r + attribute \src "ls180.v:1714.5-1714.34" + wire \main_sdmem2block_fifo_replace + attribute \src "ls180.v:1699.6-1699.38" + wire \main_sdmem2block_fifo_sink_first + attribute \src "ls180.v:1700.6-1700.37" + wire \main_sdmem2block_fifo_sink_last + attribute \src "ls180.v:1701.12-1701.51" + wire width 8 \main_sdmem2block_fifo_sink_payload_data + attribute \src "ls180.v:1698.6-1698.38" + wire \main_sdmem2block_fifo_sink_ready + attribute \src "ls180.v:1697.6-1697.38" + wire \main_sdmem2block_fifo_sink_valid + attribute \src "ls180.v:1704.6-1704.40" + wire \main_sdmem2block_fifo_source_first + attribute \src "ls180.v:1705.6-1705.39" + wire \main_sdmem2block_fifo_source_last + attribute \src "ls180.v:1706.12-1706.53" + wire width 8 \main_sdmem2block_fifo_source_payload_data + attribute \src "ls180.v:1703.6-1703.40" + wire \main_sdmem2block_fifo_source_ready + attribute \src "ls180.v:1702.6-1702.40" + wire \main_sdmem2block_fifo_source_valid + attribute \src "ls180.v:1711.12-1711.46" + wire width 10 \main_sdmem2block_fifo_syncfifo_din + attribute \src "ls180.v:1712.12-1712.47" + wire width 10 \main_sdmem2block_fifo_syncfifo_dout + attribute \src "ls180.v:1709.6-1709.39" + wire \main_sdmem2block_fifo_syncfifo_re + attribute \src "ls180.v:1710.6-1710.45" + wire \main_sdmem2block_fifo_syncfifo_readable + attribute \src "ls180.v:1707.6-1707.39" + wire \main_sdmem2block_fifo_syncfifo_we + attribute \src "ls180.v:1708.6-1708.45" + wire \main_sdmem2block_fifo_syncfifo_writable + attribute \src "ls180.v:1717.11-1717.43" + wire width 5 \main_sdmem2block_fifo_wrport_adr + attribute \src "ls180.v:1718.12-1718.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_r + attribute \src "ls180.v:1720.12-1720.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_w + attribute \src "ls180.v:1719.6-1719.37" + wire \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:1649.6-1649.43" + wire \main_sdmem2block_source_source_first0 + attribute \src "ls180.v:1694.6-1694.43" + wire \main_sdmem2block_source_source_first1 + attribute \src "ls180.v:1650.6-1650.42" + wire \main_sdmem2block_source_source_last0 + attribute \src "ls180.v:1695.6-1695.42" + wire \main_sdmem2block_source_source_last1 + attribute \src "ls180.v:1651.12-1651.56" + wire width 8 \main_sdmem2block_source_source_payload_data0 + attribute \src "ls180.v:1696.12-1696.56" + wire width 8 \main_sdmem2block_source_source_payload_data1 + attribute \src "ls180.v:1648.6-1648.43" + wire \main_sdmem2block_source_source_ready0 + attribute \src "ls180.v:1693.6-1693.43" + wire \main_sdmem2block_source_source_ready1 + attribute \src "ls180.v:1647.6-1647.43" + wire \main_sdmem2block_source_source_valid0 + attribute \src "ls180.v:1692.6-1692.43" + wire \main_sdmem2block_source_source_valid1 + attribute \src "ls180.v:1098.6-1098.27" + wire \main_sdphy_clocker_ce + attribute \src "ls180.v:1097.5-1097.28" + wire \main_sdphy_clocker_clk0 + attribute \src "ls180.v:1100.5-1100.28" + wire \main_sdphy_clocker_clk1 + attribute \src "ls180.v:1101.5-1101.29" + wire \main_sdphy_clocker_clk_d + attribute \src "ls180.v:1099.11-1099.34" + wire width 9 \main_sdphy_clocker_clks + attribute \src "ls180.v:1095.5-1095.26" + wire \main_sdphy_clocker_re + attribute \src "ls180.v:1096.6-1096.29" + wire \main_sdphy_clocker_stop + attribute \src "ls180.v:1094.11-1094.37" + wire width 9 \main_sdphy_clocker_storage + attribute \src "ls180.v:1198.6-1198.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_first + attribute \src "ls180.v:1199.6-1199.40" + wire \main_sdphy_cmdr_cmdr_buf_sink_last + attribute \src "ls180.v:1200.12-1200.54" + wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data + attribute \src "ls180.v:1197.6-1197.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_ready + attribute \src "ls180.v:1196.6-1196.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_valid + attribute \src "ls180.v:1203.5-1203.42" + wire \main_sdphy_cmdr_cmdr_buf_source_first + attribute \src "ls180.v:1204.5-1204.41" + wire \main_sdphy_cmdr_cmdr_buf_source_last + attribute \src "ls180.v:1205.11-1205.55" + wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data + attribute \src "ls180.v:1202.6-1202.43" + wire \main_sdphy_cmdr_cmdr_buf_source_ready + attribute \src "ls180.v:1201.5-1201.42" + wire \main_sdphy_cmdr_cmdr_buf_source_valid + attribute \src "ls180.v:1188.11-1188.47" + wire width 3 \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:1189.6-1189.46" + wire \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:1179.5-1179.46" + wire \main_sdphy_cmdr_cmdr_converter_sink_first + attribute \src "ls180.v:1180.5-1180.45" + wire \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:1181.6-1181.54" + wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:1178.6-1178.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_ready + attribute \src "ls180.v:1177.6-1177.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_valid + attribute \src "ls180.v:1184.5-1184.48" + wire \main_sdphy_cmdr_cmdr_converter_source_first + attribute \src "ls180.v:1185.5-1185.47" + wire \main_sdphy_cmdr_cmdr_converter_source_last + attribute \src "ls180.v:1186.11-1186.61" + wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data + attribute \src "ls180.v:1187.11-1187.74" + wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1183.6-1183.49" + wire \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:1182.6-1182.49" + wire \main_sdphy_cmdr_cmdr_converter_source_valid + attribute \src "ls180.v:1190.5-1190.46" + wire \main_sdphy_cmdr_cmdr_converter_strobe_all + attribute \src "ls180.v:1161.6-1161.40" + wire \main_sdphy_cmdr_cmdr_pads_in_first + attribute \src "ls180.v:1162.6-1162.39" + wire \main_sdphy_cmdr_cmdr_pads_in_last + attribute \src "ls180.v:1163.6-1163.46" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk + attribute \src "ls180.v:1164.6-1164.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + attribute \src "ls180.v:1165.6-1165.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o + attribute \src "ls180.v:1166.6-1166.49" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1167.12-1167.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i + attribute \src "ls180.v:1168.12-1168.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o + attribute \src "ls180.v:1169.6-1169.50" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe + attribute \src "ls180.v:1160.5-1160.39" + wire \main_sdphy_cmdr_cmdr_pads_in_ready + attribute \src "ls180.v:1159.6-1159.40" + wire \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:1206.5-1206.31" + wire \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:1801.5-1801.59" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + attribute \src "ls180.v:1802.5-1802.62" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:1176.5-1176.29" + wire \main_sdphy_cmdr_cmdr_run + attribute \src "ls180.v:1172.6-1172.47" + wire \main_sdphy_cmdr_cmdr_source_source_first0 + attribute \src "ls180.v:1193.6-1193.47" + wire \main_sdphy_cmdr_cmdr_source_source_first1 + attribute \src "ls180.v:1173.6-1173.46" + wire \main_sdphy_cmdr_cmdr_source_source_last0 + attribute \src "ls180.v:1194.6-1194.46" + wire \main_sdphy_cmdr_cmdr_source_source_last1 + attribute \src "ls180.v:1174.12-1174.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 + attribute \src "ls180.v:1195.12-1195.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 + attribute \src "ls180.v:1171.5-1171.46" + wire \main_sdphy_cmdr_cmdr_source_source_ready0 + attribute \src "ls180.v:1192.6-1192.47" + wire \main_sdphy_cmdr_cmdr_source_source_ready1 + attribute \src "ls180.v:1170.6-1170.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:1191.6-1191.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid1 + attribute \src "ls180.v:1175.6-1175.32" + wire \main_sdphy_cmdr_cmdr_start + attribute \src "ls180.v:1158.11-1158.32" + wire width 8 \main_sdphy_cmdr_count + attribute \src "ls180.v:1797.11-1797.60" + wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + attribute \src "ls180.v:1798.5-1798.57" + wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:1133.5-1133.42" + wire \main_sdphy_cmdr_pads_in_pads_in_first + attribute \src "ls180.v:1134.5-1134.41" + wire \main_sdphy_cmdr_pads_in_pads_in_last + attribute \src "ls180.v:1135.5-1135.48" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1136.6-1136.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1137.5-1137.50" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1138.5-1138.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1139.12-1139.58" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1140.11-1140.57" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1141.5-1141.52" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1132.6-1132.43" + wire \main_sdphy_cmdr_pads_in_pads_in_ready + attribute \src "ls180.v:1131.6-1131.43" + wire \main_sdphy_cmdr_pads_in_pads_in_valid + attribute \src "ls180.v:1143.5-1143.41" + wire \main_sdphy_cmdr_pads_out_payload_clk + attribute \src "ls180.v:1144.5-1144.43" + wire \main_sdphy_cmdr_pads_out_payload_cmd_o + attribute \src "ls180.v:1145.5-1145.44" + wire \main_sdphy_cmdr_pads_out_payload_cmd_oe + attribute \src "ls180.v:1146.11-1146.50" + wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o + attribute \src "ls180.v:1147.5-1147.45" + wire \main_sdphy_cmdr_pads_out_payload_data_oe + attribute \src "ls180.v:1142.6-1142.36" + wire \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:1150.5-1150.30" + wire \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:1151.11-1151.46" + wire width 8 \main_sdphy_cmdr_sink_payload_length + attribute \src "ls180.v:1149.5-1149.31" + wire \main_sdphy_cmdr_sink_ready + attribute \src "ls180.v:1148.5-1148.31" + wire \main_sdphy_cmdr_sink_valid + attribute \src "ls180.v:1154.5-1154.32" + wire \main_sdphy_cmdr_source_last + attribute \src "ls180.v:1155.11-1155.46" + wire width 8 \main_sdphy_cmdr_source_payload_data + attribute \src "ls180.v:1156.11-1156.48" + wire width 3 \main_sdphy_cmdr_source_payload_status + attribute \src "ls180.v:1153.5-1153.33" + wire \main_sdphy_cmdr_source_ready + attribute \src "ls180.v:1152.5-1152.33" + wire \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:1157.12-1157.35" + wire width 32 \main_sdphy_cmdr_timeout + attribute \src "ls180.v:1799.12-1799.63" + wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + attribute \src "ls180.v:1800.5-1800.59" + wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:1130.11-1130.32" + wire width 8 \main_sdphy_cmdw_count + attribute \src "ls180.v:1793.11-1793.59" + wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + attribute \src "ls180.v:1794.5-1794.56" + wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:1129.5-1129.25" + wire \main_sdphy_cmdw_done + attribute \src "ls180.v:1117.6-1117.43" + wire \main_sdphy_cmdw_pads_in_payload_cmd_i + attribute \src "ls180.v:1118.12-1118.50" + wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i + attribute \src "ls180.v:1116.6-1116.35" + wire \main_sdphy_cmdw_pads_in_valid + attribute \src "ls180.v:1120.5-1120.41" + wire \main_sdphy_cmdw_pads_out_payload_clk + attribute \src "ls180.v:1121.5-1121.43" + wire \main_sdphy_cmdw_pads_out_payload_cmd_o + attribute \src "ls180.v:1122.5-1122.44" + wire \main_sdphy_cmdw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1123.11-1123.50" + wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o + attribute \src "ls180.v:1124.5-1124.45" + wire \main_sdphy_cmdw_pads_out_payload_data_oe + attribute \src "ls180.v:1119.6-1119.36" + wire \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:1127.5-1127.30" + wire \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:1128.11-1128.44" + wire width 8 \main_sdphy_cmdw_sink_payload_data + attribute \src "ls180.v:1126.5-1126.31" + wire \main_sdphy_cmdw_sink_ready + attribute \src "ls180.v:1125.5-1125.31" + wire \main_sdphy_cmdw_sink_valid + attribute \src "ls180.v:1314.11-1314.33" + wire width 10 \main_sdphy_datar_count + attribute \src "ls180.v:1813.11-1813.62" + wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + attribute \src "ls180.v:1814.5-1814.59" + wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:1354.6-1354.43" + wire \main_sdphy_datar_datar_buf_sink_first + attribute \src "ls180.v:1355.6-1355.42" + wire \main_sdphy_datar_datar_buf_sink_last + attribute \src "ls180.v:1356.12-1356.56" + wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data + attribute \src "ls180.v:1353.6-1353.43" + wire \main_sdphy_datar_datar_buf_sink_ready + attribute \src "ls180.v:1352.6-1352.43" + wire \main_sdphy_datar_datar_buf_sink_valid + attribute \src "ls180.v:1359.5-1359.44" + wire \main_sdphy_datar_datar_buf_source_first + attribute \src "ls180.v:1360.5-1360.43" + wire \main_sdphy_datar_datar_buf_source_last + attribute \src "ls180.v:1361.11-1361.57" + wire width 8 \main_sdphy_datar_datar_buf_source_payload_data + attribute \src "ls180.v:1358.6-1358.45" + wire \main_sdphy_datar_datar_buf_source_ready + attribute \src "ls180.v:1357.5-1357.44" + wire \main_sdphy_datar_datar_buf_source_valid + attribute \src "ls180.v:1344.5-1344.43" + wire \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:1345.6-1345.48" + wire \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:1335.5-1335.48" + wire \main_sdphy_datar_datar_converter_sink_first + attribute \src "ls180.v:1336.5-1336.47" + wire \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:1337.12-1337.62" + wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:1334.6-1334.49" + wire \main_sdphy_datar_datar_converter_sink_ready + attribute \src "ls180.v:1333.6-1333.49" + wire \main_sdphy_datar_datar_converter_sink_valid + attribute \src "ls180.v:1340.5-1340.50" + wire \main_sdphy_datar_datar_converter_source_first + attribute \src "ls180.v:1341.5-1341.49" + wire \main_sdphy_datar_datar_converter_source_last + attribute \src "ls180.v:1342.11-1342.63" + wire width 8 \main_sdphy_datar_datar_converter_source_payload_data + attribute \src "ls180.v:1343.11-1343.76" + wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count + attribute \src "ls180.v:1339.6-1339.51" + wire \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:1338.6-1338.51" + wire \main_sdphy_datar_datar_converter_source_valid + attribute \src "ls180.v:1346.5-1346.48" + wire \main_sdphy_datar_datar_converter_strobe_all + attribute \src "ls180.v:1317.6-1317.42" + wire \main_sdphy_datar_datar_pads_in_first + attribute \src "ls180.v:1318.6-1318.41" + wire \main_sdphy_datar_datar_pads_in_last + attribute \src "ls180.v:1319.6-1319.48" + wire \main_sdphy_datar_datar_pads_in_payload_clk + attribute \src "ls180.v:1320.6-1320.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_i + attribute \src "ls180.v:1321.6-1321.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_o + attribute \src "ls180.v:1322.6-1322.51" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe + attribute \src "ls180.v:1323.12-1323.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i + attribute \src "ls180.v:1324.12-1324.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o + attribute \src "ls180.v:1325.6-1325.52" + wire \main_sdphy_datar_datar_pads_in_payload_data_oe + attribute \src "ls180.v:1316.5-1316.41" + wire \main_sdphy_datar_datar_pads_in_ready + attribute \src "ls180.v:1315.6-1315.42" + wire \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:1362.5-1362.33" + wire \main_sdphy_datar_datar_reset + attribute \src "ls180.v:1817.5-1817.62" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + attribute \src "ls180.v:1818.5-1818.65" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:1332.5-1332.31" + wire \main_sdphy_datar_datar_run + attribute \src "ls180.v:1328.6-1328.49" + wire \main_sdphy_datar_datar_source_source_first0 + attribute \src "ls180.v:1349.6-1349.49" + wire \main_sdphy_datar_datar_source_source_first1 + attribute \src "ls180.v:1329.6-1329.48" + wire \main_sdphy_datar_datar_source_source_last0 + attribute \src "ls180.v:1350.6-1350.48" + wire \main_sdphy_datar_datar_source_source_last1 + attribute \src "ls180.v:1330.12-1330.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 + attribute \src "ls180.v:1351.12-1351.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 + attribute \src "ls180.v:1327.5-1327.48" + wire \main_sdphy_datar_datar_source_source_ready0 + attribute \src "ls180.v:1348.6-1348.49" + wire \main_sdphy_datar_datar_source_source_ready1 + attribute \src "ls180.v:1326.6-1326.49" + wire \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:1347.6-1347.49" + wire \main_sdphy_datar_datar_source_source_valid1 + attribute \src "ls180.v:1331.6-1331.34" + wire \main_sdphy_datar_datar_start + attribute \src "ls180.v:1287.5-1287.43" + wire \main_sdphy_datar_pads_in_pads_in_first + attribute \src "ls180.v:1288.5-1288.42" + wire \main_sdphy_datar_pads_in_pads_in_last + attribute \src "ls180.v:1289.5-1289.49" + wire \main_sdphy_datar_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1290.6-1290.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1291.5-1291.51" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1292.5-1292.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1293.12-1293.59" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1294.11-1294.58" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1295.5-1295.53" + wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1286.6-1286.44" + wire \main_sdphy_datar_pads_in_pads_in_ready + attribute \src "ls180.v:1285.6-1285.44" + wire \main_sdphy_datar_pads_in_pads_in_valid + attribute \src "ls180.v:1297.5-1297.42" + wire \main_sdphy_datar_pads_out_payload_clk + attribute \src "ls180.v:1298.5-1298.44" + wire \main_sdphy_datar_pads_out_payload_cmd_o + attribute \src "ls180.v:1299.5-1299.45" + wire \main_sdphy_datar_pads_out_payload_cmd_oe + attribute \src "ls180.v:1300.11-1300.51" + wire width 4 \main_sdphy_datar_pads_out_payload_data_o + attribute \src "ls180.v:1301.5-1301.46" + wire \main_sdphy_datar_pads_out_payload_data_oe + attribute \src "ls180.v:1296.6-1296.37" + wire \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:1304.5-1304.31" + wire \main_sdphy_datar_sink_last + attribute \src "ls180.v:1305.11-1305.53" + wire width 10 \main_sdphy_datar_sink_payload_block_length + attribute \src "ls180.v:1303.5-1303.32" + wire \main_sdphy_datar_sink_ready + attribute \src "ls180.v:1302.5-1302.32" + wire \main_sdphy_datar_sink_valid + attribute \src "ls180.v:1308.5-1308.34" + wire \main_sdphy_datar_source_first + attribute \src "ls180.v:1309.5-1309.33" + wire \main_sdphy_datar_source_last + attribute \src "ls180.v:1310.11-1310.47" + wire width 8 \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:1311.11-1311.49" + wire width 3 \main_sdphy_datar_source_payload_status + attribute \src "ls180.v:1307.5-1307.34" + wire \main_sdphy_datar_source_ready + attribute \src "ls180.v:1306.5-1306.34" + wire \main_sdphy_datar_source_valid + attribute \src "ls180.v:1312.5-1312.26" + wire \main_sdphy_datar_stop + attribute \src "ls180.v:1313.12-1313.36" + wire width 32 \main_sdphy_datar_timeout + attribute \src "ls180.v:1815.12-1815.65" + wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + attribute \src "ls180.v:1816.5-1816.61" + wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:1222.11-1222.33" + wire width 8 \main_sdphy_dataw_count + attribute \src "ls180.v:1809.11-1809.54" + wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value + attribute \src "ls180.v:1810.5-1810.51" + wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:1276.6-1276.42" + wire \main_sdphy_dataw_crcr_buf_sink_first + attribute \src "ls180.v:1277.6-1277.41" + wire \main_sdphy_dataw_crcr_buf_sink_last + attribute \src "ls180.v:1278.12-1278.55" + wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data + attribute \src "ls180.v:1275.6-1275.42" + wire \main_sdphy_dataw_crcr_buf_sink_ready + attribute \src "ls180.v:1274.6-1274.42" + wire \main_sdphy_dataw_crcr_buf_sink_valid + attribute \src "ls180.v:1281.5-1281.43" + wire \main_sdphy_dataw_crcr_buf_source_first + attribute \src "ls180.v:1282.5-1282.42" + wire \main_sdphy_dataw_crcr_buf_source_last + attribute \src "ls180.v:1283.11-1283.56" + wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data + attribute \src "ls180.v:1280.6-1280.44" + wire \main_sdphy_dataw_crcr_buf_source_ready + attribute \src "ls180.v:1279.5-1279.43" + wire \main_sdphy_dataw_crcr_buf_source_valid + attribute \src "ls180.v:1266.11-1266.48" + wire width 3 \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:1267.6-1267.47" + wire \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:1257.5-1257.47" + wire \main_sdphy_dataw_crcr_converter_sink_first + attribute \src "ls180.v:1258.5-1258.46" + wire \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:1259.6-1259.55" + wire \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:1256.6-1256.48" + wire \main_sdphy_dataw_crcr_converter_sink_ready + attribute \src "ls180.v:1255.6-1255.48" + wire \main_sdphy_dataw_crcr_converter_sink_valid + attribute \src "ls180.v:1262.5-1262.49" + wire \main_sdphy_dataw_crcr_converter_source_first + attribute \src "ls180.v:1263.5-1263.48" + wire \main_sdphy_dataw_crcr_converter_source_last + attribute \src "ls180.v:1264.11-1264.62" + wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data + attribute \src "ls180.v:1265.11-1265.75" + wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1261.6-1261.50" + wire \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:1260.6-1260.50" + wire \main_sdphy_dataw_crcr_converter_source_valid + attribute \src "ls180.v:1268.5-1268.47" + wire \main_sdphy_dataw_crcr_converter_strobe_all + attribute \src "ls180.v:1239.6-1239.41" + wire \main_sdphy_dataw_crcr_pads_in_first + attribute \src "ls180.v:1240.6-1240.40" + wire \main_sdphy_dataw_crcr_pads_in_last + attribute \src "ls180.v:1241.6-1241.47" + wire \main_sdphy_dataw_crcr_pads_in_payload_clk + attribute \src "ls180.v:1242.6-1242.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i + attribute \src "ls180.v:1243.6-1243.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o + attribute \src "ls180.v:1244.6-1244.50" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1245.12-1245.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i + attribute \src "ls180.v:1246.12-1246.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o + attribute \src "ls180.v:1247.6-1247.51" + wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe + attribute \src "ls180.v:1238.5-1238.40" + wire \main_sdphy_dataw_crcr_pads_in_ready + attribute \src "ls180.v:1237.6-1237.41" + wire \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:1284.5-1284.32" + wire \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:1805.5-1805.59" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + attribute \src "ls180.v:1806.5-1806.62" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:1254.5-1254.30" + wire \main_sdphy_dataw_crcr_run + attribute \src "ls180.v:1250.6-1250.48" + wire \main_sdphy_dataw_crcr_source_source_first0 + attribute \src "ls180.v:1271.6-1271.48" + wire \main_sdphy_dataw_crcr_source_source_first1 + attribute \src "ls180.v:1251.6-1251.47" + wire \main_sdphy_dataw_crcr_source_source_last0 + attribute \src "ls180.v:1272.6-1272.47" + wire \main_sdphy_dataw_crcr_source_source_last1 + attribute \src "ls180.v:1252.12-1252.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 + attribute \src "ls180.v:1273.12-1273.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 + attribute \src "ls180.v:1249.5-1249.47" + wire \main_sdphy_dataw_crcr_source_source_ready0 + attribute \src "ls180.v:1270.6-1270.48" + wire \main_sdphy_dataw_crcr_source_source_ready1 + attribute \src "ls180.v:1248.6-1248.48" + wire \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:1269.6-1269.48" + wire \main_sdphy_dataw_crcr_source_source_valid1 + attribute \src "ls180.v:1253.6-1253.33" + wire \main_sdphy_dataw_crcr_start + attribute \src "ls180.v:1236.5-1236.27" + wire \main_sdphy_dataw_error + attribute \src "ls180.v:1225.5-1225.43" + wire \main_sdphy_dataw_pads_in_pads_in_first + attribute \src "ls180.v:1226.5-1226.42" + wire \main_sdphy_dataw_pads_in_pads_in_last + attribute \src "ls180.v:1227.5-1227.49" + wire \main_sdphy_dataw_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1228.5-1228.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1229.5-1229.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1230.5-1230.52" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1231.11-1231.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1232.11-1232.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1233.5-1233.53" + wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1224.6-1224.44" + wire \main_sdphy_dataw_pads_in_pads_in_ready + attribute \src "ls180.v:1223.5-1223.43" + wire \main_sdphy_dataw_pads_in_pads_in_valid + attribute \src "ls180.v:1208.6-1208.44" + wire \main_sdphy_dataw_pads_in_payload_cmd_i + attribute \src "ls180.v:1209.12-1209.51" + wire width 4 \main_sdphy_dataw_pads_in_payload_data_i + attribute \src "ls180.v:1207.6-1207.36" + wire \main_sdphy_dataw_pads_in_valid + attribute \src "ls180.v:1211.5-1211.42" + wire \main_sdphy_dataw_pads_out_payload_clk + attribute \src "ls180.v:1212.5-1212.44" + wire \main_sdphy_dataw_pads_out_payload_cmd_o + attribute \src "ls180.v:1213.5-1213.45" + wire \main_sdphy_dataw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1214.11-1214.51" + wire width 4 \main_sdphy_dataw_pads_out_payload_data_o + attribute \src "ls180.v:1215.5-1215.46" + wire \main_sdphy_dataw_pads_out_payload_data_oe + attribute \src "ls180.v:1210.6-1210.37" + wire \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:1218.5-1218.32" + wire \main_sdphy_dataw_sink_first + attribute \src "ls180.v:1219.5-1219.31" + wire \main_sdphy_dataw_sink_last + attribute \src "ls180.v:1220.11-1220.45" + wire width 8 \main_sdphy_dataw_sink_payload_data + attribute \src "ls180.v:1217.5-1217.32" + wire \main_sdphy_dataw_sink_ready + attribute \src "ls180.v:1216.5-1216.32" + wire \main_sdphy_dataw_sink_valid + attribute \src "ls180.v:1234.5-1234.27" + wire \main_sdphy_dataw_start + attribute \src "ls180.v:1221.5-1221.26" + wire \main_sdphy_dataw_stop + attribute \src "ls180.v:1235.5-1235.27" + wire \main_sdphy_dataw_valid + attribute \src "ls180.v:1115.11-1115.32" + wire width 8 \main_sdphy_init_count + attribute \src "ls180.v:1789.11-1789.59" + wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value + attribute \src "ls180.v:1790.5-1790.56" + wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:1103.6-1103.34" + wire \main_sdphy_init_initialize_r + attribute \src "ls180.v:1102.6-1102.35" + wire \main_sdphy_init_initialize_re + attribute \src "ls180.v:1105.5-1105.33" + wire \main_sdphy_init_initialize_w + attribute \src "ls180.v:1104.6-1104.35" + wire \main_sdphy_init_initialize_we + attribute \src "ls180.v:1107.6-1107.43" + wire \main_sdphy_init_pads_in_payload_cmd_i + attribute \src "ls180.v:1108.12-1108.50" + wire width 4 \main_sdphy_init_pads_in_payload_data_i + attribute \src "ls180.v:1106.6-1106.35" + wire \main_sdphy_init_pads_in_valid + attribute \src "ls180.v:1110.5-1110.41" + wire \main_sdphy_init_pads_out_payload_clk + attribute \src "ls180.v:1111.5-1111.43" + wire \main_sdphy_init_pads_out_payload_cmd_o + attribute \src "ls180.v:1112.5-1112.44" + wire \main_sdphy_init_pads_out_payload_cmd_oe + attribute \src "ls180.v:1113.11-1113.50" + wire width 4 \main_sdphy_init_pads_out_payload_data_o + attribute \src "ls180.v:1114.5-1114.45" + wire \main_sdphy_init_pads_out_payload_data_oe + attribute \src "ls180.v:1109.6-1109.36" + wire \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:1363.6-1363.27" + wire \main_sdphy_sdpads_clk + attribute \src "ls180.v:1364.5-1364.28" + wire \main_sdphy_sdpads_cmd_i + attribute \src "ls180.v:1365.6-1365.29" + wire \main_sdphy_sdpads_cmd_o + attribute \src "ls180.v:1366.6-1366.30" + wire \main_sdphy_sdpads_cmd_oe + attribute \src "ls180.v:1367.11-1367.35" + wire width 4 \main_sdphy_sdpads_data_i + attribute \src "ls180.v:1368.12-1368.36" + wire width 4 \main_sdphy_sdpads_data_o + attribute \src "ls180.v:1369.6-1369.31" + wire \main_sdphy_sdpads_data_oe + attribute \src "ls180.v:1092.6-1092.23" + wire \main_sdphy_status + attribute \src "ls180.v:1093.6-1093.19" + wire \main_sdphy_we + attribute \src "ls180.v:327.5-327.26" + wire \main_sdram_address_re + attribute \src "ls180.v:326.12-326.38" + wire width 13 \main_sdram_address_storage + attribute \src "ls180.v:329.5-329.27" + wire \main_sdram_baddress_re + attribute \src "ls180.v:328.11-328.38" + wire width 2 \main_sdram_baddress_storage + attribute \src "ls180.v:425.5-425.43" + wire \main_sdram_bankmachine0_auto_precharge + attribute \src "ls180.v:447.11-447.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + attribute \src "ls180.v:452.6-452.58" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:457.6-457.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:458.6-458.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:456.13-456.78" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:455.6-455.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:461.6-461.65" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:462.6-462.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:460.13-460.79" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:459.6-459.70" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:444.11-444.61" + wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level + attribute \src "ls180.v:446.11-446.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + attribute \src "ls180.v:453.12-453.67" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:454.13-454.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:445.5-445.57" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:428.5-428.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:429.5-429.59" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:431.13-431.75" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:430.6-430.66" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:427.6-427.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:426.6-426.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:434.6-434.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:435.6-435.62" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:437.13-437.77" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:436.6-436.68" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:433.6-433.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:432.6-432.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:442.13-442.71" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + attribute \src "ls180.v:443.13-443.72" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + attribute \src "ls180.v:440.6-440.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + attribute \src "ls180.v:441.6-441.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + attribute \src "ls180.v:438.6-438.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + attribute \src "ls180.v:439.6-439.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + attribute \src "ls180.v:448.11-448.66" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:449.13-449.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:451.13-451.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:450.6-450.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:465.6-465.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_first + attribute \src "ls180.v:466.6-466.50" + wire \main_sdram_bankmachine0_cmd_buffer_sink_last + attribute \src "ls180.v:468.13-468.65" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:467.6-467.56" + wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + attribute \src "ls180.v:464.6-464.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "ls180.v:463.6-463.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_valid + attribute \src "ls180.v:471.5-471.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_first + attribute \src "ls180.v:472.5-472.51" + wire \main_sdram_bankmachine0_cmd_buffer_source_last + attribute \src "ls180.v:474.12-474.66" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + attribute \src "ls180.v:473.5-473.57" + wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:470.6-470.53" + wire \main_sdram_bankmachine0_cmd_buffer_source_ready + attribute \src "ls180.v:469.5-469.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:417.12-417.49" + wire width 13 \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:418.12-418.50" + wire width 2 \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:419.5-419.44" + wire \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:422.5-422.47" + wire \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:423.5-423.48" + wire \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:424.5-424.49" + wire \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:420.5-420.44" + wire \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:421.5-421.43" + wire \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:416.5-416.38" + wire \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:415.5-415.38" + wire \main_sdram_bankmachine0_cmd_valid + attribute \src "ls180.v:414.5-414.40" + wire \main_sdram_bankmachine0_refresh_gnt + attribute \src "ls180.v:413.6-413.41" + wire \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:409.13-409.45" + wire width 22 \main_sdram_bankmachine0_req_addr + attribute \src "ls180.v:410.6-410.38" + wire \main_sdram_bankmachine0_req_lock + attribute \src "ls180.v:412.5-412.44" + wire \main_sdram_bankmachine0_req_rdata_valid + attribute \src "ls180.v:407.6-407.39" + wire \main_sdram_bankmachine0_req_ready + attribute \src "ls180.v:406.6-406.39" + wire \main_sdram_bankmachine0_req_valid + attribute \src "ls180.v:411.5-411.44" + wire \main_sdram_bankmachine0_req_wdata_ready + attribute \src "ls180.v:408.6-408.36" + wire \main_sdram_bankmachine0_req_we + attribute \src "ls180.v:475.12-475.39" + wire width 13 \main_sdram_bankmachine0_row + attribute \src "ls180.v:479.5-479.38" + wire \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:480.5-480.47" + wire \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:477.6-477.37" + wire \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:478.5-478.37" + wire \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:476.5-476.39" + wire \main_sdram_bankmachine0_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:487.32-487.69" + wire \main_sdram_bankmachine0_trascon_ready + attribute \src "ls180.v:486.6-486.43" + wire \main_sdram_bankmachine0_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:485.32-485.68" + wire \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:484.6-484.42" + wire \main_sdram_bankmachine0_trccon_valid + attribute \src "ls180.v:483.11-483.48" + wire width 3 \main_sdram_bankmachine0_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:482.32-482.69" + wire \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:481.6-481.43" + wire \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:507.5-507.43" + wire \main_sdram_bankmachine1_auto_precharge + attribute \src "ls180.v:529.11-529.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + attribute \src "ls180.v:534.6-534.58" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:539.6-539.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:540.6-540.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:538.13-538.78" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:537.6-537.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:543.6-543.65" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:544.6-544.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:542.13-542.79" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:541.6-541.70" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:526.11-526.61" + wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level + attribute \src "ls180.v:528.11-528.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + attribute \src "ls180.v:535.12-535.67" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:536.13-536.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:527.5-527.57" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:510.5-510.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:511.5-511.59" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:513.13-513.75" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:512.6-512.66" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:509.6-509.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:508.6-508.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:516.6-516.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:517.6-517.62" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:519.13-519.77" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:518.6-518.68" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:515.6-515.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:514.6-514.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:524.13-524.71" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + attribute \src "ls180.v:525.13-525.72" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + attribute \src "ls180.v:522.6-522.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + attribute \src "ls180.v:523.6-523.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + attribute \src "ls180.v:520.6-520.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + attribute \src "ls180.v:521.6-521.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + attribute \src "ls180.v:530.11-530.66" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:531.13-531.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:533.13-533.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:532.6-532.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:547.6-547.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_first + attribute \src "ls180.v:548.6-548.50" + wire \main_sdram_bankmachine1_cmd_buffer_sink_last + attribute \src "ls180.v:550.13-550.65" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:549.6-549.56" + wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + attribute \src "ls180.v:546.6-546.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "ls180.v:545.6-545.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_valid + attribute \src "ls180.v:553.5-553.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_first + attribute \src "ls180.v:554.5-554.51" + wire \main_sdram_bankmachine1_cmd_buffer_source_last + attribute \src "ls180.v:556.12-556.66" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + attribute \src "ls180.v:555.5-555.57" + wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:552.6-552.53" + wire \main_sdram_bankmachine1_cmd_buffer_source_ready + attribute \src "ls180.v:551.5-551.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:499.12-499.49" + wire width 13 \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:500.12-500.50" + wire width 2 \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:501.5-501.44" + wire \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:504.5-504.47" + wire \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:505.5-505.48" + wire \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:506.5-506.49" + wire \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:502.5-502.44" + wire \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:503.5-503.43" + wire \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:498.5-498.38" + wire \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:497.5-497.38" + wire \main_sdram_bankmachine1_cmd_valid + attribute \src "ls180.v:496.5-496.40" + wire \main_sdram_bankmachine1_refresh_gnt + attribute \src "ls180.v:495.6-495.41" + wire \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:491.13-491.45" + wire width 22 \main_sdram_bankmachine1_req_addr + attribute \src "ls180.v:492.6-492.38" + wire \main_sdram_bankmachine1_req_lock + attribute \src "ls180.v:494.5-494.44" + wire \main_sdram_bankmachine1_req_rdata_valid + attribute \src "ls180.v:489.6-489.39" + wire \main_sdram_bankmachine1_req_ready + attribute \src "ls180.v:488.6-488.39" + wire \main_sdram_bankmachine1_req_valid + attribute \src "ls180.v:493.5-493.44" + wire \main_sdram_bankmachine1_req_wdata_ready + attribute \src "ls180.v:490.6-490.36" + wire \main_sdram_bankmachine1_req_we + attribute \src "ls180.v:557.12-557.39" + wire width 13 \main_sdram_bankmachine1_row + attribute \src "ls180.v:561.5-561.38" + wire \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:562.5-562.47" + wire \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:559.6-559.37" + wire \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:560.5-560.37" + wire \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:558.5-558.39" + wire \main_sdram_bankmachine1_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:569.32-569.69" + wire \main_sdram_bankmachine1_trascon_ready + attribute \src "ls180.v:568.6-568.43" + wire \main_sdram_bankmachine1_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:567.32-567.68" + wire \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:566.6-566.42" + wire \main_sdram_bankmachine1_trccon_valid + attribute \src "ls180.v:565.11-565.48" + wire width 3 \main_sdram_bankmachine1_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:564.32-564.69" + wire \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:563.6-563.43" + wire \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:589.5-589.43" + wire \main_sdram_bankmachine2_auto_precharge + attribute \src "ls180.v:611.11-611.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + attribute \src "ls180.v:616.6-616.58" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:621.6-621.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:622.6-622.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:620.13-620.78" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:619.6-619.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:625.6-625.65" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:626.6-626.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:624.13-624.79" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:623.6-623.70" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:608.11-608.61" + wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level + attribute \src "ls180.v:610.11-610.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + attribute \src "ls180.v:617.12-617.67" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:618.13-618.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:609.5-609.57" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:592.5-592.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:593.5-593.59" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:595.13-595.75" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:594.6-594.66" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:591.6-591.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:590.6-590.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:598.6-598.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:599.6-599.62" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:601.13-601.77" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:600.6-600.68" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:597.6-597.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:596.6-596.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:606.13-606.71" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + attribute \src "ls180.v:607.13-607.72" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + attribute \src "ls180.v:604.6-604.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + attribute \src "ls180.v:605.6-605.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + attribute \src "ls180.v:602.6-602.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + attribute \src "ls180.v:603.6-603.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + attribute \src "ls180.v:612.11-612.66" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:613.13-613.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:615.13-615.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:614.6-614.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:629.6-629.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_first + attribute \src "ls180.v:630.6-630.50" + wire \main_sdram_bankmachine2_cmd_buffer_sink_last + attribute \src "ls180.v:632.13-632.65" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:631.6-631.56" + wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + attribute \src "ls180.v:628.6-628.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "ls180.v:627.6-627.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_valid + attribute \src "ls180.v:635.5-635.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_first + attribute \src "ls180.v:636.5-636.51" + wire \main_sdram_bankmachine2_cmd_buffer_source_last + attribute \src "ls180.v:638.12-638.66" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + attribute \src "ls180.v:637.5-637.57" + wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:634.6-634.53" + wire \main_sdram_bankmachine2_cmd_buffer_source_ready + attribute \src "ls180.v:633.5-633.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:581.12-581.49" + wire width 13 \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:582.12-582.50" + wire width 2 \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:583.5-583.44" + wire \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:586.5-586.47" + wire \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:587.5-587.48" + wire \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:588.5-588.49" + wire \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:584.5-584.44" + wire \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:585.5-585.43" + wire \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:580.5-580.38" + wire \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:579.5-579.38" + wire \main_sdram_bankmachine2_cmd_valid + attribute \src "ls180.v:578.5-578.40" + wire \main_sdram_bankmachine2_refresh_gnt + attribute \src "ls180.v:577.6-577.41" + wire \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:573.13-573.45" + wire width 22 \main_sdram_bankmachine2_req_addr + attribute \src "ls180.v:574.6-574.38" + wire \main_sdram_bankmachine2_req_lock + attribute \src "ls180.v:576.5-576.44" + wire \main_sdram_bankmachine2_req_rdata_valid + attribute \src "ls180.v:571.6-571.39" + wire \main_sdram_bankmachine2_req_ready + attribute \src "ls180.v:570.6-570.39" + wire \main_sdram_bankmachine2_req_valid + attribute \src "ls180.v:575.5-575.44" + wire \main_sdram_bankmachine2_req_wdata_ready + attribute \src "ls180.v:572.6-572.36" + wire \main_sdram_bankmachine2_req_we + attribute \src "ls180.v:639.12-639.39" + wire width 13 \main_sdram_bankmachine2_row + attribute \src "ls180.v:643.5-643.38" + wire \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:644.5-644.47" + wire \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:641.6-641.37" + wire \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:642.5-642.37" + wire \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:640.5-640.39" + wire \main_sdram_bankmachine2_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:651.32-651.69" + wire \main_sdram_bankmachine2_trascon_ready + attribute \src "ls180.v:650.6-650.43" + wire \main_sdram_bankmachine2_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:649.32-649.68" + wire \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:648.6-648.42" + wire \main_sdram_bankmachine2_trccon_valid + attribute \src "ls180.v:647.11-647.48" + wire width 3 \main_sdram_bankmachine2_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:646.32-646.69" + wire \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:645.6-645.43" + wire \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:671.5-671.43" + wire \main_sdram_bankmachine3_auto_precharge + attribute \src "ls180.v:693.11-693.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + attribute \src "ls180.v:698.6-698.58" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:703.6-703.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:704.6-704.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:702.13-702.78" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:701.6-701.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:707.6-707.65" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:708.6-708.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:706.13-706.79" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:705.6-705.70" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:690.11-690.61" + wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level + attribute \src "ls180.v:692.11-692.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + attribute \src "ls180.v:699.12-699.67" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:700.13-700.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:691.5-691.57" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:674.5-674.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:675.5-675.59" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:677.13-677.75" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:676.6-676.66" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:673.6-673.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:672.6-672.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:680.6-680.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:681.6-681.62" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:683.13-683.77" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:682.6-682.68" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:679.6-679.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:678.6-678.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:688.13-688.71" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + attribute \src "ls180.v:689.13-689.72" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + attribute \src "ls180.v:686.6-686.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + attribute \src "ls180.v:687.6-687.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + attribute \src "ls180.v:684.6-684.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + attribute \src "ls180.v:685.6-685.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + attribute \src "ls180.v:694.11-694.66" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:695.13-695.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:697.13-697.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:696.6-696.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:711.6-711.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_first + attribute \src "ls180.v:712.6-712.50" + wire \main_sdram_bankmachine3_cmd_buffer_sink_last + attribute \src "ls180.v:714.13-714.65" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:713.6-713.56" + wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + attribute \src "ls180.v:710.6-710.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "ls180.v:709.6-709.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_valid + attribute \src "ls180.v:717.5-717.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_first + attribute \src "ls180.v:718.5-718.51" + wire \main_sdram_bankmachine3_cmd_buffer_source_last + attribute \src "ls180.v:720.12-720.66" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + attribute \src "ls180.v:719.5-719.57" + wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:716.6-716.53" + wire \main_sdram_bankmachine3_cmd_buffer_source_ready + attribute \src "ls180.v:715.5-715.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:663.12-663.49" + wire width 13 \main_sdram_bankmachine3_cmd_payload_a + attribute \src "ls180.v:664.12-664.50" + wire width 2 \main_sdram_bankmachine3_cmd_payload_ba + attribute \src "ls180.v:665.5-665.44" + wire \main_sdram_bankmachine3_cmd_payload_cas + attribute \src "ls180.v:668.5-668.47" + wire \main_sdram_bankmachine3_cmd_payload_is_cmd + attribute \src "ls180.v:669.5-669.48" + wire \main_sdram_bankmachine3_cmd_payload_is_read + attribute \src "ls180.v:670.5-670.49" + wire \main_sdram_bankmachine3_cmd_payload_is_write + attribute \src "ls180.v:666.5-666.44" + wire \main_sdram_bankmachine3_cmd_payload_ras + attribute \src "ls180.v:667.5-667.43" + wire \main_sdram_bankmachine3_cmd_payload_we + attribute \src "ls180.v:662.5-662.38" + wire \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:661.5-661.38" + wire \main_sdram_bankmachine3_cmd_valid + attribute \src "ls180.v:660.5-660.40" + wire \main_sdram_bankmachine3_refresh_gnt + attribute \src "ls180.v:659.6-659.41" + wire \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:655.13-655.45" + wire width 22 \main_sdram_bankmachine3_req_addr + attribute \src "ls180.v:656.6-656.38" + wire \main_sdram_bankmachine3_req_lock + attribute \src "ls180.v:658.5-658.44" + wire \main_sdram_bankmachine3_req_rdata_valid + attribute \src "ls180.v:653.6-653.39" + wire \main_sdram_bankmachine3_req_ready + attribute \src "ls180.v:652.6-652.39" + wire \main_sdram_bankmachine3_req_valid + attribute \src "ls180.v:657.5-657.44" + wire \main_sdram_bankmachine3_req_wdata_ready + attribute \src "ls180.v:654.6-654.36" + wire \main_sdram_bankmachine3_req_we + attribute \src "ls180.v:721.12-721.39" + wire width 13 \main_sdram_bankmachine3_row + attribute \src "ls180.v:725.5-725.38" + wire \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:726.5-726.47" + wire \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:723.6-723.37" + wire \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:724.5-724.37" + wire \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:722.5-722.39" + wire \main_sdram_bankmachine3_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:733.32-733.69" + wire \main_sdram_bankmachine3_trascon_ready + attribute \src "ls180.v:732.6-732.43" + wire \main_sdram_bankmachine3_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:731.32-731.68" + wire \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:730.6-730.42" + wire \main_sdram_bankmachine3_trccon_valid + attribute \src "ls180.v:729.11-729.48" + wire width 3 \main_sdram_bankmachine3_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:728.32-728.69" + wire \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:727.6-727.43" + wire \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:735.6-735.28" + wire \main_sdram_cas_allowed + attribute \src "ls180.v:753.6-753.30" + wire \main_sdram_choose_cmd_ce + attribute \src "ls180.v:742.13-742.48" + wire width 13 \main_sdram_choose_cmd_cmd_payload_a + attribute \src "ls180.v:743.12-743.48" + wire width 2 \main_sdram_choose_cmd_cmd_payload_ba + attribute \src "ls180.v:744.5-744.42" + wire \main_sdram_choose_cmd_cmd_payload_cas + attribute \src "ls180.v:747.6-747.46" + wire \main_sdram_choose_cmd_cmd_payload_is_cmd + attribute \src "ls180.v:748.6-748.47" + wire \main_sdram_choose_cmd_cmd_payload_is_read + attribute \src "ls180.v:749.6-749.48" + wire \main_sdram_choose_cmd_cmd_payload_is_write + attribute \src "ls180.v:745.5-745.42" + wire \main_sdram_choose_cmd_cmd_payload_ras + attribute \src "ls180.v:746.5-746.41" + wire \main_sdram_choose_cmd_cmd_payload_we + attribute \src "ls180.v:741.5-741.36" + wire \main_sdram_choose_cmd_cmd_ready + attribute \src "ls180.v:740.6-740.37" + wire \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:752.11-752.38" + wire width 2 \main_sdram_choose_cmd_grant + attribute \src "ls180.v:751.12-751.41" + wire width 4 \main_sdram_choose_cmd_request + attribute \src "ls180.v:750.11-750.39" + wire width 4 \main_sdram_choose_cmd_valids + attribute \src "ls180.v:739.5-739.41" + wire \main_sdram_choose_cmd_want_activates + attribute \src "ls180.v:738.5-738.36" + wire \main_sdram_choose_cmd_want_cmds + attribute \src "ls180.v:736.5-736.37" + wire \main_sdram_choose_cmd_want_reads + attribute \src "ls180.v:737.5-737.38" + wire \main_sdram_choose_cmd_want_writes + attribute \src "ls180.v:771.6-771.30" + wire \main_sdram_choose_req_ce + attribute \src "ls180.v:760.13-760.48" + wire width 13 \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:761.12-761.48" + wire width 2 \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:762.5-762.42" + wire \main_sdram_choose_req_cmd_payload_cas + attribute \src "ls180.v:765.6-765.46" + wire \main_sdram_choose_req_cmd_payload_is_cmd + attribute \src "ls180.v:766.6-766.47" + wire \main_sdram_choose_req_cmd_payload_is_read + attribute \src "ls180.v:767.6-767.48" + wire \main_sdram_choose_req_cmd_payload_is_write + attribute \src "ls180.v:763.5-763.42" + wire \main_sdram_choose_req_cmd_payload_ras + attribute \src "ls180.v:764.5-764.41" + wire \main_sdram_choose_req_cmd_payload_we + attribute \src "ls180.v:759.5-759.36" + wire \main_sdram_choose_req_cmd_ready + attribute \src "ls180.v:758.6-758.37" + wire \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:770.11-770.38" + wire width 2 \main_sdram_choose_req_grant + attribute \src "ls180.v:769.12-769.41" + wire width 4 \main_sdram_choose_req_request + attribute \src "ls180.v:768.11-768.39" + wire width 4 \main_sdram_choose_req_valids + attribute \src "ls180.v:757.5-757.41" + wire \main_sdram_choose_req_want_activates + attribute \src "ls180.v:756.6-756.37" + wire \main_sdram_choose_req_want_cmds + attribute \src "ls180.v:754.5-754.37" + wire \main_sdram_choose_req_want_reads + attribute \src "ls180.v:755.5-755.38" + wire \main_sdram_choose_req_want_writes + attribute \src "ls180.v:315.6-315.20" + wire \main_sdram_cke + attribute \src "ls180.v:383.5-383.24" + wire \main_sdram_cmd_last + attribute \src "ls180.v:384.12-384.36" + wire width 13 \main_sdram_cmd_payload_a + attribute \src "ls180.v:385.11-385.36" + wire width 2 \main_sdram_cmd_payload_ba + attribute \src "ls180.v:386.5-386.31" + wire \main_sdram_cmd_payload_cas + attribute \src "ls180.v:389.5-389.35" + wire \main_sdram_cmd_payload_is_read + attribute \src "ls180.v:390.5-390.36" + wire \main_sdram_cmd_payload_is_write + attribute \src "ls180.v:387.5-387.31" + wire \main_sdram_cmd_payload_ras + attribute \src "ls180.v:388.5-388.30" + wire \main_sdram_cmd_payload_we + attribute \src "ls180.v:382.5-382.25" + wire \main_sdram_cmd_ready + attribute \src "ls180.v:381.5-381.25" + wire \main_sdram_cmd_valid + attribute \src "ls180.v:323.6-323.32" + wire \main_sdram_command_issue_r + attribute \src "ls180.v:322.6-322.33" + wire \main_sdram_command_issue_re + attribute \src "ls180.v:325.5-325.31" + wire \main_sdram_command_issue_w + attribute \src "ls180.v:324.6-324.33" + wire \main_sdram_command_issue_we + attribute \src "ls180.v:321.5-321.26" + wire \main_sdram_command_re + attribute \src "ls180.v:320.11-320.37" + wire width 6 \main_sdram_command_storage + attribute \src "ls180.v:374.5-374.28" + wire \main_sdram_dfi_p0_act_n + attribute \src "ls180.v:365.12-365.37" + wire width 13 \main_sdram_dfi_p0_address + attribute \src "ls180.v:366.11-366.33" + wire width 2 \main_sdram_dfi_p0_bank + attribute \src "ls180.v:367.5-367.28" + wire \main_sdram_dfi_p0_cas_n + attribute \src "ls180.v:371.6-371.27" + wire \main_sdram_dfi_p0_cke + attribute \src "ls180.v:368.5-368.27" + wire \main_sdram_dfi_p0_cs_n + attribute \src "ls180.v:372.6-372.27" + wire \main_sdram_dfi_p0_odt + attribute \src "ls180.v:369.5-369.28" + wire \main_sdram_dfi_p0_ras_n + attribute \src "ls180.v:379.13-379.37" + wire width 16 \main_sdram_dfi_p0_rddata + attribute \src "ls180.v:378.5-378.32" + wire \main_sdram_dfi_p0_rddata_en + attribute \src "ls180.v:380.6-380.36" + wire \main_sdram_dfi_p0_rddata_valid + attribute \src "ls180.v:373.6-373.31" + wire \main_sdram_dfi_p0_reset_n + attribute \src "ls180.v:370.5-370.27" + wire \main_sdram_dfi_p0_we_n + attribute \src "ls180.v:375.13-375.37" + wire width 16 \main_sdram_dfi_p0_wrdata + attribute \src "ls180.v:376.5-376.32" + wire \main_sdram_dfi_p0_wrdata_en + attribute \src "ls180.v:377.12-377.41" + wire width 2 \main_sdram_dfi_p0_wrdata_mask + attribute \src "ls180.v:789.5-789.19" + wire \main_sdram_en0 + attribute \src "ls180.v:792.5-792.19" + wire \main_sdram_en1 + attribute \src "ls180.v:795.6-795.30" + wire \main_sdram_go_to_refresh + attribute \src "ls180.v:337.13-337.44" + wire width 22 \main_sdram_interface_bank0_addr + attribute \src "ls180.v:338.6-338.37" + wire \main_sdram_interface_bank0_lock + attribute \src "ls180.v:340.6-340.44" + wire \main_sdram_interface_bank0_rdata_valid + attribute \src "ls180.v:335.6-335.38" + wire \main_sdram_interface_bank0_ready + attribute \src "ls180.v:334.6-334.38" + wire \main_sdram_interface_bank0_valid + attribute \src "ls180.v:339.6-339.44" + wire \main_sdram_interface_bank0_wdata_ready + attribute \src "ls180.v:336.6-336.35" + wire \main_sdram_interface_bank0_we + attribute \src "ls180.v:344.13-344.44" + wire width 22 \main_sdram_interface_bank1_addr + attribute \src "ls180.v:345.6-345.37" + wire \main_sdram_interface_bank1_lock + attribute \src "ls180.v:347.6-347.44" + wire \main_sdram_interface_bank1_rdata_valid + attribute \src "ls180.v:342.6-342.38" + wire \main_sdram_interface_bank1_ready + attribute \src "ls180.v:341.6-341.38" + wire \main_sdram_interface_bank1_valid + attribute \src "ls180.v:346.6-346.44" + wire \main_sdram_interface_bank1_wdata_ready + attribute \src "ls180.v:343.6-343.35" + wire \main_sdram_interface_bank1_we + attribute \src "ls180.v:351.13-351.44" + wire width 22 \main_sdram_interface_bank2_addr + attribute \src "ls180.v:352.6-352.37" + wire \main_sdram_interface_bank2_lock + attribute \src "ls180.v:354.6-354.44" + wire \main_sdram_interface_bank2_rdata_valid + attribute \src "ls180.v:349.6-349.38" + wire \main_sdram_interface_bank2_ready + attribute \src "ls180.v:348.6-348.38" + wire \main_sdram_interface_bank2_valid + attribute \src "ls180.v:353.6-353.44" + wire \main_sdram_interface_bank2_wdata_ready + attribute \src "ls180.v:350.6-350.35" + wire \main_sdram_interface_bank2_we + attribute \src "ls180.v:358.13-358.44" + wire width 22 \main_sdram_interface_bank3_addr + attribute \src "ls180.v:359.6-359.37" + wire \main_sdram_interface_bank3_lock + attribute \src "ls180.v:361.6-361.44" + wire \main_sdram_interface_bank3_rdata_valid + attribute \src "ls180.v:356.6-356.38" + wire \main_sdram_interface_bank3_ready + attribute \src "ls180.v:355.6-355.38" + wire \main_sdram_interface_bank3_valid + attribute \src "ls180.v:360.6-360.44" + wire \main_sdram_interface_bank3_wdata_ready + attribute \src "ls180.v:357.6-357.35" + wire \main_sdram_interface_bank3_we + attribute \src "ls180.v:364.13-364.39" + wire width 16 \main_sdram_interface_rdata + attribute \src "ls180.v:362.12-362.38" + wire width 16 \main_sdram_interface_wdata + attribute \src "ls180.v:363.11-363.40" + wire width 2 \main_sdram_interface_wdata_we + attribute \src "ls180.v:275.5-275.29" + wire \main_sdram_inti_p0_act_n + attribute \src "ls180.v:266.13-266.39" + wire width 13 \main_sdram_inti_p0_address + attribute \src "ls180.v:267.12-267.35" + wire width 2 \main_sdram_inti_p0_bank + attribute \src "ls180.v:268.5-268.29" + wire \main_sdram_inti_p0_cas_n + attribute \src "ls180.v:272.6-272.28" + wire \main_sdram_inti_p0_cke + attribute \src "ls180.v:269.5-269.28" + wire \main_sdram_inti_p0_cs_n + attribute \src "ls180.v:273.6-273.28" + wire \main_sdram_inti_p0_odt + attribute \src "ls180.v:270.5-270.29" + wire \main_sdram_inti_p0_ras_n + attribute \src "ls180.v:280.12-280.37" + wire width 16 \main_sdram_inti_p0_rddata + attribute \src "ls180.v:279.6-279.34" + wire \main_sdram_inti_p0_rddata_en + attribute \src "ls180.v:281.5-281.36" + wire \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:274.6-274.32" + wire \main_sdram_inti_p0_reset_n + attribute \src "ls180.v:271.5-271.28" + wire \main_sdram_inti_p0_we_n + attribute \src "ls180.v:276.13-276.38" + wire width 16 \main_sdram_inti_p0_wrdata + attribute \src "ls180.v:277.6-277.34" + wire \main_sdram_inti_p0_wrdata_en + attribute \src "ls180.v:278.12-278.42" + wire width 2 \main_sdram_inti_p0_wrdata_mask + attribute \src "ls180.v:307.5-307.31" + wire \main_sdram_master_p0_act_n + attribute \src "ls180.v:298.12-298.40" + wire width 13 \main_sdram_master_p0_address + attribute \src "ls180.v:299.11-299.36" + wire width 2 \main_sdram_master_p0_bank + attribute \src "ls180.v:300.5-300.31" + wire \main_sdram_master_p0_cas_n + attribute \src "ls180.v:304.5-304.29" + wire \main_sdram_master_p0_cke + attribute \src "ls180.v:301.5-301.30" + wire \main_sdram_master_p0_cs_n + attribute \src "ls180.v:305.5-305.29" + wire \main_sdram_master_p0_odt + attribute \src "ls180.v:302.5-302.31" + wire \main_sdram_master_p0_ras_n + attribute \src "ls180.v:312.13-312.40" + wire width 16 \main_sdram_master_p0_rddata + attribute \src "ls180.v:311.5-311.35" + wire \main_sdram_master_p0_rddata_en + attribute \src "ls180.v:313.6-313.39" + wire \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:306.5-306.33" + wire \main_sdram_master_p0_reset_n + attribute \src "ls180.v:303.5-303.30" + wire \main_sdram_master_p0_we_n + attribute \src "ls180.v:308.12-308.39" + wire width 16 \main_sdram_master_p0_wrdata + attribute \src "ls180.v:309.5-309.35" + wire \main_sdram_master_p0_wrdata_en + attribute \src "ls180.v:310.11-310.43" + wire width 2 \main_sdram_master_p0_wrdata_mask + attribute \src "ls180.v:790.6-790.26" + wire \main_sdram_max_time0 + attribute \src "ls180.v:793.6-793.26" + wire \main_sdram_max_time1 + attribute \src "ls180.v:772.12-772.28" + wire width 13 \main_sdram_nop_a + attribute \src "ls180.v:773.11-773.28" + wire width 2 \main_sdram_nop_ba + attribute \src "ls180.v:316.6-316.20" + wire \main_sdram_odt + attribute \src "ls180.v:399.5-399.31" + wire \main_sdram_postponer_count + attribute \src "ls180.v:397.6-397.32" + wire \main_sdram_postponer_req_i + attribute \src "ls180.v:398.5-398.31" + wire \main_sdram_postponer_req_o + attribute \src "ls180.v:734.6-734.28" + wire \main_sdram_ras_allowed + attribute \src "ls180.v:319.5-319.18" + wire \main_sdram_re + attribute \src "ls180.v:787.6-787.31" + wire \main_sdram_read_available + attribute \src "ls180.v:317.6-317.24" + wire \main_sdram_reset_n + attribute \src "ls180.v:314.6-314.20" + wire \main_sdram_sel + attribute \src "ls180.v:405.5-405.31" + wire \main_sdram_sequencer_count + attribute \src "ls180.v:404.11-404.39" + wire width 4 \main_sdram_sequencer_counter + attribute \src "ls180.v:401.6-401.32" + wire \main_sdram_sequencer_done0 + attribute \src "ls180.v:403.5-403.31" + wire \main_sdram_sequencer_done1 + attribute \src "ls180.v:400.5-400.32" + wire \main_sdram_sequencer_start0 + attribute \src "ls180.v:402.6-402.33" + wire \main_sdram_sequencer_start1 + attribute \src "ls180.v:291.6-291.31" + wire \main_sdram_slave_p0_act_n + attribute \src "ls180.v:282.13-282.40" + wire width 13 \main_sdram_slave_p0_address + attribute \src "ls180.v:283.12-283.36" + wire width 2 \main_sdram_slave_p0_bank + attribute \src "ls180.v:284.6-284.31" + wire \main_sdram_slave_p0_cas_n + attribute \src "ls180.v:288.6-288.29" + wire \main_sdram_slave_p0_cke + attribute \src "ls180.v:285.6-285.30" + wire \main_sdram_slave_p0_cs_n + attribute \src "ls180.v:289.6-289.29" + wire \main_sdram_slave_p0_odt + attribute \src "ls180.v:286.6-286.31" + wire \main_sdram_slave_p0_ras_n + attribute \src "ls180.v:296.12-296.38" + wire width 16 \main_sdram_slave_p0_rddata + attribute \src "ls180.v:295.6-295.35" + wire \main_sdram_slave_p0_rddata_en + attribute \src "ls180.v:297.5-297.37" + wire \main_sdram_slave_p0_rddata_valid + attribute \src "ls180.v:290.6-290.33" + wire \main_sdram_slave_p0_reset_n + attribute \src "ls180.v:287.6-287.30" + wire \main_sdram_slave_p0_we_n + attribute \src "ls180.v:292.13-292.39" + wire width 16 \main_sdram_slave_p0_wrdata + attribute \src "ls180.v:293.6-293.35" + wire \main_sdram_slave_p0_wrdata_en + attribute \src "ls180.v:294.12-294.43" + wire width 2 \main_sdram_slave_p0_wrdata_mask + attribute \src "ls180.v:332.12-332.29" + wire width 16 \main_sdram_status + attribute \src "ls180.v:775.5-775.24" + wire \main_sdram_steerer0 + attribute \src "ls180.v:776.5-776.24" + wire \main_sdram_steerer1 + attribute \src "ls180.v:774.11-774.33" + wire width 2 \main_sdram_steerer_sel + attribute \src "ls180.v:318.11-318.29" + wire width 4 \main_sdram_storage + attribute \src "ls180.v:783.5-783.29" + wire \main_sdram_tccdcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:782.32-782.56" + wire \main_sdram_tccdcon_ready + attribute \src "ls180.v:781.6-781.30" + wire \main_sdram_tccdcon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:780.32-780.56" + wire \main_sdram_tfawcon_ready + attribute \src "ls180.v:779.6-779.30" + wire \main_sdram_tfawcon_valid + attribute \src "ls180.v:791.11-791.27" + wire width 5 \main_sdram_time0 + attribute \src "ls180.v:794.11-794.27" + wire width 4 \main_sdram_time1 + attribute \src "ls180.v:394.12-394.35" + wire width 10 \main_sdram_timer_count0 + attribute \src "ls180.v:396.11-396.34" + wire width 10 \main_sdram_timer_count1 + attribute \src "ls180.v:393.6-393.28" + wire \main_sdram_timer_done0 + attribute \src "ls180.v:395.6-395.28" + wire \main_sdram_timer_done1 + attribute \src "ls180.v:392.6-392.27" + wire \main_sdram_timer_wait + attribute \no_retiming "true" + attribute \src "ls180.v:778.32-778.56" + wire \main_sdram_trrdcon_ready + attribute \src "ls180.v:777.6-777.30" + wire \main_sdram_trrdcon_valid + attribute \src "ls180.v:786.11-786.35" + wire width 3 \main_sdram_twtrcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:785.32-785.56" + wire \main_sdram_twtrcon_ready + attribute \src "ls180.v:784.6-784.30" + wire \main_sdram_twtrcon_valid + attribute \src "ls180.v:391.6-391.30" + wire \main_sdram_wants_refresh + attribute \src "ls180.v:333.6-333.19" + wire \main_sdram_we + attribute \src "ls180.v:331.5-331.25" + wire \main_sdram_wrdata_re + attribute \src "ls180.v:330.12-330.37" + wire width 16 \main_sdram_wrdata_storage + attribute \src "ls180.v:788.6-788.32" + wire \main_sdram_write_available + attribute \src "ls180.v:988.6-988.27" + wire \main_spimaster0_start + attribute \src "ls180.v:998.12-998.35" + wire width 8 \main_spimaster10_length + attribute \src "ls180.v:999.12-999.36" + wire width 16 \main_spimaster11_storage + attribute \src "ls180.v:1000.5-1000.24" + wire \main_spimaster12_re + attribute \src "ls180.v:1001.6-1001.27" + wire \main_spimaster13_done + attribute \src "ls180.v:1002.6-1002.29" + wire \main_spimaster14_status + attribute \src "ls180.v:1003.6-1003.25" + wire \main_spimaster15_we + attribute \src "ls180.v:1004.11-1004.35" + wire width 8 \main_spimaster16_storage + attribute \src "ls180.v:1005.5-1005.24" + wire \main_spimaster17_re + attribute \src "ls180.v:1006.12-1006.35" + wire width 8 \main_spimaster18_status + attribute \src "ls180.v:1007.6-1007.25" + wire \main_spimaster19_we + attribute \src "ls180.v:989.12-989.34" + wire width 8 \main_spimaster1_length + attribute \src "ls180.v:1061.5-1061.23" + wire \main_spimaster1_re + attribute \src "ls180.v:1060.12-1060.35" + wire width 16 \main_spimaster1_storage + attribute \src "ls180.v:1008.6-1008.26" + wire \main_spimaster20_sel + attribute \src "ls180.v:1009.5-1009.29" + wire \main_spimaster21_storage + attribute \src "ls180.v:1010.5-1010.24" + wire \main_spimaster22_re + attribute \src "ls180.v:1011.5-1011.29" + wire \main_spimaster23_storage + attribute \src "ls180.v:1012.5-1012.24" + wire \main_spimaster24_re + attribute \src "ls180.v:1013.5-1013.32" + wire \main_spimaster25_clk_enable + attribute \src "ls180.v:1014.5-1014.31" + wire \main_spimaster26_cs_enable + attribute \src "ls180.v:1015.11-1015.33" + wire width 3 \main_spimaster27_count + attribute \src "ls180.v:1781.11-1781.55" + wire width 3 \main_spimaster27_count_spimaster0_next_value + attribute \src "ls180.v:1782.5-1782.52" + wire \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:1016.5-1016.32" + wire \main_spimaster28_mosi_latch + attribute \src "ls180.v:1017.5-1017.32" + wire \main_spimaster29_miso_latch + attribute \src "ls180.v:990.5-990.25" + wire \main_spimaster2_done + attribute \src "ls180.v:1018.12-1018.40" + wire width 16 \main_spimaster30_clk_divider + attribute \src "ls180.v:1019.6-1019.31" + wire \main_spimaster31_clk_rise + attribute \src "ls180.v:1020.6-1020.31" + wire \main_spimaster32_clk_fall + attribute \src "ls180.v:1021.11-1021.37" + wire width 8 \main_spimaster33_mosi_data + attribute \src "ls180.v:1022.11-1022.36" + wire width 3 \main_spimaster34_mosi_sel + attribute \src "ls180.v:1023.11-1023.37" + wire width 8 \main_spimaster35_miso_data + attribute \src "ls180.v:991.5-991.24" + wire \main_spimaster3_irq + attribute \src "ls180.v:992.12-992.32" + wire width 8 \main_spimaster4_mosi + attribute \src "ls180.v:993.11-993.31" + wire width 8 \main_spimaster5_miso + attribute \src "ls180.v:994.6-994.24" + wire \main_spimaster6_cs + attribute \src "ls180.v:995.6-995.30" + wire \main_spimaster7_loopback + attribute \src "ls180.v:996.12-996.39" + wire width 16 \main_spimaster8_clk_divider + attribute \src "ls180.v:997.5-997.26" + wire \main_spimaster9_start + attribute \src "ls180.v:1032.13-1032.40" + wire width 16 \main_spisdcard_clk_divider0 + attribute \src "ls180.v:1054.12-1054.39" + wire width 16 \main_spisdcard_clk_divider1 + attribute \src "ls180.v:1049.5-1049.30" + wire \main_spisdcard_clk_enable + attribute \src "ls180.v:1056.6-1056.29" + wire \main_spisdcard_clk_fall + attribute \src "ls180.v:1055.6-1055.29" + wire \main_spisdcard_clk_rise + attribute \src "ls180.v:1036.5-1036.30" + wire \main_spisdcard_control_re + attribute \src "ls180.v:1035.12-1035.42" + wire width 16 \main_spisdcard_control_storage + attribute \src "ls180.v:1051.11-1051.31" + wire width 3 \main_spisdcard_count + attribute \src "ls180.v:1785.11-1785.53" + wire width 3 \main_spisdcard_count_spimaster1_next_value + attribute \src "ls180.v:1786.5-1786.50" + wire \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:1030.6-1030.23" + wire \main_spisdcard_cs + attribute \src "ls180.v:1050.5-1050.29" + wire \main_spisdcard_cs_enable + attribute \src "ls180.v:1046.5-1046.25" + wire \main_spisdcard_cs_re + attribute \src "ls180.v:1045.5-1045.30" + wire \main_spisdcard_cs_storage + attribute \src "ls180.v:1026.5-1026.25" + wire \main_spisdcard_done0 + attribute \src "ls180.v:1037.6-1037.26" + wire \main_spisdcard_done1 + attribute \src "ls180.v:1027.5-1027.23" + wire \main_spisdcard_irq + attribute \src "ls180.v:1025.12-1025.34" + wire width 8 \main_spisdcard_length0 + attribute \src "ls180.v:1034.12-1034.34" + wire width 8 \main_spisdcard_length1 + attribute \src "ls180.v:1031.6-1031.29" + wire \main_spisdcard_loopback + attribute \src "ls180.v:1048.5-1048.31" + wire \main_spisdcard_loopback_re + attribute \src "ls180.v:1047.5-1047.36" + wire \main_spisdcard_loopback_storage + attribute \src "ls180.v:1029.11-1029.30" + wire width 8 \main_spisdcard_miso + attribute \src "ls180.v:1059.11-1059.35" + wire width 8 \main_spisdcard_miso_data + attribute \src "ls180.v:1053.5-1053.30" + wire \main_spisdcard_miso_latch + attribute \src "ls180.v:1042.12-1042.38" + wire width 8 \main_spisdcard_miso_status + attribute \src "ls180.v:1043.6-1043.28" + wire \main_spisdcard_miso_we + attribute \src "ls180.v:1028.12-1028.31" + wire width 8 \main_spisdcard_mosi + attribute \src "ls180.v:1057.11-1057.35" + wire width 8 \main_spisdcard_mosi_data + attribute \src "ls180.v:1052.5-1052.30" + wire \main_spisdcard_mosi_latch + attribute \src "ls180.v:1041.5-1041.27" + wire \main_spisdcard_mosi_re + attribute \src "ls180.v:1058.11-1058.34" + wire width 3 \main_spisdcard_mosi_sel + attribute \src "ls180.v:1040.11-1040.38" + wire width 8 \main_spisdcard_mosi_storage + attribute \src "ls180.v:1044.6-1044.24" + wire \main_spisdcard_sel + attribute \src "ls180.v:1024.6-1024.27" + wire \main_spisdcard_start0 + attribute \src "ls180.v:1033.5-1033.26" + wire \main_spisdcard_start1 + attribute \src "ls180.v:1038.6-1038.34" + wire \main_spisdcard_status_status + attribute \src "ls180.v:1039.6-1039.30" + wire \main_spisdcard_status_we + attribute \src "ls180.v:885.12-885.44" + wire width 2 \main_uart_eventmanager_pending_r + attribute \src "ls180.v:884.6-884.39" + wire \main_uart_eventmanager_pending_re + attribute \src "ls180.v:887.11-887.43" + wire width 2 \main_uart_eventmanager_pending_w + attribute \src "ls180.v:886.6-886.39" + wire \main_uart_eventmanager_pending_we + attribute \src "ls180.v:889.5-889.30" + wire \main_uart_eventmanager_re + attribute \src "ls180.v:881.12-881.43" + wire width 2 \main_uart_eventmanager_status_r + attribute \src "ls180.v:880.6-880.38" + wire \main_uart_eventmanager_status_re + attribute \src "ls180.v:883.11-883.42" + wire width 2 \main_uart_eventmanager_status_w + attribute \src "ls180.v:882.6-882.38" + wire \main_uart_eventmanager_status_we + attribute \src "ls180.v:888.11-888.41" + wire width 2 \main_uart_eventmanager_storage + attribute \src "ls180.v:869.6-869.19" + wire \main_uart_irq + attribute \src "ls180.v:855.12-855.46" + wire width 32 \main_uart_phy_phase_accumulator_rx + attribute \src "ls180.v:845.12-845.46" + wire width 32 \main_uart_phy_phase_accumulator_tx + attribute \src "ls180.v:838.5-838.21" + wire \main_uart_phy_re + attribute \src "ls180.v:856.6-856.22" + wire \main_uart_phy_rx + attribute \src "ls180.v:859.11-859.36" + wire width 4 \main_uart_phy_rx_bitcount + attribute \src "ls180.v:860.5-860.26" + wire \main_uart_phy_rx_busy + attribute \src "ls180.v:857.5-857.23" + wire \main_uart_phy_rx_r + attribute \src "ls180.v:858.11-858.31" + wire width 8 \main_uart_phy_rx_reg + attribute \src "ls180.v:841.6-841.30" + wire \main_uart_phy_sink_first + attribute \src "ls180.v:842.6-842.29" + wire \main_uart_phy_sink_last + attribute \src "ls180.v:843.12-843.43" + wire width 8 \main_uart_phy_sink_payload_data + attribute \src "ls180.v:840.5-840.29" + wire \main_uart_phy_sink_ready + attribute \src "ls180.v:839.6-839.30" + wire \main_uart_phy_sink_valid + attribute \src "ls180.v:851.5-851.31" + wire \main_uart_phy_source_first + attribute \src "ls180.v:852.5-852.30" + wire \main_uart_phy_source_last + attribute \src "ls180.v:853.11-853.44" + wire width 8 \main_uart_phy_source_payload_data + attribute \src "ls180.v:850.6-850.32" + wire \main_uart_phy_source_ready + attribute \src "ls180.v:849.5-849.31" + wire \main_uart_phy_source_valid + attribute \src "ls180.v:837.12-837.33" + wire width 32 \main_uart_phy_storage + attribute \src "ls180.v:847.11-847.36" + wire width 4 \main_uart_phy_tx_bitcount + attribute \src "ls180.v:848.5-848.26" + wire \main_uart_phy_tx_busy + attribute \src "ls180.v:846.11-846.31" + wire width 8 \main_uart_phy_tx_reg + attribute \src "ls180.v:854.5-854.32" + wire \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:844.5-844.32" + wire \main_uart_phy_uart_clk_txen + attribute \src "ls180.v:978.5-978.20" + wire \main_uart_reset + attribute \src "ls180.v:878.5-878.23" + wire \main_uart_rx_clear + attribute \src "ls180.v:962.11-962.36" + wire width 4 \main_uart_rx_fifo_consume + attribute \src "ls180.v:967.6-967.31" + wire \main_uart_rx_fifo_do_read + attribute \src "ls180.v:973.6-973.37" + wire \main_uart_rx_fifo_fifo_in_first + attribute \src "ls180.v:974.6-974.36" + wire \main_uart_rx_fifo_fifo_in_last + attribute \src "ls180.v:972.12-972.50" + wire width 8 \main_uart_rx_fifo_fifo_in_payload_data + attribute \src "ls180.v:976.6-976.38" + wire \main_uart_rx_fifo_fifo_out_first + attribute \src "ls180.v:977.6-977.37" + wire \main_uart_rx_fifo_fifo_out_last + attribute \src "ls180.v:975.12-975.51" + wire width 8 \main_uart_rx_fifo_fifo_out_payload_data + attribute \src "ls180.v:959.11-959.35" + wire width 5 \main_uart_rx_fifo_level0 + attribute \src "ls180.v:971.12-971.36" + wire width 5 \main_uart_rx_fifo_level1 + attribute \src "ls180.v:961.11-961.36" + wire width 4 \main_uart_rx_fifo_produce + attribute \src "ls180.v:968.12-968.40" + wire width 4 \main_uart_rx_fifo_rdport_adr + attribute \src "ls180.v:969.12-969.42" + wire width 10 \main_uart_rx_fifo_rdport_dat_r + attribute \src "ls180.v:970.6-970.33" + wire \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:951.6-951.26" + wire \main_uart_rx_fifo_re + attribute \src "ls180.v:952.5-952.31" + wire \main_uart_rx_fifo_readable + attribute \src "ls180.v:960.5-960.30" + wire \main_uart_rx_fifo_replace + attribute \src "ls180.v:943.6-943.34" + wire \main_uart_rx_fifo_sink_first + attribute \src "ls180.v:944.6-944.33" + wire \main_uart_rx_fifo_sink_last + attribute \src "ls180.v:945.12-945.47" + wire width 8 \main_uart_rx_fifo_sink_payload_data + attribute \src "ls180.v:942.6-942.34" + wire \main_uart_rx_fifo_sink_ready + attribute \src "ls180.v:941.6-941.34" + wire \main_uart_rx_fifo_sink_valid + attribute \src "ls180.v:948.6-948.36" + wire \main_uart_rx_fifo_source_first + attribute \src "ls180.v:949.6-949.35" + wire \main_uart_rx_fifo_source_last + attribute \src "ls180.v:950.12-950.49" + wire width 8 \main_uart_rx_fifo_source_payload_data + attribute \src "ls180.v:947.6-947.36" + wire \main_uart_rx_fifo_source_ready + attribute \src "ls180.v:946.6-946.36" + wire \main_uart_rx_fifo_source_valid + attribute \src "ls180.v:957.12-957.42" + wire width 10 \main_uart_rx_fifo_syncfifo_din + attribute \src "ls180.v:958.12-958.43" + wire width 10 \main_uart_rx_fifo_syncfifo_dout + attribute \src "ls180.v:955.6-955.35" + wire \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:956.6-956.41" + wire \main_uart_rx_fifo_syncfifo_readable + attribute \src "ls180.v:953.6-953.35" + wire \main_uart_rx_fifo_syncfifo_we + attribute \src "ls180.v:954.6-954.41" + wire \main_uart_rx_fifo_syncfifo_writable + attribute \src "ls180.v:963.11-963.39" + wire width 4 \main_uart_rx_fifo_wrport_adr + attribute \src "ls180.v:964.12-964.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_r + attribute \src "ls180.v:966.12-966.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_w + attribute \src "ls180.v:965.6-965.33" + wire \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:879.5-879.29" + wire \main_uart_rx_old_trigger + attribute \src "ls180.v:876.5-876.25" + wire \main_uart_rx_pending + attribute \src "ls180.v:875.6-875.25" + wire \main_uart_rx_status + attribute \src "ls180.v:877.6-877.26" + wire \main_uart_rx_trigger + attribute \src "ls180.v:867.6-867.30" + wire \main_uart_rxempty_status + attribute \src "ls180.v:868.6-868.26" + wire \main_uart_rxempty_we + attribute \src "ls180.v:892.6-892.29" + wire \main_uart_rxfull_status + attribute \src "ls180.v:893.6-893.25" + wire \main_uart_rxfull_we + attribute \src "ls180.v:862.12-862.28" + wire width 8 \main_uart_rxtx_r + attribute \src "ls180.v:861.6-861.23" + wire \main_uart_rxtx_re + attribute \src "ls180.v:864.12-864.28" + wire width 8 \main_uart_rxtx_w + attribute \src "ls180.v:863.6-863.23" + wire \main_uart_rxtx_we + attribute \src "ls180.v:873.5-873.23" + wire \main_uart_tx_clear + attribute \src "ls180.v:925.11-925.36" + wire width 4 \main_uart_tx_fifo_consume + attribute \src "ls180.v:930.6-930.31" + wire \main_uart_tx_fifo_do_read + attribute \src "ls180.v:936.6-936.37" + wire \main_uart_tx_fifo_fifo_in_first + attribute \src "ls180.v:937.6-937.36" + wire \main_uart_tx_fifo_fifo_in_last + attribute \src "ls180.v:935.12-935.50" + wire width 8 \main_uart_tx_fifo_fifo_in_payload_data + attribute \src "ls180.v:939.6-939.38" + wire \main_uart_tx_fifo_fifo_out_first + attribute \src "ls180.v:940.6-940.37" + wire \main_uart_tx_fifo_fifo_out_last + attribute \src "ls180.v:938.12-938.51" + wire width 8 \main_uart_tx_fifo_fifo_out_payload_data + attribute \src "ls180.v:922.11-922.35" + wire width 5 \main_uart_tx_fifo_level0 + attribute \src "ls180.v:934.12-934.36" + wire width 5 \main_uart_tx_fifo_level1 + attribute \src "ls180.v:924.11-924.36" + wire width 4 \main_uart_tx_fifo_produce + attribute \src "ls180.v:931.12-931.40" + wire width 4 \main_uart_tx_fifo_rdport_adr + attribute \src "ls180.v:932.12-932.42" + wire width 10 \main_uart_tx_fifo_rdport_dat_r + attribute \src "ls180.v:933.6-933.33" + wire \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:914.6-914.26" + wire \main_uart_tx_fifo_re + attribute \src "ls180.v:915.5-915.31" + wire \main_uart_tx_fifo_readable + attribute \src "ls180.v:923.5-923.30" + wire \main_uart_tx_fifo_replace + attribute \src "ls180.v:906.5-906.33" + wire \main_uart_tx_fifo_sink_first + attribute \src "ls180.v:907.5-907.32" + wire \main_uart_tx_fifo_sink_last + attribute \src "ls180.v:908.12-908.47" + wire width 8 \main_uart_tx_fifo_sink_payload_data + attribute \src "ls180.v:905.6-905.34" + wire \main_uart_tx_fifo_sink_ready + attribute \src "ls180.v:904.6-904.34" + wire \main_uart_tx_fifo_sink_valid + attribute \src "ls180.v:911.6-911.36" + wire \main_uart_tx_fifo_source_first + attribute \src "ls180.v:912.6-912.35" + wire \main_uart_tx_fifo_source_last + attribute \src "ls180.v:913.12-913.49" + wire width 8 \main_uart_tx_fifo_source_payload_data + attribute \src "ls180.v:910.6-910.36" + wire \main_uart_tx_fifo_source_ready + attribute \src "ls180.v:909.6-909.36" + wire \main_uart_tx_fifo_source_valid + attribute \src "ls180.v:920.12-920.42" + wire width 10 \main_uart_tx_fifo_syncfifo_din + attribute \src "ls180.v:921.12-921.43" + wire width 10 \main_uart_tx_fifo_syncfifo_dout + attribute \src "ls180.v:918.6-918.35" + wire \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:919.6-919.41" + wire \main_uart_tx_fifo_syncfifo_readable + attribute \src "ls180.v:916.6-916.35" + wire \main_uart_tx_fifo_syncfifo_we + attribute \src "ls180.v:917.6-917.41" + wire \main_uart_tx_fifo_syncfifo_writable + attribute \src "ls180.v:926.11-926.39" + wire width 4 \main_uart_tx_fifo_wrport_adr + attribute \src "ls180.v:927.12-927.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_r + attribute \src "ls180.v:929.12-929.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_w + attribute \src "ls180.v:928.6-928.33" + wire \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:874.5-874.29" + wire \main_uart_tx_old_trigger + attribute \src "ls180.v:871.5-871.25" + wire \main_uart_tx_pending + attribute \src "ls180.v:870.6-870.25" + wire \main_uart_tx_status + attribute \src "ls180.v:872.6-872.26" + wire \main_uart_tx_trigger + attribute \src "ls180.v:890.6-890.30" + wire \main_uart_txempty_status + attribute \src "ls180.v:891.6-891.26" + wire \main_uart_txempty_we + attribute \src "ls180.v:865.6-865.29" + wire \main_uart_txfull_status + attribute \src "ls180.v:866.6-866.25" + wire \main_uart_txfull_we + attribute \src "ls180.v:896.6-896.31" + wire \main_uart_uart_sink_first + attribute \src "ls180.v:897.6-897.30" + wire \main_uart_uart_sink_last + attribute \src "ls180.v:898.12-898.44" + wire width 8 \main_uart_uart_sink_payload_data + attribute \src "ls180.v:895.6-895.31" + wire \main_uart_uart_sink_ready + attribute \src "ls180.v:894.6-894.31" + wire \main_uart_uart_sink_valid + attribute \src "ls180.v:901.6-901.33" + wire \main_uart_uart_source_first + attribute \src "ls180.v:902.6-902.32" + wire \main_uart_uart_source_last + attribute \src "ls180.v:903.12-903.46" + wire width 8 \main_uart_uart_source_payload_data + attribute \src "ls180.v:900.6-900.33" + wire \main_uart_uart_source_ready + attribute \src "ls180.v:899.6-899.33" + wire \main_uart_uart_source_valid + attribute \src "ls180.v:815.5-815.22" + wire \main_wb_sdram_ack + attribute \src "ls180.v:809.13-809.30" + wire width 30 \main_wb_sdram_adr + attribute \src "ls180.v:818.12-818.29" + wire width 2 \main_wb_sdram_bte + attribute \src "ls180.v:817.12-817.29" + wire width 3 \main_wb_sdram_cti + attribute \src "ls180.v:813.6-813.23" + wire \main_wb_sdram_cyc + attribute \src "ls180.v:811.13-811.32" + wire width 32 \main_wb_sdram_dat_r + attribute \src "ls180.v:810.13-810.32" + wire width 32 \main_wb_sdram_dat_w + attribute \src "ls180.v:819.5-819.22" + wire \main_wb_sdram_err + attribute \src "ls180.v:812.12-812.29" + wire width 4 \main_wb_sdram_sel + attribute \src "ls180.v:814.6-814.23" + wire \main_wb_sdram_stb + attribute \src "ls180.v:816.6-816.22" + wire \main_wb_sdram_we + attribute \src "ls180.v:833.5-833.24" + wire \main_wdata_consumed + attribute \src "ls180.v:10042.11-10042.17" + wire width 7 \memadr + attribute \src "ls180.v:10062.12-10062.18" + wire width 25 \memdat + attribute \src "ls180.v:10076.12-10076.20" + wire width 25 \memdat_1 + attribute \src "ls180.v:10090.12-10090.20" + wire width 25 \memdat_2 + attribute \src "ls180.v:10104.12-10104.20" + wire width 25 \memdat_3 + attribute \src "ls180.v:10118.11-10118.19" + wire width 10 \memdat_4 + attribute \src "ls180.v:10119.11-10119.19" + wire width 10 \memdat_5 + attribute \src "ls180.v:10135.11-10135.19" + wire width 10 \memdat_6 + attribute \src "ls180.v:10136.11-10136.19" + wire width 10 \memdat_7 + attribute \src "ls180.v:10152.11-10152.19" + wire width 10 \memdat_8 + attribute \src "ls180.v:10166.11-10166.19" + wire width 10 \memdat_9 + attribute \src "ls180.v:52.20-52.22" + wire width 24 input 48 \nc + attribute \src "ls180.v:247.6-247.13" + wire \por_clk + attribute \src "ls180.v:41.19-41.22" + wire width 2 output 37 \pwm + attribute \src "ls180.v:156.12-156.17" + wire width 2 \pwm_1 + attribute \src "ls180.v:5.13-5.23" + wire output 1 \sdcard_clk + attribute \src "ls180.v:6.13-6.25" + wire input 2 \sdcard_cmd_i + attribute \src "ls180.v:7.13-7.25" + wire output 3 \sdcard_cmd_o + attribute \src "ls180.v:8.13-8.26" + wire output 4 \sdcard_cmd_oe + attribute \src "ls180.v:9.19-9.32" + wire width 4 input 5 \sdcard_data_i + attribute \src "ls180.v:10.19-10.32" + wire width 4 output 6 \sdcard_data_o + attribute \src "ls180.v:11.13-11.27" + wire output 7 \sdcard_data_oe + attribute \src "ls180.v:16.20-16.27" + wire width 13 output 12 \sdram_a + attribute \src "ls180.v:25.19-25.27" + wire width 2 output 21 \sdram_ba + attribute \src "ls180.v:22.13-22.24" + wire output 18 \sdram_cas_n + attribute \src "ls180.v:24.13-24.22" + wire output 20 \sdram_cke + attribute \src "ls180.v:27.13-27.24" + wire output 23 \sdram_clock + attribute \src "ls180.v:144.6-144.19" + wire \sdram_clock_1 + attribute \src "ls180.v:23.13-23.23" + wire output 19 \sdram_cs_n + attribute \src "ls180.v:26.19-26.27" + wire width 2 output 22 \sdram_dm + attribute \src "ls180.v:17.20-17.30" + wire width 16 input 13 \sdram_dq_i + attribute \src "ls180.v:18.20-18.30" + wire width 16 output 14 \sdram_dq_o + attribute \src "ls180.v:19.13-19.24" + wire output 15 \sdram_dq_oe + attribute \src "ls180.v:21.13-21.24" + wire output 17 \sdram_ras_n + attribute \src "ls180.v:20.13-20.23" + wire output 16 \sdram_we_n + attribute \src "ls180.v:2643.6-2643.15" + wire \sdrio_clk + attribute \src "ls180.v:2644.6-2644.17" + wire \sdrio_clk_1 + attribute \src "ls180.v:2653.6-2653.18" + wire \sdrio_clk_10 + attribute \src "ls180.v:2654.6-2654.18" + wire \sdrio_clk_11 + attribute \src "ls180.v:2655.6-2655.18" + wire \sdrio_clk_12 + attribute \src "ls180.v:2656.6-2656.18" + wire \sdrio_clk_13 + attribute \src "ls180.v:2657.6-2657.18" + wire \sdrio_clk_14 + attribute \src "ls180.v:2658.6-2658.18" + wire \sdrio_clk_15 + attribute \src "ls180.v:2659.6-2659.18" + wire \sdrio_clk_16 + attribute \src "ls180.v:2660.6-2660.18" + wire \sdrio_clk_17 + attribute \src "ls180.v:2661.6-2661.18" + wire \sdrio_clk_18 + attribute \src "ls180.v:2662.6-2662.18" + wire \sdrio_clk_19 + attribute \src "ls180.v:2645.6-2645.17" + wire \sdrio_clk_2 + attribute \src "ls180.v:2663.6-2663.18" + wire \sdrio_clk_20 + attribute \src "ls180.v:2664.6-2664.18" + wire \sdrio_clk_21 + attribute \src "ls180.v:2665.6-2665.18" + wire \sdrio_clk_22 + attribute \src "ls180.v:2666.6-2666.18" + wire \sdrio_clk_23 + attribute \src "ls180.v:2667.6-2667.18" + wire \sdrio_clk_24 + attribute \src "ls180.v:2668.6-2668.18" + wire \sdrio_clk_25 + attribute \src "ls180.v:2669.6-2669.18" + wire \sdrio_clk_26 + attribute \src "ls180.v:2670.6-2670.18" + wire \sdrio_clk_27 + attribute \src "ls180.v:2671.6-2671.18" + wire \sdrio_clk_28 + attribute \src "ls180.v:2672.6-2672.18" + wire \sdrio_clk_29 + attribute \src "ls180.v:2646.6-2646.17" + wire \sdrio_clk_3 + attribute \src "ls180.v:2673.6-2673.18" + wire \sdrio_clk_30 + attribute \src "ls180.v:2674.6-2674.18" + wire \sdrio_clk_31 + attribute \src "ls180.v:2675.6-2675.18" + wire \sdrio_clk_32 + attribute \src "ls180.v:2676.6-2676.18" + wire \sdrio_clk_33 + attribute \src "ls180.v:2677.6-2677.18" + wire \sdrio_clk_34 + attribute \src "ls180.v:2678.6-2678.18" + wire \sdrio_clk_35 + attribute \src "ls180.v:2679.6-2679.18" + wire \sdrio_clk_36 + attribute \src "ls180.v:2680.6-2680.18" + wire \sdrio_clk_37 + attribute \src "ls180.v:2681.6-2681.18" + wire \sdrio_clk_38 + attribute \src "ls180.v:2682.6-2682.18" + wire \sdrio_clk_39 + attribute \src "ls180.v:2647.6-2647.17" + wire \sdrio_clk_4 + attribute \src "ls180.v:2683.6-2683.18" + wire \sdrio_clk_40 + attribute \src "ls180.v:2684.6-2684.18" + wire \sdrio_clk_41 + attribute \src "ls180.v:2685.6-2685.18" + wire \sdrio_clk_42 + attribute \src "ls180.v:2686.6-2686.18" + wire \sdrio_clk_43 + attribute \src "ls180.v:2687.6-2687.18" + wire \sdrio_clk_44 + attribute \src "ls180.v:2688.6-2688.18" + wire \sdrio_clk_45 + attribute \src "ls180.v:2689.6-2689.18" + wire \sdrio_clk_46 + attribute \src "ls180.v:2690.6-2690.18" + wire \sdrio_clk_47 + attribute \src "ls180.v:2691.6-2691.18" + wire \sdrio_clk_48 + attribute \src "ls180.v:2692.6-2692.18" + wire \sdrio_clk_49 + attribute \src "ls180.v:2648.6-2648.17" + wire \sdrio_clk_5 + attribute \src "ls180.v:2693.6-2693.18" + wire \sdrio_clk_50 + attribute \src "ls180.v:2694.6-2694.18" + wire \sdrio_clk_51 + attribute \src "ls180.v:2695.6-2695.18" + wire \sdrio_clk_52 + attribute \src "ls180.v:2696.6-2696.18" + wire \sdrio_clk_53 + attribute \src "ls180.v:2697.6-2697.18" + wire \sdrio_clk_54 + attribute \src "ls180.v:2698.6-2698.18" + wire \sdrio_clk_55 + attribute \src "ls180.v:2733.6-2733.18" + wire \sdrio_clk_56 + attribute \src "ls180.v:2734.6-2734.18" + wire \sdrio_clk_57 + attribute \src "ls180.v:2735.6-2735.18" + wire \sdrio_clk_58 + attribute \src "ls180.v:2736.6-2736.18" + wire \sdrio_clk_59 + attribute \src "ls180.v:2649.6-2649.17" + wire \sdrio_clk_6 + attribute \src "ls180.v:2737.6-2737.18" + wire \sdrio_clk_60 + attribute \src "ls180.v:2738.6-2738.18" + wire \sdrio_clk_61 + attribute \src "ls180.v:2739.6-2739.18" + wire \sdrio_clk_62 + attribute \src "ls180.v:2740.6-2740.18" + wire \sdrio_clk_63 + attribute \src "ls180.v:2741.6-2741.18" + wire \sdrio_clk_64 + attribute \src "ls180.v:2742.6-2742.18" + wire \sdrio_clk_65 + attribute \src "ls180.v:2743.6-2743.18" + wire \sdrio_clk_66 + attribute \src "ls180.v:2744.6-2744.18" + wire \sdrio_clk_67 + attribute \src "ls180.v:2745.6-2745.18" + wire \sdrio_clk_68 + attribute \src "ls180.v:2650.6-2650.17" + wire \sdrio_clk_7 + attribute \src "ls180.v:2651.6-2651.17" + wire \sdrio_clk_8 + attribute \src "ls180.v:2652.6-2652.17" + wire \sdrio_clk_9 + attribute \src "ls180.v:12.13-12.26" + wire output 8 \spimaster_clk + attribute \src "ls180.v:14.13-14.27" + wire output 10 \spimaster_cs_n + attribute \src "ls180.v:15.13-15.27" + wire input 11 \spimaster_miso + attribute \src "ls180.v:13.13-13.27" + wire output 9 \spimaster_mosi + attribute \src "ls180.v:31.13-31.26" + wire output 27 \spisdcard_clk + attribute \src "ls180.v:33.13-33.27" + wire output 29 \spisdcard_cs_n + attribute \src "ls180.v:34.13-34.27" + wire input 30 \spisdcard_miso + attribute \src "ls180.v:32.13-32.27" + wire output 28 \spisdcard_mosi + attribute \src "ls180.v:43.13-43.20" + wire input 39 \sys_clk + attribute \src "ls180.v:245.6-245.15" + wire \sys_clk_1 + attribute \src "ls180.v:45.19-45.31" + wire width 2 input 41 \sys_clksel_i + attribute \src "ls180.v:46.14-46.26" + wire output 42 \sys_pll_18_o + attribute \src "ls180.v:47.14-47.27" + wire output 43 \sys_pll_lck_o + attribute \src "ls180.v:44.13-44.20" + wire input 40 \sys_rst + attribute \src "ls180.v:246.6-246.15" + wire \sys_rst_1 + attribute \src "ls180.v:40.13-40.20" + wire input 36 \uart_rx + attribute \src "ls180.v:39.13-39.20" + wire output 35 \uart_tx + attribute \src "ls180.v:10041.12-10041.15" + memory width 32 size 128 \mem + attribute \src "ls180.v:10061.12-10061.19" + memory width 25 size 8 \storage + attribute \src "ls180.v:10075.12-10075.21" + memory width 25 size 8 \storage_1 + attribute \src "ls180.v:10089.12-10089.21" + memory width 25 size 8 \storage_2 + attribute \src "ls180.v:10103.12-10103.21" + memory width 25 size 8 \storage_3 + attribute \src "ls180.v:10117.11-10117.20" + memory width 10 size 16 \storage_4 + attribute \src "ls180.v:10134.11-10134.20" + memory width 10 size 16 \storage_5 + attribute \src "ls180.v:10151.11-10151.20" + memory width 10 size 32 \storage_6 + attribute \src "ls180.v:10165.11-10165.20" + memory width 10 size 32 \storage_7 + attribute \src "ls180.v:2815.68-2815.110" + cell $add $add$ls180.v:2815$22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $add$ls180.v:2815$22_Y + end + attribute \src "ls180.v:2875.68-2875.110" + cell $add $add$ls180.v:2875$33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $add$ls180.v:2875$33_Y + end + attribute \src "ls180.v:2935.68-2935.110" + cell $add $add$ls180.v:2935$44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_counter + connect \B 1'1 + connect \Y $add$ls180.v:2935$44_Y + end + attribute \src "ls180.v:4068.54-4068.83" + cell $add $add$ls180.v:4068$537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $add$ls180.v:4068$537_Y + end + attribute \src "ls180.v:4168.36-4168.89" + cell $add $add$ls180.v:4168$583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B \main_uart_tx_fifo_readable + connect \Y $add$ls180.v:4168$583_Y + end + attribute \src "ls180.v:4198.36-4198.89" + cell $add $add$ls180.v:4198$594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B \main_uart_rx_fifo_readable + connect \Y $add$ls180.v:4198$594_Y + end + attribute \src "ls180.v:4253.54-4253.83" + cell $add $add$ls180.v:4253$607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spimaster27_count + connect \B 1'1 + connect \Y $add$ls180.v:4253$607_Y + end + attribute \src "ls180.v:4312.52-4312.79" + cell $add $add$ls180.v:4312$615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_count + connect \B 1'1 + connect \Y $add$ls180.v:4312$615_Y + end + attribute \src "ls180.v:4416.58-4416.86" + cell $add $add$ls180.v:4416$643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_init_count + connect \B 1'1 + connect \Y $add$ls180.v:4416$643_Y + end + attribute \src "ls180.v:4473.58-4473.86" + cell $add $add$ls180.v:4473$646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4473$646_Y + end + attribute \src "ls180.v:4490.58-4490.86" + cell $add $add$ls180.v:4490$648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4490$648_Y + end + attribute \src "ls180.v:4583.59-4583.87" + cell $add $add$ls180.v:4583$665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4583$665_Y + end + attribute \src "ls180.v:4608.59-4608.87" + cell $add $add$ls180.v:4608$668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4608$668_Y + end + attribute \src "ls180.v:4730.53-4730.82" + cell $add $add$ls180.v:4730$685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $add$ls180.v:4730$685_Y + end + attribute \src "ls180.v:4841.65-4841.114" + cell $add $add$ls180.v:4841$699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_sink_payload_block_length + connect \B 4'1000 + connect \Y $add$ls180.v:4841$699_Y + end + attribute \src "ls180.v:4846.62-4846.91" + cell $add $add$ls180.v:4846$702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4846$702_Y + end + attribute \src "ls180.v:4872.61-4872.90" + cell $add $add$ls180.v:4872$705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4872$705_Y + end + attribute \src "ls180.v:5076.80-5076.117" + cell $add $add$ls180.v:5076$890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 1'1 + connect \Y $add$ls180.v:5076$890_Y + end + attribute \src "ls180.v:5270.54-5270.82" + cell $add $add$ls180.v:5270$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_cmd_count + connect \B 1'1 + connect \Y $add$ls180.v:5270$965_Y + end + attribute \src "ls180.v:5322.55-5322.84" + cell $add $add$ls180.v:5322$975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5322$975_Y + end + attribute \src "ls180.v:5348.57-5348.86" + cell $add $add$ls180.v:5348$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5348$983_Y + end + attribute \src "ls180.v:5469.51-5469.134" + cell $add $add$ls180.v:5469$999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_base + connect \B \main_sdblock2mem_wishbonedmawriter_offset + connect \Y $add$ls180.v:5469$999_Y + end + attribute \src "ls180.v:5472.77-5472.125" + cell $add $add$ls180.v:5472$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B 1'1 + connect \Y $add$ls180.v:5472$1001_Y + end + attribute \src "ls180.v:5565.50-5565.105" + cell $add $add$ls180.v:5565$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_base + connect \B \main_sdmem2block_dma_offset + connect \Y $add$ls180.v:5565$1010_Y + end + attribute \src "ls180.v:5567.77-5567.111" + cell $add $add$ls180.v:5567$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_offset + connect \B 1'1 + connect \Y $add$ls180.v:5567$1011_Y + end + attribute \src "ls180.v:7487.36-7487.70" + cell $add $add$ls180.v:7487$2403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_bus_errors + connect \B 1'1 + connect \Y $add$ls180.v:7487$2403_Y + end + attribute \src "ls180.v:7572.37-7572.72" + cell $add $add$ls180.v:7572$2424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_sequencer_counter + connect \B 1'1 + connect \Y $add$ls180.v:7572$2424_Y + end + attribute \src "ls180.v:7589.60-7589.119" + cell $add $add$ls180.v:7589$2428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7589$2428_Y + end + attribute \src "ls180.v:7592.60-7592.119" + cell $add $add$ls180.v:7592$2429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7592$2429_Y + end + attribute \src "ls180.v:7596.59-7596.116" + cell $add $add$ls180.v:7596$2434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7596$2434_Y + end + attribute \src "ls180.v:7635.60-7635.119" + cell $add $add$ls180.v:7635$2444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7635$2444_Y + end + attribute \src "ls180.v:7638.60-7638.119" + cell $add $add$ls180.v:7638$2445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7638$2445_Y + end + attribute \src "ls180.v:7642.59-7642.116" + cell $add $add$ls180.v:7642$2450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7642$2450_Y + end + attribute \src "ls180.v:7681.60-7681.119" + cell $add $add$ls180.v:7681$2460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7681$2460_Y + end + attribute \src "ls180.v:7684.60-7684.119" + cell $add $add$ls180.v:7684$2461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7684$2461_Y + end + attribute \src "ls180.v:7688.59-7688.116" + cell $add $add$ls180.v:7688$2466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7688$2466_Y + end + attribute \src "ls180.v:7727.60-7727.119" + cell $add $add$ls180.v:7727$2476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7727$2476_Y + end + attribute \src "ls180.v:7730.60-7730.119" + cell $add $add$ls180.v:7730$2477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7730$2477_Y + end + attribute \src "ls180.v:7734.59-7734.116" + cell $add $add$ls180.v:7734$2482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7734$2482_Y + end + attribute \src "ls180.v:7964.34-7964.66" + cell $add $add$ls180.v:7964$2536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_tx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:7964$2536_Y + end + attribute \src "ls180.v:7980.73-7980.131" + cell $add $add$ls180.v:7980$2539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_tx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:7980$2539_Y + end + attribute \src "ls180.v:7993.34-7993.66" + cell $add $add$ls180.v:7993$2543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:7993$2543_Y + end + attribute \src "ls180.v:8012.73-8012.131" + cell $add $add$ls180.v:8012$2546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_rx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:8012$2546_Y + end + attribute \src "ls180.v:8038.33-8038.65" + cell $add $add$ls180.v:8038$2554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8038$2554_Y + end + attribute \src "ls180.v:8041.33-8041.65" + cell $add $add$ls180.v:8041$2555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8041$2555_Y + end + attribute \src "ls180.v:8045.33-8045.64" + cell $add $add$ls180.v:8045$2560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8045$2560_Y + end + attribute \src "ls180.v:8060.33-8060.65" + cell $add $add$ls180.v:8060$2565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8060$2565_Y + end + attribute \src "ls180.v:8063.33-8063.65" + cell $add $add$ls180.v:8063$2566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8063$2566_Y + end + attribute \src "ls180.v:8067.33-8067.64" + cell $add $add$ls180.v:8067$2571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8067$2571_Y + end + attribute \src "ls180.v:8088.35-8088.70" + cell $add $add$ls180.v:8088$2573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster30_clk_divider + connect \B 1'1 + connect \Y $add$ls180.v:8088$2573_Y + end + attribute \src "ls180.v:8123.34-8123.68" + cell $add $add$ls180.v:8123$2578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8123$2578_Y + end + attribute \src "ls180.v:8159.25-8159.49" + cell $add $add$ls180.v:8159$2583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_counter + connect \B 1'1 + connect \Y $add$ls180.v:8159$2583_Y + end + attribute \src "ls180.v:8173.25-8173.49" + cell $add $add$ls180.v:8173$2587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_counter + connect \B 1'1 + connect \Y $add$ls180.v:8173$2587_Y + end + attribute \src "ls180.v:8187.31-8187.61" + cell $add $add$ls180.v:8187$2592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 9 + connect \A \main_sdphy_clocker_clks + connect \B 1'1 + connect \Y $add$ls180.v:8187$2592_Y + end + attribute \src "ls180.v:8210.45-8210.88" + cell $add $add$ls180.v:8210$2596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8210$2596_Y + end + attribute \src "ls180.v:8256.71-8256.114" + cell $add $add$ls180.v:8256$2602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8256$2602_Y + end + attribute \src "ls180.v:8291.46-8291.90" + cell $add $add$ls180.v:8291$2608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8291$2608_Y + end + attribute \src "ls180.v:8337.72-8337.116" + cell $add $add$ls180.v:8337$2614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8337$2614_Y + end + attribute \src "ls180.v:8370.47-8370.92" + cell $add $add$ls180.v:8370$2620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8370$2620_Y + end + attribute \src "ls180.v:8398.73-8398.118" + cell $add $add$ls180.v:8398$2626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8398$2626_Y + end + attribute \src "ls180.v:8510.39-8510.75" + cell $add $add$ls180.v:8510$2639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 1'1 + connect \Y $add$ls180.v:8510$2639_Y + end + attribute \src "ls180.v:8571.37-8571.73" + cell $add $add$ls180.v:8571$2643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8571$2643_Y + end + attribute \src "ls180.v:8574.37-8574.73" + cell $add $add$ls180.v:8574$2644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8574$2644_Y + end + attribute \src "ls180.v:8578.36-8578.70" + cell $add $add$ls180.v:8578$2649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8578$2649_Y + end + attribute \src "ls180.v:8593.41-8593.80" + cell $add $add$ls180.v:8593$2653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8593$2653_Y + end + attribute \src "ls180.v:8627.67-8627.106" + cell $add $add$ls180.v:8627$2659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8627$2659_Y + end + attribute \src "ls180.v:8653.39-8653.76" + cell $add $add$ls180.v:8653$2661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdmem2block_converter_mux + connect \B 1'1 + connect \Y $add$ls180.v:8653$2661_Y + end + attribute \src "ls180.v:8657.37-8657.73" + cell $add $add$ls180.v:8657$2665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8657$2665_Y + end + attribute \src "ls180.v:8660.37-8660.73" + cell $add $add$ls180.v:8660$2666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8660$2666_Y + end + attribute \src "ls180.v:8664.36-8664.70" + cell $add $add$ls180.v:8664$2671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8664$2671_Y + end + attribute \src "ls180.v:2809.9-2809.80" + cell $and $and$ls180.v:2809$17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:2809$17_Y + end + attribute \src "ls180.v:2827.9-2827.80" + cell $and $and$ls180.v:2827$24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:2827$24_Y + end + attribute \src "ls180.v:2869.9-2869.80" + cell $and $and$ls180.v:2869$28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:2869$28_Y + end + attribute \src "ls180.v:2887.9-2887.80" + cell $and $and$ls180.v:2887$35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:2887$35_Y + end + attribute \src "ls180.v:2929.9-2929.86" + cell $and $and$ls180.v:2929$39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_stb + connect \B \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:2929$39_Y + end + attribute \src "ls180.v:2947.9-2947.86" + cell $and $and$ls180.v:2947$46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_stb + connect \B \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:2947$46_Y + end + attribute \src "ls180.v:2957.31-2957.90" + cell $and $and$ls180.v:2957$48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2957$48_Y + end + attribute \src "ls180.v:2957.30-2957.121" + cell $and $and$ls180.v:2957$49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2957$48_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2957$49_Y + end + attribute \src "ls180.v:2957.29-2957.156" + cell $and $and$ls180.v:2957$50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2957$49_Y + connect \B \main_libresocsim_ram_bus_sel [0] + connect \Y $and$ls180.v:2957$50_Y + end + attribute \src "ls180.v:2958.31-2958.90" + cell $and $and$ls180.v:2958$51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2958$51_Y + end + attribute \src "ls180.v:2958.30-2958.121" + cell $and $and$ls180.v:2958$52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2958$51_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2958$52_Y + end + attribute \src "ls180.v:2958.29-2958.156" + cell $and $and$ls180.v:2958$53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2958$52_Y + connect \B \main_libresocsim_ram_bus_sel [1] + connect \Y $and$ls180.v:2958$53_Y + end + attribute \src "ls180.v:2959.31-2959.90" + cell $and $and$ls180.v:2959$54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2959$54_Y + end + attribute \src "ls180.v:2959.30-2959.121" + cell $and $and$ls180.v:2959$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2959$54_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2959$55_Y + end + attribute \src "ls180.v:2959.29-2959.156" + cell $and $and$ls180.v:2959$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2959$55_Y + connect \B \main_libresocsim_ram_bus_sel [2] + connect \Y $and$ls180.v:2959$56_Y + end + attribute \src "ls180.v:2960.31-2960.90" + cell $and $and$ls180.v:2960$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2960$57_Y + end + attribute \src "ls180.v:2960.30-2960.121" + cell $and $and$ls180.v:2960$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2960$57_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2960$58_Y + end + attribute \src "ls180.v:2960.29-2960.156" + cell $and $and$ls180.v:2960$59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2960$58_Y + connect \B \main_libresocsim_ram_bus_sel [3] + connect \Y $and$ls180.v:2960$59_Y + end + attribute \src "ls180.v:2969.7-2969.89" + cell $and $and$ls180.v:2969$62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_re + connect \B \main_libresocsim_eventmanager_pending_r + connect \Y $and$ls180.v:2969$62_Y + end + attribute \src "ls180.v:2974.32-2974.111" + cell $and $and$ls180.v:2974$63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_w + connect \B \main_libresocsim_eventmanager_storage + connect \Y $and$ls180.v:2974$63_Y + end + attribute \src "ls180.v:3088.40-3088.99" + cell $and $and$ls180.v:3088$70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [4] + connect \Y $and$ls180.v:3088$70_Y + end + attribute \src "ls180.v:3089.40-3089.99" + cell $and $and$ls180.v:3089$71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [5] + connect \Y $and$ls180.v:3089$71_Y + end + attribute \src "ls180.v:3127.38-3127.103" + cell $and $and$ls180.v:3127$77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_done1 + connect \B $eq$ls180.v:3127$76_Y + connect \Y $and$ls180.v:3127$77_Y + end + attribute \src "ls180.v:3181.50-3181.119" + cell $and $and$ls180.v:3181$85 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3181$85_Y + end + attribute \src "ls180.v:3181.49-3181.167" + cell $and $and$ls180.v:3181$86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3181$85_Y + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3181$86_Y + end + attribute \src "ls180.v:3182.49-3182.118" + cell $and $and$ls180.v:3182$87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3182$87_Y + end + attribute \src "ls180.v:3182.48-3182.154" + cell $and $and$ls180.v:3182$88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3182$87_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3182$88_Y + end + attribute \src "ls180.v:3183.50-3183.119" + cell $and $and$ls180.v:3183$89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3183$89_Y + end + attribute \src "ls180.v:3183.49-3183.155" + cell $and $and$ls180.v:3183$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3183$89_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3183$90_Y + end + attribute \src "ls180.v:3186.7-3186.114" + cell $and $and$ls180.v:3186$92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$ls180.v:3186$92_Y + end + attribute \src "ls180.v:3215.66-3215.246" + cell $and $and$ls180.v:3215$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$ls180.v:3215$97_Y + connect \Y $and$ls180.v:3215$98_Y + end + attribute \src "ls180.v:3216.64-3216.187" + cell $and $and$ls180.v:3216$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$ls180.v:3216$99_Y + end + attribute \src "ls180.v:3240.9-3240.86" + cell $and $and$ls180.v:3240$105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3240$105_Y + end + attribute \src "ls180.v:3252.9-3252.86" + cell $and $and$ls180.v:3252$106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3252$106_Y + end + attribute \src "ls180.v:3302.13-3302.87" + cell $and $and$ls180.v:3302$108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_ready + connect \B \main_sdram_bankmachine0_auto_precharge + connect \Y $and$ls180.v:3302$108_Y + end + attribute \src "ls180.v:3338.50-3338.119" + cell $and $and$ls180.v:3338$115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3338$115_Y + end + attribute \src "ls180.v:3338.49-3338.167" + cell $and $and$ls180.v:3338$116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3338$115_Y + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3338$116_Y + end + attribute \src "ls180.v:3339.49-3339.118" + cell $and $and$ls180.v:3339$117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3339$117_Y + end + attribute \src "ls180.v:3339.48-3339.154" + cell $and $and$ls180.v:3339$118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3339$117_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3339$118_Y + end + attribute \src "ls180.v:3340.50-3340.119" + cell $and $and$ls180.v:3340$119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3340$119_Y + end + attribute \src "ls180.v:3340.49-3340.155" + cell $and $and$ls180.v:3340$120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3340$119_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3340$120_Y + end + attribute \src "ls180.v:3343.7-3343.114" + cell $and $and$ls180.v:3343$122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$ls180.v:3343$122_Y + end + attribute \src "ls180.v:3372.66-3372.246" + cell $and $and$ls180.v:3372$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$ls180.v:3372$127_Y + connect \Y $and$ls180.v:3372$128_Y + end + attribute \src "ls180.v:3373.64-3373.187" + cell $and $and$ls180.v:3373$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$ls180.v:3373$129_Y + end + attribute \src "ls180.v:3397.9-3397.86" + cell $and $and$ls180.v:3397$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3397$135_Y + end + attribute \src "ls180.v:3409.9-3409.86" + cell $and $and$ls180.v:3409$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3409$136_Y + end + attribute \src "ls180.v:3459.13-3459.87" + cell $and $and$ls180.v:3459$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_ready + connect \B \main_sdram_bankmachine1_auto_precharge + connect \Y $and$ls180.v:3459$138_Y + end + attribute \src "ls180.v:3495.50-3495.119" + cell $and $and$ls180.v:3495$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3495$145_Y + end + attribute \src "ls180.v:3495.49-3495.167" + cell $and $and$ls180.v:3495$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3495$145_Y + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3495$146_Y + end + attribute \src "ls180.v:3496.49-3496.118" + cell $and $and$ls180.v:3496$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3496$147_Y + end + attribute \src "ls180.v:3496.48-3496.154" + cell $and $and$ls180.v:3496$148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3496$147_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3496$148_Y + end + attribute \src "ls180.v:3497.50-3497.119" + cell $and $and$ls180.v:3497$149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3497$149_Y + end + attribute \src "ls180.v:3497.49-3497.155" + cell $and $and$ls180.v:3497$150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3497$149_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3497$150_Y + end + attribute \src "ls180.v:3500.7-3500.114" + cell $and $and$ls180.v:3500$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$ls180.v:3500$152_Y + end + attribute \src "ls180.v:3529.66-3529.246" + cell $and $and$ls180.v:3529$158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$ls180.v:3529$157_Y + connect \Y $and$ls180.v:3529$158_Y + end + attribute \src "ls180.v:3530.64-3530.187" + cell $and $and$ls180.v:3530$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$ls180.v:3530$159_Y + end + attribute \src "ls180.v:3554.9-3554.86" + cell $and $and$ls180.v:3554$165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3554$165_Y + end + attribute \src "ls180.v:3566.9-3566.86" + cell $and $and$ls180.v:3566$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3566$166_Y + end + attribute \src "ls180.v:3616.13-3616.87" + cell $and $and$ls180.v:3616$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_ready + connect \B \main_sdram_bankmachine2_auto_precharge + connect \Y $and$ls180.v:3616$168_Y + end + attribute \src "ls180.v:3652.50-3652.119" + cell $and $and$ls180.v:3652$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3652$175_Y + end + attribute \src "ls180.v:3652.49-3652.167" + cell $and $and$ls180.v:3652$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3652$175_Y + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3652$176_Y + end + attribute \src "ls180.v:3653.49-3653.118" + cell $and $and$ls180.v:3653$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3653$177_Y + end + attribute \src "ls180.v:3653.48-3653.154" + cell $and $and$ls180.v:3653$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3653$177_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3653$178_Y + end + attribute \src "ls180.v:3654.50-3654.119" + cell $and $and$ls180.v:3654$179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3654$179_Y + end + attribute \src "ls180.v:3654.49-3654.155" + cell $and $and$ls180.v:3654$180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3654$179_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3654$180_Y + end + attribute \src "ls180.v:3657.7-3657.114" + cell $and $and$ls180.v:3657$182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$ls180.v:3657$182_Y + end + attribute \src "ls180.v:3686.66-3686.246" + cell $and $and$ls180.v:3686$188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$ls180.v:3686$187_Y + connect \Y $and$ls180.v:3686$188_Y + end + attribute \src "ls180.v:3687.64-3687.187" + cell $and $and$ls180.v:3687$189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$ls180.v:3687$189_Y + end + attribute \src "ls180.v:3711.9-3711.86" + cell $and $and$ls180.v:3711$195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3711$195_Y + end + attribute \src "ls180.v:3723.9-3723.86" + cell $and $and$ls180.v:3723$196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3723$196_Y + end + attribute \src "ls180.v:3773.13-3773.87" + cell $and $and$ls180.v:3773$198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_ready + connect \B \main_sdram_bankmachine3_auto_precharge + connect \Y $and$ls180.v:3773$198_Y + end + attribute \src "ls180.v:3788.37-3788.102" + cell $and $and$ls180.v:3788$199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3788$199_Y + end + attribute \src "ls180.v:3788.108-3788.188" + cell $and $and$ls180.v:3788$201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3788$200_Y + connect \Y $and$ls180.v:3788$201_Y + end + attribute \src "ls180.v:3788.107-3788.231" + cell $and $and$ls180.v:3788$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3788$201_Y + connect \B $not$ls180.v:3788$202_Y + connect \Y $and$ls180.v:3788$203_Y + end + attribute \src "ls180.v:3788.36-3788.232" + cell $and $and$ls180.v:3788$204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3788$199_Y + connect \B $and$ls180.v:3788$203_Y + connect \Y $and$ls180.v:3788$204_Y + end + attribute \src "ls180.v:3789.37-3789.102" + cell $and $and$ls180.v:3789$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3789$205_Y + end + attribute \src "ls180.v:3789.108-3789.188" + cell $and $and$ls180.v:3789$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3789$206_Y + connect \Y $and$ls180.v:3789$207_Y + end + attribute \src "ls180.v:3789.107-3789.231" + cell $and $and$ls180.v:3789$209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3789$207_Y + connect \B $not$ls180.v:3789$208_Y + connect \Y $and$ls180.v:3789$209_Y + end + attribute \src "ls180.v:3789.36-3789.232" + cell $and $and$ls180.v:3789$210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3789$205_Y + connect \B $and$ls180.v:3789$209_Y + connect \Y $and$ls180.v:3789$210_Y + end + attribute \src "ls180.v:3790.34-3790.85" + cell $and $and$ls180.v:3790$211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_trrdcon_ready + connect \B \main_sdram_tfawcon_ready + connect \Y $and$ls180.v:3790$211_Y + end + attribute \src "ls180.v:3791.37-3791.102" + cell $and $and$ls180.v:3791$212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3791$212_Y + end + attribute \src "ls180.v:3791.36-3791.194" + cell $and $and$ls180.v:3791$214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3791$212_Y + connect \B $or$ls180.v:3791$213_Y + connect \Y $and$ls180.v:3791$214_Y + end + attribute \src "ls180.v:3793.37-3793.102" + cell $and $and$ls180.v:3793$215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3793$215_Y + end + attribute \src "ls180.v:3793.36-3793.148" + cell $and $and$ls180.v:3793$216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3793$215_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:3793$216_Y + end + attribute \src "ls180.v:3794.40-3794.119" + cell $and $and$ls180.v:3794$217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$ls180.v:3794$217_Y + end + attribute \src "ls180.v:3794.124-3794.203" + cell $and $and$ls180.v:3794$218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$ls180.v:3794$218_Y + end + attribute \src "ls180.v:3794.209-3794.288" + cell $and $and$ls180.v:3794$220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$ls180.v:3794$220_Y + end + attribute \src "ls180.v:3794.294-3794.373" + cell $and $and$ls180.v:3794$222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$ls180.v:3794$222_Y + end + attribute \src "ls180.v:3795.41-3795.121" + cell $and $and$ls180.v:3795$224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3795$224_Y + end + attribute \src "ls180.v:3795.126-3795.206" + cell $and $and$ls180.v:3795$225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3795$225_Y + end + attribute \src "ls180.v:3795.212-3795.292" + cell $and $and$ls180.v:3795$227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3795$227_Y + end + attribute \src "ls180.v:3795.298-3795.378" + cell $and $and$ls180.v:3795$229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3795$229_Y + end + attribute \src "ls180.v:3802.38-3802.111" + cell $and $and$ls180.v:3802$233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_gnt + connect \B \main_sdram_bankmachine1_refresh_gnt + connect \Y $and$ls180.v:3802$233_Y + end + attribute \src "ls180.v:3802.37-3802.150" + cell $and $and$ls180.v:3802$234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3802$233_Y + connect \B \main_sdram_bankmachine2_refresh_gnt + connect \Y $and$ls180.v:3802$234_Y + end + attribute \src "ls180.v:3802.36-3802.189" + cell $and $and$ls180.v:3802$235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3802$234_Y + connect \B \main_sdram_bankmachine3_refresh_gnt + connect \Y $and$ls180.v:3802$235_Y + end + attribute \src "ls180.v:3808.77-3808.153" + cell $and $and$ls180.v:3808$238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3808$238_Y + end + attribute \src "ls180.v:3808.162-3808.246" + cell $and $and$ls180.v:3808$240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3808$239_Y + connect \Y $and$ls180.v:3808$240_Y + end + attribute \src "ls180.v:3808.161-3808.291" + cell $and $and$ls180.v:3808$242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3808$240_Y + connect \B $not$ls180.v:3808$241_Y + connect \Y $and$ls180.v:3808$242_Y + end + attribute \src "ls180.v:3808.76-3808.333" + cell $and $and$ls180.v:3808$245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3808$238_Y + connect \B $or$ls180.v:3808$244_Y + connect \Y $and$ls180.v:3808$245_Y + end + attribute \src "ls180.v:3808.338-3808.505" + cell $and $and$ls180.v:3808$248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3808$246_Y + connect \B $eq$ls180.v:3808$247_Y + connect \Y $and$ls180.v:3808$248_Y + end + attribute \src "ls180.v:3808.38-3808.507" + cell $and $and$ls180.v:3808$250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3808$249_Y + connect \Y $and$ls180.v:3808$250_Y + end + attribute \src "ls180.v:3809.77-3809.153" + cell $and $and$ls180.v:3809$251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3809$251_Y + end + attribute \src "ls180.v:3809.162-3809.246" + cell $and $and$ls180.v:3809$253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3809$252_Y + connect \Y $and$ls180.v:3809$253_Y + end + attribute \src "ls180.v:3809.161-3809.291" + cell $and $and$ls180.v:3809$255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3809$253_Y + connect \B $not$ls180.v:3809$254_Y + connect \Y $and$ls180.v:3809$255_Y + end + attribute \src "ls180.v:3809.76-3809.333" + cell $and $and$ls180.v:3809$258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3809$251_Y + connect \B $or$ls180.v:3809$257_Y + connect \Y $and$ls180.v:3809$258_Y + end + attribute \src "ls180.v:3809.338-3809.505" + cell $and $and$ls180.v:3809$261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3809$259_Y + connect \B $eq$ls180.v:3809$260_Y + connect \Y $and$ls180.v:3809$261_Y + end + attribute \src "ls180.v:3809.38-3809.507" + cell $and $and$ls180.v:3809$263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3809$262_Y + connect \Y $and$ls180.v:3809$263_Y + end + attribute \src "ls180.v:3810.77-3810.153" + cell $and $and$ls180.v:3810$264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3810$264_Y + end + attribute \src "ls180.v:3810.162-3810.246" + cell $and $and$ls180.v:3810$266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3810$265_Y + connect \Y $and$ls180.v:3810$266_Y + end + attribute \src "ls180.v:3810.161-3810.291" + cell $and $and$ls180.v:3810$268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3810$266_Y + connect \B $not$ls180.v:3810$267_Y + connect \Y $and$ls180.v:3810$268_Y + end + attribute \src "ls180.v:3810.76-3810.333" + cell $and $and$ls180.v:3810$271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3810$264_Y + connect \B $or$ls180.v:3810$270_Y + connect \Y $and$ls180.v:3810$271_Y + end + attribute \src "ls180.v:3810.338-3810.505" + cell $and $and$ls180.v:3810$274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3810$272_Y + connect \B $eq$ls180.v:3810$273_Y + connect \Y $and$ls180.v:3810$274_Y + end + attribute \src "ls180.v:3810.38-3810.507" + cell $and $and$ls180.v:3810$276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3810$275_Y + connect \Y $and$ls180.v:3810$276_Y + end + attribute \src "ls180.v:3811.77-3811.153" + cell $and $and$ls180.v:3811$277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3811$277_Y + end + attribute \src "ls180.v:3811.162-3811.246" + cell $and $and$ls180.v:3811$279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3811$278_Y + connect \Y $and$ls180.v:3811$279_Y + end + attribute \src "ls180.v:3811.161-3811.291" + cell $and $and$ls180.v:3811$281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3811$279_Y + connect \B $not$ls180.v:3811$280_Y + connect \Y $and$ls180.v:3811$281_Y + end + attribute \src "ls180.v:3811.76-3811.333" + cell $and $and$ls180.v:3811$284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3811$277_Y + connect \B $or$ls180.v:3811$283_Y + connect \Y $and$ls180.v:3811$284_Y + end + attribute \src "ls180.v:3811.338-3811.505" + cell $and $and$ls180.v:3811$287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3811$285_Y + connect \B $eq$ls180.v:3811$286_Y + connect \Y $and$ls180.v:3811$287_Y + end + attribute \src "ls180.v:3811.38-3811.507" + cell $and $and$ls180.v:3811$289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3811$288_Y + connect \Y $and$ls180.v:3811$289_Y + end + attribute \src "ls180.v:3841.77-3841.153" + cell $and $and$ls180.v:3841$296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3841$296_Y + end + attribute \src "ls180.v:3841.162-3841.246" + cell $and $and$ls180.v:3841$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3841$297_Y + connect \Y $and$ls180.v:3841$298_Y + end + attribute \src "ls180.v:3841.161-3841.291" + cell $and $and$ls180.v:3841$300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3841$298_Y + connect \B $not$ls180.v:3841$299_Y + connect \Y $and$ls180.v:3841$300_Y + end + attribute \src "ls180.v:3841.76-3841.333" + cell $and $and$ls180.v:3841$303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3841$296_Y + connect \B $or$ls180.v:3841$302_Y + connect \Y $and$ls180.v:3841$303_Y + end + attribute \src "ls180.v:3841.338-3841.505" + cell $and $and$ls180.v:3841$306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3841$304_Y + connect \B $eq$ls180.v:3841$305_Y + connect \Y $and$ls180.v:3841$306_Y + end + attribute \src "ls180.v:3841.38-3841.507" + cell $and $and$ls180.v:3841$308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3841$307_Y + connect \Y $and$ls180.v:3841$308_Y + end + attribute \src "ls180.v:3842.77-3842.153" + cell $and $and$ls180.v:3842$309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3842$309_Y + end + attribute \src "ls180.v:3842.162-3842.246" + cell $and $and$ls180.v:3842$311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3842$310_Y + connect \Y $and$ls180.v:3842$311_Y + end + attribute \src "ls180.v:3842.161-3842.291" + cell $and $and$ls180.v:3842$313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3842$311_Y + connect \B $not$ls180.v:3842$312_Y + connect \Y $and$ls180.v:3842$313_Y + end + attribute \src "ls180.v:3842.76-3842.333" + cell $and $and$ls180.v:3842$316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3842$309_Y + connect \B $or$ls180.v:3842$315_Y + connect \Y $and$ls180.v:3842$316_Y + end + attribute \src "ls180.v:3842.338-3842.505" + cell $and $and$ls180.v:3842$319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3842$317_Y + connect \B $eq$ls180.v:3842$318_Y + connect \Y $and$ls180.v:3842$319_Y + end + attribute \src "ls180.v:3842.38-3842.507" + cell $and $and$ls180.v:3842$321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3842$320_Y + connect \Y $and$ls180.v:3842$321_Y + end + attribute \src "ls180.v:3843.77-3843.153" + cell $and $and$ls180.v:3843$322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3843$322_Y + end + attribute \src "ls180.v:3843.162-3843.246" + cell $and $and$ls180.v:3843$324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3843$323_Y + connect \Y $and$ls180.v:3843$324_Y + end + attribute \src "ls180.v:3843.161-3843.291" + cell $and $and$ls180.v:3843$326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3843$324_Y + connect \B $not$ls180.v:3843$325_Y + connect \Y $and$ls180.v:3843$326_Y + end + attribute \src "ls180.v:3843.76-3843.333" + cell $and $and$ls180.v:3843$329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3843$322_Y + connect \B $or$ls180.v:3843$328_Y + connect \Y $and$ls180.v:3843$329_Y + end + attribute \src "ls180.v:3843.338-3843.505" + cell $and $and$ls180.v:3843$332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3843$330_Y + connect \B $eq$ls180.v:3843$331_Y + connect \Y $and$ls180.v:3843$332_Y + end + attribute \src "ls180.v:3843.38-3843.507" + cell $and $and$ls180.v:3843$334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3843$333_Y + connect \Y $and$ls180.v:3843$334_Y + end + attribute \src "ls180.v:3844.77-3844.153" + cell $and $and$ls180.v:3844$335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3844$335_Y + end + attribute \src "ls180.v:3844.162-3844.246" + cell $and $and$ls180.v:3844$337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3844$336_Y + connect \Y $and$ls180.v:3844$337_Y + end + attribute \src "ls180.v:3844.161-3844.291" + cell $and $and$ls180.v:3844$339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3844$337_Y + connect \B $not$ls180.v:3844$338_Y + connect \Y $and$ls180.v:3844$339_Y + end + attribute \src "ls180.v:3844.76-3844.333" + cell $and $and$ls180.v:3844$342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3844$335_Y + connect \B $or$ls180.v:3844$341_Y + connect \Y $and$ls180.v:3844$342_Y + end + attribute \src "ls180.v:3844.338-3844.505" + cell $and $and$ls180.v:3844$345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3844$343_Y + connect \B $eq$ls180.v:3844$344_Y + connect \Y $and$ls180.v:3844$345_Y + end + attribute \src "ls180.v:3844.38-3844.507" + cell $and $and$ls180.v:3844$347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3844$346_Y + connect \Y $and$ls180.v:3844$347_Y + end + attribute \src "ls180.v:3873.8-3873.73" + cell $and $and$ls180.v:3873$352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3873$352_Y + end + attribute \src "ls180.v:3873.7-3873.114" + cell $and $and$ls180.v:3873$354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3873$352_Y + connect \B $eq$ls180.v:3873$353_Y + connect \Y $and$ls180.v:3873$354_Y + end + attribute \src "ls180.v:3876.8-3876.73" + cell $and $and$ls180.v:3876$355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3876$355_Y + end + attribute \src "ls180.v:3876.7-3876.114" + cell $and $and$ls180.v:3876$357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3876$355_Y + connect \B $eq$ls180.v:3876$356_Y + connect \Y $and$ls180.v:3876$357_Y + end + attribute \src "ls180.v:3882.8-3882.73" + cell $and $and$ls180.v:3882$359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3882$359_Y + end + attribute \src "ls180.v:3882.7-3882.114" + cell $and $and$ls180.v:3882$361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3882$359_Y + connect \B $eq$ls180.v:3882$360_Y + connect \Y $and$ls180.v:3882$361_Y + end + attribute \src "ls180.v:3885.8-3885.73" + cell $and $and$ls180.v:3885$362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3885$362_Y + end + attribute \src "ls180.v:3885.7-3885.114" + cell $and $and$ls180.v:3885$364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3885$362_Y + connect \B $eq$ls180.v:3885$363_Y + connect \Y $and$ls180.v:3885$364_Y + end + attribute \src "ls180.v:3891.8-3891.73" + cell $and $and$ls180.v:3891$366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3891$366_Y + end + attribute \src "ls180.v:3891.7-3891.114" + cell $and $and$ls180.v:3891$368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3891$366_Y + connect \B $eq$ls180.v:3891$367_Y + connect \Y $and$ls180.v:3891$368_Y + end + attribute \src "ls180.v:3894.8-3894.73" + cell $and $and$ls180.v:3894$369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3894$369_Y + end + attribute \src "ls180.v:3894.7-3894.114" + cell $and $and$ls180.v:3894$371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3894$369_Y + connect \B $eq$ls180.v:3894$370_Y + connect \Y $and$ls180.v:3894$371_Y + end + attribute \src "ls180.v:3900.8-3900.73" + cell $and $and$ls180.v:3900$373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3900$373_Y + end + attribute \src "ls180.v:3900.7-3900.114" + cell $and $and$ls180.v:3900$375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3900$373_Y + connect \B $eq$ls180.v:3900$374_Y + connect \Y $and$ls180.v:3900$375_Y + end + attribute \src "ls180.v:3903.8-3903.73" + cell $and $and$ls180.v:3903$376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3903$376_Y + end + attribute \src "ls180.v:3903.7-3903.114" + cell $and $and$ls180.v:3903$378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3903$376_Y + connect \B $eq$ls180.v:3903$377_Y + connect \Y $and$ls180.v:3903$378_Y + end + attribute \src "ls180.v:3928.71-3928.151" + cell $and $and$ls180.v:3928$383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3928$382_Y + connect \Y $and$ls180.v:3928$383_Y + end + attribute \src "ls180.v:3928.70-3928.194" + cell $and $and$ls180.v:3928$385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3928$383_Y + connect \B $not$ls180.v:3928$384_Y + connect \Y $and$ls180.v:3928$385_Y + end + attribute \src "ls180.v:3928.41-3928.222" + cell $and $and$ls180.v:3928$388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:3928$387_Y + connect \Y $and$ls180.v:3928$388_Y + end + attribute \src "ls180.v:3966.71-3966.151" + cell $and $and$ls180.v:3966$392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3966$391_Y + connect \Y $and$ls180.v:3966$392_Y + end + attribute \src "ls180.v:3966.70-3966.194" + cell $and $and$ls180.v:3966$394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3966$392_Y + connect \B $not$ls180.v:3966$393_Y + connect \Y $and$ls180.v:3966$394_Y + end + attribute \src "ls180.v:3966.41-3966.222" + cell $and $and$ls180.v:3966$397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:3966$396_Y + connect \Y $and$ls180.v:3966$397_Y + end + attribute \src "ls180.v:3984.110-3984.179" + cell $and $and$ls180.v:3984$402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3984$401_Y + connect \Y $and$ls180.v:3984$402_Y + end + attribute \src "ls180.v:3984.185-3984.254" + cell $and $and$ls180.v:3984$405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3984$404_Y + connect \Y $and$ls180.v:3984$405_Y + end + attribute \src "ls180.v:3984.260-3984.329" + cell $and $and$ls180.v:3984$408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3984$407_Y + connect \Y $and$ls180.v:3984$408_Y + end + attribute \src "ls180.v:3984.41-3984.332" + cell $and $and$ls180.v:3984$411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3984$400_Y + connect \B $not$ls180.v:3984$410_Y + connect \Y $and$ls180.v:3984$411_Y + end + attribute \src "ls180.v:3984.40-3984.355" + cell $and $and$ls180.v:3984$412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3984$411_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3984$412_Y + end + attribute \src "ls180.v:3985.34-3985.106" + cell $and $and$ls180.v:3985$415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3985$413_Y + connect \B $not$ls180.v:3985$414_Y + connect \Y $and$ls180.v:3985$415_Y + end + attribute \src "ls180.v:3989.110-3989.179" + cell $and $and$ls180.v:3989$418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3989$417_Y + connect \Y $and$ls180.v:3989$418_Y + end + attribute \src "ls180.v:3989.185-3989.254" + cell $and $and$ls180.v:3989$421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3989$420_Y + connect \Y $and$ls180.v:3989$421_Y + end + attribute \src "ls180.v:3989.260-3989.329" + cell $and $and$ls180.v:3989$424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3989$423_Y + connect \Y $and$ls180.v:3989$424_Y + end + attribute \src "ls180.v:3989.41-3989.332" + cell $and $and$ls180.v:3989$427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3989$416_Y + connect \B $not$ls180.v:3989$426_Y + connect \Y $and$ls180.v:3989$427_Y + end + attribute \src "ls180.v:3989.40-3989.355" + cell $and $and$ls180.v:3989$428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3989$427_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3989$428_Y + end + attribute \src "ls180.v:3990.34-3990.106" + cell $and $and$ls180.v:3990$431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3990$429_Y + connect \B $not$ls180.v:3990$430_Y + connect \Y $and$ls180.v:3990$431_Y + end + attribute \src "ls180.v:3994.110-3994.179" + cell $and $and$ls180.v:3994$434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3994$433_Y + connect \Y $and$ls180.v:3994$434_Y + end + attribute \src "ls180.v:3994.185-3994.254" + cell $and $and$ls180.v:3994$437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3994$436_Y + connect \Y $and$ls180.v:3994$437_Y + end + attribute \src "ls180.v:3994.260-3994.329" + cell $and $and$ls180.v:3994$440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3994$439_Y + connect \Y $and$ls180.v:3994$440_Y + end + attribute \src "ls180.v:3994.41-3994.332" + cell $and $and$ls180.v:3994$443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3994$432_Y + connect \B $not$ls180.v:3994$442_Y + connect \Y $and$ls180.v:3994$443_Y + end + attribute \src "ls180.v:3994.40-3994.355" + cell $and $and$ls180.v:3994$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3994$443_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3994$444_Y + end + attribute \src "ls180.v:3995.34-3995.106" + cell $and $and$ls180.v:3995$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3995$445_Y + connect \B $not$ls180.v:3995$446_Y + connect \Y $and$ls180.v:3995$447_Y + end + attribute \src "ls180.v:3999.110-3999.179" + cell $and $and$ls180.v:3999$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3999$449_Y + connect \Y $and$ls180.v:3999$450_Y + end + attribute \src "ls180.v:3999.185-3999.254" + cell $and $and$ls180.v:3999$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3999$452_Y + connect \Y $and$ls180.v:3999$453_Y + end + attribute \src "ls180.v:3999.260-3999.329" + cell $and $and$ls180.v:3999$456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3999$455_Y + connect \Y $and$ls180.v:3999$456_Y + end + attribute \src "ls180.v:3999.41-3999.332" + cell $and $and$ls180.v:3999$459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3999$448_Y + connect \B $not$ls180.v:3999$458_Y + connect \Y $and$ls180.v:3999$459_Y + end + attribute \src "ls180.v:3999.40-3999.355" + cell $and $and$ls180.v:3999$460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3999$459_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3999$460_Y + end + attribute \src "ls180.v:4000.34-4000.106" + cell $and $and$ls180.v:4000$463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4000$461_Y + connect \B $not$ls180.v:4000$462_Y + connect \Y $and$ls180.v:4000$463_Y + end + attribute \src "ls180.v:4004.151-4004.220" + cell $and $and$ls180.v:4004$467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4004$466_Y + connect \Y $and$ls180.v:4004$467_Y + end + attribute \src "ls180.v:4004.226-4004.295" + cell $and $and$ls180.v:4004$470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4004$469_Y + connect \Y $and$ls180.v:4004$470_Y + end + attribute \src "ls180.v:4004.301-4004.370" + cell $and $and$ls180.v:4004$473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4004$472_Y + connect \Y $and$ls180.v:4004$473_Y + end + attribute \src "ls180.v:4004.82-4004.373" + cell $and $and$ls180.v:4004$476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4004$465_Y + connect \B $not$ls180.v:4004$475_Y + connect \Y $and$ls180.v:4004$476_Y + end + attribute \src "ls180.v:4004.43-4004.374" + cell $and $and$ls180.v:4004$477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4004$464_Y + connect \B $and$ls180.v:4004$476_Y + connect \Y $and$ls180.v:4004$477_Y + end + attribute \src "ls180.v:4004.42-4004.410" + cell $and $and$ls180.v:4004$478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4004$477_Y + connect \B \main_sdram_interface_bank0_ready + connect \Y $and$ls180.v:4004$478_Y + end + attribute \src "ls180.v:4004.525-4004.594" + cell $and $and$ls180.v:4004$483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4004$482_Y + connect \Y $and$ls180.v:4004$483_Y + end + attribute \src "ls180.v:4004.600-4004.669" + cell $and $and$ls180.v:4004$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4004$485_Y + connect \Y $and$ls180.v:4004$486_Y + end + attribute \src "ls180.v:4004.675-4004.744" + cell $and $and$ls180.v:4004$489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4004$488_Y + connect \Y $and$ls180.v:4004$489_Y + end + attribute \src "ls180.v:4004.456-4004.747" + cell $and $and$ls180.v:4004$492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4004$481_Y + connect \B $not$ls180.v:4004$491_Y + connect \Y $and$ls180.v:4004$492_Y + end + attribute \src "ls180.v:4004.417-4004.748" + cell $and $and$ls180.v:4004$493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4004$480_Y + connect \B $and$ls180.v:4004$492_Y + connect \Y $and$ls180.v:4004$493_Y + end + attribute \src "ls180.v:4004.416-4004.784" + cell $and $and$ls180.v:4004$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4004$493_Y + connect \B \main_sdram_interface_bank1_ready + connect \Y $and$ls180.v:4004$494_Y + end + attribute \src "ls180.v:4004.899-4004.968" + cell $and $and$ls180.v:4004$499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4004$498_Y + connect \Y $and$ls180.v:4004$499_Y + end + attribute \src "ls180.v:4004.974-4004.1043" + cell $and $and$ls180.v:4004$502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4004$501_Y + connect \Y $and$ls180.v:4004$502_Y + end + attribute \src "ls180.v:4004.1049-4004.1118" + cell $and $and$ls180.v:4004$505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4004$504_Y + connect \Y $and$ls180.v:4004$505_Y + end + attribute \src "ls180.v:4004.830-4004.1121" + cell $and $and$ls180.v:4004$508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4004$497_Y + connect \B $not$ls180.v:4004$507_Y + connect \Y $and$ls180.v:4004$508_Y + end + attribute \src "ls180.v:4004.791-4004.1122" + cell $and $and$ls180.v:4004$509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4004$496_Y + connect \B $and$ls180.v:4004$508_Y + connect \Y $and$ls180.v:4004$509_Y + end + attribute \src "ls180.v:4004.790-4004.1158" + cell $and $and$ls180.v:4004$510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4004$509_Y + connect \B \main_sdram_interface_bank2_ready + connect \Y $and$ls180.v:4004$510_Y + end + attribute \src "ls180.v:4004.1273-4004.1342" + cell $and $and$ls180.v:4004$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4004$514_Y + connect \Y $and$ls180.v:4004$515_Y + end + attribute \src "ls180.v:4004.1348-4004.1417" + cell $and $and$ls180.v:4004$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4004$517_Y + connect \Y $and$ls180.v:4004$518_Y + end + attribute \src "ls180.v:4004.1423-4004.1492" + cell $and $and$ls180.v:4004$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4004$520_Y + connect \Y $and$ls180.v:4004$521_Y + end + attribute \src "ls180.v:4004.1204-4004.1495" + cell $and $and$ls180.v:4004$524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4004$513_Y + connect \B $not$ls180.v:4004$523_Y + connect \Y $and$ls180.v:4004$524_Y + end + attribute \src "ls180.v:4004.1165-4004.1496" + cell $and $and$ls180.v:4004$525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4004$512_Y + connect \B $and$ls180.v:4004$524_Y + connect \Y $and$ls180.v:4004$525_Y + end + attribute \src "ls180.v:4004.1164-4004.1532" + cell $and $and$ls180.v:4004$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4004$525_Y + connect \B \main_sdram_interface_bank3_ready + connect \Y $and$ls180.v:4004$526_Y + end + attribute \src "ls180.v:4062.9-4062.46" + cell $and $and$ls180.v:4062$532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4062$532_Y + end + attribute \src "ls180.v:4080.9-4080.46" + cell $and $and$ls180.v:4080$539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4080$539_Y + end + attribute \src "ls180.v:4093.32-4093.75" + cell $and $and$ls180.v:4093$543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \B \main_litedram_wb_stb + connect \Y $and$ls180.v:4093$543_Y + end + attribute \src "ls180.v:4093.31-4093.99" + cell $and $and$ls180.v:4093$545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4093$543_Y + connect \B $not$ls180.v:4093$544_Y + connect \Y $and$ls180.v:4093$545_Y + end + attribute \src "ls180.v:4094.34-4094.102" + cell $and $and$ls180.v:4094$547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4094$546_Y + connect \B \main_port_cmd_payload_we + connect \Y $and$ls180.v:4094$547_Y + end + attribute \src "ls180.v:4094.33-4094.128" + cell $and $and$ls180.v:4094$549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4094$547_Y + connect \B $not$ls180.v:4094$548_Y + connect \Y $and$ls180.v:4094$549_Y + end + attribute \src "ls180.v:4095.33-4095.104" + cell $and $and$ls180.v:4095$552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4095$550_Y + connect \B $not$ls180.v:4095$551_Y + connect \Y $and$ls180.v:4095$552_Y + end + attribute \src "ls180.v:4096.49-4096.85" + cell $and $and$ls180.v:4096$553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \B \main_ack_wdata + connect \Y $and$ls180.v:4096$553_Y + end + attribute \src "ls180.v:4096.90-4096.129" + cell $and $and$ls180.v:4096$555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4096$554_Y + connect \B \main_ack_rdata + connect \Y $and$ls180.v:4096$555_Y + end + attribute \src "ls180.v:4096.32-4096.131" + cell $and $and$ls180.v:4096$557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ack_cmd + connect \B $or$ls180.v:4096$556_Y + connect \Y $and$ls180.v:4096$557_Y + end + attribute \src "ls180.v:4097.25-4097.66" + cell $and $and$ls180.v:4097$558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:4097$558_Y + end + attribute \src "ls180.v:4098.27-4098.72" + cell $and $and$ls180.v:4098$560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:4098$560_Y + end + attribute \src "ls180.v:4099.26-4099.71" + cell $and $and$ls180.v:4099$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_rdata_valid + connect \B \main_port_rdata_ready + connect \Y $and$ls180.v:4099$562_Y + end + attribute \src "ls180.v:4128.64-4128.88" + cell $and $and$ls180.v:4128$568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \main_uart_rxtx_we + connect \Y $and$ls180.v:4128$568_Y + end + attribute \src "ls180.v:4132.7-4132.78" + cell $and $and$ls180.v:4132$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [0] + connect \Y $and$ls180.v:4132$572_Y + end + attribute \src "ls180.v:4143.7-4143.78" + cell $and $and$ls180.v:4143$575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [1] + connect \Y $and$ls180.v:4143$575_Y + end + attribute \src "ls180.v:4152.26-4152.97" + cell $and $and$ls180.v:4152$577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [0] + connect \B \main_uart_eventmanager_storage [0] + connect \Y $and$ls180.v:4152$577_Y + end + attribute \src "ls180.v:4152.102-4152.173" + cell $and $and$ls180.v:4152$578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [1] + connect \B \main_uart_eventmanager_storage [1] + connect \Y $and$ls180.v:4152$578_Y + end + attribute \src "ls180.v:4167.41-4167.133" + cell $and $and$ls180.v:4167$582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B $or$ls180.v:4167$581_Y + connect \Y $and$ls180.v:4167$582_Y + end + attribute \src "ls180.v:4178.39-4178.136" + cell $and $and$ls180.v:4178$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B $or$ls180.v:4178$586_Y + connect \Y $and$ls180.v:4178$587_Y + end + attribute \src "ls180.v:4179.37-4179.104" + cell $and $and$ls180.v:4179$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B \main_uart_tx_fifo_syncfifo_re + connect \Y $and$ls180.v:4179$588_Y + end + attribute \src "ls180.v:4197.41-4197.133" + cell $and $and$ls180.v:4197$593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B $or$ls180.v:4197$592_Y + connect \Y $and$ls180.v:4197$593_Y + end + attribute \src "ls180.v:4208.39-4208.136" + cell $and $and$ls180.v:4208$598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B $or$ls180.v:4208$597_Y + connect \Y $and$ls180.v:4208$598_Y + end + attribute \src "ls180.v:4209.37-4209.104" + cell $and $and$ls180.v:4209$599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B \main_uart_rx_fifo_syncfifo_re + connect \Y $and$ls180.v:4209$599_Y + end + attribute \src "ls180.v:4397.33-4397.86" + cell $and $and$ls180.v:4397$641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk1 + connect \B $not$ls180.v:4397$640_Y + connect \Y $and$ls180.v:4397$641_Y + end + attribute \src "ls180.v:4501.9-4501.68" + cell $and $and$ls180.v:4501$650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_pads_out_ready + connect \Y $and$ls180.v:4501$650_Y + end + attribute \src "ls180.v:4521.53-4521.145" + cell $and $and$ls180.v:4521$653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_valid + connect \B $or$ls180.v:4521$652_Y + connect \Y $and$ls180.v:4521$653_Y + end + attribute \src "ls180.v:4540.52-4540.137" + cell $and $and$ls180.v:4540$656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:4540$656_Y + end + attribute \src "ls180.v:4581.9-4581.68" + cell $and $and$ls180.v:4581$664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4581$664_Y + end + attribute \src "ls180.v:4619.9-4619.68" + cell $and $and$ls180.v:4619$670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4619$670_Y + end + attribute \src "ls180.v:4628.10-4628.69" + cell $and $and$ls180.v:4628$671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_sink_valid + connect \B \main_sdphy_cmdr_pads_out_ready + connect \Y $and$ls180.v:4628$671_Y + end + attribute \src "ls180.v:4628.9-4628.93" + cell $and $and$ls180.v:4628$672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4628$671_Y + connect \B \main_sdphy_cmdw_done + connect \Y $and$ls180.v:4628$672_Y + end + attribute \src "ls180.v:4648.54-4648.117" + cell $and $and$ls180.v:4648$674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_valid + connect \B \main_sdphy_dataw_crcr_run + connect \Y $and$ls180.v:4648$674_Y + end + attribute \src "ls180.v:4667.53-4667.140" + cell $and $and$ls180.v:4667$677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:4667$677_Y + end + attribute \src "ls180.v:4764.9-4764.70" + cell $and $and$ls180.v:4764$687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_pads_out_ready + connect \Y $and$ls180.v:4764$687_Y + end + attribute \src "ls180.v:4782.55-4782.120" + cell $and $and$ls180.v:4782$689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_valid + connect \B \main_sdphy_datar_datar_run + connect \Y $and$ls180.v:4782$689_Y + end + attribute \src "ls180.v:4801.54-4801.143" + cell $and $and$ls180.v:4801$692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:4801$692_Y + end + attribute \src "ls180.v:4883.9-4883.70" + cell $and $and$ls180.v:4883$707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_valid + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:4883$707_Y + end + attribute \src "ls180.v:4890.9-4890.70" + cell $and $and$ls180.v:4890$708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_sink_valid + connect \B \main_sdphy_datar_pads_out_ready + connect \Y $and$ls180.v:4890$708_Y + end + attribute \src "ls180.v:4971.48-4971.124" + cell $and $and$ls180.v:4971$831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4971$831_Y + end + attribute \src "ls180.v:4971.47-4971.165" + cell $and $and$ls180.v:4971$832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4971$831_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4971$832_Y + end + attribute \src "ls180.v:4972.50-4972.127" + cell $and $and$ls180.v:4972$833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4972$833_Y + end + attribute \src "ls180.v:4974.48-4974.124" + cell $and $and$ls180.v:4974$834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4974$834_Y + end + attribute \src "ls180.v:4974.47-4974.165" + cell $and $and$ls180.v:4974$835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4974$834_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4974$835_Y + end + attribute \src "ls180.v:4975.50-4975.127" + cell $and $and$ls180.v:4975$836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4975$836_Y + end + attribute \src "ls180.v:4977.48-4977.124" + cell $and $and$ls180.v:4977$837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4977$837_Y + end + attribute \src "ls180.v:4977.47-4977.165" + cell $and $and$ls180.v:4977$838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4977$837_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4977$838_Y + end + attribute \src "ls180.v:4978.50-4978.127" + cell $and $and$ls180.v:4978$839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4978$839_Y + end + attribute \src "ls180.v:4980.48-4980.124" + cell $and $and$ls180.v:4980$840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4980$840_Y + end + attribute \src "ls180.v:4980.47-4980.165" + cell $and $and$ls180.v:4980$841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4980$840_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4980$841_Y + end + attribute \src "ls180.v:4981.50-4981.127" + cell $and $and$ls180.v:4981$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4981$842_Y + end + attribute \src "ls180.v:5094.10-5094.86" + cell $and $and$ls180.v:5094$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_last + connect \Y $and$ls180.v:5094$891_Y + end + attribute \src "ls180.v:5094.9-5094.127" + cell $and $and$ls180.v:5094$892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5094$891_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5094$892_Y + end + attribute \src "ls180.v:5104.9-5104.152" + cell $and $and$ls180.v:5104$896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:5104$894_Y + connect \B $eq$ls180.v:5104$895_Y + connect \Y $and$ls180.v:5104$896_Y + end + attribute \src "ls180.v:5104.8-5104.226" + cell $and $and$ls180.v:5104$898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5104$896_Y + connect \B $eq$ls180.v:5104$897_Y + connect \Y $and$ls180.v:5104$898_Y + end + attribute \src "ls180.v:5104.7-5104.300" + cell $and $and$ls180.v:5104$900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5104$898_Y + connect \B $eq$ls180.v:5104$899_Y + connect \Y $and$ls180.v:5104$900_Y + end + attribute \src "ls180.v:5109.49-5109.124" + cell $and $and$ls180.v:5109$901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5109$901_Y + end + attribute \src "ls180.v:5119.49-5119.124" + cell $and $and$ls180.v:5119$904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5119$904_Y + end + attribute \src "ls180.v:5129.49-5129.124" + cell $and $and$ls180.v:5129$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5129$907_Y + end + attribute \src "ls180.v:5139.49-5139.124" + cell $and $and$ls180.v:5139$910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5139$910_Y + end + attribute \src "ls180.v:5151.7-5151.84" + cell $and $and$ls180.v:5151$915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B $gt$ls180.v:5151$914_Y + connect \Y $and$ls180.v:5151$915_Y + end + attribute \src "ls180.v:5269.9-5269.64" + cell $and $and$ls180.v:5269$964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_sink_ready + connect \Y $and$ls180.v:5269$964_Y + end + attribute \src "ls180.v:5321.10-5321.66" + cell $and $and$ls180.v:5321$973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_sink_last + connect \Y $and$ls180.v:5321$973_Y + end + attribute \src "ls180.v:5321.9-5321.97" + cell $and $and$ls180.v:5321$974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5321$973_Y + connect \B \main_sdphy_dataw_sink_ready + connect \Y $and$ls180.v:5321$974_Y + end + attribute \src "ls180.v:5347.11-5347.71" + cell $and $and$ls180.v:5347$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_last + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:5347$982_Y + end + attribute \src "ls180.v:5431.43-5431.152" + cell $and $and$ls180.v:5431$990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B $or$ls180.v:5431$989_Y + connect \Y $and$ls180.v:5431$990_Y + end + attribute \src "ls180.v:5432.41-5432.116" + cell $and $and$ls180.v:5432$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_readable + connect \B \main_sdblock2mem_fifo_syncfifo_re + connect \Y $and$ls180.v:5432$991_Y + end + attribute \src "ls180.v:5444.48-5444.125" + cell $and $and$ls180.v:5444$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:5444$996_Y + end + attribute \src "ls180.v:5471.9-5471.102" + cell $and $and$ls180.v:5471$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid + connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \Y $and$ls180.v:5471$1000_Y + end + attribute \src "ls180.v:5544.9-5544.58" + cell $and $and$ls180.v:5544$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_bus_stb + connect \B \main_interface1_bus_ack + connect \Y $and$ls180.v:5544$1006_Y + end + attribute \src "ls180.v:5597.51-5597.123" + cell $and $and$ls180.v:5597$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_first + connect \B \main_sdmem2block_converter_first + connect \Y $and$ls180.v:5597$1014_Y + end + attribute \src "ls180.v:5598.50-5598.120" + cell $and $and$ls180.v:5598$1015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_last + connect \B \main_sdmem2block_converter_last + connect \Y $and$ls180.v:5598$1015_Y + end + attribute \src "ls180.v:5599.49-5599.122" + cell $and $and$ls180.v:5599$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_last + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:5599$1016_Y + end + attribute \src "ls180.v:5639.43-5639.152" + cell $and $and$ls180.v:5639$1021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B $or$ls180.v:5639$1020_Y + connect \Y $and$ls180.v:5639$1021_Y + end + attribute \src "ls180.v:5640.41-5640.116" + cell $and $and$ls180.v:5640$1022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_readable + connect \B \main_sdmem2block_fifo_syncfifo_re + connect \Y $and$ls180.v:5640$1022_Y + end + attribute \src "ls180.v:5672.9-5672.76" + cell $and $and$ls180.v:5672$1026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_cyc + connect \B \builder_libresocsim_wishbone_stb + connect \Y $and$ls180.v:5672$1026_Y + end + attribute \src "ls180.v:5675.44-5675.120" + cell $and $and$ls180.v:5675$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_we + connect \B $ne$ls180.v:5675$1027_Y + connect \Y $and$ls180.v:5675$1028_Y + end + attribute \src "ls180.v:5695.63-5695.107" + cell $and $and$ls180.v:5695$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5695$1029_Y + connect \Y $and$ls180.v:5695$1030_Y + end + attribute \src "ls180.v:5696.63-5696.107" + cell $and $and$ls180.v:5696$1032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5696$1031_Y + connect \Y $and$ls180.v:5696$1032_Y + end + attribute \src "ls180.v:5697.63-5697.107" + cell $and $and$ls180.v:5697$1034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5697$1033_Y + connect \Y $and$ls180.v:5697$1034_Y + end + attribute \src "ls180.v:5698.35-5698.79" + cell $and $and$ls180.v:5698$1036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5698$1035_Y + connect \Y $and$ls180.v:5698$1036_Y + end + attribute \src "ls180.v:5699.35-5699.79" + cell $and $and$ls180.v:5699$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5699$1037_Y + connect \Y $and$ls180.v:5699$1038_Y + end + attribute \src "ls180.v:5700.63-5700.107" + cell $and $and$ls180.v:5700$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5700$1039_Y + connect \Y $and$ls180.v:5700$1040_Y + end + attribute \src "ls180.v:5701.63-5701.107" + cell $and $and$ls180.v:5701$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5701$1041_Y + connect \Y $and$ls180.v:5701$1042_Y + end + attribute \src "ls180.v:5702.63-5702.107" + cell $and $and$ls180.v:5702$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5702$1043_Y + connect \Y $and$ls180.v:5702$1044_Y + end + attribute \src "ls180.v:5703.35-5703.79" + cell $and $and$ls180.v:5703$1046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5703$1045_Y + connect \Y $and$ls180.v:5703$1046_Y + end + attribute \src "ls180.v:5704.35-5704.79" + cell $and $and$ls180.v:5704$1048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5704$1047_Y + connect \Y $and$ls180.v:5704$1048_Y + end + attribute \src "ls180.v:5749.40-5749.81" + cell $and $and$ls180.v:5749$1055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [0] + connect \Y $and$ls180.v:5749$1055_Y + end + attribute \src "ls180.v:5750.50-5750.91" + cell $and $and$ls180.v:5750$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [1] + connect \Y $and$ls180.v:5750$1056_Y + end + attribute \src "ls180.v:5751.50-5751.91" + cell $and $and$ls180.v:5751$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [2] + connect \Y $and$ls180.v:5751$1057_Y + end + attribute \src "ls180.v:5752.29-5752.70" + cell $and $and$ls180.v:5752$1058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [3] + connect \Y $and$ls180.v:5752$1058_Y + end + attribute \src "ls180.v:5753.44-5753.85" + cell $and $and$ls180.v:5753$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [4] + connect \Y $and$ls180.v:5753$1059_Y + end + attribute \src "ls180.v:5755.25-5755.64" + cell $and $and$ls180.v:5755$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_stb + connect \B \builder_shared_cyc + connect \Y $and$ls180.v:5755$1064_Y + end + attribute \src "ls180.v:5755.24-5755.89" + cell $and $and$ls180.v:5755$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5755$1064_Y + connect \B $not$ls180.v:5755$1065_Y + connect \Y $and$ls180.v:5755$1066_Y + end + attribute \src "ls180.v:5761.31-5761.92" + cell $and $and$ls180.v:5761$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + connect \B \main_libresocsim_ram_bus_dat_r + connect \Y $and$ls180.v:5761$1072_Y + end + attribute \src "ls180.v:5761.97-5761.168" + cell $and $and$ls180.v:5761$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + connect \B \main_libresocsim_libresoc_xics_icp_dat_r + connect \Y $and$ls180.v:5761$1073_Y + end + attribute \src "ls180.v:5761.174-5761.245" + cell $and $and$ls180.v:5761$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + connect \B \main_libresocsim_libresoc_xics_ics_dat_r + connect \Y $and$ls180.v:5761$1075_Y + end + attribute \src "ls180.v:5761.251-5761.301" + cell $and $and$ls180.v:5761$1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + connect \B \main_wb_sdram_dat_r + connect \Y $and$ls180.v:5761$1077_Y + end + attribute \src "ls180.v:5761.307-5761.372" + cell $and $and$ls180.v:5761$1079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \builder_libresocsim_wishbone_dat_r + connect \Y $and$ls180.v:5761$1079_Y + end + attribute \src "ls180.v:5771.39-5771.92" + cell $and $and$ls180.v:5771$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5771$1083_Y + end + attribute \src "ls180.v:5771.38-5771.142" + cell $and $and$ls180.v:5771$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5771$1083_Y + connect \B $eq$ls180.v:5771$1084_Y + connect \Y $and$ls180.v:5771$1085_Y + end + attribute \src "ls180.v:5772.39-5772.95" + cell $and $and$ls180.v:5772$1087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5772$1086_Y + connect \Y $and$ls180.v:5772$1087_Y + end + attribute \src "ls180.v:5772.38-5772.145" + cell $and $and$ls180.v:5772$1089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5772$1087_Y + connect \B $eq$ls180.v:5772$1088_Y + connect \Y $and$ls180.v:5772$1089_Y + end + attribute \src "ls180.v:5774.41-5774.94" + cell $and $and$ls180.v:5774$1090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5774$1090_Y + end + attribute \src "ls180.v:5774.40-5774.144" + cell $and $and$ls180.v:5774$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5774$1090_Y + connect \B $eq$ls180.v:5774$1091_Y + connect \Y $and$ls180.v:5774$1092_Y + end + attribute \src "ls180.v:5775.41-5775.97" + cell $and $and$ls180.v:5775$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5775$1093_Y + connect \Y $and$ls180.v:5775$1094_Y + end + attribute \src "ls180.v:5775.40-5775.147" + cell $and $and$ls180.v:5775$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5775$1094_Y + connect \B $eq$ls180.v:5775$1095_Y + connect \Y $and$ls180.v:5775$1096_Y + end + attribute \src "ls180.v:5777.41-5777.94" + cell $and $and$ls180.v:5777$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5777$1097_Y + end + attribute \src "ls180.v:5777.40-5777.144" + cell $and $and$ls180.v:5777$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5777$1097_Y + connect \B $eq$ls180.v:5777$1098_Y + connect \Y $and$ls180.v:5777$1099_Y + end + attribute \src "ls180.v:5778.41-5778.97" + cell $and $and$ls180.v:5778$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5778$1100_Y + connect \Y $and$ls180.v:5778$1101_Y + end + attribute \src "ls180.v:5778.40-5778.147" + cell $and $and$ls180.v:5778$1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5778$1101_Y + connect \B $eq$ls180.v:5778$1102_Y + connect \Y $and$ls180.v:5778$1103_Y + end + attribute \src "ls180.v:5780.41-5780.94" + cell $and $and$ls180.v:5780$1104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5780$1104_Y + end + attribute \src "ls180.v:5780.40-5780.144" + cell $and $and$ls180.v:5780$1106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5780$1104_Y + connect \B $eq$ls180.v:5780$1105_Y + connect \Y $and$ls180.v:5780$1106_Y + end + attribute \src "ls180.v:5781.41-5781.97" + cell $and $and$ls180.v:5781$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5781$1107_Y + connect \Y $and$ls180.v:5781$1108_Y + end + attribute \src "ls180.v:5781.40-5781.147" + cell $and $and$ls180.v:5781$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5781$1108_Y + connect \B $eq$ls180.v:5781$1109_Y + connect \Y $and$ls180.v:5781$1110_Y + end + attribute \src "ls180.v:5783.41-5783.94" + cell $and $and$ls180.v:5783$1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5783$1111_Y + end + attribute \src "ls180.v:5783.40-5783.144" + cell $and $and$ls180.v:5783$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5783$1111_Y + connect \B $eq$ls180.v:5783$1112_Y + connect \Y $and$ls180.v:5783$1113_Y + end + attribute \src "ls180.v:5784.41-5784.97" + cell $and $and$ls180.v:5784$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5784$1114_Y + connect \Y $and$ls180.v:5784$1115_Y + end + attribute \src "ls180.v:5784.40-5784.147" + cell $and $and$ls180.v:5784$1117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5784$1115_Y + connect \B $eq$ls180.v:5784$1116_Y + connect \Y $and$ls180.v:5784$1117_Y + end + attribute \src "ls180.v:5786.44-5786.97" + cell $and $and$ls180.v:5786$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5786$1118_Y + end + attribute \src "ls180.v:5786.43-5786.147" + cell $and $and$ls180.v:5786$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5786$1118_Y + connect \B $eq$ls180.v:5786$1119_Y + connect \Y $and$ls180.v:5786$1120_Y + end + attribute \src "ls180.v:5787.44-5787.100" + cell $and $and$ls180.v:5787$1122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5787$1121_Y + connect \Y $and$ls180.v:5787$1122_Y + end + attribute \src "ls180.v:5787.43-5787.150" + cell $and $and$ls180.v:5787$1124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5787$1122_Y + connect \B $eq$ls180.v:5787$1123_Y + connect \Y $and$ls180.v:5787$1124_Y + end + attribute \src "ls180.v:5789.44-5789.97" + cell $and $and$ls180.v:5789$1125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5789$1125_Y + end + attribute \src "ls180.v:5789.43-5789.147" + cell $and $and$ls180.v:5789$1127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5789$1125_Y + connect \B $eq$ls180.v:5789$1126_Y + connect \Y $and$ls180.v:5789$1127_Y + end + attribute \src "ls180.v:5790.44-5790.100" + cell $and $and$ls180.v:5790$1129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5790$1128_Y + connect \Y $and$ls180.v:5790$1129_Y + end + attribute \src "ls180.v:5790.43-5790.150" + cell $and $and$ls180.v:5790$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5790$1129_Y + connect \B $eq$ls180.v:5790$1130_Y + connect \Y $and$ls180.v:5790$1131_Y + end + attribute \src "ls180.v:5792.44-5792.97" + cell $and $and$ls180.v:5792$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5792$1132_Y + end + attribute \src "ls180.v:5792.43-5792.147" + cell $and $and$ls180.v:5792$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5792$1132_Y + connect \B $eq$ls180.v:5792$1133_Y + connect \Y $and$ls180.v:5792$1134_Y + end + attribute \src "ls180.v:5793.44-5793.100" + cell $and $and$ls180.v:5793$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5793$1135_Y + connect \Y $and$ls180.v:5793$1136_Y + end + attribute \src "ls180.v:5793.43-5793.150" + cell $and $and$ls180.v:5793$1138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5793$1136_Y + connect \B $eq$ls180.v:5793$1137_Y + connect \Y $and$ls180.v:5793$1138_Y + end + attribute \src "ls180.v:5795.44-5795.97" + cell $and $and$ls180.v:5795$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5795$1139_Y + end + attribute \src "ls180.v:5795.43-5795.147" + cell $and $and$ls180.v:5795$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5795$1139_Y + connect \B $eq$ls180.v:5795$1140_Y + connect \Y $and$ls180.v:5795$1141_Y + end + attribute \src "ls180.v:5796.44-5796.100" + cell $and $and$ls180.v:5796$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5796$1142_Y + connect \Y $and$ls180.v:5796$1143_Y + end + attribute \src "ls180.v:5796.43-5796.150" + cell $and $and$ls180.v:5796$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5796$1143_Y + connect \B $eq$ls180.v:5796$1144_Y + connect \Y $and$ls180.v:5796$1145_Y + end + attribute \src "ls180.v:5809.36-5809.89" + cell $and $and$ls180.v:5809$1147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5809$1147_Y + end + attribute \src "ls180.v:5809.35-5809.139" + cell $and $and$ls180.v:5809$1149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5809$1147_Y + connect \B $eq$ls180.v:5809$1148_Y + connect \Y $and$ls180.v:5809$1149_Y + end + attribute \src "ls180.v:5810.36-5810.92" + cell $and $and$ls180.v:5810$1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5810$1150_Y + connect \Y $and$ls180.v:5810$1151_Y + end + attribute \src "ls180.v:5810.35-5810.142" + cell $and $and$ls180.v:5810$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5810$1151_Y + connect \B $eq$ls180.v:5810$1152_Y + connect \Y $and$ls180.v:5810$1153_Y + end + attribute \src "ls180.v:5812.36-5812.89" + cell $and $and$ls180.v:5812$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5812$1154_Y + end + attribute \src "ls180.v:5812.35-5812.139" + cell $and $and$ls180.v:5812$1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5812$1154_Y + connect \B $eq$ls180.v:5812$1155_Y + connect \Y $and$ls180.v:5812$1156_Y + end + attribute \src "ls180.v:5813.36-5813.92" + cell $and $and$ls180.v:5813$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5813$1157_Y + connect \Y $and$ls180.v:5813$1158_Y + end + attribute \src "ls180.v:5813.35-5813.142" + cell $and $and$ls180.v:5813$1160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5813$1158_Y + connect \B $eq$ls180.v:5813$1159_Y + connect \Y $and$ls180.v:5813$1160_Y + end + attribute \src "ls180.v:5815.36-5815.89" + cell $and $and$ls180.v:5815$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5815$1161_Y + end + attribute \src "ls180.v:5815.35-5815.139" + cell $and $and$ls180.v:5815$1163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5815$1161_Y + connect \B $eq$ls180.v:5815$1162_Y + connect \Y $and$ls180.v:5815$1163_Y + end + attribute \src "ls180.v:5816.36-5816.92" + cell $and $and$ls180.v:5816$1165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5816$1164_Y + connect \Y $and$ls180.v:5816$1165_Y + end + attribute \src "ls180.v:5816.35-5816.142" + cell $and $and$ls180.v:5816$1167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5816$1165_Y + connect \B $eq$ls180.v:5816$1166_Y + connect \Y $and$ls180.v:5816$1167_Y + end + attribute \src "ls180.v:5818.36-5818.89" + cell $and $and$ls180.v:5818$1168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5818$1168_Y + end + attribute \src "ls180.v:5818.35-5818.139" + cell $and $and$ls180.v:5818$1170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5818$1168_Y + connect \B $eq$ls180.v:5818$1169_Y + connect \Y $and$ls180.v:5818$1170_Y + end + attribute \src "ls180.v:5819.36-5819.92" + cell $and $and$ls180.v:5819$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5819$1171_Y + connect \Y $and$ls180.v:5819$1172_Y + end + attribute \src "ls180.v:5819.35-5819.142" + cell $and $and$ls180.v:5819$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5819$1172_Y + connect \B $eq$ls180.v:5819$1173_Y + connect \Y $and$ls180.v:5819$1174_Y + end + attribute \src "ls180.v:5821.37-5821.90" + cell $and $and$ls180.v:5821$1175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5821$1175_Y + end + attribute \src "ls180.v:5821.36-5821.140" + cell $and $and$ls180.v:5821$1177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5821$1175_Y + connect \B $eq$ls180.v:5821$1176_Y + connect \Y $and$ls180.v:5821$1177_Y + end + attribute \src "ls180.v:5822.37-5822.93" + cell $and $and$ls180.v:5822$1179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5822$1178_Y + connect \Y $and$ls180.v:5822$1179_Y + end + attribute \src "ls180.v:5822.36-5822.143" + cell $and $and$ls180.v:5822$1181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5822$1179_Y + connect \B $eq$ls180.v:5822$1180_Y + connect \Y $and$ls180.v:5822$1181_Y + end + attribute \src "ls180.v:5824.37-5824.90" + cell $and $and$ls180.v:5824$1182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5824$1182_Y + end + attribute \src "ls180.v:5824.36-5824.140" + cell $and $and$ls180.v:5824$1184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5824$1182_Y + connect \B $eq$ls180.v:5824$1183_Y + connect \Y $and$ls180.v:5824$1184_Y + end + attribute \src "ls180.v:5825.37-5825.93" + cell $and $and$ls180.v:5825$1186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5825$1185_Y + connect \Y $and$ls180.v:5825$1186_Y + end + attribute \src "ls180.v:5825.36-5825.143" + cell $and $and$ls180.v:5825$1188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5825$1186_Y + connect \B $eq$ls180.v:5825$1187_Y + connect \Y $and$ls180.v:5825$1188_Y + end + attribute \src "ls180.v:5835.35-5835.88" + cell $and $and$ls180.v:5835$1190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5835$1190_Y + end + attribute \src "ls180.v:5835.34-5835.136" + cell $and $and$ls180.v:5835$1192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5835$1190_Y + connect \B $eq$ls180.v:5835$1191_Y + connect \Y $and$ls180.v:5835$1192_Y + end + attribute \src "ls180.v:5836.35-5836.91" + cell $and $and$ls180.v:5836$1194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5836$1193_Y + connect \Y $and$ls180.v:5836$1194_Y + end + attribute \src "ls180.v:5836.34-5836.139" + cell $and $and$ls180.v:5836$1196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5836$1194_Y + connect \B $eq$ls180.v:5836$1195_Y + connect \Y $and$ls180.v:5836$1196_Y + end + attribute \src "ls180.v:5838.34-5838.87" + cell $and $and$ls180.v:5838$1197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5838$1197_Y + end + attribute \src "ls180.v:5838.33-5838.135" + cell $and $and$ls180.v:5838$1199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5838$1197_Y + connect \B $eq$ls180.v:5838$1198_Y + connect \Y $and$ls180.v:5838$1199_Y + end + attribute \src "ls180.v:5839.34-5839.90" + cell $and $and$ls180.v:5839$1201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5839$1200_Y + connect \Y $and$ls180.v:5839$1201_Y + end + attribute \src "ls180.v:5839.33-5839.138" + cell $and $and$ls180.v:5839$1203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5839$1201_Y + connect \B $eq$ls180.v:5839$1202_Y + connect \Y $and$ls180.v:5839$1203_Y + end + attribute \src "ls180.v:5849.40-5849.93" + cell $and $and$ls180.v:5849$1205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5849$1205_Y + end + attribute \src "ls180.v:5849.39-5849.143" + cell $and $and$ls180.v:5849$1207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5849$1205_Y + connect \B $eq$ls180.v:5849$1206_Y + connect \Y $and$ls180.v:5849$1207_Y + end + attribute \src "ls180.v:5850.40-5850.96" + cell $and $and$ls180.v:5850$1209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5850$1208_Y + connect \Y $and$ls180.v:5850$1209_Y + end + attribute \src "ls180.v:5850.39-5850.146" + cell $and $and$ls180.v:5850$1211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5850$1209_Y + connect \B $eq$ls180.v:5850$1210_Y + connect \Y $and$ls180.v:5850$1211_Y + end + attribute \src "ls180.v:5852.39-5852.92" + cell $and $and$ls180.v:5852$1212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5852$1212_Y + end + attribute \src "ls180.v:5852.38-5852.142" + cell $and $and$ls180.v:5852$1214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5852$1212_Y + connect \B $eq$ls180.v:5852$1213_Y + connect \Y $and$ls180.v:5852$1214_Y + end + attribute \src "ls180.v:5853.39-5853.95" + cell $and $and$ls180.v:5853$1216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5853$1215_Y + connect \Y $and$ls180.v:5853$1216_Y + end + attribute \src "ls180.v:5853.38-5853.145" + cell $and $and$ls180.v:5853$1218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5853$1216_Y + connect \B $eq$ls180.v:5853$1217_Y + connect \Y $and$ls180.v:5853$1218_Y + end + attribute \src "ls180.v:5855.39-5855.92" + cell $and $and$ls180.v:5855$1219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5855$1219_Y + end + attribute \src "ls180.v:5855.38-5855.142" + cell $and $and$ls180.v:5855$1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5855$1219_Y + connect \B $eq$ls180.v:5855$1220_Y + connect \Y $and$ls180.v:5855$1221_Y + end + attribute \src "ls180.v:5856.39-5856.95" + cell $and $and$ls180.v:5856$1223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5856$1222_Y + connect \Y $and$ls180.v:5856$1223_Y + end + attribute \src "ls180.v:5856.38-5856.145" + cell $and $and$ls180.v:5856$1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5856$1223_Y + connect \B $eq$ls180.v:5856$1224_Y + connect \Y $and$ls180.v:5856$1225_Y + end + attribute \src "ls180.v:5858.39-5858.92" + cell $and $and$ls180.v:5858$1226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5858$1226_Y + end + attribute \src "ls180.v:5858.38-5858.142" + cell $and $and$ls180.v:5858$1228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5858$1226_Y + connect \B $eq$ls180.v:5858$1227_Y + connect \Y $and$ls180.v:5858$1228_Y + end + attribute \src "ls180.v:5859.39-5859.95" + cell $and $and$ls180.v:5859$1230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5859$1229_Y + connect \Y $and$ls180.v:5859$1230_Y + end + attribute \src "ls180.v:5859.38-5859.145" + cell $and $and$ls180.v:5859$1232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5859$1230_Y + connect \B $eq$ls180.v:5859$1231_Y + connect \Y $and$ls180.v:5859$1232_Y + end + attribute \src "ls180.v:5861.39-5861.92" + cell $and $and$ls180.v:5861$1233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5861$1233_Y + end + attribute \src "ls180.v:5861.38-5861.142" + cell $and $and$ls180.v:5861$1235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5861$1233_Y + connect \B $eq$ls180.v:5861$1234_Y + connect \Y $and$ls180.v:5861$1235_Y + end + attribute \src "ls180.v:5862.39-5862.95" + cell $and $and$ls180.v:5862$1237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5862$1236_Y + connect \Y $and$ls180.v:5862$1237_Y + end + attribute \src "ls180.v:5862.38-5862.145" + cell $and $and$ls180.v:5862$1239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5862$1237_Y + connect \B $eq$ls180.v:5862$1238_Y + connect \Y $and$ls180.v:5862$1239_Y + end + attribute \src "ls180.v:5864.40-5864.93" + cell $and $and$ls180.v:5864$1240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5864$1240_Y + end + attribute \src "ls180.v:5864.39-5864.143" + cell $and $and$ls180.v:5864$1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5864$1240_Y + connect \B $eq$ls180.v:5864$1241_Y + connect \Y $and$ls180.v:5864$1242_Y + end + attribute \src "ls180.v:5865.40-5865.96" + cell $and $and$ls180.v:5865$1244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5865$1243_Y + connect \Y $and$ls180.v:5865$1244_Y + end + attribute \src "ls180.v:5865.39-5865.146" + cell $and $and$ls180.v:5865$1246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5865$1244_Y + connect \B $eq$ls180.v:5865$1245_Y + connect \Y $and$ls180.v:5865$1246_Y + end + attribute \src "ls180.v:5867.40-5867.93" + cell $and $and$ls180.v:5867$1247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5867$1247_Y + end + attribute \src "ls180.v:5867.39-5867.143" + cell $and $and$ls180.v:5867$1249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5867$1247_Y + connect \B $eq$ls180.v:5867$1248_Y + connect \Y $and$ls180.v:5867$1249_Y + end + attribute \src "ls180.v:5868.40-5868.96" + cell $and $and$ls180.v:5868$1251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5868$1250_Y + connect \Y $and$ls180.v:5868$1251_Y + end + attribute \src "ls180.v:5868.39-5868.146" + cell $and $and$ls180.v:5868$1253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5868$1251_Y + connect \B $eq$ls180.v:5868$1252_Y + connect \Y $and$ls180.v:5868$1253_Y + end + attribute \src "ls180.v:5870.40-5870.93" + cell $and $and$ls180.v:5870$1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5870$1254_Y + end + attribute \src "ls180.v:5870.39-5870.143" + cell $and $and$ls180.v:5870$1256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5870$1254_Y + connect \B $eq$ls180.v:5870$1255_Y + connect \Y $and$ls180.v:5870$1256_Y + end + attribute \src "ls180.v:5871.40-5871.96" + cell $and $and$ls180.v:5871$1258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5871$1257_Y + connect \Y $and$ls180.v:5871$1258_Y + end + attribute \src "ls180.v:5871.39-5871.146" + cell $and $and$ls180.v:5871$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5871$1258_Y + connect \B $eq$ls180.v:5871$1259_Y + connect \Y $and$ls180.v:5871$1260_Y + end + attribute \src "ls180.v:5873.40-5873.93" + cell $and $and$ls180.v:5873$1261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5873$1261_Y + end + attribute \src "ls180.v:5873.39-5873.143" + cell $and $and$ls180.v:5873$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5873$1261_Y + connect \B $eq$ls180.v:5873$1262_Y + connect \Y $and$ls180.v:5873$1263_Y + end + attribute \src "ls180.v:5874.40-5874.96" + cell $and $and$ls180.v:5874$1265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5874$1264_Y + connect \Y $and$ls180.v:5874$1265_Y + end + attribute \src "ls180.v:5874.39-5874.146" + cell $and $and$ls180.v:5874$1267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5874$1265_Y + connect \B $eq$ls180.v:5874$1266_Y + connect \Y $and$ls180.v:5874$1267_Y + end + attribute \src "ls180.v:5886.40-5886.93" + cell $and $and$ls180.v:5886$1269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5886$1269_Y + end + attribute \src "ls180.v:5886.39-5886.143" + cell $and $and$ls180.v:5886$1271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5886$1269_Y + connect \B $eq$ls180.v:5886$1270_Y + connect \Y $and$ls180.v:5886$1271_Y + end + attribute \src "ls180.v:5887.40-5887.96" + cell $and $and$ls180.v:5887$1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5887$1272_Y + connect \Y $and$ls180.v:5887$1273_Y + end + attribute \src "ls180.v:5887.39-5887.146" + cell $and $and$ls180.v:5887$1275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5887$1273_Y + connect \B $eq$ls180.v:5887$1274_Y + connect \Y $and$ls180.v:5887$1275_Y + end + attribute \src "ls180.v:5889.39-5889.92" + cell $and $and$ls180.v:5889$1276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5889$1276_Y + end + attribute \src "ls180.v:5889.38-5889.142" + cell $and $and$ls180.v:5889$1278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5889$1276_Y + connect \B $eq$ls180.v:5889$1277_Y + connect \Y $and$ls180.v:5889$1278_Y + end + attribute \src "ls180.v:5890.39-5890.95" + cell $and $and$ls180.v:5890$1280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5890$1279_Y + connect \Y $and$ls180.v:5890$1280_Y + end + attribute \src "ls180.v:5890.38-5890.145" + cell $and $and$ls180.v:5890$1282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5890$1280_Y + connect \B $eq$ls180.v:5890$1281_Y + connect \Y $and$ls180.v:5890$1282_Y + end + attribute \src "ls180.v:5892.39-5892.92" + cell $and $and$ls180.v:5892$1283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5892$1283_Y + end + attribute \src "ls180.v:5892.38-5892.142" + cell $and $and$ls180.v:5892$1285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5892$1283_Y + connect \B $eq$ls180.v:5892$1284_Y + connect \Y $and$ls180.v:5892$1285_Y + end + attribute \src "ls180.v:5893.39-5893.95" + cell $and $and$ls180.v:5893$1287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5893$1286_Y + connect \Y $and$ls180.v:5893$1287_Y + end + attribute \src "ls180.v:5893.38-5893.145" + cell $and $and$ls180.v:5893$1289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5893$1287_Y + connect \B $eq$ls180.v:5893$1288_Y + connect \Y $and$ls180.v:5893$1289_Y + end + attribute \src "ls180.v:5895.39-5895.92" + cell $and $and$ls180.v:5895$1290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5895$1290_Y + end + attribute \src "ls180.v:5895.38-5895.142" + cell $and $and$ls180.v:5895$1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5895$1290_Y + connect \B $eq$ls180.v:5895$1291_Y + connect \Y $and$ls180.v:5895$1292_Y + end + attribute \src "ls180.v:5896.39-5896.95" + cell $and $and$ls180.v:5896$1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5896$1293_Y + connect \Y $and$ls180.v:5896$1294_Y + end + attribute \src "ls180.v:5896.38-5896.145" + cell $and $and$ls180.v:5896$1296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5896$1294_Y + connect \B $eq$ls180.v:5896$1295_Y + connect \Y $and$ls180.v:5896$1296_Y + end + attribute \src "ls180.v:5898.39-5898.92" + cell $and $and$ls180.v:5898$1297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5898$1297_Y + end + attribute \src "ls180.v:5898.38-5898.142" + cell $and $and$ls180.v:5898$1299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5898$1297_Y + connect \B $eq$ls180.v:5898$1298_Y + connect \Y $and$ls180.v:5898$1299_Y + end + attribute \src "ls180.v:5899.39-5899.95" + cell $and $and$ls180.v:5899$1301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5899$1300_Y + connect \Y $and$ls180.v:5899$1301_Y + end + attribute \src "ls180.v:5899.38-5899.145" + cell $and $and$ls180.v:5899$1303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5899$1301_Y + connect \B $eq$ls180.v:5899$1302_Y + connect \Y $and$ls180.v:5899$1303_Y + end + attribute \src "ls180.v:5901.40-5901.93" + cell $and $and$ls180.v:5901$1304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5901$1304_Y + end + attribute \src "ls180.v:5901.39-5901.143" + cell $and $and$ls180.v:5901$1306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5901$1304_Y + connect \B $eq$ls180.v:5901$1305_Y + connect \Y $and$ls180.v:5901$1306_Y + end + attribute \src "ls180.v:5902.40-5902.96" + cell $and $and$ls180.v:5902$1308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5902$1307_Y + connect \Y $and$ls180.v:5902$1308_Y + end + attribute \src "ls180.v:5902.39-5902.146" + cell $and $and$ls180.v:5902$1310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5902$1308_Y + connect \B $eq$ls180.v:5902$1309_Y + connect \Y $and$ls180.v:5902$1310_Y + end + attribute \src "ls180.v:5904.40-5904.93" + cell $and $and$ls180.v:5904$1311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5904$1311_Y + end + attribute \src "ls180.v:5904.39-5904.143" + cell $and $and$ls180.v:5904$1313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5904$1311_Y + connect \B $eq$ls180.v:5904$1312_Y + connect \Y $and$ls180.v:5904$1313_Y + end + attribute \src "ls180.v:5905.40-5905.96" + cell $and $and$ls180.v:5905$1315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5905$1314_Y + connect \Y $and$ls180.v:5905$1315_Y + end + attribute \src "ls180.v:5905.39-5905.146" + cell $and $and$ls180.v:5905$1317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5905$1315_Y + connect \B $eq$ls180.v:5905$1316_Y + connect \Y $and$ls180.v:5905$1317_Y + end + attribute \src "ls180.v:5907.40-5907.93" + cell $and $and$ls180.v:5907$1318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5907$1318_Y + end + attribute \src "ls180.v:5907.39-5907.143" + cell $and $and$ls180.v:5907$1320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5907$1318_Y + connect \B $eq$ls180.v:5907$1319_Y + connect \Y $and$ls180.v:5907$1320_Y + end + attribute \src "ls180.v:5908.40-5908.96" + cell $and $and$ls180.v:5908$1322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5908$1321_Y + connect \Y $and$ls180.v:5908$1322_Y + end + attribute \src "ls180.v:5908.39-5908.146" + cell $and $and$ls180.v:5908$1324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5908$1322_Y + connect \B $eq$ls180.v:5908$1323_Y + connect \Y $and$ls180.v:5908$1324_Y + end + attribute \src "ls180.v:5910.40-5910.93" + cell $and $and$ls180.v:5910$1325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5910$1325_Y + end + attribute \src "ls180.v:5910.39-5910.143" + cell $and $and$ls180.v:5910$1327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5910$1325_Y + connect \B $eq$ls180.v:5910$1326_Y + connect \Y $and$ls180.v:5910$1327_Y + end + attribute \src "ls180.v:5911.40-5911.96" + cell $and $and$ls180.v:5911$1329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5911$1328_Y + connect \Y $and$ls180.v:5911$1329_Y + end + attribute \src "ls180.v:5911.39-5911.146" + cell $and $and$ls180.v:5911$1331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5911$1329_Y + connect \B $eq$ls180.v:5911$1330_Y + connect \Y $and$ls180.v:5911$1331_Y + end + attribute \src "ls180.v:5923.42-5923.95" + cell $and $and$ls180.v:5923$1333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5923$1333_Y + end + attribute \src "ls180.v:5923.41-5923.145" + cell $and $and$ls180.v:5923$1335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5923$1333_Y + connect \B $eq$ls180.v:5923$1334_Y + connect \Y $and$ls180.v:5923$1335_Y + end + attribute \src "ls180.v:5924.42-5924.98" + cell $and $and$ls180.v:5924$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5924$1336_Y + connect \Y $and$ls180.v:5924$1337_Y + end + attribute \src "ls180.v:5924.41-5924.148" + cell $and $and$ls180.v:5924$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5924$1337_Y + connect \B $eq$ls180.v:5924$1338_Y + connect \Y $and$ls180.v:5924$1339_Y + end + attribute \src "ls180.v:5926.42-5926.95" + cell $and $and$ls180.v:5926$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5926$1340_Y + end + attribute \src "ls180.v:5926.41-5926.145" + cell $and $and$ls180.v:5926$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5926$1340_Y + connect \B $eq$ls180.v:5926$1341_Y + connect \Y $and$ls180.v:5926$1342_Y + end + attribute \src "ls180.v:5927.42-5927.98" + cell $and $and$ls180.v:5927$1344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5927$1343_Y + connect \Y $and$ls180.v:5927$1344_Y + end + attribute \src "ls180.v:5927.41-5927.148" + cell $and $and$ls180.v:5927$1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5927$1344_Y + connect \B $eq$ls180.v:5927$1345_Y + connect \Y $and$ls180.v:5927$1346_Y + end + attribute \src "ls180.v:5929.42-5929.95" + cell $and $and$ls180.v:5929$1347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5929$1347_Y + end + attribute \src "ls180.v:5929.41-5929.145" + cell $and $and$ls180.v:5929$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5929$1347_Y + connect \B $eq$ls180.v:5929$1348_Y + connect \Y $and$ls180.v:5929$1349_Y + end + attribute \src "ls180.v:5930.42-5930.98" + cell $and $and$ls180.v:5930$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5930$1350_Y + connect \Y $and$ls180.v:5930$1351_Y + end + attribute \src "ls180.v:5930.41-5930.148" + cell $and $and$ls180.v:5930$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5930$1351_Y + connect \B $eq$ls180.v:5930$1352_Y + connect \Y $and$ls180.v:5930$1353_Y + end + attribute \src "ls180.v:5932.42-5932.95" + cell $and $and$ls180.v:5932$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5932$1354_Y + end + attribute \src "ls180.v:5932.41-5932.145" + cell $and $and$ls180.v:5932$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5932$1354_Y + connect \B $eq$ls180.v:5932$1355_Y + connect \Y $and$ls180.v:5932$1356_Y + end + attribute \src "ls180.v:5933.42-5933.98" + cell $and $and$ls180.v:5933$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5933$1357_Y + connect \Y $and$ls180.v:5933$1358_Y + end + attribute \src "ls180.v:5933.41-5933.148" + cell $and $and$ls180.v:5933$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5933$1358_Y + connect \B $eq$ls180.v:5933$1359_Y + connect \Y $and$ls180.v:5933$1360_Y + end + attribute \src "ls180.v:5935.42-5935.95" + cell $and $and$ls180.v:5935$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5935$1361_Y + end + attribute \src "ls180.v:5935.41-5935.145" + cell $and $and$ls180.v:5935$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5935$1361_Y + connect \B $eq$ls180.v:5935$1362_Y + connect \Y $and$ls180.v:5935$1363_Y + end + attribute \src "ls180.v:5936.42-5936.98" + cell $and $and$ls180.v:5936$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5936$1364_Y + connect \Y $and$ls180.v:5936$1365_Y + end + attribute \src "ls180.v:5936.41-5936.148" + cell $and $and$ls180.v:5936$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5936$1365_Y + connect \B $eq$ls180.v:5936$1366_Y + connect \Y $and$ls180.v:5936$1367_Y + end + attribute \src "ls180.v:5938.42-5938.95" + cell $and $and$ls180.v:5938$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5938$1368_Y + end + attribute \src "ls180.v:5938.41-5938.145" + cell $and $and$ls180.v:5938$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5938$1368_Y + connect \B $eq$ls180.v:5938$1369_Y + connect \Y $and$ls180.v:5938$1370_Y + end + attribute \src "ls180.v:5939.42-5939.98" + cell $and $and$ls180.v:5939$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5939$1371_Y + connect \Y $and$ls180.v:5939$1372_Y + end + attribute \src "ls180.v:5939.41-5939.148" + cell $and $and$ls180.v:5939$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5939$1372_Y + connect \B $eq$ls180.v:5939$1373_Y + connect \Y $and$ls180.v:5939$1374_Y + end + attribute \src "ls180.v:5941.42-5941.95" + cell $and $and$ls180.v:5941$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5941$1375_Y + end + attribute \src "ls180.v:5941.41-5941.145" + cell $and $and$ls180.v:5941$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5941$1375_Y + connect \B $eq$ls180.v:5941$1376_Y + connect \Y $and$ls180.v:5941$1377_Y + end + attribute \src "ls180.v:5942.42-5942.98" + cell $and $and$ls180.v:5942$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5942$1378_Y + connect \Y $and$ls180.v:5942$1379_Y + end + attribute \src "ls180.v:5942.41-5942.148" + cell $and $and$ls180.v:5942$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5942$1379_Y + connect \B $eq$ls180.v:5942$1380_Y + connect \Y $and$ls180.v:5942$1381_Y + end + attribute \src "ls180.v:5944.42-5944.95" + cell $and $and$ls180.v:5944$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5944$1382_Y + end + attribute \src "ls180.v:5944.41-5944.145" + cell $and $and$ls180.v:5944$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5944$1382_Y + connect \B $eq$ls180.v:5944$1383_Y + connect \Y $and$ls180.v:5944$1384_Y + end + attribute \src "ls180.v:5945.42-5945.98" + cell $and $and$ls180.v:5945$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5945$1385_Y + connect \Y $and$ls180.v:5945$1386_Y + end + attribute \src "ls180.v:5945.41-5945.148" + cell $and $and$ls180.v:5945$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5945$1386_Y + connect \B $eq$ls180.v:5945$1387_Y + connect \Y $and$ls180.v:5945$1388_Y + end + attribute \src "ls180.v:5947.44-5947.97" + cell $and $and$ls180.v:5947$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5947$1389_Y + end + attribute \src "ls180.v:5947.43-5947.147" + cell $and $and$ls180.v:5947$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5947$1389_Y + connect \B $eq$ls180.v:5947$1390_Y + connect \Y $and$ls180.v:5947$1391_Y + end + attribute \src "ls180.v:5948.44-5948.100" + cell $and $and$ls180.v:5948$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5948$1392_Y + connect \Y $and$ls180.v:5948$1393_Y + end + attribute \src "ls180.v:5948.43-5948.150" + cell $and $and$ls180.v:5948$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5948$1393_Y + connect \B $eq$ls180.v:5948$1394_Y + connect \Y $and$ls180.v:5948$1395_Y + end + attribute \src "ls180.v:5950.44-5950.97" + cell $and $and$ls180.v:5950$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5950$1396_Y + end + attribute \src "ls180.v:5950.43-5950.147" + cell $and $and$ls180.v:5950$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5950$1396_Y + connect \B $eq$ls180.v:5950$1397_Y + connect \Y $and$ls180.v:5950$1398_Y + end + attribute \src "ls180.v:5951.44-5951.100" + cell $and $and$ls180.v:5951$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5951$1399_Y + connect \Y $and$ls180.v:5951$1400_Y + end + attribute \src "ls180.v:5951.43-5951.150" + cell $and $and$ls180.v:5951$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5951$1400_Y + connect \B $eq$ls180.v:5951$1401_Y + connect \Y $and$ls180.v:5951$1402_Y + end + attribute \src "ls180.v:5953.44-5953.97" + cell $and $and$ls180.v:5953$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5953$1403_Y + end + attribute \src "ls180.v:5953.43-5953.148" + cell $and $and$ls180.v:5953$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5953$1403_Y + connect \B $eq$ls180.v:5953$1404_Y + connect \Y $and$ls180.v:5953$1405_Y + end + attribute \src "ls180.v:5954.44-5954.100" + cell $and $and$ls180.v:5954$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5954$1406_Y + connect \Y $and$ls180.v:5954$1407_Y + end + attribute \src "ls180.v:5954.43-5954.151" + cell $and $and$ls180.v:5954$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5954$1407_Y + connect \B $eq$ls180.v:5954$1408_Y + connect \Y $and$ls180.v:5954$1409_Y + end + attribute \src "ls180.v:5956.44-5956.97" + cell $and $and$ls180.v:5956$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5956$1410_Y + end + attribute \src "ls180.v:5956.43-5956.148" + cell $and $and$ls180.v:5956$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5956$1410_Y + connect \B $eq$ls180.v:5956$1411_Y + connect \Y $and$ls180.v:5956$1412_Y + end + attribute \src "ls180.v:5957.44-5957.100" + cell $and $and$ls180.v:5957$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5957$1413_Y + connect \Y $and$ls180.v:5957$1414_Y + end + attribute \src "ls180.v:5957.43-5957.151" + cell $and $and$ls180.v:5957$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5957$1414_Y + connect \B $eq$ls180.v:5957$1415_Y + connect \Y $and$ls180.v:5957$1416_Y + end + attribute \src "ls180.v:5959.44-5959.97" + cell $and $and$ls180.v:5959$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5959$1417_Y + end + attribute \src "ls180.v:5959.43-5959.148" + cell $and $and$ls180.v:5959$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5959$1417_Y + connect \B $eq$ls180.v:5959$1418_Y + connect \Y $and$ls180.v:5959$1419_Y + end + attribute \src "ls180.v:5960.44-5960.100" + cell $and $and$ls180.v:5960$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5960$1420_Y + connect \Y $and$ls180.v:5960$1421_Y + end + attribute \src "ls180.v:5960.43-5960.151" + cell $and $and$ls180.v:5960$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5960$1421_Y + connect \B $eq$ls180.v:5960$1422_Y + connect \Y $and$ls180.v:5960$1423_Y + end + attribute \src "ls180.v:5962.41-5962.94" + cell $and $and$ls180.v:5962$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5962$1424_Y + end + attribute \src "ls180.v:5962.40-5962.145" + cell $and $and$ls180.v:5962$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5962$1424_Y + connect \B $eq$ls180.v:5962$1425_Y + connect \Y $and$ls180.v:5962$1426_Y + end + attribute \src "ls180.v:5963.41-5963.97" + cell $and $and$ls180.v:5963$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5963$1427_Y + connect \Y $and$ls180.v:5963$1428_Y + end + attribute \src "ls180.v:5963.40-5963.148" + cell $and $and$ls180.v:5963$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5963$1428_Y + connect \B $eq$ls180.v:5963$1429_Y + connect \Y $and$ls180.v:5963$1430_Y + end + attribute \src "ls180.v:5965.42-5965.95" + cell $and $and$ls180.v:5965$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5965$1431_Y + end + attribute \src "ls180.v:5965.41-5965.146" + cell $and $and$ls180.v:5965$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5965$1431_Y + connect \B $eq$ls180.v:5965$1432_Y + connect \Y $and$ls180.v:5965$1433_Y + end + attribute \src "ls180.v:5966.42-5966.98" + cell $and $and$ls180.v:5966$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5966$1434_Y + connect \Y $and$ls180.v:5966$1435_Y + end + attribute \src "ls180.v:5966.41-5966.149" + cell $and $and$ls180.v:5966$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5966$1435_Y + connect \B $eq$ls180.v:5966$1436_Y + connect \Y $and$ls180.v:5966$1437_Y + end + attribute \src "ls180.v:5985.46-5985.99" + cell $and $and$ls180.v:5985$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5985$1439_Y + end + attribute \src "ls180.v:5985.45-5985.149" + cell $and $and$ls180.v:5985$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5985$1439_Y + connect \B $eq$ls180.v:5985$1440_Y + connect \Y $and$ls180.v:5985$1441_Y + end + attribute \src "ls180.v:5986.46-5986.102" + cell $and $and$ls180.v:5986$1443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5986$1442_Y + connect \Y $and$ls180.v:5986$1443_Y + end + attribute \src "ls180.v:5986.45-5986.152" + cell $and $and$ls180.v:5986$1445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5986$1443_Y + connect \B $eq$ls180.v:5986$1444_Y + connect \Y $and$ls180.v:5986$1445_Y + end + attribute \src "ls180.v:5988.46-5988.99" + cell $and $and$ls180.v:5988$1446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5988$1446_Y + end + attribute \src "ls180.v:5988.45-5988.149" + cell $and $and$ls180.v:5988$1448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5988$1446_Y + connect \B $eq$ls180.v:5988$1447_Y + connect \Y $and$ls180.v:5988$1448_Y + end + attribute \src "ls180.v:5989.46-5989.102" + cell $and $and$ls180.v:5989$1450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5989$1449_Y + connect \Y $and$ls180.v:5989$1450_Y + end + attribute \src "ls180.v:5989.45-5989.152" + cell $and $and$ls180.v:5989$1452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5989$1450_Y + connect \B $eq$ls180.v:5989$1451_Y + connect \Y $and$ls180.v:5989$1452_Y + end + attribute \src "ls180.v:5991.46-5991.99" + cell $and $and$ls180.v:5991$1453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5991$1453_Y + end + attribute \src "ls180.v:5991.45-5991.149" + cell $and $and$ls180.v:5991$1455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5991$1453_Y + connect \B $eq$ls180.v:5991$1454_Y + connect \Y $and$ls180.v:5991$1455_Y + end + attribute \src "ls180.v:5992.46-5992.102" + cell $and $and$ls180.v:5992$1457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5992$1456_Y + connect \Y $and$ls180.v:5992$1457_Y + end + attribute \src "ls180.v:5992.45-5992.152" + cell $and $and$ls180.v:5992$1459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5992$1457_Y + connect \B $eq$ls180.v:5992$1458_Y + connect \Y $and$ls180.v:5992$1459_Y + end + attribute \src "ls180.v:5994.46-5994.99" + cell $and $and$ls180.v:5994$1460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5994$1460_Y + end + attribute \src "ls180.v:5994.45-5994.149" + cell $and $and$ls180.v:5994$1462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5994$1460_Y + connect \B $eq$ls180.v:5994$1461_Y + connect \Y $and$ls180.v:5994$1462_Y + end + attribute \src "ls180.v:5995.46-5995.102" + cell $and $and$ls180.v:5995$1464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5995$1463_Y + connect \Y $and$ls180.v:5995$1464_Y + end + attribute \src "ls180.v:5995.45-5995.152" + cell $and $and$ls180.v:5995$1466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5995$1464_Y + connect \B $eq$ls180.v:5995$1465_Y + connect \Y $and$ls180.v:5995$1466_Y + end + attribute \src "ls180.v:5997.45-5997.98" + cell $and $and$ls180.v:5997$1467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5997$1467_Y + end + attribute \src "ls180.v:5997.44-5997.148" + cell $and $and$ls180.v:5997$1469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5997$1467_Y + connect \B $eq$ls180.v:5997$1468_Y + connect \Y $and$ls180.v:5997$1469_Y + end + attribute \src "ls180.v:5998.45-5998.101" + cell $and $and$ls180.v:5998$1471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5998$1470_Y + connect \Y $and$ls180.v:5998$1471_Y + end + attribute \src "ls180.v:5998.44-5998.151" + cell $and $and$ls180.v:5998$1473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5998$1471_Y + connect \B $eq$ls180.v:5998$1472_Y + connect \Y $and$ls180.v:5998$1473_Y + end + attribute \src "ls180.v:6000.45-6000.98" + cell $and $and$ls180.v:6000$1474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6000$1474_Y + end + attribute \src "ls180.v:6000.44-6000.148" + cell $and $and$ls180.v:6000$1476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6000$1474_Y + connect \B $eq$ls180.v:6000$1475_Y + connect \Y $and$ls180.v:6000$1476_Y + end + attribute \src "ls180.v:6001.45-6001.101" + cell $and $and$ls180.v:6001$1478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6001$1477_Y + connect \Y $and$ls180.v:6001$1478_Y + end + attribute \src "ls180.v:6001.44-6001.151" + cell $and $and$ls180.v:6001$1480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6001$1478_Y + connect \B $eq$ls180.v:6001$1479_Y + connect \Y $and$ls180.v:6001$1480_Y + end + attribute \src "ls180.v:6003.45-6003.98" + cell $and $and$ls180.v:6003$1481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6003$1481_Y + end + attribute \src "ls180.v:6003.44-6003.148" + cell $and $and$ls180.v:6003$1483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6003$1481_Y + connect \B $eq$ls180.v:6003$1482_Y + connect \Y $and$ls180.v:6003$1483_Y + end + attribute \src "ls180.v:6004.45-6004.101" + cell $and $and$ls180.v:6004$1485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6004$1484_Y + connect \Y $and$ls180.v:6004$1485_Y + end + attribute \src "ls180.v:6004.44-6004.151" + cell $and $and$ls180.v:6004$1487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6004$1485_Y + connect \B $eq$ls180.v:6004$1486_Y + connect \Y $and$ls180.v:6004$1487_Y + end + attribute \src "ls180.v:6006.45-6006.98" + cell $and $and$ls180.v:6006$1488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6006$1488_Y + end + attribute \src "ls180.v:6006.44-6006.148" + cell $and $and$ls180.v:6006$1490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6006$1488_Y + connect \B $eq$ls180.v:6006$1489_Y + connect \Y $and$ls180.v:6006$1490_Y + end + attribute \src "ls180.v:6007.45-6007.101" + cell $and $and$ls180.v:6007$1492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6007$1491_Y + connect \Y $and$ls180.v:6007$1492_Y + end + attribute \src "ls180.v:6007.44-6007.151" + cell $and $and$ls180.v:6007$1494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6007$1492_Y + connect \B $eq$ls180.v:6007$1493_Y + connect \Y $and$ls180.v:6007$1494_Y + end + attribute \src "ls180.v:6009.36-6009.89" + cell $and $and$ls180.v:6009$1495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6009$1495_Y + end + attribute \src "ls180.v:6009.35-6009.139" + cell $and $and$ls180.v:6009$1497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6009$1495_Y + connect \B $eq$ls180.v:6009$1496_Y + connect \Y $and$ls180.v:6009$1497_Y + end + attribute \src "ls180.v:6010.36-6010.92" + cell $and $and$ls180.v:6010$1499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6010$1498_Y + connect \Y $and$ls180.v:6010$1499_Y + end + attribute \src "ls180.v:6010.35-6010.142" + cell $and $and$ls180.v:6010$1501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6010$1499_Y + connect \B $eq$ls180.v:6010$1500_Y + connect \Y $and$ls180.v:6010$1501_Y + end + attribute \src "ls180.v:6012.47-6012.100" + cell $and $and$ls180.v:6012$1502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6012$1502_Y + end + attribute \src "ls180.v:6012.46-6012.150" + cell $and $and$ls180.v:6012$1504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6012$1502_Y + connect \B $eq$ls180.v:6012$1503_Y + connect \Y $and$ls180.v:6012$1504_Y + end + attribute \src "ls180.v:6013.47-6013.103" + cell $and $and$ls180.v:6013$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6013$1505_Y + connect \Y $and$ls180.v:6013$1506_Y + end + attribute \src "ls180.v:6013.46-6013.153" + cell $and $and$ls180.v:6013$1508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6013$1506_Y + connect \B $eq$ls180.v:6013$1507_Y + connect \Y $and$ls180.v:6013$1508_Y + end + attribute \src "ls180.v:6015.47-6015.100" + cell $and $and$ls180.v:6015$1509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6015$1509_Y + end + attribute \src "ls180.v:6015.46-6015.151" + cell $and $and$ls180.v:6015$1511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6015$1509_Y + connect \B $eq$ls180.v:6015$1510_Y + connect \Y $and$ls180.v:6015$1511_Y + end + attribute \src "ls180.v:6016.47-6016.103" + cell $and $and$ls180.v:6016$1513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6016$1512_Y + connect \Y $and$ls180.v:6016$1513_Y + end + attribute \src "ls180.v:6016.46-6016.154" + cell $and $and$ls180.v:6016$1515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6016$1513_Y + connect \B $eq$ls180.v:6016$1514_Y + connect \Y $and$ls180.v:6016$1515_Y + end + attribute \src "ls180.v:6018.47-6018.100" + cell $and $and$ls180.v:6018$1516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6018$1516_Y + end + attribute \src "ls180.v:6018.46-6018.151" + cell $and $and$ls180.v:6018$1518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6018$1516_Y + connect \B $eq$ls180.v:6018$1517_Y + connect \Y $and$ls180.v:6018$1518_Y + end + attribute \src "ls180.v:6019.47-6019.103" + cell $and $and$ls180.v:6019$1520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6019$1519_Y + connect \Y $and$ls180.v:6019$1520_Y + end + attribute \src "ls180.v:6019.46-6019.154" + cell $and $and$ls180.v:6019$1522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6019$1520_Y + connect \B $eq$ls180.v:6019$1521_Y + connect \Y $and$ls180.v:6019$1522_Y + end + attribute \src "ls180.v:6021.47-6021.100" + cell $and $and$ls180.v:6021$1523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6021$1523_Y + end + attribute \src "ls180.v:6021.46-6021.151" + cell $and $and$ls180.v:6021$1525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6021$1523_Y + connect \B $eq$ls180.v:6021$1524_Y + connect \Y $and$ls180.v:6021$1525_Y + end + attribute \src "ls180.v:6022.47-6022.103" + cell $and $and$ls180.v:6022$1527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6022$1526_Y + connect \Y $and$ls180.v:6022$1527_Y + end + attribute \src "ls180.v:6022.46-6022.154" + cell $and $and$ls180.v:6022$1529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6022$1527_Y + connect \B $eq$ls180.v:6022$1528_Y + connect \Y $and$ls180.v:6022$1529_Y + end + attribute \src "ls180.v:6024.47-6024.100" + cell $and $and$ls180.v:6024$1530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6024$1530_Y + end + attribute \src "ls180.v:6024.46-6024.151" + cell $and $and$ls180.v:6024$1532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6024$1530_Y + connect \B $eq$ls180.v:6024$1531_Y + connect \Y $and$ls180.v:6024$1532_Y + end + attribute \src "ls180.v:6025.47-6025.103" + cell $and $and$ls180.v:6025$1534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6025$1533_Y + connect \Y $and$ls180.v:6025$1534_Y + end + attribute \src "ls180.v:6025.46-6025.154" + cell $and $and$ls180.v:6025$1536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6025$1534_Y + connect \B $eq$ls180.v:6025$1535_Y + connect \Y $and$ls180.v:6025$1536_Y + end + attribute \src "ls180.v:6027.47-6027.100" + cell $and $and$ls180.v:6027$1537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6027$1537_Y + end + attribute \src "ls180.v:6027.46-6027.151" + cell $and $and$ls180.v:6027$1539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6027$1537_Y + connect \B $eq$ls180.v:6027$1538_Y + connect \Y $and$ls180.v:6027$1539_Y + end + attribute \src "ls180.v:6028.47-6028.103" + cell $and $and$ls180.v:6028$1541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6028$1540_Y + connect \Y $and$ls180.v:6028$1541_Y + end + attribute \src "ls180.v:6028.46-6028.154" + cell $and $and$ls180.v:6028$1543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6028$1541_Y + connect \B $eq$ls180.v:6028$1542_Y + connect \Y $and$ls180.v:6028$1543_Y + end + attribute \src "ls180.v:6030.46-6030.99" + cell $and $and$ls180.v:6030$1544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6030$1544_Y + end + attribute \src "ls180.v:6030.45-6030.150" + cell $and $and$ls180.v:6030$1546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6030$1544_Y + connect \B $eq$ls180.v:6030$1545_Y + connect \Y $and$ls180.v:6030$1546_Y + end + attribute \src "ls180.v:6031.46-6031.102" + cell $and $and$ls180.v:6031$1548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6031$1547_Y + connect \Y $and$ls180.v:6031$1548_Y + end + attribute \src "ls180.v:6031.45-6031.153" + cell $and $and$ls180.v:6031$1550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6031$1548_Y + connect \B $eq$ls180.v:6031$1549_Y + connect \Y $and$ls180.v:6031$1550_Y + end + attribute \src "ls180.v:6033.46-6033.99" + cell $and $and$ls180.v:6033$1551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6033$1551_Y + end + attribute \src "ls180.v:6033.45-6033.150" + cell $and $and$ls180.v:6033$1553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6033$1551_Y + connect \B $eq$ls180.v:6033$1552_Y + connect \Y $and$ls180.v:6033$1553_Y + end + attribute \src "ls180.v:6034.46-6034.102" + cell $and $and$ls180.v:6034$1555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6034$1554_Y + connect \Y $and$ls180.v:6034$1555_Y + end + attribute \src "ls180.v:6034.45-6034.153" + cell $and $and$ls180.v:6034$1557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6034$1555_Y + connect \B $eq$ls180.v:6034$1556_Y + connect \Y $and$ls180.v:6034$1557_Y + end + attribute \src "ls180.v:6036.46-6036.99" + cell $and $and$ls180.v:6036$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6036$1558_Y + end + attribute \src "ls180.v:6036.45-6036.150" + cell $and $and$ls180.v:6036$1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6036$1558_Y + connect \B $eq$ls180.v:6036$1559_Y + connect \Y $and$ls180.v:6036$1560_Y + end + attribute \src "ls180.v:6037.46-6037.102" + cell $and $and$ls180.v:6037$1562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6037$1561_Y + connect \Y $and$ls180.v:6037$1562_Y + end + attribute \src "ls180.v:6037.45-6037.153" + cell $and $and$ls180.v:6037$1564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6037$1562_Y + connect \B $eq$ls180.v:6037$1563_Y + connect \Y $and$ls180.v:6037$1564_Y + end + attribute \src "ls180.v:6039.46-6039.99" + cell $and $and$ls180.v:6039$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6039$1565_Y + end + attribute \src "ls180.v:6039.45-6039.150" + cell $and $and$ls180.v:6039$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6039$1565_Y + connect \B $eq$ls180.v:6039$1566_Y + connect \Y $and$ls180.v:6039$1567_Y + end + attribute \src "ls180.v:6040.46-6040.102" + cell $and $and$ls180.v:6040$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6040$1568_Y + connect \Y $and$ls180.v:6040$1569_Y + end + attribute \src "ls180.v:6040.45-6040.153" + cell $and $and$ls180.v:6040$1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6040$1569_Y + connect \B $eq$ls180.v:6040$1570_Y + connect \Y $and$ls180.v:6040$1571_Y + end + attribute \src "ls180.v:6042.46-6042.99" + cell $and $and$ls180.v:6042$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6042$1572_Y + end + attribute \src "ls180.v:6042.45-6042.150" + cell $and $and$ls180.v:6042$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6042$1572_Y + connect \B $eq$ls180.v:6042$1573_Y + connect \Y $and$ls180.v:6042$1574_Y + end + attribute \src "ls180.v:6043.46-6043.102" + cell $and $and$ls180.v:6043$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6043$1575_Y + connect \Y $and$ls180.v:6043$1576_Y + end + attribute \src "ls180.v:6043.45-6043.153" + cell $and $and$ls180.v:6043$1578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6043$1576_Y + connect \B $eq$ls180.v:6043$1577_Y + connect \Y $and$ls180.v:6043$1578_Y + end + attribute \src "ls180.v:6045.46-6045.99" + cell $and $and$ls180.v:6045$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6045$1579_Y + end + attribute \src "ls180.v:6045.45-6045.150" + cell $and $and$ls180.v:6045$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6045$1579_Y + connect \B $eq$ls180.v:6045$1580_Y + connect \Y $and$ls180.v:6045$1581_Y + end + attribute \src "ls180.v:6046.46-6046.102" + cell $and $and$ls180.v:6046$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6046$1582_Y + connect \Y $and$ls180.v:6046$1583_Y + end + attribute \src "ls180.v:6046.45-6046.153" + cell $and $and$ls180.v:6046$1585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6046$1583_Y + connect \B $eq$ls180.v:6046$1584_Y + connect \Y $and$ls180.v:6046$1585_Y + end + attribute \src "ls180.v:6048.46-6048.99" + cell $and $and$ls180.v:6048$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6048$1586_Y + end + attribute \src "ls180.v:6048.45-6048.150" + cell $and $and$ls180.v:6048$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6048$1586_Y + connect \B $eq$ls180.v:6048$1587_Y + connect \Y $and$ls180.v:6048$1588_Y + end + attribute \src "ls180.v:6049.46-6049.102" + cell $and $and$ls180.v:6049$1590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6049$1589_Y + connect \Y $and$ls180.v:6049$1590_Y + end + attribute \src "ls180.v:6049.45-6049.153" + cell $and $and$ls180.v:6049$1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6049$1590_Y + connect \B $eq$ls180.v:6049$1591_Y + connect \Y $and$ls180.v:6049$1592_Y + end + attribute \src "ls180.v:6051.46-6051.99" + cell $and $and$ls180.v:6051$1593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6051$1593_Y + end + attribute \src "ls180.v:6051.45-6051.150" + cell $and $and$ls180.v:6051$1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6051$1593_Y + connect \B $eq$ls180.v:6051$1594_Y + connect \Y $and$ls180.v:6051$1595_Y + end + attribute \src "ls180.v:6052.46-6052.102" + cell $and $and$ls180.v:6052$1597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6052$1596_Y + connect \Y $and$ls180.v:6052$1597_Y + end + attribute \src "ls180.v:6052.45-6052.153" + cell $and $and$ls180.v:6052$1599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6052$1597_Y + connect \B $eq$ls180.v:6052$1598_Y + connect \Y $and$ls180.v:6052$1599_Y + end + attribute \src "ls180.v:6054.46-6054.99" + cell $and $and$ls180.v:6054$1600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6054$1600_Y + end + attribute \src "ls180.v:6054.45-6054.150" + cell $and $and$ls180.v:6054$1602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6054$1600_Y + connect \B $eq$ls180.v:6054$1601_Y + connect \Y $and$ls180.v:6054$1602_Y + end + attribute \src "ls180.v:6055.46-6055.102" + cell $and $and$ls180.v:6055$1604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6055$1603_Y + connect \Y $and$ls180.v:6055$1604_Y + end + attribute \src "ls180.v:6055.45-6055.153" + cell $and $and$ls180.v:6055$1606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6055$1604_Y + connect \B $eq$ls180.v:6055$1605_Y + connect \Y $and$ls180.v:6055$1606_Y + end + attribute \src "ls180.v:6057.46-6057.99" + cell $and $and$ls180.v:6057$1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6057$1607_Y + end + attribute \src "ls180.v:6057.45-6057.150" + cell $and $and$ls180.v:6057$1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6057$1607_Y + connect \B $eq$ls180.v:6057$1608_Y + connect \Y $and$ls180.v:6057$1609_Y + end + attribute \src "ls180.v:6058.46-6058.102" + cell $and $and$ls180.v:6058$1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6058$1610_Y + connect \Y $and$ls180.v:6058$1611_Y + end + attribute \src "ls180.v:6058.45-6058.153" + cell $and $and$ls180.v:6058$1613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6058$1611_Y + connect \B $eq$ls180.v:6058$1612_Y + connect \Y $and$ls180.v:6058$1613_Y + end + attribute \src "ls180.v:6060.42-6060.95" + cell $and $and$ls180.v:6060$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6060$1614_Y + end + attribute \src "ls180.v:6060.41-6060.146" + cell $and $and$ls180.v:6060$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6060$1614_Y + connect \B $eq$ls180.v:6060$1615_Y + connect \Y $and$ls180.v:6060$1616_Y + end + attribute \src "ls180.v:6061.42-6061.98" + cell $and $and$ls180.v:6061$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6061$1617_Y + connect \Y $and$ls180.v:6061$1618_Y + end + attribute \src "ls180.v:6061.41-6061.149" + cell $and $and$ls180.v:6061$1620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6061$1618_Y + connect \B $eq$ls180.v:6061$1619_Y + connect \Y $and$ls180.v:6061$1620_Y + end + attribute \src "ls180.v:6063.43-6063.96" + cell $and $and$ls180.v:6063$1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6063$1621_Y + end + attribute \src "ls180.v:6063.42-6063.147" + cell $and $and$ls180.v:6063$1623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6063$1621_Y + connect \B $eq$ls180.v:6063$1622_Y + connect \Y $and$ls180.v:6063$1623_Y + end + attribute \src "ls180.v:6064.43-6064.99" + cell $and $and$ls180.v:6064$1625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6064$1624_Y + connect \Y $and$ls180.v:6064$1625_Y + end + attribute \src "ls180.v:6064.42-6064.150" + cell $and $and$ls180.v:6064$1627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6064$1625_Y + connect \B $eq$ls180.v:6064$1626_Y + connect \Y $and$ls180.v:6064$1627_Y + end + attribute \src "ls180.v:6066.46-6066.99" + cell $and $and$ls180.v:6066$1628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6066$1628_Y + end + attribute \src "ls180.v:6066.45-6066.150" + cell $and $and$ls180.v:6066$1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6066$1628_Y + connect \B $eq$ls180.v:6066$1629_Y + connect \Y $and$ls180.v:6066$1630_Y + end + attribute \src "ls180.v:6067.46-6067.102" + cell $and $and$ls180.v:6067$1632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6067$1631_Y + connect \Y $and$ls180.v:6067$1632_Y + end + attribute \src "ls180.v:6067.45-6067.153" + cell $and $and$ls180.v:6067$1634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6067$1632_Y + connect \B $eq$ls180.v:6067$1633_Y + connect \Y $and$ls180.v:6067$1634_Y + end + attribute \src "ls180.v:6069.46-6069.99" + cell $and $and$ls180.v:6069$1635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6069$1635_Y + end + attribute \src "ls180.v:6069.45-6069.150" + cell $and $and$ls180.v:6069$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6069$1635_Y + connect \B $eq$ls180.v:6069$1636_Y + connect \Y $and$ls180.v:6069$1637_Y + end + attribute \src "ls180.v:6070.46-6070.102" + cell $and $and$ls180.v:6070$1639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6070$1638_Y + connect \Y $and$ls180.v:6070$1639_Y + end + attribute \src "ls180.v:6070.45-6070.153" + cell $and $and$ls180.v:6070$1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6070$1639_Y + connect \B $eq$ls180.v:6070$1640_Y + connect \Y $and$ls180.v:6070$1641_Y + end + attribute \src "ls180.v:6072.45-6072.98" + cell $and $and$ls180.v:6072$1642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6072$1642_Y + end + attribute \src "ls180.v:6072.44-6072.149" + cell $and $and$ls180.v:6072$1644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6072$1642_Y + connect \B $eq$ls180.v:6072$1643_Y + connect \Y $and$ls180.v:6072$1644_Y + end + attribute \src "ls180.v:6073.45-6073.101" + cell $and $and$ls180.v:6073$1646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6073$1645_Y + connect \Y $and$ls180.v:6073$1646_Y + end + attribute \src "ls180.v:6073.44-6073.152" + cell $and $and$ls180.v:6073$1648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6073$1646_Y + connect \B $eq$ls180.v:6073$1647_Y + connect \Y $and$ls180.v:6073$1648_Y + end + attribute \src "ls180.v:6075.45-6075.98" + cell $and $and$ls180.v:6075$1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6075$1649_Y + end + attribute \src "ls180.v:6075.44-6075.149" + cell $and $and$ls180.v:6075$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6075$1649_Y + connect \B $eq$ls180.v:6075$1650_Y + connect \Y $and$ls180.v:6075$1651_Y + end + attribute \src "ls180.v:6076.45-6076.101" + cell $and $and$ls180.v:6076$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6076$1652_Y + connect \Y $and$ls180.v:6076$1653_Y + end + attribute \src "ls180.v:6076.44-6076.152" + cell $and $and$ls180.v:6076$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6076$1653_Y + connect \B $eq$ls180.v:6076$1654_Y + connect \Y $and$ls180.v:6076$1655_Y + end + attribute \src "ls180.v:6078.45-6078.98" + cell $and $and$ls180.v:6078$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6078$1656_Y + end + attribute \src "ls180.v:6078.44-6078.149" + cell $and $and$ls180.v:6078$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6078$1656_Y + connect \B $eq$ls180.v:6078$1657_Y + connect \Y $and$ls180.v:6078$1658_Y + end + attribute \src "ls180.v:6079.45-6079.101" + cell $and $and$ls180.v:6079$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6079$1659_Y + connect \Y $and$ls180.v:6079$1660_Y + end + attribute \src "ls180.v:6079.44-6079.152" + cell $and $and$ls180.v:6079$1662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6079$1660_Y + connect \B $eq$ls180.v:6079$1661_Y + connect \Y $and$ls180.v:6079$1662_Y + end + attribute \src "ls180.v:6081.45-6081.98" + cell $and $and$ls180.v:6081$1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6081$1663_Y + end + attribute \src "ls180.v:6081.44-6081.149" + cell $and $and$ls180.v:6081$1665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6081$1663_Y + connect \B $eq$ls180.v:6081$1664_Y + connect \Y $and$ls180.v:6081$1665_Y + end + attribute \src "ls180.v:6082.45-6082.101" + cell $and $and$ls180.v:6082$1667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6082$1666_Y + connect \Y $and$ls180.v:6082$1667_Y + end + attribute \src "ls180.v:6082.44-6082.152" + cell $and $and$ls180.v:6082$1669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6082$1667_Y + connect \B $eq$ls180.v:6082$1668_Y + connect \Y $and$ls180.v:6082$1669_Y + end + attribute \src "ls180.v:6120.42-6120.95" + cell $and $and$ls180.v:6120$1671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6120$1671_Y + end + attribute \src "ls180.v:6120.41-6120.145" + cell $and $and$ls180.v:6120$1673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6120$1671_Y + connect \B $eq$ls180.v:6120$1672_Y + connect \Y $and$ls180.v:6120$1673_Y + end + attribute \src "ls180.v:6121.42-6121.98" + cell $and $and$ls180.v:6121$1675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6121$1674_Y + connect \Y $and$ls180.v:6121$1675_Y + end + attribute \src "ls180.v:6121.41-6121.148" + cell $and $and$ls180.v:6121$1677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6121$1675_Y + connect \B $eq$ls180.v:6121$1676_Y + connect \Y $and$ls180.v:6121$1677_Y + end + attribute \src "ls180.v:6123.42-6123.95" + cell $and $and$ls180.v:6123$1678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6123$1678_Y + end + attribute \src "ls180.v:6123.41-6123.145" + cell $and $and$ls180.v:6123$1680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6123$1678_Y + connect \B $eq$ls180.v:6123$1679_Y + connect \Y $and$ls180.v:6123$1680_Y + end + attribute \src "ls180.v:6124.42-6124.98" + cell $and $and$ls180.v:6124$1682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6124$1681_Y + connect \Y $and$ls180.v:6124$1682_Y + end + attribute \src "ls180.v:6124.41-6124.148" + cell $and $and$ls180.v:6124$1684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6124$1682_Y + connect \B $eq$ls180.v:6124$1683_Y + connect \Y $and$ls180.v:6124$1684_Y + end + attribute \src "ls180.v:6126.42-6126.95" + cell $and $and$ls180.v:6126$1685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6126$1685_Y + end + attribute \src "ls180.v:6126.41-6126.145" + cell $and $and$ls180.v:6126$1687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6126$1685_Y + connect \B $eq$ls180.v:6126$1686_Y + connect \Y $and$ls180.v:6126$1687_Y + end + attribute \src "ls180.v:6127.42-6127.98" + cell $and $and$ls180.v:6127$1689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6127$1688_Y + connect \Y $and$ls180.v:6127$1689_Y + end + attribute \src "ls180.v:6127.41-6127.148" + cell $and $and$ls180.v:6127$1691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6127$1689_Y + connect \B $eq$ls180.v:6127$1690_Y + connect \Y $and$ls180.v:6127$1691_Y + end + attribute \src "ls180.v:6129.42-6129.95" + cell $and $and$ls180.v:6129$1692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6129$1692_Y + end + attribute \src "ls180.v:6129.41-6129.145" + cell $and $and$ls180.v:6129$1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6129$1692_Y + connect \B $eq$ls180.v:6129$1693_Y + connect \Y $and$ls180.v:6129$1694_Y + end + attribute \src "ls180.v:6130.42-6130.98" + cell $and $and$ls180.v:6130$1696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6130$1695_Y + connect \Y $and$ls180.v:6130$1696_Y + end + attribute \src "ls180.v:6130.41-6130.148" + cell $and $and$ls180.v:6130$1698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6130$1696_Y + connect \B $eq$ls180.v:6130$1697_Y + connect \Y $and$ls180.v:6130$1698_Y + end + attribute \src "ls180.v:6132.42-6132.95" + cell $and $and$ls180.v:6132$1699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6132$1699_Y + end + attribute \src "ls180.v:6132.41-6132.145" + cell $and $and$ls180.v:6132$1701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6132$1699_Y + connect \B $eq$ls180.v:6132$1700_Y + connect \Y $and$ls180.v:6132$1701_Y + end + attribute \src "ls180.v:6133.42-6133.98" + cell $and $and$ls180.v:6133$1703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6133$1702_Y + connect \Y $and$ls180.v:6133$1703_Y + end + attribute \src "ls180.v:6133.41-6133.148" + cell $and $and$ls180.v:6133$1705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6133$1703_Y + connect \B $eq$ls180.v:6133$1704_Y + connect \Y $and$ls180.v:6133$1705_Y + end + attribute \src "ls180.v:6135.42-6135.95" + cell $and $and$ls180.v:6135$1706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6135$1706_Y + end + attribute \src "ls180.v:6135.41-6135.145" + cell $and $and$ls180.v:6135$1708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6135$1706_Y + connect \B $eq$ls180.v:6135$1707_Y + connect \Y $and$ls180.v:6135$1708_Y + end + attribute \src "ls180.v:6136.42-6136.98" + cell $and $and$ls180.v:6136$1710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6136$1709_Y + connect \Y $and$ls180.v:6136$1710_Y + end + attribute \src "ls180.v:6136.41-6136.148" + cell $and $and$ls180.v:6136$1712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6136$1710_Y + connect \B $eq$ls180.v:6136$1711_Y + connect \Y $and$ls180.v:6136$1712_Y + end + attribute \src "ls180.v:6138.42-6138.95" + cell $and $and$ls180.v:6138$1713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6138$1713_Y + end + attribute \src "ls180.v:6138.41-6138.145" + cell $and $and$ls180.v:6138$1715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6138$1713_Y + connect \B $eq$ls180.v:6138$1714_Y + connect \Y $and$ls180.v:6138$1715_Y + end + attribute \src "ls180.v:6139.42-6139.98" + cell $and $and$ls180.v:6139$1717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6139$1716_Y + connect \Y $and$ls180.v:6139$1717_Y + end + attribute \src "ls180.v:6139.41-6139.148" + cell $and $and$ls180.v:6139$1719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6139$1717_Y + connect \B $eq$ls180.v:6139$1718_Y + connect \Y $and$ls180.v:6139$1719_Y + end + attribute \src "ls180.v:6141.42-6141.95" + cell $and $and$ls180.v:6141$1720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6141$1720_Y + end + attribute \src "ls180.v:6141.41-6141.145" + cell $and $and$ls180.v:6141$1722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6141$1720_Y + connect \B $eq$ls180.v:6141$1721_Y + connect \Y $and$ls180.v:6141$1722_Y + end + attribute \src "ls180.v:6142.42-6142.98" + cell $and $and$ls180.v:6142$1724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6142$1723_Y + connect \Y $and$ls180.v:6142$1724_Y + end + attribute \src "ls180.v:6142.41-6142.148" + cell $and $and$ls180.v:6142$1726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6142$1724_Y + connect \B $eq$ls180.v:6142$1725_Y + connect \Y $and$ls180.v:6142$1726_Y + end + attribute \src "ls180.v:6144.44-6144.97" + cell $and $and$ls180.v:6144$1727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6144$1727_Y + end + attribute \src "ls180.v:6144.43-6144.147" + cell $and $and$ls180.v:6144$1729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6144$1727_Y + connect \B $eq$ls180.v:6144$1728_Y + connect \Y $and$ls180.v:6144$1729_Y + end + attribute \src "ls180.v:6145.44-6145.100" + cell $and $and$ls180.v:6145$1731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6145$1730_Y + connect \Y $and$ls180.v:6145$1731_Y + end + attribute \src "ls180.v:6145.43-6145.150" + cell $and $and$ls180.v:6145$1733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6145$1731_Y + connect \B $eq$ls180.v:6145$1732_Y + connect \Y $and$ls180.v:6145$1733_Y + end + attribute \src "ls180.v:6147.44-6147.97" + cell $and $and$ls180.v:6147$1734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6147$1734_Y + end + attribute \src "ls180.v:6147.43-6147.147" + cell $and $and$ls180.v:6147$1736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6147$1734_Y + connect \B $eq$ls180.v:6147$1735_Y + connect \Y $and$ls180.v:6147$1736_Y + end + attribute \src "ls180.v:6148.44-6148.100" + cell $and $and$ls180.v:6148$1738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6148$1737_Y + connect \Y $and$ls180.v:6148$1738_Y + end + attribute \src "ls180.v:6148.43-6148.150" + cell $and $and$ls180.v:6148$1740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6148$1738_Y + connect \B $eq$ls180.v:6148$1739_Y + connect \Y $and$ls180.v:6148$1740_Y + end + attribute \src "ls180.v:6150.44-6150.97" + cell $and $and$ls180.v:6150$1741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6150$1741_Y + end + attribute \src "ls180.v:6150.43-6150.148" + cell $and $and$ls180.v:6150$1743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6150$1741_Y + connect \B $eq$ls180.v:6150$1742_Y + connect \Y $and$ls180.v:6150$1743_Y + end + attribute \src "ls180.v:6151.44-6151.100" + cell $and $and$ls180.v:6151$1745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6151$1744_Y + connect \Y $and$ls180.v:6151$1745_Y + end + attribute \src "ls180.v:6151.43-6151.151" + cell $and $and$ls180.v:6151$1747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6151$1745_Y + connect \B $eq$ls180.v:6151$1746_Y + connect \Y $and$ls180.v:6151$1747_Y + end + attribute \src "ls180.v:6153.44-6153.97" + cell $and $and$ls180.v:6153$1748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6153$1748_Y + end + attribute \src "ls180.v:6153.43-6153.148" + cell $and $and$ls180.v:6153$1750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6153$1748_Y + connect \B $eq$ls180.v:6153$1749_Y + connect \Y $and$ls180.v:6153$1750_Y + end + attribute \src "ls180.v:6154.44-6154.100" + cell $and $and$ls180.v:6154$1752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6154$1751_Y + connect \Y $and$ls180.v:6154$1752_Y + end + attribute \src "ls180.v:6154.43-6154.151" + cell $and $and$ls180.v:6154$1754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6154$1752_Y + connect \B $eq$ls180.v:6154$1753_Y + connect \Y $and$ls180.v:6154$1754_Y + end + attribute \src "ls180.v:6156.44-6156.97" + cell $and $and$ls180.v:6156$1755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6156$1755_Y + end + attribute \src "ls180.v:6156.43-6156.148" + cell $and $and$ls180.v:6156$1757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6156$1755_Y + connect \B $eq$ls180.v:6156$1756_Y + connect \Y $and$ls180.v:6156$1757_Y + end + attribute \src "ls180.v:6157.44-6157.100" + cell $and $and$ls180.v:6157$1759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6157$1758_Y + connect \Y $and$ls180.v:6157$1759_Y + end + attribute \src "ls180.v:6157.43-6157.151" + cell $and $and$ls180.v:6157$1761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6157$1759_Y + connect \B $eq$ls180.v:6157$1760_Y + connect \Y $and$ls180.v:6157$1761_Y + end + attribute \src "ls180.v:6159.41-6159.94" + cell $and $and$ls180.v:6159$1762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6159$1762_Y + end + attribute \src "ls180.v:6159.40-6159.145" + cell $and $and$ls180.v:6159$1764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6159$1762_Y + connect \B $eq$ls180.v:6159$1763_Y + connect \Y $and$ls180.v:6159$1764_Y + end + attribute \src "ls180.v:6160.41-6160.97" + cell $and $and$ls180.v:6160$1766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6160$1765_Y + connect \Y $and$ls180.v:6160$1766_Y + end + attribute \src "ls180.v:6160.40-6160.148" + cell $and $and$ls180.v:6160$1768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6160$1766_Y + connect \B $eq$ls180.v:6160$1767_Y + connect \Y $and$ls180.v:6160$1768_Y + end + attribute \src "ls180.v:6162.42-6162.95" + cell $and $and$ls180.v:6162$1769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6162$1769_Y + end + attribute \src "ls180.v:6162.41-6162.146" + cell $and $and$ls180.v:6162$1771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6162$1769_Y + connect \B $eq$ls180.v:6162$1770_Y + connect \Y $and$ls180.v:6162$1771_Y + end + attribute \src "ls180.v:6163.42-6163.98" + cell $and $and$ls180.v:6163$1773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6163$1772_Y + connect \Y $and$ls180.v:6163$1773_Y + end + attribute \src "ls180.v:6163.41-6163.149" + cell $and $and$ls180.v:6163$1775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6163$1773_Y + connect \B $eq$ls180.v:6163$1774_Y + connect \Y $and$ls180.v:6163$1775_Y + end + attribute \src "ls180.v:6165.44-6165.97" + cell $and $and$ls180.v:6165$1776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6165$1776_Y + end + attribute \src "ls180.v:6165.43-6165.148" + cell $and $and$ls180.v:6165$1778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6165$1776_Y + connect \B $eq$ls180.v:6165$1777_Y + connect \Y $and$ls180.v:6165$1778_Y + end + attribute \src "ls180.v:6166.44-6166.100" + cell $and $and$ls180.v:6166$1780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6166$1779_Y + connect \Y $and$ls180.v:6166$1780_Y + end + attribute \src "ls180.v:6166.43-6166.151" + cell $and $and$ls180.v:6166$1782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6166$1780_Y + connect \B $eq$ls180.v:6166$1781_Y + connect \Y $and$ls180.v:6166$1782_Y + end + attribute \src "ls180.v:6168.44-6168.97" + cell $and $and$ls180.v:6168$1783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6168$1783_Y + end + attribute \src "ls180.v:6168.43-6168.148" + cell $and $and$ls180.v:6168$1785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6168$1783_Y + connect \B $eq$ls180.v:6168$1784_Y + connect \Y $and$ls180.v:6168$1785_Y + end + attribute \src "ls180.v:6169.44-6169.100" + cell $and $and$ls180.v:6169$1787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6169$1786_Y + connect \Y $and$ls180.v:6169$1787_Y + end + attribute \src "ls180.v:6169.43-6169.151" + cell $and $and$ls180.v:6169$1789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6169$1787_Y + connect \B $eq$ls180.v:6169$1788_Y + connect \Y $and$ls180.v:6169$1789_Y + end + attribute \src "ls180.v:6171.44-6171.97" + cell $and $and$ls180.v:6171$1790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6171$1790_Y + end + attribute \src "ls180.v:6171.43-6171.148" + cell $and $and$ls180.v:6171$1792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6171$1790_Y + connect \B $eq$ls180.v:6171$1791_Y + connect \Y $and$ls180.v:6171$1792_Y + end + attribute \src "ls180.v:6172.44-6172.100" + cell $and $and$ls180.v:6172$1794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6172$1793_Y + connect \Y $and$ls180.v:6172$1794_Y + end + attribute \src "ls180.v:6172.43-6172.151" + cell $and $and$ls180.v:6172$1796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6172$1794_Y + connect \B $eq$ls180.v:6172$1795_Y + connect \Y $and$ls180.v:6172$1796_Y + end + attribute \src "ls180.v:6174.44-6174.97" + cell $and $and$ls180.v:6174$1797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6174$1797_Y + end + attribute \src "ls180.v:6174.43-6174.148" + cell $and $and$ls180.v:6174$1799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6174$1797_Y + connect \B $eq$ls180.v:6174$1798_Y + connect \Y $and$ls180.v:6174$1799_Y + end + attribute \src "ls180.v:6175.44-6175.100" + cell $and $and$ls180.v:6175$1801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6175$1800_Y + connect \Y $and$ls180.v:6175$1801_Y + end + attribute \src "ls180.v:6175.43-6175.151" + cell $and $and$ls180.v:6175$1803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6175$1801_Y + connect \B $eq$ls180.v:6175$1802_Y + connect \Y $and$ls180.v:6175$1803_Y + end + attribute \src "ls180.v:6199.44-6199.97" + cell $and $and$ls180.v:6199$1805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6199$1805_Y + end + attribute \src "ls180.v:6199.43-6199.147" + cell $and $and$ls180.v:6199$1807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6199$1805_Y + connect \B $eq$ls180.v:6199$1806_Y + connect \Y $and$ls180.v:6199$1807_Y + end + attribute \src "ls180.v:6200.44-6200.100" + cell $and $and$ls180.v:6200$1809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6200$1808_Y + connect \Y $and$ls180.v:6200$1809_Y + end + attribute \src "ls180.v:6200.43-6200.150" + cell $and $and$ls180.v:6200$1811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6200$1809_Y + connect \B $eq$ls180.v:6200$1810_Y + connect \Y $and$ls180.v:6200$1811_Y + end + attribute \src "ls180.v:6202.49-6202.102" + cell $and $and$ls180.v:6202$1812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6202$1812_Y + end + attribute \src "ls180.v:6202.48-6202.152" + cell $and $and$ls180.v:6202$1814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6202$1812_Y + connect \B $eq$ls180.v:6202$1813_Y + connect \Y $and$ls180.v:6202$1814_Y + end + attribute \src "ls180.v:6203.49-6203.105" + cell $and $and$ls180.v:6203$1816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6203$1815_Y + connect \Y $and$ls180.v:6203$1816_Y + end + attribute \src "ls180.v:6203.48-6203.155" + cell $and $and$ls180.v:6203$1818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6203$1816_Y + connect \B $eq$ls180.v:6203$1817_Y + connect \Y $and$ls180.v:6203$1818_Y + end + attribute \src "ls180.v:6205.49-6205.102" + cell $and $and$ls180.v:6205$1819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6205$1819_Y + end + attribute \src "ls180.v:6205.48-6205.152" + cell $and $and$ls180.v:6205$1821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6205$1819_Y + connect \B $eq$ls180.v:6205$1820_Y + connect \Y $and$ls180.v:6205$1821_Y + end + attribute \src "ls180.v:6206.49-6206.105" + cell $and $and$ls180.v:6206$1823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6206$1822_Y + connect \Y $and$ls180.v:6206$1823_Y + end + attribute \src "ls180.v:6206.48-6206.155" + cell $and $and$ls180.v:6206$1825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6206$1823_Y + connect \B $eq$ls180.v:6206$1824_Y + connect \Y $and$ls180.v:6206$1825_Y + end + attribute \src "ls180.v:6208.42-6208.95" + cell $and $and$ls180.v:6208$1826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6208$1826_Y + end + attribute \src "ls180.v:6208.41-6208.145" + cell $and $and$ls180.v:6208$1828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6208$1826_Y + connect \B $eq$ls180.v:6208$1827_Y + connect \Y $and$ls180.v:6208$1828_Y + end + attribute \src "ls180.v:6209.42-6209.98" + cell $and $and$ls180.v:6209$1830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6209$1829_Y + connect \Y $and$ls180.v:6209$1830_Y + end + attribute \src "ls180.v:6209.41-6209.148" + cell $and $and$ls180.v:6209$1832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6209$1830_Y + connect \B $eq$ls180.v:6209$1831_Y + connect \Y $and$ls180.v:6209$1832_Y + end + attribute \src "ls180.v:6216.46-6216.99" + cell $and $and$ls180.v:6216$1834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6216$1834_Y + end + attribute \src "ls180.v:6216.45-6216.149" + cell $and $and$ls180.v:6216$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6216$1834_Y + connect \B $eq$ls180.v:6216$1835_Y + connect \Y $and$ls180.v:6216$1836_Y + end + attribute \src "ls180.v:6217.46-6217.102" + cell $and $and$ls180.v:6217$1838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6217$1837_Y + connect \Y $and$ls180.v:6217$1838_Y + end + attribute \src "ls180.v:6217.45-6217.152" + cell $and $and$ls180.v:6217$1840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6217$1838_Y + connect \B $eq$ls180.v:6217$1839_Y + connect \Y $and$ls180.v:6217$1840_Y + end + attribute \src "ls180.v:6219.50-6219.103" + cell $and $and$ls180.v:6219$1841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6219$1841_Y + end + attribute \src "ls180.v:6219.49-6219.153" + cell $and $and$ls180.v:6219$1843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6219$1841_Y + connect \B $eq$ls180.v:6219$1842_Y + connect \Y $and$ls180.v:6219$1843_Y + end + attribute \src "ls180.v:6220.50-6220.106" + cell $and $and$ls180.v:6220$1845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6220$1844_Y + connect \Y $and$ls180.v:6220$1845_Y + end + attribute \src "ls180.v:6220.49-6220.156" + cell $and $and$ls180.v:6220$1847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6220$1845_Y + connect \B $eq$ls180.v:6220$1846_Y + connect \Y $and$ls180.v:6220$1847_Y + end + attribute \src "ls180.v:6222.40-6222.93" + cell $and $and$ls180.v:6222$1848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6222$1848_Y + end + attribute \src "ls180.v:6222.39-6222.143" + cell $and $and$ls180.v:6222$1850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6222$1848_Y + connect \B $eq$ls180.v:6222$1849_Y + connect \Y $and$ls180.v:6222$1850_Y + end + attribute \src "ls180.v:6223.40-6223.96" + cell $and $and$ls180.v:6223$1852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6223$1851_Y + connect \Y $and$ls180.v:6223$1852_Y + end + attribute \src "ls180.v:6223.39-6223.146" + cell $and $and$ls180.v:6223$1854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6223$1852_Y + connect \B $eq$ls180.v:6223$1853_Y + connect \Y $and$ls180.v:6223$1854_Y + end + attribute \src "ls180.v:6225.50-6225.103" + cell $and $and$ls180.v:6225$1855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6225$1855_Y + end + attribute \src "ls180.v:6225.49-6225.153" + cell $and $and$ls180.v:6225$1857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6225$1855_Y + connect \B $eq$ls180.v:6225$1856_Y + connect \Y $and$ls180.v:6225$1857_Y + end + attribute \src "ls180.v:6226.50-6226.106" + cell $and $and$ls180.v:6226$1859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6226$1858_Y + connect \Y $and$ls180.v:6226$1859_Y + end + attribute \src "ls180.v:6226.49-6226.156" + cell $and $and$ls180.v:6226$1861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6226$1859_Y + connect \B $eq$ls180.v:6226$1860_Y + connect \Y $and$ls180.v:6226$1861_Y + end + attribute \src "ls180.v:6228.50-6228.103" + cell $and $and$ls180.v:6228$1862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6228$1862_Y + end + attribute \src "ls180.v:6228.49-6228.153" + cell $and $and$ls180.v:6228$1864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6228$1862_Y + connect \B $eq$ls180.v:6228$1863_Y + connect \Y $and$ls180.v:6228$1864_Y + end + attribute \src "ls180.v:6229.50-6229.106" + cell $and $and$ls180.v:6229$1866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6229$1865_Y + connect \Y $and$ls180.v:6229$1866_Y + end + attribute \src "ls180.v:6229.49-6229.156" + cell $and $and$ls180.v:6229$1868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6229$1866_Y + connect \B $eq$ls180.v:6229$1867_Y + connect \Y $and$ls180.v:6229$1868_Y + end + attribute \src "ls180.v:6231.51-6231.104" + cell $and $and$ls180.v:6231$1869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6231$1869_Y + end + attribute \src "ls180.v:6231.50-6231.154" + cell $and $and$ls180.v:6231$1871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6231$1869_Y + connect \B $eq$ls180.v:6231$1870_Y + connect \Y $and$ls180.v:6231$1871_Y + end + attribute \src "ls180.v:6232.51-6232.107" + cell $and $and$ls180.v:6232$1873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6232$1872_Y + connect \Y $and$ls180.v:6232$1873_Y + end + attribute \src "ls180.v:6232.50-6232.157" + cell $and $and$ls180.v:6232$1875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6232$1873_Y + connect \B $eq$ls180.v:6232$1874_Y + connect \Y $and$ls180.v:6232$1875_Y + end + attribute \src "ls180.v:6234.49-6234.102" + cell $and $and$ls180.v:6234$1876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6234$1876_Y + end + attribute \src "ls180.v:6234.48-6234.152" + cell $and $and$ls180.v:6234$1878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6234$1876_Y + connect \B $eq$ls180.v:6234$1877_Y + connect \Y $and$ls180.v:6234$1878_Y + end + attribute \src "ls180.v:6235.49-6235.105" + cell $and $and$ls180.v:6235$1880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6235$1879_Y + connect \Y $and$ls180.v:6235$1880_Y + end + attribute \src "ls180.v:6235.48-6235.155" + cell $and $and$ls180.v:6235$1882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6235$1880_Y + connect \B $eq$ls180.v:6235$1881_Y + connect \Y $and$ls180.v:6235$1882_Y + end + attribute \src "ls180.v:6237.49-6237.102" + cell $and $and$ls180.v:6237$1883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6237$1883_Y + end + attribute \src "ls180.v:6237.48-6237.152" + cell $and $and$ls180.v:6237$1885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6237$1883_Y + connect \B $eq$ls180.v:6237$1884_Y + connect \Y $and$ls180.v:6237$1885_Y + end + attribute \src "ls180.v:6238.49-6238.105" + cell $and $and$ls180.v:6238$1887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6238$1886_Y + connect \Y $and$ls180.v:6238$1887_Y + end + attribute \src "ls180.v:6238.48-6238.155" + cell $and $and$ls180.v:6238$1889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6238$1887_Y + connect \B $eq$ls180.v:6238$1888_Y + connect \Y $and$ls180.v:6238$1889_Y + end + attribute \src "ls180.v:6240.49-6240.102" + cell $and $and$ls180.v:6240$1890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6240$1890_Y + end + attribute \src "ls180.v:6240.48-6240.152" + cell $and $and$ls180.v:6240$1892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6240$1890_Y + connect \B $eq$ls180.v:6240$1891_Y + connect \Y $and$ls180.v:6240$1892_Y + end + attribute \src "ls180.v:6241.49-6241.105" + cell $and $and$ls180.v:6241$1894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6241$1893_Y + connect \Y $and$ls180.v:6241$1894_Y + end + attribute \src "ls180.v:6241.48-6241.155" + cell $and $and$ls180.v:6241$1896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6241$1894_Y + connect \B $eq$ls180.v:6241$1895_Y + connect \Y $and$ls180.v:6241$1896_Y + end + attribute \src "ls180.v:6243.49-6243.102" + cell $and $and$ls180.v:6243$1897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6243$1897_Y + end + attribute \src "ls180.v:6243.48-6243.152" + cell $and $and$ls180.v:6243$1899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6243$1897_Y + connect \B $eq$ls180.v:6243$1898_Y + connect \Y $and$ls180.v:6243$1899_Y + end + attribute \src "ls180.v:6244.49-6244.105" + cell $and $and$ls180.v:6244$1901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6244$1900_Y + connect \Y $and$ls180.v:6244$1901_Y + end + attribute \src "ls180.v:6244.48-6244.155" + cell $and $and$ls180.v:6244$1903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6244$1901_Y + connect \B $eq$ls180.v:6244$1902_Y + connect \Y $and$ls180.v:6244$1903_Y + end + attribute \src "ls180.v:6261.42-6261.97" + cell $and $and$ls180.v:6261$1905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6261$1905_Y + end + attribute \src "ls180.v:6261.41-6261.148" + cell $and $and$ls180.v:6261$1907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6261$1905_Y + connect \B $eq$ls180.v:6261$1906_Y + connect \Y $and$ls180.v:6261$1907_Y + end + attribute \src "ls180.v:6262.42-6262.100" + cell $and $and$ls180.v:6262$1909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6262$1908_Y + connect \Y $and$ls180.v:6262$1909_Y + end + attribute \src "ls180.v:6262.41-6262.151" + cell $and $and$ls180.v:6262$1911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6262$1909_Y + connect \B $eq$ls180.v:6262$1910_Y + connect \Y $and$ls180.v:6262$1911_Y + end + attribute \src "ls180.v:6264.42-6264.97" + cell $and $and$ls180.v:6264$1912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6264$1912_Y + end + attribute \src "ls180.v:6264.41-6264.148" + cell $and $and$ls180.v:6264$1914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6264$1912_Y + connect \B $eq$ls180.v:6264$1913_Y + connect \Y $and$ls180.v:6264$1914_Y + end + attribute \src "ls180.v:6265.42-6265.100" + cell $and $and$ls180.v:6265$1916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6265$1915_Y + connect \Y $and$ls180.v:6265$1916_Y + end + attribute \src "ls180.v:6265.41-6265.151" + cell $and $and$ls180.v:6265$1918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6265$1916_Y + connect \B $eq$ls180.v:6265$1917_Y + connect \Y $and$ls180.v:6265$1918_Y + end + attribute \src "ls180.v:6267.40-6267.95" + cell $and $and$ls180.v:6267$1919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6267$1919_Y + end + attribute \src "ls180.v:6267.39-6267.146" + cell $and $and$ls180.v:6267$1921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6267$1919_Y + connect \B $eq$ls180.v:6267$1920_Y + connect \Y $and$ls180.v:6267$1921_Y + end + attribute \src "ls180.v:6268.40-6268.98" + cell $and $and$ls180.v:6268$1923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6268$1922_Y + connect \Y $and$ls180.v:6268$1923_Y + end + attribute \src "ls180.v:6268.39-6268.149" + cell $and $and$ls180.v:6268$1925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6268$1923_Y + connect \B $eq$ls180.v:6268$1924_Y + connect \Y $and$ls180.v:6268$1925_Y + end + attribute \src "ls180.v:6270.39-6270.94" + cell $and $and$ls180.v:6270$1926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6270$1926_Y + end + attribute \src "ls180.v:6270.38-6270.145" + cell $and $and$ls180.v:6270$1928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6270$1926_Y + connect \B $eq$ls180.v:6270$1927_Y + connect \Y $and$ls180.v:6270$1928_Y + end + attribute \src "ls180.v:6271.39-6271.97" + cell $and $and$ls180.v:6271$1930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6271$1929_Y + connect \Y $and$ls180.v:6271$1930_Y + end + attribute \src "ls180.v:6271.38-6271.148" + cell $and $and$ls180.v:6271$1932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6271$1930_Y + connect \B $eq$ls180.v:6271$1931_Y + connect \Y $and$ls180.v:6271$1932_Y + end + attribute \src "ls180.v:6273.38-6273.93" + cell $and $and$ls180.v:6273$1933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6273$1933_Y + end + attribute \src "ls180.v:6273.37-6273.144" + cell $and $and$ls180.v:6273$1935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6273$1933_Y + connect \B $eq$ls180.v:6273$1934_Y + connect \Y $and$ls180.v:6273$1935_Y + end + attribute \src "ls180.v:6274.38-6274.96" + cell $and $and$ls180.v:6274$1937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6274$1936_Y + connect \Y $and$ls180.v:6274$1937_Y + end + attribute \src "ls180.v:6274.37-6274.147" + cell $and $and$ls180.v:6274$1939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6274$1937_Y + connect \B $eq$ls180.v:6274$1938_Y + connect \Y $and$ls180.v:6274$1939_Y + end + attribute \src "ls180.v:6276.37-6276.92" + cell $and $and$ls180.v:6276$1940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6276$1940_Y + end + attribute \src "ls180.v:6276.36-6276.143" + cell $and $and$ls180.v:6276$1942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6276$1940_Y + connect \B $eq$ls180.v:6276$1941_Y + connect \Y $and$ls180.v:6276$1942_Y + end + attribute \src "ls180.v:6277.37-6277.95" + cell $and $and$ls180.v:6277$1944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6277$1943_Y + connect \Y $and$ls180.v:6277$1944_Y + end + attribute \src "ls180.v:6277.36-6277.146" + cell $and $and$ls180.v:6277$1946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6277$1944_Y + connect \B $eq$ls180.v:6277$1945_Y + connect \Y $and$ls180.v:6277$1946_Y + end + attribute \src "ls180.v:6279.43-6279.98" + cell $and $and$ls180.v:6279$1947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6279$1947_Y + end + attribute \src "ls180.v:6279.42-6279.149" + cell $and $and$ls180.v:6279$1949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6279$1947_Y + connect \B $eq$ls180.v:6279$1948_Y + connect \Y $and$ls180.v:6279$1949_Y + end + attribute \src "ls180.v:6280.43-6280.101" + cell $and $and$ls180.v:6280$1951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6280$1950_Y + connect \Y $and$ls180.v:6280$1951_Y + end + attribute \src "ls180.v:6280.42-6280.152" + cell $and $and$ls180.v:6280$1953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6280$1951_Y + connect \B $eq$ls180.v:6280$1952_Y + connect \Y $and$ls180.v:6280$1953_Y + end + attribute \src "ls180.v:6301.42-6301.97" + cell $and $and$ls180.v:6301$1956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6301$1956_Y + end + attribute \src "ls180.v:6301.41-6301.148" + cell $and $and$ls180.v:6301$1958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6301$1956_Y + connect \B $eq$ls180.v:6301$1957_Y + connect \Y $and$ls180.v:6301$1958_Y + end + attribute \src "ls180.v:6302.42-6302.100" + cell $and $and$ls180.v:6302$1960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6302$1959_Y + connect \Y $and$ls180.v:6302$1960_Y + end + attribute \src "ls180.v:6302.41-6302.151" + cell $and $and$ls180.v:6302$1962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6302$1960_Y + connect \B $eq$ls180.v:6302$1961_Y + connect \Y $and$ls180.v:6302$1962_Y + end + attribute \src "ls180.v:6304.42-6304.97" + cell $and $and$ls180.v:6304$1963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6304$1963_Y + end + attribute \src "ls180.v:6304.41-6304.148" + cell $and $and$ls180.v:6304$1965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6304$1963_Y + connect \B $eq$ls180.v:6304$1964_Y + connect \Y $and$ls180.v:6304$1965_Y + end + attribute \src "ls180.v:6305.42-6305.100" + cell $and $and$ls180.v:6305$1967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6305$1966_Y + connect \Y $and$ls180.v:6305$1967_Y + end + attribute \src "ls180.v:6305.41-6305.151" + cell $and $and$ls180.v:6305$1969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6305$1967_Y + connect \B $eq$ls180.v:6305$1968_Y + connect \Y $and$ls180.v:6305$1969_Y + end + attribute \src "ls180.v:6307.40-6307.95" + cell $and $and$ls180.v:6307$1970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6307$1970_Y + end + attribute \src "ls180.v:6307.39-6307.146" + cell $and $and$ls180.v:6307$1972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6307$1970_Y + connect \B $eq$ls180.v:6307$1971_Y + connect \Y $and$ls180.v:6307$1972_Y + end + attribute \src "ls180.v:6308.40-6308.98" + cell $and $and$ls180.v:6308$1974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6308$1973_Y + connect \Y $and$ls180.v:6308$1974_Y + end + attribute \src "ls180.v:6308.39-6308.149" + cell $and $and$ls180.v:6308$1976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6308$1974_Y + connect \B $eq$ls180.v:6308$1975_Y + connect \Y $and$ls180.v:6308$1976_Y + end + attribute \src "ls180.v:6310.39-6310.94" + cell $and $and$ls180.v:6310$1977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6310$1977_Y + end + attribute \src "ls180.v:6310.38-6310.145" + cell $and $and$ls180.v:6310$1979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6310$1977_Y + connect \B $eq$ls180.v:6310$1978_Y + connect \Y $and$ls180.v:6310$1979_Y + end + attribute \src "ls180.v:6311.39-6311.97" + cell $and $and$ls180.v:6311$1981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6311$1980_Y + connect \Y $and$ls180.v:6311$1981_Y + end + attribute \src "ls180.v:6311.38-6311.148" + cell $and $and$ls180.v:6311$1983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6311$1981_Y + connect \B $eq$ls180.v:6311$1982_Y + connect \Y $and$ls180.v:6311$1983_Y + end + attribute \src "ls180.v:6313.38-6313.93" + cell $and $and$ls180.v:6313$1984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6313$1984_Y + end + attribute \src "ls180.v:6313.37-6313.144" + cell $and $and$ls180.v:6313$1986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6313$1984_Y + connect \B $eq$ls180.v:6313$1985_Y + connect \Y $and$ls180.v:6313$1986_Y + end + attribute \src "ls180.v:6314.38-6314.96" + cell $and $and$ls180.v:6314$1988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6314$1987_Y + connect \Y $and$ls180.v:6314$1988_Y + end + attribute \src "ls180.v:6314.37-6314.147" + cell $and $and$ls180.v:6314$1990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6314$1988_Y + connect \B $eq$ls180.v:6314$1989_Y + connect \Y $and$ls180.v:6314$1990_Y + end + attribute \src "ls180.v:6316.37-6316.92" + cell $and $and$ls180.v:6316$1991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6316$1991_Y + end + attribute \src "ls180.v:6316.36-6316.143" + cell $and $and$ls180.v:6316$1993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6316$1991_Y + connect \B $eq$ls180.v:6316$1992_Y + connect \Y $and$ls180.v:6316$1993_Y + end + attribute \src "ls180.v:6317.37-6317.95" + cell $and $and$ls180.v:6317$1995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6317$1994_Y + connect \Y $and$ls180.v:6317$1995_Y + end + attribute \src "ls180.v:6317.36-6317.146" + cell $and $and$ls180.v:6317$1997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6317$1995_Y + connect \B $eq$ls180.v:6317$1996_Y + connect \Y $and$ls180.v:6317$1997_Y + end + attribute \src "ls180.v:6319.43-6319.98" + cell $and $and$ls180.v:6319$1998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6319$1998_Y + end + attribute \src "ls180.v:6319.42-6319.149" + cell $and $and$ls180.v:6319$2000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6319$1998_Y + connect \B $eq$ls180.v:6319$1999_Y + connect \Y $and$ls180.v:6319$2000_Y + end + attribute \src "ls180.v:6320.43-6320.101" + cell $and $and$ls180.v:6320$2002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6320$2001_Y + connect \Y $and$ls180.v:6320$2002_Y + end + attribute \src "ls180.v:6320.42-6320.152" + cell $and $and$ls180.v:6320$2004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6320$2002_Y + connect \B $eq$ls180.v:6320$2003_Y + connect \Y $and$ls180.v:6320$2004_Y + end + attribute \src "ls180.v:6322.46-6322.101" + cell $and $and$ls180.v:6322$2005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6322$2005_Y + end + attribute \src "ls180.v:6322.45-6322.152" + cell $and $and$ls180.v:6322$2007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6322$2005_Y + connect \B $eq$ls180.v:6322$2006_Y + connect \Y $and$ls180.v:6322$2007_Y + end + attribute \src "ls180.v:6323.46-6323.104" + cell $and $and$ls180.v:6323$2009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6323$2008_Y + connect \Y $and$ls180.v:6323$2009_Y + end + attribute \src "ls180.v:6323.45-6323.155" + cell $and $and$ls180.v:6323$2011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6323$2009_Y + connect \B $eq$ls180.v:6323$2010_Y + connect \Y $and$ls180.v:6323$2011_Y + end + attribute \src "ls180.v:6325.46-6325.101" + cell $and $and$ls180.v:6325$2012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6325$2012_Y + end + attribute \src "ls180.v:6325.45-6325.152" + cell $and $and$ls180.v:6325$2014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6325$2012_Y + connect \B $eq$ls180.v:6325$2013_Y + connect \Y $and$ls180.v:6325$2014_Y + end + attribute \src "ls180.v:6326.46-6326.104" + cell $and $and$ls180.v:6326$2016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6326$2015_Y + connect \Y $and$ls180.v:6326$2016_Y + end + attribute \src "ls180.v:6326.45-6326.155" + cell $and $and$ls180.v:6326$2018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6326$2016_Y + connect \B $eq$ls180.v:6326$2017_Y + connect \Y $and$ls180.v:6326$2018_Y + end + attribute \src "ls180.v:6349.39-6349.94" + cell $and $and$ls180.v:6349$2021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6349$2021_Y + end + attribute \src "ls180.v:6349.38-6349.145" + cell $and $and$ls180.v:6349$2023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6349$2021_Y + connect \B $eq$ls180.v:6349$2022_Y + connect \Y $and$ls180.v:6349$2023_Y + end + attribute \src "ls180.v:6350.39-6350.97" + cell $and $and$ls180.v:6350$2025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6350$2024_Y + connect \Y $and$ls180.v:6350$2025_Y + end + attribute \src "ls180.v:6350.38-6350.148" + cell $and $and$ls180.v:6350$2027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6350$2025_Y + connect \B $eq$ls180.v:6350$2026_Y + connect \Y $and$ls180.v:6350$2027_Y + end + attribute \src "ls180.v:6352.39-6352.94" + cell $and $and$ls180.v:6352$2028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6352$2028_Y + end + attribute \src "ls180.v:6352.38-6352.145" + cell $and $and$ls180.v:6352$2030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6352$2028_Y + connect \B $eq$ls180.v:6352$2029_Y + connect \Y $and$ls180.v:6352$2030_Y + end + attribute \src "ls180.v:6353.39-6353.97" + cell $and $and$ls180.v:6353$2032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6353$2031_Y + connect \Y $and$ls180.v:6353$2032_Y + end + attribute \src "ls180.v:6353.38-6353.148" + cell $and $and$ls180.v:6353$2034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6353$2032_Y + connect \B $eq$ls180.v:6353$2033_Y + connect \Y $and$ls180.v:6353$2034_Y + end + attribute \src "ls180.v:6355.39-6355.94" + cell $and $and$ls180.v:6355$2035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6355$2035_Y + end + attribute \src "ls180.v:6355.38-6355.145" + cell $and $and$ls180.v:6355$2037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6355$2035_Y + connect \B $eq$ls180.v:6355$2036_Y + connect \Y $and$ls180.v:6355$2037_Y + end + attribute \src "ls180.v:6356.39-6356.97" + cell $and $and$ls180.v:6356$2039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6356$2038_Y + connect \Y $and$ls180.v:6356$2039_Y + end + attribute \src "ls180.v:6356.38-6356.148" + cell $and $and$ls180.v:6356$2041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6356$2039_Y + connect \B $eq$ls180.v:6356$2040_Y + connect \Y $and$ls180.v:6356$2041_Y + end + attribute \src "ls180.v:6358.39-6358.94" + cell $and $and$ls180.v:6358$2042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6358$2042_Y + end + attribute \src "ls180.v:6358.38-6358.145" + cell $and $and$ls180.v:6358$2044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6358$2042_Y + connect \B $eq$ls180.v:6358$2043_Y + connect \Y $and$ls180.v:6358$2044_Y + end + attribute \src "ls180.v:6359.39-6359.97" + cell $and $and$ls180.v:6359$2046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6359$2045_Y + connect \Y $and$ls180.v:6359$2046_Y + end + attribute \src "ls180.v:6359.38-6359.148" + cell $and $and$ls180.v:6359$2048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6359$2046_Y + connect \B $eq$ls180.v:6359$2047_Y + connect \Y $and$ls180.v:6359$2048_Y + end + attribute \src "ls180.v:6361.41-6361.96" + cell $and $and$ls180.v:6361$2049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6361$2049_Y + end + attribute \src "ls180.v:6361.40-6361.147" + cell $and $and$ls180.v:6361$2051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6361$2049_Y + connect \B $eq$ls180.v:6361$2050_Y + connect \Y $and$ls180.v:6361$2051_Y + end + attribute \src "ls180.v:6362.41-6362.99" + cell $and $and$ls180.v:6362$2053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6362$2052_Y + connect \Y $and$ls180.v:6362$2053_Y + end + attribute \src "ls180.v:6362.40-6362.150" + cell $and $and$ls180.v:6362$2055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6362$2053_Y + connect \B $eq$ls180.v:6362$2054_Y + connect \Y $and$ls180.v:6362$2055_Y + end + attribute \src "ls180.v:6364.41-6364.96" + cell $and $and$ls180.v:6364$2056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6364$2056_Y + end + attribute \src "ls180.v:6364.40-6364.147" + cell $and $and$ls180.v:6364$2058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6364$2056_Y + connect \B $eq$ls180.v:6364$2057_Y + connect \Y $and$ls180.v:6364$2058_Y + end + attribute \src "ls180.v:6365.41-6365.99" + cell $and $and$ls180.v:6365$2060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6365$2059_Y + connect \Y $and$ls180.v:6365$2060_Y + end + attribute \src "ls180.v:6365.40-6365.150" + cell $and $and$ls180.v:6365$2062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6365$2060_Y + connect \B $eq$ls180.v:6365$2061_Y + connect \Y $and$ls180.v:6365$2062_Y + end + attribute \src "ls180.v:6367.41-6367.96" + cell $and $and$ls180.v:6367$2063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6367$2063_Y + end + attribute \src "ls180.v:6367.40-6367.147" + cell $and $and$ls180.v:6367$2065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6367$2063_Y + connect \B $eq$ls180.v:6367$2064_Y + connect \Y $and$ls180.v:6367$2065_Y + end + attribute \src "ls180.v:6368.41-6368.99" + cell $and $and$ls180.v:6368$2067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6368$2066_Y + connect \Y $and$ls180.v:6368$2067_Y + end + attribute \src "ls180.v:6368.40-6368.150" + cell $and $and$ls180.v:6368$2069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6368$2067_Y + connect \B $eq$ls180.v:6368$2068_Y + connect \Y $and$ls180.v:6368$2069_Y + end + attribute \src "ls180.v:6370.41-6370.96" + cell $and $and$ls180.v:6370$2070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6370$2070_Y + end + attribute \src "ls180.v:6370.40-6370.147" + cell $and $and$ls180.v:6370$2072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6370$2070_Y + connect \B $eq$ls180.v:6370$2071_Y + connect \Y $and$ls180.v:6370$2072_Y + end + attribute \src "ls180.v:6371.41-6371.99" + cell $and $and$ls180.v:6371$2074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6371$2073_Y + connect \Y $and$ls180.v:6371$2074_Y + end + attribute \src "ls180.v:6371.40-6371.150" + cell $and $and$ls180.v:6371$2076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6371$2074_Y + connect \B $eq$ls180.v:6371$2075_Y + connect \Y $and$ls180.v:6371$2076_Y + end + attribute \src "ls180.v:6373.37-6373.92" + cell $and $and$ls180.v:6373$2077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6373$2077_Y + end + attribute \src "ls180.v:6373.36-6373.143" + cell $and $and$ls180.v:6373$2079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6373$2077_Y + connect \B $eq$ls180.v:6373$2078_Y + connect \Y $and$ls180.v:6373$2079_Y + end + attribute \src "ls180.v:6374.37-6374.95" + cell $and $and$ls180.v:6374$2081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6374$2080_Y + connect \Y $and$ls180.v:6374$2081_Y + end + attribute \src "ls180.v:6374.36-6374.146" + cell $and $and$ls180.v:6374$2083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6374$2081_Y + connect \B $eq$ls180.v:6374$2082_Y + connect \Y $and$ls180.v:6374$2083_Y + end + attribute \src "ls180.v:6376.47-6376.102" + cell $and $and$ls180.v:6376$2084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6376$2084_Y + end + attribute \src "ls180.v:6376.46-6376.153" + cell $and $and$ls180.v:6376$2086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6376$2084_Y + connect \B $eq$ls180.v:6376$2085_Y + connect \Y $and$ls180.v:6376$2086_Y + end + attribute \src "ls180.v:6377.47-6377.105" + cell $and $and$ls180.v:6377$2088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6377$2087_Y + connect \Y $and$ls180.v:6377$2088_Y + end + attribute \src "ls180.v:6377.46-6377.156" + cell $and $and$ls180.v:6377$2090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6377$2088_Y + connect \B $eq$ls180.v:6377$2089_Y + connect \Y $and$ls180.v:6377$2090_Y + end + attribute \src "ls180.v:6379.40-6379.95" + cell $and $and$ls180.v:6379$2091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6379$2091_Y + end + attribute \src "ls180.v:6379.39-6379.147" + cell $and $and$ls180.v:6379$2093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6379$2091_Y + connect \B $eq$ls180.v:6379$2092_Y + connect \Y $and$ls180.v:6379$2093_Y + end + attribute \src "ls180.v:6380.40-6380.98" + cell $and $and$ls180.v:6380$2095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6380$2094_Y + connect \Y $and$ls180.v:6380$2095_Y + end + attribute \src "ls180.v:6380.39-6380.150" + cell $and $and$ls180.v:6380$2097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6380$2095_Y + connect \B $eq$ls180.v:6380$2096_Y + connect \Y $and$ls180.v:6380$2097_Y + end + attribute \src "ls180.v:6382.40-6382.95" + cell $and $and$ls180.v:6382$2098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6382$2098_Y + end + attribute \src "ls180.v:6382.39-6382.147" + cell $and $and$ls180.v:6382$2100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6382$2098_Y + connect \B $eq$ls180.v:6382$2099_Y + connect \Y $and$ls180.v:6382$2100_Y + end + attribute \src "ls180.v:6383.40-6383.98" + cell $and $and$ls180.v:6383$2102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6383$2101_Y + connect \Y $and$ls180.v:6383$2102_Y + end + attribute \src "ls180.v:6383.39-6383.150" + cell $and $and$ls180.v:6383$2104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6383$2102_Y + connect \B $eq$ls180.v:6383$2103_Y + connect \Y $and$ls180.v:6383$2104_Y + end + attribute \src "ls180.v:6385.40-6385.95" + cell $and $and$ls180.v:6385$2105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6385$2105_Y + end + attribute \src "ls180.v:6385.39-6385.147" + cell $and $and$ls180.v:6385$2107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6385$2105_Y + connect \B $eq$ls180.v:6385$2106_Y + connect \Y $and$ls180.v:6385$2107_Y + end + attribute \src "ls180.v:6386.40-6386.98" + cell $and $and$ls180.v:6386$2109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6386$2108_Y + connect \Y $and$ls180.v:6386$2109_Y + end + attribute \src "ls180.v:6386.39-6386.150" + cell $and $and$ls180.v:6386$2111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6386$2109_Y + connect \B $eq$ls180.v:6386$2110_Y + connect \Y $and$ls180.v:6386$2111_Y + end + attribute \src "ls180.v:6388.40-6388.95" + cell $and $and$ls180.v:6388$2112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6388$2112_Y + end + attribute \src "ls180.v:6388.39-6388.147" + cell $and $and$ls180.v:6388$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6388$2112_Y + connect \B $eq$ls180.v:6388$2113_Y + connect \Y $and$ls180.v:6388$2114_Y + end + attribute \src "ls180.v:6389.40-6389.98" + cell $and $and$ls180.v:6389$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6389$2115_Y + connect \Y $and$ls180.v:6389$2116_Y + end + attribute \src "ls180.v:6389.39-6389.150" + cell $and $and$ls180.v:6389$2118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6389$2116_Y + connect \B $eq$ls180.v:6389$2117_Y + connect \Y $and$ls180.v:6389$2118_Y + end + attribute \src "ls180.v:6391.52-6391.107" + cell $and $and$ls180.v:6391$2119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6391$2119_Y + end + attribute \src "ls180.v:6391.51-6391.159" + cell $and $and$ls180.v:6391$2121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6391$2119_Y + connect \B $eq$ls180.v:6391$2120_Y + connect \Y $and$ls180.v:6391$2121_Y + end + attribute \src "ls180.v:6392.52-6392.110" + cell $and $and$ls180.v:6392$2123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6392$2122_Y + connect \Y $and$ls180.v:6392$2123_Y + end + attribute \src "ls180.v:6392.51-6392.162" + cell $and $and$ls180.v:6392$2125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6392$2123_Y + connect \B $eq$ls180.v:6392$2124_Y + connect \Y $and$ls180.v:6392$2125_Y + end + attribute \src "ls180.v:6394.53-6394.108" + cell $and $and$ls180.v:6394$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6394$2126_Y + end + attribute \src "ls180.v:6394.52-6394.160" + cell $and $and$ls180.v:6394$2128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6394$2126_Y + connect \B $eq$ls180.v:6394$2127_Y + connect \Y $and$ls180.v:6394$2128_Y + end + attribute \src "ls180.v:6395.53-6395.111" + cell $and $and$ls180.v:6395$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6395$2129_Y + connect \Y $and$ls180.v:6395$2130_Y + end + attribute \src "ls180.v:6395.52-6395.163" + cell $and $and$ls180.v:6395$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6395$2130_Y + connect \B $eq$ls180.v:6395$2131_Y + connect \Y $and$ls180.v:6395$2132_Y + end + attribute \src "ls180.v:6397.44-6397.99" + cell $and $and$ls180.v:6397$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6397$2133_Y + end + attribute \src "ls180.v:6397.43-6397.151" + cell $and $and$ls180.v:6397$2135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6397$2133_Y + connect \B $eq$ls180.v:6397$2134_Y + connect \Y $and$ls180.v:6397$2135_Y + end + attribute \src "ls180.v:6398.44-6398.102" + cell $and $and$ls180.v:6398$2137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6398$2136_Y + connect \Y $and$ls180.v:6398$2137_Y + end + attribute \src "ls180.v:6398.43-6398.154" + cell $and $and$ls180.v:6398$2139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6398$2137_Y + connect \B $eq$ls180.v:6398$2138_Y + connect \Y $and$ls180.v:6398$2139_Y + end + attribute \src "ls180.v:6417.30-6417.85" + cell $and $and$ls180.v:6417$2141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6417$2141_Y + end + attribute \src "ls180.v:6417.29-6417.136" + cell $and $and$ls180.v:6417$2143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6417$2141_Y + connect \B $eq$ls180.v:6417$2142_Y + connect \Y $and$ls180.v:6417$2143_Y + end + attribute \src "ls180.v:6418.30-6418.88" + cell $and $and$ls180.v:6418$2145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6418$2144_Y + connect \Y $and$ls180.v:6418$2145_Y + end + attribute \src "ls180.v:6418.29-6418.139" + cell $and $and$ls180.v:6418$2147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6418$2145_Y + connect \B $eq$ls180.v:6418$2146_Y + connect \Y $and$ls180.v:6418$2147_Y + end + attribute \src "ls180.v:6420.40-6420.95" + cell $and $and$ls180.v:6420$2148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6420$2148_Y + end + attribute \src "ls180.v:6420.39-6420.146" + cell $and $and$ls180.v:6420$2150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6420$2148_Y + connect \B $eq$ls180.v:6420$2149_Y + connect \Y $and$ls180.v:6420$2150_Y + end + attribute \src "ls180.v:6421.40-6421.98" + cell $and $and$ls180.v:6421$2152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6421$2151_Y + connect \Y $and$ls180.v:6421$2152_Y + end + attribute \src "ls180.v:6421.39-6421.149" + cell $and $and$ls180.v:6421$2154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6421$2152_Y + connect \B $eq$ls180.v:6421$2153_Y + connect \Y $and$ls180.v:6421$2154_Y + end + attribute \src "ls180.v:6423.41-6423.96" + cell $and $and$ls180.v:6423$2155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6423$2155_Y + end + attribute \src "ls180.v:6423.40-6423.147" + cell $and $and$ls180.v:6423$2157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6423$2155_Y + connect \B $eq$ls180.v:6423$2156_Y + connect \Y $and$ls180.v:6423$2157_Y + end + attribute \src "ls180.v:6424.41-6424.99" + cell $and $and$ls180.v:6424$2159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6424$2158_Y + connect \Y $and$ls180.v:6424$2159_Y + end + attribute \src "ls180.v:6424.40-6424.150" + cell $and $and$ls180.v:6424$2161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6424$2159_Y + connect \B $eq$ls180.v:6424$2160_Y + connect \Y $and$ls180.v:6424$2161_Y + end + attribute \src "ls180.v:6426.45-6426.100" + cell $and $and$ls180.v:6426$2162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6426$2162_Y + end + attribute \src "ls180.v:6426.44-6426.151" + cell $and $and$ls180.v:6426$2164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6426$2162_Y + connect \B $eq$ls180.v:6426$2163_Y + connect \Y $and$ls180.v:6426$2164_Y + end + attribute \src "ls180.v:6427.45-6427.103" + cell $and $and$ls180.v:6427$2166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6427$2165_Y + connect \Y $and$ls180.v:6427$2166_Y + end + attribute \src "ls180.v:6427.44-6427.154" + cell $and $and$ls180.v:6427$2168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6427$2166_Y + connect \B $eq$ls180.v:6427$2167_Y + connect \Y $and$ls180.v:6427$2168_Y + end + attribute \src "ls180.v:6429.46-6429.101" + cell $and $and$ls180.v:6429$2169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6429$2169_Y + end + attribute \src "ls180.v:6429.45-6429.152" + cell $and $and$ls180.v:6429$2171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6429$2169_Y + connect \B $eq$ls180.v:6429$2170_Y + connect \Y $and$ls180.v:6429$2171_Y + end + attribute \src "ls180.v:6430.46-6430.104" + cell $and $and$ls180.v:6430$2173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6430$2172_Y + connect \Y $and$ls180.v:6430$2173_Y + end + attribute \src "ls180.v:6430.45-6430.155" + cell $and $and$ls180.v:6430$2175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6430$2173_Y + connect \B $eq$ls180.v:6430$2174_Y + connect \Y $and$ls180.v:6430$2175_Y + end + attribute \src "ls180.v:6432.44-6432.99" + cell $and $and$ls180.v:6432$2176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6432$2176_Y + end + attribute \src "ls180.v:6432.43-6432.150" + cell $and $and$ls180.v:6432$2178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6432$2176_Y + connect \B $eq$ls180.v:6432$2177_Y + connect \Y $and$ls180.v:6432$2178_Y + end + attribute \src "ls180.v:6433.44-6433.102" + cell $and $and$ls180.v:6433$2180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6433$2179_Y + connect \Y $and$ls180.v:6433$2180_Y + end + attribute \src "ls180.v:6433.43-6433.153" + cell $and $and$ls180.v:6433$2182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6433$2180_Y + connect \B $eq$ls180.v:6433$2181_Y + connect \Y $and$ls180.v:6433$2182_Y + end + attribute \src "ls180.v:6435.41-6435.96" + cell $and $and$ls180.v:6435$2183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6435$2183_Y + end + attribute \src "ls180.v:6435.40-6435.147" + cell $and $and$ls180.v:6435$2185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6435$2183_Y + connect \B $eq$ls180.v:6435$2184_Y + connect \Y $and$ls180.v:6435$2185_Y + end + attribute \src "ls180.v:6436.41-6436.99" + cell $and $and$ls180.v:6436$2187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6436$2186_Y + connect \Y $and$ls180.v:6436$2187_Y + end + attribute \src "ls180.v:6436.40-6436.150" + cell $and $and$ls180.v:6436$2189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6436$2187_Y + connect \B $eq$ls180.v:6436$2188_Y + connect \Y $and$ls180.v:6436$2189_Y + end + attribute \src "ls180.v:6438.40-6438.95" + cell $and $and$ls180.v:6438$2190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6438$2190_Y + end + attribute \src "ls180.v:6438.39-6438.146" + cell $and $and$ls180.v:6438$2192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6438$2190_Y + connect \B $eq$ls180.v:6438$2191_Y + connect \Y $and$ls180.v:6438$2192_Y + end + attribute \src "ls180.v:6439.40-6439.98" + cell $and $and$ls180.v:6439$2194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6439$2193_Y + connect \Y $and$ls180.v:6439$2194_Y + end + attribute \src "ls180.v:6439.39-6439.149" + cell $and $and$ls180.v:6439$2196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6439$2194_Y + connect \B $eq$ls180.v:6439$2195_Y + connect \Y $and$ls180.v:6439$2196_Y + end + attribute \src "ls180.v:6451.46-6451.101" + cell $and $and$ls180.v:6451$2198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6451$2198_Y + end + attribute \src "ls180.v:6451.45-6451.152" + cell $and $and$ls180.v:6451$2200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6451$2198_Y + connect \B $eq$ls180.v:6451$2199_Y + connect \Y $and$ls180.v:6451$2200_Y + end + attribute \src "ls180.v:6452.46-6452.104" + cell $and $and$ls180.v:6452$2202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6452$2201_Y + connect \Y $and$ls180.v:6452$2202_Y + end + attribute \src "ls180.v:6452.45-6452.155" + cell $and $and$ls180.v:6452$2204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6452$2202_Y + connect \B $eq$ls180.v:6452$2203_Y + connect \Y $and$ls180.v:6452$2204_Y + end + attribute \src "ls180.v:6454.46-6454.101" + cell $and $and$ls180.v:6454$2205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6454$2205_Y + end + attribute \src "ls180.v:6454.45-6454.152" + cell $and $and$ls180.v:6454$2207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6454$2205_Y + connect \B $eq$ls180.v:6454$2206_Y + connect \Y $and$ls180.v:6454$2207_Y + end + attribute \src "ls180.v:6455.46-6455.104" + cell $and $and$ls180.v:6455$2209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6455$2208_Y + connect \Y $and$ls180.v:6455$2209_Y + end + attribute \src "ls180.v:6455.45-6455.155" + cell $and $and$ls180.v:6455$2211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6455$2209_Y + connect \B $eq$ls180.v:6455$2210_Y + connect \Y $and$ls180.v:6455$2211_Y + end + attribute \src "ls180.v:6457.46-6457.101" + cell $and $and$ls180.v:6457$2212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6457$2212_Y + end + attribute \src "ls180.v:6457.45-6457.152" + cell $and $and$ls180.v:6457$2214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6457$2212_Y + connect \B $eq$ls180.v:6457$2213_Y + connect \Y $and$ls180.v:6457$2214_Y + end + attribute \src "ls180.v:6458.46-6458.104" + cell $and $and$ls180.v:6458$2216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6458$2215_Y + connect \Y $and$ls180.v:6458$2216_Y + end + attribute \src "ls180.v:6458.45-6458.155" + cell $and $and$ls180.v:6458$2218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6458$2216_Y + connect \B $eq$ls180.v:6458$2217_Y + connect \Y $and$ls180.v:6458$2218_Y + end + attribute \src "ls180.v:6460.46-6460.101" + cell $and $and$ls180.v:6460$2219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6460$2219_Y + end + attribute \src "ls180.v:6460.45-6460.152" + cell $and $and$ls180.v:6460$2221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6460$2219_Y + connect \B $eq$ls180.v:6460$2220_Y + connect \Y $and$ls180.v:6460$2221_Y + end + attribute \src "ls180.v:6461.46-6461.104" + cell $and $and$ls180.v:6461$2223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6461$2222_Y + connect \Y $and$ls180.v:6461$2223_Y + end + attribute \src "ls180.v:6461.45-6461.155" + cell $and $and$ls180.v:6461$2225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6461$2223_Y + connect \B $eq$ls180.v:6461$2224_Y + connect \Y $and$ls180.v:6461$2225_Y + end + attribute \src "ls180.v:6842.109-6842.178" + cell $and $and$ls180.v:6842$2263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6842$2262_Y + connect \Y $and$ls180.v:6842$2263_Y + end + attribute \src "ls180.v:6842.184-6842.253" + cell $and $and$ls180.v:6842$2266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6842$2265_Y + connect \Y $and$ls180.v:6842$2266_Y + end + attribute \src "ls180.v:6842.259-6842.328" + cell $and $and$ls180.v:6842$2269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6842$2268_Y + connect \Y $and$ls180.v:6842$2269_Y + end + attribute \src "ls180.v:6842.40-6842.331" + cell $and $and$ls180.v:6842$2272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6842$2261_Y + connect \B $not$ls180.v:6842$2271_Y + connect \Y $and$ls180.v:6842$2272_Y + end + attribute \src "ls180.v:6842.39-6842.354" + cell $and $and$ls180.v:6842$2273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6842$2272_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6842$2273_Y + end + attribute \src "ls180.v:6866.109-6866.178" + cell $and $and$ls180.v:6866$2279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6866$2278_Y + connect \Y $and$ls180.v:6866$2279_Y + end + attribute \src "ls180.v:6866.184-6866.253" + cell $and $and$ls180.v:6866$2282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6866$2281_Y + connect \Y $and$ls180.v:6866$2282_Y + end + attribute \src "ls180.v:6866.259-6866.328" + cell $and $and$ls180.v:6866$2285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6866$2284_Y + connect \Y $and$ls180.v:6866$2285_Y + end + attribute \src "ls180.v:6866.40-6866.331" + cell $and $and$ls180.v:6866$2288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6866$2277_Y + connect \B $not$ls180.v:6866$2287_Y + connect \Y $and$ls180.v:6866$2288_Y + end + attribute \src "ls180.v:6866.39-6866.354" + cell $and $and$ls180.v:6866$2289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6866$2288_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6866$2289_Y + end + attribute \src "ls180.v:6890.109-6890.178" + cell $and $and$ls180.v:6890$2295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6890$2294_Y + connect \Y $and$ls180.v:6890$2295_Y + end + attribute \src "ls180.v:6890.184-6890.253" + cell $and $and$ls180.v:6890$2298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6890$2297_Y + connect \Y $and$ls180.v:6890$2298_Y + end + attribute \src "ls180.v:6890.259-6890.328" + cell $and $and$ls180.v:6890$2301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6890$2300_Y + connect \Y $and$ls180.v:6890$2301_Y + end + attribute \src "ls180.v:6890.40-6890.331" + cell $and $and$ls180.v:6890$2304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6890$2293_Y + connect \B $not$ls180.v:6890$2303_Y + connect \Y $and$ls180.v:6890$2304_Y + end + attribute \src "ls180.v:6890.39-6890.354" + cell $and $and$ls180.v:6890$2305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6890$2304_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6890$2305_Y + end + attribute \src "ls180.v:6914.109-6914.178" + cell $and $and$ls180.v:6914$2311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6914$2310_Y + connect \Y $and$ls180.v:6914$2311_Y + end + attribute \src "ls180.v:6914.184-6914.253" + cell $and $and$ls180.v:6914$2314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6914$2313_Y + connect \Y $and$ls180.v:6914$2314_Y + end + attribute \src "ls180.v:6914.259-6914.328" + cell $and $and$ls180.v:6914$2317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6914$2316_Y + connect \Y $and$ls180.v:6914$2317_Y + end + attribute \src "ls180.v:6914.40-6914.331" + cell $and $and$ls180.v:6914$2320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6914$2309_Y + connect \B $not$ls180.v:6914$2319_Y + connect \Y $and$ls180.v:6914$2320_Y + end + attribute \src "ls180.v:6914.39-6914.354" + cell $and $and$ls180.v:6914$2321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6914$2320_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6914$2321_Y + end + attribute \src "ls180.v:7119.39-7119.104" + cell $and $and$ls180.v:7119$2333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7119$2333_Y + end + attribute \src "ls180.v:7119.38-7119.145" + cell $and $and$ls180.v:7119$2334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7119$2333_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7119$2334_Y + end + attribute \src "ls180.v:7122.39-7122.104" + cell $and $and$ls180.v:7122$2335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7122$2335_Y + end + attribute \src "ls180.v:7122.38-7122.145" + cell $and $and$ls180.v:7122$2336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7122$2335_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7122$2336_Y + end + attribute \src "ls180.v:7125.39-7125.82" + cell $and $and$ls180.v:7125$2337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7125$2337_Y + end + attribute \src "ls180.v:7125.38-7125.112" + cell $and $and$ls180.v:7125$2338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7125$2337_Y + connect \B \main_sdram_cmd_payload_cas + connect \Y $and$ls180.v:7125$2338_Y + end + attribute \src "ls180.v:7136.39-7136.104" + cell $and $and$ls180.v:7136$2340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7136$2340_Y + end + attribute \src "ls180.v:7136.38-7136.145" + cell $and $and$ls180.v:7136$2341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7136$2340_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7136$2341_Y + end + attribute \src "ls180.v:7139.39-7139.104" + cell $and $and$ls180.v:7139$2342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7139$2342_Y + end + attribute \src "ls180.v:7139.38-7139.145" + cell $and $and$ls180.v:7139$2343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7139$2342_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7139$2343_Y + end + attribute \src "ls180.v:7142.39-7142.82" + cell $and $and$ls180.v:7142$2344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7142$2344_Y + end + attribute \src "ls180.v:7142.38-7142.112" + cell $and $and$ls180.v:7142$2345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7142$2344_Y + connect \B \main_sdram_cmd_payload_ras + connect \Y $and$ls180.v:7142$2345_Y + end + attribute \src "ls180.v:7153.39-7153.104" + cell $and $and$ls180.v:7153$2347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7153$2347_Y + end + attribute \src "ls180.v:7153.38-7153.144" + cell $and $and$ls180.v:7153$2348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7153$2347_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7153$2348_Y + end + attribute \src "ls180.v:7156.39-7156.104" + cell $and $and$ls180.v:7156$2349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7156$2349_Y + end + attribute \src "ls180.v:7156.38-7156.144" + cell $and $and$ls180.v:7156$2350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7156$2349_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7156$2350_Y + end + attribute \src "ls180.v:7159.39-7159.82" + cell $and $and$ls180.v:7159$2351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7159$2351_Y + end + attribute \src "ls180.v:7159.38-7159.111" + cell $and $and$ls180.v:7159$2352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7159$2351_Y + connect \B \main_sdram_cmd_payload_we + connect \Y $and$ls180.v:7159$2352_Y + end + attribute \src "ls180.v:7170.39-7170.104" + cell $and $and$ls180.v:7170$2354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7170$2354_Y + end + attribute \src "ls180.v:7170.38-7170.149" + cell $and $and$ls180.v:7170$2355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7170$2354_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7170$2355_Y + end + attribute \src "ls180.v:7173.39-7173.104" + cell $and $and$ls180.v:7173$2356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7173$2356_Y + end + attribute \src "ls180.v:7173.38-7173.149" + cell $and $and$ls180.v:7173$2357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7173$2356_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7173$2357_Y + end + attribute \src "ls180.v:7176.39-7176.82" + cell $and $and$ls180.v:7176$2358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7176$2358_Y + end + attribute \src "ls180.v:7176.38-7176.116" + cell $and $and$ls180.v:7176$2359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7176$2358_Y + connect \B \main_sdram_cmd_payload_is_read + connect \Y $and$ls180.v:7176$2359_Y + end + attribute \src "ls180.v:7187.39-7187.104" + cell $and $and$ls180.v:7187$2361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7187$2361_Y + end + attribute \src "ls180.v:7187.38-7187.150" + cell $and $and$ls180.v:7187$2362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7187$2361_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7187$2362_Y + end + attribute \src "ls180.v:7190.39-7190.104" + cell $and $and$ls180.v:7190$2363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7190$2363_Y + end + attribute \src "ls180.v:7190.38-7190.150" + cell $and $and$ls180.v:7190$2364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7190$2363_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7190$2364_Y + end + attribute \src "ls180.v:7193.39-7193.82" + cell $and $and$ls180.v:7193$2365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7193$2365_Y + end + attribute \src "ls180.v:7193.38-7193.117" + cell $and $and$ls180.v:7193$2366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7193$2365_Y + connect \B \main_sdram_cmd_payload_is_write + connect \Y $and$ls180.v:7193$2366_Y + end + attribute \src "ls180.v:7412.17-7412.67" + cell $and $and$ls180.v:7412$2373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7412$2372_Y + connect \B \main_sdphy_sdpads_clk + connect \Y $and$ls180.v:7412$2373_Y + end + attribute \src "ls180.v:7491.8-7491.67" + cell $and $and$ls180.v:7491$2404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:7491$2404_Y + end + attribute \src "ls180.v:7491.7-7491.102" + cell $and $and$ls180.v:7491$2406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7491$2404_Y + connect \B $not$ls180.v:7491$2405_Y + connect \Y $and$ls180.v:7491$2406_Y + end + attribute \src "ls180.v:7510.7-7510.75" + cell $and $and$ls180.v:7510$2410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7510$2409_Y + connect \B \main_libresocsim_zero_old_trigger + connect \Y $and$ls180.v:7510$2410_Y + end + attribute \src "ls180.v:7518.7-7518.56" + cell $and $and$ls180.v:7518$2412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_wait + connect \B $not$ls180.v:7518$2411_Y + connect \Y $and$ls180.v:7518$2412_Y + end + attribute \src "ls180.v:7546.7-7546.75" + cell $and $and$ls180.v:7546$2419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start1 + connect \B $eq$ls180.v:7546$2418_Y + connect \Y $and$ls180.v:7546$2419_Y + end + attribute \src "ls180.v:7588.8-7588.131" + cell $and $and$ls180.v:7588$2425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7588$2425_Y + end + attribute \src "ls180.v:7588.7-7588.190" + cell $and $and$ls180.v:7588$2427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7588$2425_Y + connect \B $not$ls180.v:7588$2426_Y + connect \Y $and$ls180.v:7588$2427_Y + end + attribute \src "ls180.v:7594.8-7594.131" + cell $and $and$ls180.v:7594$2430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7594$2430_Y + end + attribute \src "ls180.v:7594.7-7594.190" + cell $and $and$ls180.v:7594$2432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7594$2430_Y + connect \B $not$ls180.v:7594$2431_Y + connect \Y $and$ls180.v:7594$2432_Y + end + attribute \src "ls180.v:7634.8-7634.131" + cell $and $and$ls180.v:7634$2441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7634$2441_Y + end + attribute \src "ls180.v:7634.7-7634.190" + cell $and $and$ls180.v:7634$2443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7634$2441_Y + connect \B $not$ls180.v:7634$2442_Y + connect \Y $and$ls180.v:7634$2443_Y + end + attribute \src "ls180.v:7640.8-7640.131" + cell $and $and$ls180.v:7640$2446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7640$2446_Y + end + attribute \src "ls180.v:7640.7-7640.190" + cell $and $and$ls180.v:7640$2448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7640$2446_Y + connect \B $not$ls180.v:7640$2447_Y + connect \Y $and$ls180.v:7640$2448_Y + end + attribute \src "ls180.v:7680.8-7680.131" + cell $and $and$ls180.v:7680$2457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7680$2457_Y + end + attribute \src "ls180.v:7680.7-7680.190" + cell $and $and$ls180.v:7680$2459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7680$2457_Y + connect \B $not$ls180.v:7680$2458_Y + connect \Y $and$ls180.v:7680$2459_Y + end + attribute \src "ls180.v:7686.8-7686.131" + cell $and $and$ls180.v:7686$2462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7686$2462_Y + end + attribute \src "ls180.v:7686.7-7686.190" + cell $and $and$ls180.v:7686$2464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7686$2462_Y + connect \B $not$ls180.v:7686$2463_Y + connect \Y $and$ls180.v:7686$2464_Y + end + attribute \src "ls180.v:7726.8-7726.131" + cell $and $and$ls180.v:7726$2473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7726$2473_Y + end + attribute \src "ls180.v:7726.7-7726.190" + cell $and $and$ls180.v:7726$2475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7726$2473_Y + connect \B $not$ls180.v:7726$2474_Y + connect \Y $and$ls180.v:7726$2475_Y + end + attribute \src "ls180.v:7732.8-7732.131" + cell $and $and$ls180.v:7732$2478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7732$2478_Y + end + attribute \src "ls180.v:7732.7-7732.190" + cell $and $and$ls180.v:7732$2480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7732$2478_Y + connect \B $not$ls180.v:7732$2479_Y + connect \Y $and$ls180.v:7732$2480_Y + end + attribute \src "ls180.v:7929.48-7929.124" + cell $and $and$ls180.v:7929$2505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7929$2504_Y + connect \B \main_sdram_interface_bank0_wdata_ready + connect \Y $and$ls180.v:7929$2505_Y + end + attribute \src "ls180.v:7929.130-7929.206" + cell $and $and$ls180.v:7929$2508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7929$2507_Y + connect \B \main_sdram_interface_bank1_wdata_ready + connect \Y $and$ls180.v:7929$2508_Y + end + attribute \src "ls180.v:7929.212-7929.288" + cell $and $and$ls180.v:7929$2511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7929$2510_Y + connect \B \main_sdram_interface_bank2_wdata_ready + connect \Y $and$ls180.v:7929$2511_Y + end + attribute \src "ls180.v:7929.294-7929.370" + cell $and $and$ls180.v:7929$2514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7929$2513_Y + connect \B \main_sdram_interface_bank3_wdata_ready + connect \Y $and$ls180.v:7929$2514_Y + end + attribute \src "ls180.v:7930.49-7930.125" + cell $and $and$ls180.v:7930$2517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7930$2516_Y + connect \B \main_sdram_interface_bank0_rdata_valid + connect \Y $and$ls180.v:7930$2517_Y + end + attribute \src "ls180.v:7930.131-7930.207" + cell $and $and$ls180.v:7930$2520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7930$2519_Y + connect \B \main_sdram_interface_bank1_rdata_valid + connect \Y $and$ls180.v:7930$2520_Y + end + attribute \src "ls180.v:7930.213-7930.289" + cell $and $and$ls180.v:7930$2523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7930$2522_Y + connect \B \main_sdram_interface_bank2_rdata_valid + connect \Y $and$ls180.v:7930$2523_Y + end + attribute \src "ls180.v:7930.295-7930.371" + cell $and $and$ls180.v:7930$2526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7930$2525_Y + connect \B \main_sdram_interface_bank3_rdata_valid + connect \Y $and$ls180.v:7930$2526_Y + end + attribute \src "ls180.v:7949.8-7949.49" + cell $and $and$ls180.v:7949$2529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:7949$2529_Y + end + attribute \src "ls180.v:7952.8-7952.53" + cell $and $and$ls180.v:7952$2530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:7952$2530_Y + end + attribute \src "ls180.v:7957.8-7957.59" + cell $and $and$ls180.v:7957$2532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_valid + connect \B $not$ls180.v:7957$2531_Y + connect \Y $and$ls180.v:7957$2532_Y + end + attribute \src "ls180.v:7957.7-7957.90" + cell $and $and$ls180.v:7957$2534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7957$2532_Y + connect \B $not$ls180.v:7957$2533_Y + connect \Y $and$ls180.v:7957$2534_Y + end + attribute \src "ls180.v:7963.8-7963.59" + cell $and $and$ls180.v:7963$2535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_uart_clk_txen + connect \B \main_uart_phy_tx_busy + connect \Y $and$ls180.v:7963$2535_Y + end + attribute \src "ls180.v:7987.8-7987.48" + cell $and $and$ls180.v:7987$2542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7987$2541_Y + connect \B \main_uart_phy_rx_r + connect \Y $and$ls180.v:7987$2542_Y + end + attribute \src "ls180.v:8020.7-8020.57" + cell $and $and$ls180.v:8020$2548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8020$2547_Y + connect \B \main_uart_tx_old_trigger + connect \Y $and$ls180.v:8020$2548_Y + end + attribute \src "ls180.v:8027.7-8027.57" + cell $and $and$ls180.v:8027$2550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8027$2549_Y + connect \B \main_uart_rx_old_trigger + connect \Y $and$ls180.v:8027$2550_Y + end + attribute \src "ls180.v:8037.8-8037.75" + cell $and $and$ls180.v:8037$2551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8037$2551_Y + end + attribute \src "ls180.v:8037.7-8037.107" + cell $and $and$ls180.v:8037$2553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8037$2551_Y + connect \B $not$ls180.v:8037$2552_Y + connect \Y $and$ls180.v:8037$2553_Y + end + attribute \src "ls180.v:8043.8-8043.75" + cell $and $and$ls180.v:8043$2556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8043$2556_Y + end + attribute \src "ls180.v:8043.7-8043.107" + cell $and $and$ls180.v:8043$2558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8043$2556_Y + connect \B $not$ls180.v:8043$2557_Y + connect \Y $and$ls180.v:8043$2558_Y + end + attribute \src "ls180.v:8059.8-8059.75" + cell $and $and$ls180.v:8059$2562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8059$2562_Y + end + attribute \src "ls180.v:8059.7-8059.107" + cell $and $and$ls180.v:8059$2564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8059$2562_Y + connect \B $not$ls180.v:8059$2563_Y + connect \Y $and$ls180.v:8059$2564_Y + end + attribute \src "ls180.v:8065.8-8065.75" + cell $and $and$ls180.v:8065$2567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8065$2567_Y + end + attribute \src "ls180.v:8065.7-8065.107" + cell $and $and$ls180.v:8065$2569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8065$2567_Y + connect \B $not$ls180.v:8065$2568_Y + connect \Y $and$ls180.v:8065$2569_Y + end + attribute \src "ls180.v:8213.7-8213.96" + cell $and $and$ls180.v:8213$2597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_source_valid + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $and$ls180.v:8213$2597_Y + end + attribute \src "ls180.v:8214.8-8214.93" + cell $and $and$ls180.v:8214$2598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8214$2598_Y + end + attribute \src "ls180.v:8222.8-8222.93" + cell $and $and$ls180.v:8222$2599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8222$2599_Y + end + attribute \src "ls180.v:8294.7-8294.98" + cell $and $and$ls180.v:8294$2609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_source_valid + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $and$ls180.v:8294$2609_Y + end + attribute \src "ls180.v:8295.8-8295.95" + cell $and $and$ls180.v:8295$2610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8295$2610_Y + end + attribute \src "ls180.v:8303.8-8303.95" + cell $and $and$ls180.v:8303$2611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8303$2611_Y + end + attribute \src "ls180.v:8373.7-8373.100" + cell $and $and$ls180.v:8373$2621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_source_valid + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $and$ls180.v:8373$2621_Y + end + attribute \src "ls180.v:8374.8-8374.97" + cell $and $and$ls180.v:8374$2622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8374$2622_Y + end + attribute \src "ls180.v:8382.8-8382.97" + cell $and $and$ls180.v:8382$2623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8382$2623_Y + end + attribute \src "ls180.v:8473.7-8473.82" + cell $and $and$ls180.v:8473$2629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8473$2629_Y + end + attribute \src "ls180.v:8476.7-8476.82" + cell $and $and$ls180.v:8476$2630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8476$2630_Y + end + attribute \src "ls180.v:8479.7-8479.82" + cell $and $and$ls180.v:8479$2631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8479$2631_Y + end + attribute \src "ls180.v:8482.7-8482.82" + cell $and $and$ls180.v:8482$2632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8482$2632_Y + end + attribute \src "ls180.v:8485.7-8485.82" + cell $and $and$ls180.v:8485$2633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8485$2633_Y + end + attribute \src "ls180.v:8490.7-8490.82" + cell $and $and$ls180.v:8490$2634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8490$2634_Y + end + attribute \src "ls180.v:8495.7-8495.82" + cell $and $and$ls180.v:8495$2635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8495$2635_Y + end + attribute \src "ls180.v:8500.7-8500.82" + cell $and $and$ls180.v:8500$2636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8500$2636_Y + end + attribute \src "ls180.v:8505.7-8505.82" + cell $and $and$ls180.v:8505$2637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8505$2637_Y + end + attribute \src "ls180.v:8570.8-8570.83" + cell $and $and$ls180.v:8570$2640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8570$2640_Y + end + attribute \src "ls180.v:8570.7-8570.119" + cell $and $and$ls180.v:8570$2642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8570$2640_Y + connect \B $not$ls180.v:8570$2641_Y + connect \Y $and$ls180.v:8570$2642_Y + end + attribute \src "ls180.v:8576.8-8576.83" + cell $and $and$ls180.v:8576$2645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8576$2645_Y + end + attribute \src "ls180.v:8576.7-8576.119" + cell $and $and$ls180.v:8576$2647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8576$2645_Y + connect \B $not$ls180.v:8576$2646_Y + connect \Y $and$ls180.v:8576$2647_Y + end + attribute \src "ls180.v:8596.7-8596.88" + cell $and $and$ls180.v:8596$2654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_source_valid + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $and$ls180.v:8596$2654_Y + end + attribute \src "ls180.v:8597.8-8597.85" + cell $and $and$ls180.v:8597$2655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8597$2655_Y + end + attribute \src "ls180.v:8605.8-8605.85" + cell $and $and$ls180.v:8605$2656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8605$2656_Y + end + attribute \src "ls180.v:8649.7-8649.88" + cell $and $and$ls180.v:8649$2660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_source_valid + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:8649$2660_Y + end + attribute \src "ls180.v:8656.8-8656.83" + cell $and $and$ls180.v:8656$2662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8656$2662_Y + end + attribute \src "ls180.v:8656.7-8656.119" + cell $and $and$ls180.v:8656$2664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8656$2662_Y + connect \B $not$ls180.v:8656$2663_Y + connect \Y $and$ls180.v:8656$2664_Y + end + attribute \src "ls180.v:8662.8-8662.83" + cell $and $and$ls180.v:8662$2667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8662$2667_Y + end + attribute \src "ls180.v:8662.7-8662.119" + cell $and $and$ls180.v:8662$2669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8662$2667_Y + connect \B $not$ls180.v:8662$2668_Y + connect \Y $and$ls180.v:8662$2669_Y + end + attribute \src "ls180.v:2810.42-2810.101" + cell $eq $eq$ls180.v:2810$18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2810$18_Y + end + attribute \src "ls180.v:2817.11-2817.54" + cell $eq $eq$ls180.v:2817$23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2817$23_Y + end + attribute \src "ls180.v:2870.42-2870.101" + cell $eq $eq$ls180.v:2870$29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2870$29_Y + end + attribute \src "ls180.v:2877.11-2877.54" + cell $eq $eq$ls180.v:2877$34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2877$34_Y + end + attribute \src "ls180.v:2930.42-2930.101" + cell $eq $eq$ls180.v:2930$40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2930$40_Y + end + attribute \src "ls180.v:2937.11-2937.54" + cell $eq $eq$ls180.v:2937$45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2937$45_Y + end + attribute \src "ls180.v:3123.34-3123.65" + cell $eq $eq$ls180.v:3123$73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_count1 + connect \B 1'0 + connect \Y $eq$ls180.v:3123$73_Y + end + attribute \src "ls180.v:3127.68-3127.102" + cell $eq $eq$ls180.v:3127$76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $eq$ls180.v:3127$76_Y + end + attribute \src "ls180.v:3171.43-3171.134" + cell $eq $eq$ls180.v:3171$81 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3171$81_Y + end + attribute \src "ls180.v:3188.47-3188.88" + cell $eq $eq$ls180.v:3188$94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3188$94_Y + end + attribute \src "ls180.v:3328.43-3328.134" + cell $eq $eq$ls180.v:3328$111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3328$111_Y + end + attribute \src "ls180.v:3345.47-3345.88" + cell $eq $eq$ls180.v:3345$124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3345$124_Y + end + attribute \src "ls180.v:3485.43-3485.134" + cell $eq $eq$ls180.v:3485$141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3485$141_Y + end + attribute \src "ls180.v:3502.47-3502.88" + cell $eq $eq$ls180.v:3502$154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3502$154_Y + end + attribute \src "ls180.v:3642.43-3642.134" + cell $eq $eq$ls180.v:3642$171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3642$171_Y + end + attribute \src "ls180.v:3659.47-3659.88" + cell $eq $eq$ls180.v:3659$184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3659$184_Y + end + attribute \src "ls180.v:3796.32-3796.56" + cell $eq $eq$ls180.v:3796$231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time0 + connect \B 1'0 + connect \Y $eq$ls180.v:3796$231_Y + end + attribute \src "ls180.v:3797.32-3797.56" + cell $eq $eq$ls180.v:3797$232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time1 + connect \B 1'0 + connect \Y $eq$ls180.v:3797$232_Y + end + attribute \src "ls180.v:3808.339-3808.418" + cell $eq $eq$ls180.v:3808$246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3808$246_Y + end + attribute \src "ls180.v:3808.423-3808.504" + cell $eq $eq$ls180.v:3808$247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3808$247_Y + end + attribute \src "ls180.v:3809.339-3809.418" + cell $eq $eq$ls180.v:3809$259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3809$259_Y + end + attribute \src "ls180.v:3809.423-3809.504" + cell $eq $eq$ls180.v:3809$260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3809$260_Y + end + attribute \src "ls180.v:3810.339-3810.418" + cell $eq $eq$ls180.v:3810$272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3810$272_Y + end + attribute \src "ls180.v:3810.423-3810.504" + cell $eq $eq$ls180.v:3810$273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3810$273_Y + end + attribute \src "ls180.v:3811.339-3811.418" + cell $eq $eq$ls180.v:3811$285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3811$285_Y + end + attribute \src "ls180.v:3811.423-3811.504" + cell $eq $eq$ls180.v:3811$286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3811$286_Y + end + attribute \src "ls180.v:3841.339-3841.418" + cell $eq $eq$ls180.v:3841$304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3841$304_Y + end + attribute \src "ls180.v:3841.423-3841.504" + cell $eq $eq$ls180.v:3841$305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3841$305_Y + end + attribute \src "ls180.v:3842.339-3842.418" + cell $eq $eq$ls180.v:3842$317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3842$317_Y + end + attribute \src "ls180.v:3842.423-3842.504" + cell $eq $eq$ls180.v:3842$318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3842$318_Y + end + attribute \src "ls180.v:3843.339-3843.418" + cell $eq $eq$ls180.v:3843$330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3843$330_Y + end + attribute \src "ls180.v:3843.423-3843.504" + cell $eq $eq$ls180.v:3843$331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3843$331_Y + end + attribute \src "ls180.v:3844.339-3844.418" + cell $eq $eq$ls180.v:3844$343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3844$343_Y + end + attribute \src "ls180.v:3844.423-3844.504" + cell $eq $eq$ls180.v:3844$344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3844$344_Y + end + attribute \src "ls180.v:3873.78-3873.113" + cell $eq $eq$ls180.v:3873$353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3873$353_Y + end + attribute \src "ls180.v:3876.78-3876.113" + cell $eq $eq$ls180.v:3876$356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3876$356_Y + end + attribute \src "ls180.v:3882.78-3882.113" + cell $eq $eq$ls180.v:3882$360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3882$360_Y + end + attribute \src "ls180.v:3885.78-3885.113" + cell $eq $eq$ls180.v:3885$363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3885$363_Y + end + attribute \src "ls180.v:3891.78-3891.113" + cell $eq $eq$ls180.v:3891$367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3891$367_Y + end + attribute \src "ls180.v:3894.78-3894.113" + cell $eq $eq$ls180.v:3894$370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3894$370_Y + end + attribute \src "ls180.v:3900.78-3900.113" + cell $eq $eq$ls180.v:3900$374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3900$374_Y + end + attribute \src "ls180.v:3903.78-3903.113" + cell $eq $eq$ls180.v:3903$377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3903$377_Y + end + attribute \src "ls180.v:3984.42-3984.82" + cell $eq $eq$ls180.v:3984$400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:3984$400_Y + end + attribute \src "ls180.v:3984.145-3984.178" + cell $eq $eq$ls180.v:3984$401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3984$401_Y + end + attribute \src "ls180.v:3984.220-3984.253" + cell $eq $eq$ls180.v:3984$404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3984$404_Y + end + attribute \src "ls180.v:3984.295-3984.328" + cell $eq $eq$ls180.v:3984$407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3984$407_Y + end + attribute \src "ls180.v:3989.42-3989.82" + cell $eq $eq$ls180.v:3989$416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:3989$416_Y + end + attribute \src "ls180.v:3989.145-3989.178" + cell $eq $eq$ls180.v:3989$417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3989$417_Y + end + attribute \src "ls180.v:3989.220-3989.253" + cell $eq $eq$ls180.v:3989$420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3989$420_Y + end + attribute \src "ls180.v:3989.295-3989.328" + cell $eq $eq$ls180.v:3989$423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3989$423_Y + end + attribute \src "ls180.v:3994.42-3994.82" + cell $eq $eq$ls180.v:3994$432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:3994$432_Y + end + attribute \src "ls180.v:3994.145-3994.178" + cell $eq $eq$ls180.v:3994$433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3994$433_Y + end + attribute \src "ls180.v:3994.220-3994.253" + cell $eq $eq$ls180.v:3994$436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3994$436_Y + end + attribute \src "ls180.v:3994.295-3994.328" + cell $eq $eq$ls180.v:3994$439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3994$439_Y + end + attribute \src "ls180.v:3999.42-3999.82" + cell $eq $eq$ls180.v:3999$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:3999$448_Y + end + attribute \src "ls180.v:3999.145-3999.178" + cell $eq $eq$ls180.v:3999$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3999$449_Y + end + attribute \src "ls180.v:3999.220-3999.253" + cell $eq $eq$ls180.v:3999$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3999$452_Y + end + attribute \src "ls180.v:3999.295-3999.328" + cell $eq $eq$ls180.v:3999$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3999$455_Y + end + attribute \src "ls180.v:4004.44-4004.77" + cell $eq $eq$ls180.v:4004$464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$464_Y + end + attribute \src "ls180.v:4004.83-4004.123" + cell $eq $eq$ls180.v:4004$465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:4004$465_Y + end + attribute \src "ls180.v:4004.186-4004.219" + cell $eq $eq$ls180.v:4004$466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$466_Y + end + attribute \src "ls180.v:4004.261-4004.294" + cell $eq $eq$ls180.v:4004$469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$469_Y + end + attribute \src "ls180.v:4004.336-4004.369" + cell $eq $eq$ls180.v:4004$472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$472_Y + end + attribute \src "ls180.v:4004.418-4004.451" + cell $eq $eq$ls180.v:4004$480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$480_Y + end + attribute \src "ls180.v:4004.457-4004.497" + cell $eq $eq$ls180.v:4004$481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:4004$481_Y + end + attribute \src "ls180.v:4004.560-4004.593" + cell $eq $eq$ls180.v:4004$482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$482_Y + end + attribute \src "ls180.v:4004.635-4004.668" + cell $eq $eq$ls180.v:4004$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$485_Y + end + attribute \src "ls180.v:4004.710-4004.743" + cell $eq $eq$ls180.v:4004$488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$488_Y + end + attribute \src "ls180.v:4004.792-4004.825" + cell $eq $eq$ls180.v:4004$496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$496_Y + end + attribute \src "ls180.v:4004.831-4004.871" + cell $eq $eq$ls180.v:4004$497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:4004$497_Y + end + attribute \src "ls180.v:4004.934-4004.967" + cell $eq $eq$ls180.v:4004$498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$498_Y + end + attribute \src "ls180.v:4004.1009-4004.1042" + cell $eq $eq$ls180.v:4004$501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$501_Y + end + attribute \src "ls180.v:4004.1084-4004.1117" + cell $eq $eq$ls180.v:4004$504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$504_Y + end + attribute \src "ls180.v:4004.1166-4004.1199" + cell $eq $eq$ls180.v:4004$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$512_Y + end + attribute \src "ls180.v:4004.1205-4004.1245" + cell $eq $eq$ls180.v:4004$513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:4004$513_Y + end + attribute \src "ls180.v:4004.1308-4004.1341" + cell $eq $eq$ls180.v:4004$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$514_Y + end + attribute \src "ls180.v:4004.1383-4004.1416" + cell $eq $eq$ls180.v:4004$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$517_Y + end + attribute \src "ls180.v:4004.1458-4004.1491" + cell $eq $eq$ls180.v:4004$520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4004$520_Y + end + attribute \src "ls180.v:4063.29-4063.57" + cell $eq $eq$ls180.v:4063$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_sel + connect \B 1'0 + connect \Y $eq$ls180.v:4063$533_Y + end + attribute \src "ls180.v:4070.11-4070.41" + cell $eq $eq$ls180.v:4070$538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $eq$ls180.v:4070$538_Y + end + attribute \src "ls180.v:4227.37-4227.111" + cell $eq $eq$ls180.v:4227$603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4227$602_Y + connect \Y $eq$ls180.v:4227$603_Y + end + attribute \src "ls180.v:4228.37-4228.105" + cell $eq $eq$ls180.v:4228$605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4228$604_Y + connect \Y $eq$ls180.v:4228$605_Y + end + attribute \src "ls180.v:4255.10-4255.67" + cell $eq $eq$ls180.v:4255$609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spimaster27_count + connect \B $sub$ls180.v:4255$608_Y + connect \Y $eq$ls180.v:4255$609_Y + end + attribute \src "ls180.v:4285.35-4285.108" + cell $eq $eq$ls180.v:4285$611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4285$610_Y + connect \Y $eq$ls180.v:4285$611_Y + end + attribute \src "ls180.v:4286.35-4286.102" + cell $eq $eq$ls180.v:4286$613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4286$612_Y + connect \Y $eq$ls180.v:4286$613_Y + end + attribute \src "ls180.v:4314.10-4314.65" + cell $eq $eq$ls180.v:4314$617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_count + connect \B $sub$ls180.v:4314$616_Y + connect \Y $eq$ls180.v:4314$617_Y + end + attribute \src "ls180.v:4418.10-4418.40" + cell $eq $eq$ls180.v:4418$644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_count + connect \B 7'1001111 + connect \Y $eq$ls180.v:4418$644_Y + end + attribute \src "ls180.v:4475.10-4475.39" + cell $eq $eq$ls180.v:4475$647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4475$647_Y + end + attribute \src "ls180.v:4492.10-4492.39" + cell $eq $eq$ls180.v:4492$649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4492$649_Y + end + attribute \src "ls180.v:4520.38-4520.88" + cell $eq $eq$ls180.v:4520$651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \B 1'0 + connect \Y $eq$ls180.v:4520$651_Y + end + attribute \src "ls180.v:4570.9-4570.40" + cell $eq $eq$ls180.v:4570$661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4570$661_Y + end + attribute \src "ls180.v:4579.36-4579.105" + cell $eq $eq$ls180.v:4579$663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B $sub$ls180.v:4579$662_Y + connect \Y $eq$ls180.v:4579$663_Y + end + attribute \src "ls180.v:4598.9-4598.40" + cell $eq $eq$ls180.v:4598$667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4598$667_Y + end + attribute \src "ls180.v:4610.10-4610.39" + cell $eq $eq$ls180.v:4610$669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B 3'111 + connect \Y $eq$ls180.v:4610$669_Y + end + attribute \src "ls180.v:4647.39-4647.94" + cell $eq $eq$ls180.v:4647$673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \B 1'0 + connect \Y $eq$ls180.v:4647$673_Y + end + attribute \src "ls180.v:4684.32-4684.89" + cell $eq $eq$ls180.v:4684$682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $eq$ls180.v:4684$682_Y + end + attribute \src "ls180.v:4732.10-4732.40" + cell $eq $eq$ls180.v:4732$686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $eq$ls180.v:4732$686_Y + end + attribute \src "ls180.v:4781.40-4781.98" + cell $eq $eq$ls180.v:4781$688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_payload_data_i + connect \B 1'0 + connect \Y $eq$ls180.v:4781$688_Y + end + attribute \src "ls180.v:4832.9-4832.41" + cell $eq $eq$ls180.v:4832$698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4832$698_Y + end + attribute \src "ls180.v:4841.37-4841.123" + cell $eq $eq$ls180.v:4841$701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B $sub$ls180.v:4841$700_Y + connect \Y $eq$ls180.v:4841$701_Y + end + attribute \src "ls180.v:4864.9-4864.41" + cell $eq $eq$ls180.v:4864$704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4864$704_Y + end + attribute \src "ls180.v:4874.10-4874.41" + cell $eq $eq$ls180.v:4874$706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B 6'100111 + connect \Y $eq$ls180.v:4874$706_Y + end + attribute \src "ls180.v:5043.9-5043.47" + cell $eq $eq$ls180.v:5043$888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5043$888_Y + end + attribute \src "ls180.v:5073.10-5073.48" + cell $eq $eq$ls180.v:5073$889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5073$889_Y + end + attribute \src "ls180.v:5104.10-5104.78" + cell $eq $eq$ls180.v:5104$894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo0 + connect \B \main_sdcore_crc16_checker_crctmp0 + connect \Y $eq$ls180.v:5104$894_Y + end + attribute \src "ls180.v:5104.83-5104.151" + cell $eq $eq$ls180.v:5104$895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo1 + connect \B \main_sdcore_crc16_checker_crctmp1 + connect \Y $eq$ls180.v:5104$895_Y + end + attribute \src "ls180.v:5104.157-5104.225" + cell $eq $eq$ls180.v:5104$897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo2 + connect \B \main_sdcore_crc16_checker_crctmp2 + connect \Y $eq$ls180.v:5104$897_Y + end + attribute \src "ls180.v:5104.231-5104.299" + cell $eq $eq$ls180.v:5104$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo3 + connect \B \main_sdcore_crc16_checker_crctmp3 + connect \Y $eq$ls180.v:5104$899_Y + end + attribute \src "ls180.v:5112.7-5112.44" + cell $eq $eq$ls180.v:5112$903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5112$903_Y + end + attribute \src "ls180.v:5122.7-5122.44" + cell $eq $eq$ls180.v:5122$906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5122$906_Y + end + attribute \src "ls180.v:5132.7-5132.44" + cell $eq $eq$ls180.v:5132$909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5132$909_Y + end + attribute \src "ls180.v:5142.7-5142.44" + cell $eq $eq$ls180.v:5142$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5142$912_Y + end + attribute \src "ls180.v:5266.36-5266.64" + cell $eq $eq$ls180.v:5266$963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5266$963_Y + end + attribute \src "ls180.v:5272.10-5272.39" + cell $eq $eq$ls180.v:5272$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_count + connect \B 3'101 + connect \Y $eq$ls180.v:5272$966_Y + end + attribute \src "ls180.v:5273.11-5273.39" + cell $eq $eq$ls180.v:5273$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5273$967_Y + end + attribute \src "ls180.v:5285.34-5285.63" + cell $eq $eq$ls180.v:5285$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'0 + connect \Y $eq$ls180.v:5285$968_Y + end + attribute \src "ls180.v:5286.9-5286.37" + cell $eq $eq$ls180.v:5286$969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 2'10 + connect \Y $eq$ls180.v:5286$969_Y + end + attribute \src "ls180.v:5293.10-5293.55" + cell $eq $eq$ls180.v:5293$970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5293$970_Y + end + attribute \src "ls180.v:5299.12-5299.41" + cell $eq $eq$ls180.v:5299$971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 2'10 + connect \Y $eq$ls180.v:5299$971_Y + end + attribute \src "ls180.v:5302.13-5302.42" + cell $eq $eq$ls180.v:5302$972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'1 + connect \Y $eq$ls180.v:5302$972_Y + end + attribute \src "ls180.v:5324.10-5324.76" + cell $eq $eq$ls180.v:5324$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5324$976_Y + connect \Y $eq$ls180.v:5324$977_Y + end + attribute \src "ls180.v:5339.35-5339.101" + cell $eq $eq$ls180.v:5339$980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5339$979_Y + connect \Y $eq$ls180.v:5339$980_Y + end + attribute \src "ls180.v:5341.10-5341.56" + cell $eq $eq$ls180.v:5341$981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'0 + connect \Y $eq$ls180.v:5341$981_Y + end + attribute \src "ls180.v:5350.12-5350.78" + cell $eq $eq$ls180.v:5350$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5350$984_Y + connect \Y $eq$ls180.v:5350$985_Y + end + attribute \src "ls180.v:5357.11-5357.57" + cell $eq $eq$ls180.v:5357$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5357$986_Y + end + attribute \src "ls180.v:5474.10-5474.105" + cell $eq $eq$ls180.v:5474$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B $sub$ls180.v:5474$1002_Y + connect \Y $eq$ls180.v:5474$1003_Y + end + attribute \src "ls180.v:5564.39-5564.106" + cell $eq $eq$ls180.v:5564$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_offset + connect \B $sub$ls180.v:5564$1008_Y + connect \Y $eq$ls180.v:5564$1009_Y + end + attribute \src "ls180.v:5594.44-5594.82" + cell $eq $eq$ls180.v:5594$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 1'0 + connect \Y $eq$ls180.v:5594$1012_Y + end + attribute \src "ls180.v:5595.43-5595.81" + cell $eq $eq$ls180.v:5595$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 2'11 + connect \Y $eq$ls180.v:5595$1013_Y + end + attribute \src "ls180.v:5695.85-5695.106" + cell $eq $eq$ls180.v:5695$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5695$1029_Y + end + attribute \src "ls180.v:5696.85-5696.106" + cell $eq $eq$ls180.v:5696$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5696$1031_Y + end + attribute \src "ls180.v:5697.85-5697.106" + cell $eq $eq$ls180.v:5697$1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5697$1033_Y + end + attribute \src "ls180.v:5698.57-5698.78" + cell $eq $eq$ls180.v:5698$1035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5698$1035_Y + end + attribute \src "ls180.v:5699.57-5699.78" + cell $eq $eq$ls180.v:5699$1037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5699$1037_Y + end + attribute \src "ls180.v:5700.85-5700.106" + cell $eq $eq$ls180.v:5700$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5700$1039_Y + end + attribute \src "ls180.v:5701.85-5701.106" + cell $eq $eq$ls180.v:5701$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5701$1041_Y + end + attribute \src "ls180.v:5702.85-5702.106" + cell $eq $eq$ls180.v:5702$1043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5702$1043_Y + end + attribute \src "ls180.v:5703.57-5703.78" + cell $eq $eq$ls180.v:5703$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5703$1045_Y + end + attribute \src "ls180.v:5704.57-5704.78" + cell $eq $eq$ls180.v:5704$1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5704$1047_Y + end + attribute \src "ls180.v:5708.27-5708.59" + cell $eq $eq$ls180.v:5708$1050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 23 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:7] + connect \B 1'0 + connect \Y $eq$ls180.v:5708$1050_Y + end + attribute \src "ls180.v:5709.27-5709.68" + cell $eq $eq$ls180.v:5709$1051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 27 + parameter \B_SIGNED 0 + parameter \B_WIDTH 27 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:3] + connect \B 27'110000000000000100000000000 + connect \Y $eq$ls180.v:5709$1051_Y + end + attribute \src "ls180.v:5710.27-5710.66" + cell $eq $eq$ls180.v:5710$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 20 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:10] + connect \B 20'11000000000000010001 + connect \Y $eq$ls180.v:5710$1052_Y + end + attribute \src "ls180.v:5711.27-5711.61" + cell $eq $eq$ls180.v:5711$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:23] + connect \B 7'1001000 + connect \Y $eq$ls180.v:5711$1053_Y + end + attribute \src "ls180.v:5712.27-5712.65" + cell $eq $eq$ls180.v:5712$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:14] + connect \B 16'1100000000000000 + connect \Y $eq$ls180.v:5712$1054_Y + end + attribute \src "ls180.v:5768.24-5768.45" + cell $eq $eq$ls180.v:5768$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_count + connect \B 1'0 + connect \Y $eq$ls180.v:5768$1081_Y + end + attribute \src "ls180.v:5769.32-5769.77" + cell $eq $eq$ls180.v:5769$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [13:9] + connect \B 1'0 + connect \Y $eq$ls180.v:5769$1082_Y + end + attribute \src "ls180.v:5771.97-5771.141" + cell $eq $eq$ls180.v:5771$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5771$1084_Y + end + attribute \src "ls180.v:5772.100-5772.144" + cell $eq $eq$ls180.v:5772$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5772$1088_Y + end + attribute \src "ls180.v:5774.99-5774.143" + cell $eq $eq$ls180.v:5774$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5774$1091_Y + end + attribute \src "ls180.v:5775.102-5775.146" + cell $eq $eq$ls180.v:5775$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5775$1095_Y + end + attribute \src "ls180.v:5777.99-5777.143" + cell $eq $eq$ls180.v:5777$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5777$1098_Y + end + attribute \src "ls180.v:5778.102-5778.146" + cell $eq $eq$ls180.v:5778$1102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5778$1102_Y + end + attribute \src "ls180.v:5780.99-5780.143" + cell $eq $eq$ls180.v:5780$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5780$1105_Y + end + attribute \src "ls180.v:5781.102-5781.146" + cell $eq $eq$ls180.v:5781$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5781$1109_Y + end + attribute \src "ls180.v:5783.99-5783.143" + cell $eq $eq$ls180.v:5783$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5783$1112_Y + end + attribute \src "ls180.v:5784.102-5784.146" + cell $eq $eq$ls180.v:5784$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5784$1116_Y + end + attribute \src "ls180.v:5786.102-5786.146" + cell $eq $eq$ls180.v:5786$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5786$1119_Y + end + attribute \src "ls180.v:5787.105-5787.149" + cell $eq $eq$ls180.v:5787$1123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5787$1123_Y + end + attribute \src "ls180.v:5789.102-5789.146" + cell $eq $eq$ls180.v:5789$1126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5789$1126_Y + end + attribute \src "ls180.v:5790.105-5790.149" + cell $eq $eq$ls180.v:5790$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5790$1130_Y + end + attribute \src "ls180.v:5792.102-5792.146" + cell $eq $eq$ls180.v:5792$1133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5792$1133_Y + end + attribute \src "ls180.v:5793.105-5793.149" + cell $eq $eq$ls180.v:5793$1137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5793$1137_Y + end + attribute \src "ls180.v:5795.102-5795.146" + cell $eq $eq$ls180.v:5795$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5795$1140_Y + end + attribute \src "ls180.v:5796.105-5796.149" + cell $eq $eq$ls180.v:5796$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5796$1144_Y + end + attribute \src "ls180.v:5807.32-5807.77" + cell $eq $eq$ls180.v:5807$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [13:9] + connect \B 3'110 + connect \Y $eq$ls180.v:5807$1146_Y + end + attribute \src "ls180.v:5809.94-5809.138" + cell $eq $eq$ls180.v:5809$1148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5809$1148_Y + end + attribute \src "ls180.v:5810.97-5810.141" + cell $eq $eq$ls180.v:5810$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5810$1152_Y + end + attribute \src "ls180.v:5812.94-5812.138" + cell $eq $eq$ls180.v:5812$1155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5812$1155_Y + end + attribute \src "ls180.v:5813.97-5813.141" + cell $eq $eq$ls180.v:5813$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5813$1159_Y + end + attribute \src "ls180.v:5815.94-5815.138" + cell $eq $eq$ls180.v:5815$1162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5815$1162_Y + end + attribute \src "ls180.v:5816.97-5816.141" + cell $eq $eq$ls180.v:5816$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5816$1166_Y + end + attribute \src "ls180.v:5818.94-5818.138" + cell $eq $eq$ls180.v:5818$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5818$1169_Y + end + attribute \src "ls180.v:5819.97-5819.141" + cell $eq $eq$ls180.v:5819$1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5819$1173_Y + end + attribute \src "ls180.v:5821.95-5821.139" + cell $eq $eq$ls180.v:5821$1176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5821$1176_Y + end + attribute \src "ls180.v:5822.98-5822.142" + cell $eq $eq$ls180.v:5822$1180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5822$1180_Y + end + attribute \src "ls180.v:5824.95-5824.139" + cell $eq $eq$ls180.v:5824$1183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5824$1183_Y + end + attribute \src "ls180.v:5825.98-5825.142" + cell $eq $eq$ls180.v:5825$1187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5825$1187_Y + end + attribute \src "ls180.v:5833.32-5833.78" + cell $eq $eq$ls180.v:5833$1189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [13:9] + connect \B 4'1011 + connect \Y $eq$ls180.v:5833$1189_Y + end + attribute \src "ls180.v:5835.93-5835.135" + cell $eq $eq$ls180.v:5835$1191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:5835$1191_Y + end + attribute \src "ls180.v:5836.96-5836.138" + cell $eq $eq$ls180.v:5836$1195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:5836$1195_Y + end + attribute \src "ls180.v:5838.92-5838.134" + cell $eq $eq$ls180.v:5838$1198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:5838$1198_Y + end + attribute \src "ls180.v:5839.95-5839.137" + cell $eq $eq$ls180.v:5839$1202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:5839$1202_Y + end + attribute \src "ls180.v:5847.32-5847.77" + cell $eq $eq$ls180.v:5847$1204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [13:9] + connect \B 4'1001 + connect \Y $eq$ls180.v:5847$1204_Y + end + attribute \src "ls180.v:5849.98-5849.142" + cell $eq $eq$ls180.v:5849$1206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5849$1206_Y + end + attribute \src "ls180.v:5850.101-5850.145" + cell $eq $eq$ls180.v:5850$1210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5850$1210_Y + end + attribute \src "ls180.v:5852.97-5852.141" + cell $eq $eq$ls180.v:5852$1213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5852$1213_Y + end + attribute \src "ls180.v:5853.100-5853.144" + cell $eq $eq$ls180.v:5853$1217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5853$1217_Y + end + attribute \src "ls180.v:5855.97-5855.141" + cell $eq $eq$ls180.v:5855$1220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5855$1220_Y + end + attribute \src "ls180.v:5856.100-5856.144" + cell $eq $eq$ls180.v:5856$1224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5856$1224_Y + end + attribute \src "ls180.v:5858.97-5858.141" + cell $eq $eq$ls180.v:5858$1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5858$1227_Y + end + attribute \src "ls180.v:5859.100-5859.144" + cell $eq $eq$ls180.v:5859$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5859$1231_Y + end + attribute \src "ls180.v:5861.97-5861.141" + cell $eq $eq$ls180.v:5861$1234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5861$1234_Y + end + attribute \src "ls180.v:5862.100-5862.144" + cell $eq $eq$ls180.v:5862$1238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5862$1238_Y + end + attribute \src "ls180.v:5864.98-5864.142" + cell $eq $eq$ls180.v:5864$1241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5864$1241_Y + end + attribute \src "ls180.v:5865.101-5865.145" + cell $eq $eq$ls180.v:5865$1245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5865$1245_Y + end + attribute \src "ls180.v:5867.98-5867.142" + cell $eq $eq$ls180.v:5867$1248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5867$1248_Y + end + attribute \src "ls180.v:5868.101-5868.145" + cell $eq $eq$ls180.v:5868$1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5868$1252_Y + end + attribute \src "ls180.v:5870.98-5870.142" + cell $eq $eq$ls180.v:5870$1255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5870$1255_Y + end + attribute \src "ls180.v:5871.101-5871.145" + cell $eq $eq$ls180.v:5871$1259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5871$1259_Y + end + attribute \src "ls180.v:5873.98-5873.142" + cell $eq $eq$ls180.v:5873$1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5873$1262_Y + end + attribute \src "ls180.v:5874.101-5874.145" + cell $eq $eq$ls180.v:5874$1266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5874$1266_Y + end + attribute \src "ls180.v:5884.32-5884.78" + cell $eq $eq$ls180.v:5884$1268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [13:9] + connect \B 4'1010 + connect \Y $eq$ls180.v:5884$1268_Y + end + attribute \src "ls180.v:5886.98-5886.142" + cell $eq $eq$ls180.v:5886$1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5886$1270_Y + end + attribute \src "ls180.v:5887.101-5887.145" + cell $eq $eq$ls180.v:5887$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5887$1274_Y + end + attribute \src "ls180.v:5889.97-5889.141" + cell $eq $eq$ls180.v:5889$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5889$1277_Y + end + attribute \src "ls180.v:5890.100-5890.144" + cell $eq $eq$ls180.v:5890$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5890$1281_Y + end + attribute \src "ls180.v:5892.97-5892.141" + cell $eq $eq$ls180.v:5892$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5892$1284_Y + end + attribute \src "ls180.v:5893.100-5893.144" + cell $eq $eq$ls180.v:5893$1288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5893$1288_Y + end + attribute \src "ls180.v:5895.97-5895.141" + cell $eq $eq$ls180.v:5895$1291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5895$1291_Y + end + attribute \src "ls180.v:5896.100-5896.144" + cell $eq $eq$ls180.v:5896$1295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5896$1295_Y + end + attribute \src "ls180.v:5898.97-5898.141" + cell $eq $eq$ls180.v:5898$1298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5898$1298_Y + end + attribute \src "ls180.v:5899.100-5899.144" + cell $eq $eq$ls180.v:5899$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5899$1302_Y + end + attribute \src "ls180.v:5901.98-5901.142" + cell $eq $eq$ls180.v:5901$1305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5901$1305_Y + end + attribute \src "ls180.v:5902.101-5902.145" + cell $eq $eq$ls180.v:5902$1309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5902$1309_Y + end + attribute \src "ls180.v:5904.98-5904.142" + cell $eq $eq$ls180.v:5904$1312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5904$1312_Y + end + attribute \src "ls180.v:5905.101-5905.145" + cell $eq $eq$ls180.v:5905$1316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5905$1316_Y + end + attribute \src "ls180.v:5907.98-5907.142" + cell $eq $eq$ls180.v:5907$1319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5907$1319_Y + end + attribute \src "ls180.v:5908.101-5908.145" + cell $eq $eq$ls180.v:5908$1323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5908$1323_Y + end + attribute \src "ls180.v:5910.98-5910.142" + cell $eq $eq$ls180.v:5910$1326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5910$1326_Y + end + attribute \src "ls180.v:5911.101-5911.145" + cell $eq $eq$ls180.v:5911$1330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5911$1330_Y + end + attribute \src "ls180.v:5921.32-5921.78" + cell $eq $eq$ls180.v:5921$1332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [13:9] + connect \B 4'1110 + connect \Y $eq$ls180.v:5921$1332_Y + end + attribute \src "ls180.v:5923.100-5923.144" + cell $eq $eq$ls180.v:5923$1334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5923$1334_Y + end + attribute \src "ls180.v:5924.103-5924.147" + cell $eq $eq$ls180.v:5924$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5924$1338_Y + end + attribute \src "ls180.v:5926.100-5926.144" + cell $eq $eq$ls180.v:5926$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5926$1341_Y + end + attribute \src "ls180.v:5927.103-5927.147" + cell $eq $eq$ls180.v:5927$1345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5927$1345_Y + end + attribute \src "ls180.v:5929.100-5929.144" + cell $eq $eq$ls180.v:5929$1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5929$1348_Y + end + attribute \src "ls180.v:5930.103-5930.147" + cell $eq $eq$ls180.v:5930$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5930$1352_Y + end + attribute \src "ls180.v:5932.100-5932.144" + cell $eq $eq$ls180.v:5932$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5932$1355_Y + end + attribute \src "ls180.v:5933.103-5933.147" + cell $eq $eq$ls180.v:5933$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5933$1359_Y + end + attribute \src "ls180.v:5935.100-5935.144" + cell $eq $eq$ls180.v:5935$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5935$1362_Y + end + attribute \src "ls180.v:5936.103-5936.147" + cell $eq $eq$ls180.v:5936$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5936$1366_Y + end + attribute \src "ls180.v:5938.100-5938.144" + cell $eq $eq$ls180.v:5938$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5938$1369_Y + end + attribute \src "ls180.v:5939.103-5939.147" + cell $eq $eq$ls180.v:5939$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5939$1373_Y + end + attribute \src "ls180.v:5941.100-5941.144" + cell $eq $eq$ls180.v:5941$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5941$1376_Y + end + attribute \src "ls180.v:5942.103-5942.147" + cell $eq $eq$ls180.v:5942$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5942$1380_Y + end + attribute \src "ls180.v:5944.100-5944.144" + cell $eq $eq$ls180.v:5944$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5944$1383_Y + end + attribute \src "ls180.v:5945.103-5945.147" + cell $eq $eq$ls180.v:5945$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5945$1387_Y + end + attribute \src "ls180.v:5947.102-5947.146" + cell $eq $eq$ls180.v:5947$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5947$1390_Y + end + attribute \src "ls180.v:5948.105-5948.149" + cell $eq $eq$ls180.v:5948$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5948$1394_Y + end + attribute \src "ls180.v:5950.102-5950.146" + cell $eq $eq$ls180.v:5950$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5950$1397_Y + end + attribute \src "ls180.v:5951.105-5951.149" + cell $eq $eq$ls180.v:5951$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5951$1401_Y + end + attribute \src "ls180.v:5953.102-5953.147" + cell $eq $eq$ls180.v:5953$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5953$1404_Y + end + attribute \src "ls180.v:5954.105-5954.150" + cell $eq $eq$ls180.v:5954$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5954$1408_Y + end + attribute \src "ls180.v:5956.102-5956.147" + cell $eq $eq$ls180.v:5956$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5956$1411_Y + end + attribute \src "ls180.v:5957.105-5957.150" + cell $eq $eq$ls180.v:5957$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5957$1415_Y + end + attribute \src "ls180.v:5959.102-5959.147" + cell $eq $eq$ls180.v:5959$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5959$1418_Y + end + attribute \src "ls180.v:5960.105-5960.150" + cell $eq $eq$ls180.v:5960$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5960$1422_Y + end + attribute \src "ls180.v:5962.99-5962.144" + cell $eq $eq$ls180.v:5962$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5962$1425_Y + end + attribute \src "ls180.v:5963.102-5963.147" + cell $eq $eq$ls180.v:5963$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5963$1429_Y + end + attribute \src "ls180.v:5965.100-5965.145" + cell $eq $eq$ls180.v:5965$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5965$1432_Y + end + attribute \src "ls180.v:5966.103-5966.148" + cell $eq $eq$ls180.v:5966$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5966$1436_Y + end + attribute \src "ls180.v:5983.32-5983.78" + cell $eq $eq$ls180.v:5983$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [13:9] + connect \B 4'1101 + connect \Y $eq$ls180.v:5983$1438_Y + end + attribute \src "ls180.v:5985.104-5985.148" + cell $eq $eq$ls180.v:5985$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5985$1440_Y + end + attribute \src "ls180.v:5986.107-5986.151" + cell $eq $eq$ls180.v:5986$1444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5986$1444_Y + end + attribute \src "ls180.v:5988.104-5988.148" + cell $eq $eq$ls180.v:5988$1447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5988$1447_Y + end + attribute \src "ls180.v:5989.107-5989.151" + cell $eq $eq$ls180.v:5989$1451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5989$1451_Y + end + attribute \src "ls180.v:5991.104-5991.148" + cell $eq $eq$ls180.v:5991$1454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5991$1454_Y + end + attribute \src "ls180.v:5992.107-5992.151" + cell $eq $eq$ls180.v:5992$1458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5992$1458_Y + end + attribute \src "ls180.v:5994.104-5994.148" + cell $eq $eq$ls180.v:5994$1461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5994$1461_Y + end + attribute \src "ls180.v:5995.107-5995.151" + cell $eq $eq$ls180.v:5995$1465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5995$1465_Y + end + attribute \src "ls180.v:5997.103-5997.147" + cell $eq $eq$ls180.v:5997$1468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5997$1468_Y + end + attribute \src "ls180.v:5998.106-5998.150" + cell $eq $eq$ls180.v:5998$1472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5998$1472_Y + end + attribute \src "ls180.v:6000.103-6000.147" + cell $eq $eq$ls180.v:6000$1475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6000$1475_Y + end + attribute \src "ls180.v:6001.106-6001.150" + cell $eq $eq$ls180.v:6001$1479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6001$1479_Y + end + attribute \src "ls180.v:6003.103-6003.147" + cell $eq $eq$ls180.v:6003$1482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6003$1482_Y + end + attribute \src "ls180.v:6004.106-6004.150" + cell $eq $eq$ls180.v:6004$1486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6004$1486_Y + end + attribute \src "ls180.v:6006.103-6006.147" + cell $eq $eq$ls180.v:6006$1489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6006$1489_Y + end + attribute \src "ls180.v:6007.106-6007.150" + cell $eq $eq$ls180.v:6007$1493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6007$1493_Y + end + attribute \src "ls180.v:6009.94-6009.138" + cell $eq $eq$ls180.v:6009$1496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6009$1496_Y + end + attribute \src "ls180.v:6010.97-6010.141" + cell $eq $eq$ls180.v:6010$1500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6010$1500_Y + end + attribute \src "ls180.v:6012.105-6012.149" + cell $eq $eq$ls180.v:6012$1503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6012$1503_Y + end + attribute \src "ls180.v:6013.108-6013.152" + cell $eq $eq$ls180.v:6013$1507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6013$1507_Y + end + attribute \src "ls180.v:6015.105-6015.150" + cell $eq $eq$ls180.v:6015$1510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6015$1510_Y + end + attribute \src "ls180.v:6016.108-6016.153" + cell $eq $eq$ls180.v:6016$1514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6016$1514_Y + end + attribute \src "ls180.v:6018.105-6018.150" + cell $eq $eq$ls180.v:6018$1517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6018$1517_Y + end + attribute \src "ls180.v:6019.108-6019.153" + cell $eq $eq$ls180.v:6019$1521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6019$1521_Y + end + attribute \src "ls180.v:6021.105-6021.150" + cell $eq $eq$ls180.v:6021$1524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6021$1524_Y + end + attribute \src "ls180.v:6022.108-6022.153" + cell $eq $eq$ls180.v:6022$1528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6022$1528_Y + end + attribute \src "ls180.v:6024.105-6024.150" + cell $eq $eq$ls180.v:6024$1531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6024$1531_Y + end + attribute \src "ls180.v:6025.108-6025.153" + cell $eq $eq$ls180.v:6025$1535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6025$1535_Y + end + attribute \src "ls180.v:6027.105-6027.150" + cell $eq $eq$ls180.v:6027$1538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6027$1538_Y + end + attribute \src "ls180.v:6028.108-6028.153" + cell $eq $eq$ls180.v:6028$1542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6028$1542_Y + end + attribute \src "ls180.v:6030.104-6030.149" + cell $eq $eq$ls180.v:6030$1545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6030$1545_Y + end + attribute \src "ls180.v:6031.107-6031.152" + cell $eq $eq$ls180.v:6031$1549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6031$1549_Y + end + attribute \src "ls180.v:6033.104-6033.149" + cell $eq $eq$ls180.v:6033$1552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6033$1552_Y + end + attribute \src "ls180.v:6034.107-6034.152" + cell $eq $eq$ls180.v:6034$1556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6034$1556_Y + end + attribute \src "ls180.v:6036.104-6036.149" + cell $eq $eq$ls180.v:6036$1559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6036$1559_Y + end + attribute \src "ls180.v:6037.107-6037.152" + cell $eq $eq$ls180.v:6037$1563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6037$1563_Y + end + attribute \src "ls180.v:6039.104-6039.149" + cell $eq $eq$ls180.v:6039$1566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6039$1566_Y + end + attribute \src "ls180.v:6040.107-6040.152" + cell $eq $eq$ls180.v:6040$1570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6040$1570_Y + end + attribute \src "ls180.v:6042.104-6042.149" + cell $eq $eq$ls180.v:6042$1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6042$1573_Y + end + attribute \src "ls180.v:6043.107-6043.152" + cell $eq $eq$ls180.v:6043$1577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6043$1577_Y + end + attribute \src "ls180.v:6045.104-6045.149" + cell $eq $eq$ls180.v:6045$1580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6045$1580_Y + end + attribute \src "ls180.v:6046.107-6046.152" + cell $eq $eq$ls180.v:6046$1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6046$1584_Y + end + attribute \src "ls180.v:6048.104-6048.149" + cell $eq $eq$ls180.v:6048$1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6048$1587_Y + end + attribute \src "ls180.v:6049.107-6049.152" + cell $eq $eq$ls180.v:6049$1591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6049$1591_Y + end + attribute \src "ls180.v:6051.104-6051.149" + cell $eq $eq$ls180.v:6051$1594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6051$1594_Y + end + attribute \src "ls180.v:6052.107-6052.152" + cell $eq $eq$ls180.v:6052$1598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6052$1598_Y + end + attribute \src "ls180.v:6054.104-6054.149" + cell $eq $eq$ls180.v:6054$1601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6054$1601_Y + end + attribute \src "ls180.v:6055.107-6055.152" + cell $eq $eq$ls180.v:6055$1605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6055$1605_Y + end + attribute \src "ls180.v:6057.104-6057.149" + cell $eq $eq$ls180.v:6057$1608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6057$1608_Y + end + attribute \src "ls180.v:6058.107-6058.152" + cell $eq $eq$ls180.v:6058$1612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6058$1612_Y + end + attribute \src "ls180.v:6060.100-6060.145" + cell $eq $eq$ls180.v:6060$1615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6060$1615_Y + end + attribute \src "ls180.v:6061.103-6061.148" + cell $eq $eq$ls180.v:6061$1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6061$1619_Y + end + attribute \src "ls180.v:6063.101-6063.146" + cell $eq $eq$ls180.v:6063$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6063$1622_Y + end + attribute \src "ls180.v:6064.104-6064.149" + cell $eq $eq$ls180.v:6064$1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6064$1626_Y + end + attribute \src "ls180.v:6066.104-6066.149" + cell $eq $eq$ls180.v:6066$1629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6066$1629_Y + end + attribute \src "ls180.v:6067.107-6067.152" + cell $eq $eq$ls180.v:6067$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6067$1633_Y + end + attribute \src "ls180.v:6069.104-6069.149" + cell $eq $eq$ls180.v:6069$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6069$1636_Y + end + attribute \src "ls180.v:6070.107-6070.152" + cell $eq $eq$ls180.v:6070$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6070$1640_Y + end + attribute \src "ls180.v:6072.103-6072.148" + cell $eq $eq$ls180.v:6072$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6072$1643_Y + end + attribute \src "ls180.v:6073.106-6073.151" + cell $eq $eq$ls180.v:6073$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6073$1647_Y + end + attribute \src "ls180.v:6075.103-6075.148" + cell $eq $eq$ls180.v:6075$1650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6075$1650_Y + end + attribute \src "ls180.v:6076.106-6076.151" + cell $eq $eq$ls180.v:6076$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6076$1654_Y + end + attribute \src "ls180.v:6078.103-6078.148" + cell $eq $eq$ls180.v:6078$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6078$1657_Y + end + attribute \src "ls180.v:6079.106-6079.151" + cell $eq $eq$ls180.v:6079$1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6079$1661_Y + end + attribute \src "ls180.v:6081.103-6081.148" + cell $eq $eq$ls180.v:6081$1664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6081$1664_Y + end + attribute \src "ls180.v:6082.106-6082.151" + cell $eq $eq$ls180.v:6082$1668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6082$1668_Y + end + attribute \src "ls180.v:6118.32-6118.78" + cell $eq $eq$ls180.v:6118$1670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [13:9] + connect \B 4'1111 + connect \Y $eq$ls180.v:6118$1670_Y + end + attribute \src "ls180.v:6120.100-6120.144" + cell $eq $eq$ls180.v:6120$1672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6120$1672_Y + end + attribute \src "ls180.v:6121.103-6121.147" + cell $eq $eq$ls180.v:6121$1676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6121$1676_Y + end + attribute \src "ls180.v:6123.100-6123.144" + cell $eq $eq$ls180.v:6123$1679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6123$1679_Y + end + attribute \src "ls180.v:6124.103-6124.147" + cell $eq $eq$ls180.v:6124$1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6124$1683_Y + end + attribute \src "ls180.v:6126.100-6126.144" + cell $eq $eq$ls180.v:6126$1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6126$1686_Y + end + attribute \src "ls180.v:6127.103-6127.147" + cell $eq $eq$ls180.v:6127$1690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6127$1690_Y + end + attribute \src "ls180.v:6129.100-6129.144" + cell $eq $eq$ls180.v:6129$1693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6129$1693_Y + end + attribute \src "ls180.v:6130.103-6130.147" + cell $eq $eq$ls180.v:6130$1697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6130$1697_Y + end + attribute \src "ls180.v:6132.100-6132.144" + cell $eq $eq$ls180.v:6132$1700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6132$1700_Y + end + attribute \src "ls180.v:6133.103-6133.147" + cell $eq $eq$ls180.v:6133$1704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6133$1704_Y + end + attribute \src "ls180.v:6135.100-6135.144" + cell $eq $eq$ls180.v:6135$1707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6135$1707_Y + end + attribute \src "ls180.v:6136.103-6136.147" + cell $eq $eq$ls180.v:6136$1711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6136$1711_Y + end + attribute \src "ls180.v:6138.100-6138.144" + cell $eq $eq$ls180.v:6138$1714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6138$1714_Y + end + attribute \src "ls180.v:6139.103-6139.147" + cell $eq $eq$ls180.v:6139$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6139$1718_Y + end + attribute \src "ls180.v:6141.100-6141.144" + cell $eq $eq$ls180.v:6141$1721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6141$1721_Y + end + attribute \src "ls180.v:6142.103-6142.147" + cell $eq $eq$ls180.v:6142$1725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6142$1725_Y + end + attribute \src "ls180.v:6144.102-6144.146" + cell $eq $eq$ls180.v:6144$1728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6144$1728_Y + end + attribute \src "ls180.v:6145.105-6145.149" + cell $eq $eq$ls180.v:6145$1732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6145$1732_Y + end + attribute \src "ls180.v:6147.102-6147.146" + cell $eq $eq$ls180.v:6147$1735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6147$1735_Y + end + attribute \src "ls180.v:6148.105-6148.149" + cell $eq $eq$ls180.v:6148$1739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6148$1739_Y + end + attribute \src "ls180.v:6150.102-6150.147" + cell $eq $eq$ls180.v:6150$1742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6150$1742_Y + end + attribute \src "ls180.v:6151.105-6151.150" + cell $eq $eq$ls180.v:6151$1746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6151$1746_Y + end + attribute \src "ls180.v:6153.102-6153.147" + cell $eq $eq$ls180.v:6153$1749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6153$1749_Y + end + attribute \src "ls180.v:6154.105-6154.150" + cell $eq $eq$ls180.v:6154$1753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6154$1753_Y + end + attribute \src "ls180.v:6156.102-6156.147" + cell $eq $eq$ls180.v:6156$1756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6156$1756_Y + end + attribute \src "ls180.v:6157.105-6157.150" + cell $eq $eq$ls180.v:6157$1760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6157$1760_Y + end + attribute \src "ls180.v:6159.99-6159.144" + cell $eq $eq$ls180.v:6159$1763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6159$1763_Y + end + attribute \src "ls180.v:6160.102-6160.147" + cell $eq $eq$ls180.v:6160$1767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6160$1767_Y + end + attribute \src "ls180.v:6162.100-6162.145" + cell $eq $eq$ls180.v:6162$1770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6162$1770_Y + end + attribute \src "ls180.v:6163.103-6163.148" + cell $eq $eq$ls180.v:6163$1774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6163$1774_Y + end + attribute \src "ls180.v:6165.102-6165.147" + cell $eq $eq$ls180.v:6165$1777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6165$1777_Y + end + attribute \src "ls180.v:6166.105-6166.150" + cell $eq $eq$ls180.v:6166$1781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6166$1781_Y + end + attribute \src "ls180.v:6168.102-6168.147" + cell $eq $eq$ls180.v:6168$1784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6168$1784_Y + end + attribute \src "ls180.v:6169.105-6169.150" + cell $eq $eq$ls180.v:6169$1788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6169$1788_Y + end + attribute \src "ls180.v:6171.102-6171.147" + cell $eq $eq$ls180.v:6171$1791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6171$1791_Y + end + attribute \src "ls180.v:6172.105-6172.150" + cell $eq $eq$ls180.v:6172$1795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6172$1795_Y + end + attribute \src "ls180.v:6174.102-6174.147" + cell $eq $eq$ls180.v:6174$1798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6174$1798_Y + end + attribute \src "ls180.v:6175.105-6175.150" + cell $eq $eq$ls180.v:6175$1802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6175$1802_Y + end + attribute \src "ls180.v:6197.32-6197.78" + cell $eq $eq$ls180.v:6197$1804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [13:9] + connect \B 4'1100 + connect \Y $eq$ls180.v:6197$1804_Y + end + attribute \src "ls180.v:6199.102-6199.146" + cell $eq $eq$ls180.v:6199$1806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6199$1806_Y + end + attribute \src "ls180.v:6200.105-6200.149" + cell $eq $eq$ls180.v:6200$1810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6200$1810_Y + end + attribute \src "ls180.v:6202.107-6202.151" + cell $eq $eq$ls180.v:6202$1813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6202$1813_Y + end + attribute \src "ls180.v:6203.110-6203.154" + cell $eq $eq$ls180.v:6203$1817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6203$1817_Y + end + attribute \src "ls180.v:6205.107-6205.151" + cell $eq $eq$ls180.v:6205$1820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6205$1820_Y + end + attribute \src "ls180.v:6206.110-6206.154" + cell $eq $eq$ls180.v:6206$1824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6206$1824_Y + end + attribute \src "ls180.v:6208.100-6208.144" + cell $eq $eq$ls180.v:6208$1827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6208$1827_Y + end + attribute \src "ls180.v:6209.103-6209.147" + cell $eq $eq$ls180.v:6209$1831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6209$1831_Y + end + attribute \src "ls180.v:6214.32-6214.77" + cell $eq $eq$ls180.v:6214$1833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [13:9] + connect \B 2'11 + connect \Y $eq$ls180.v:6214$1833_Y + end + attribute \src "ls180.v:6216.104-6216.148" + cell $eq $eq$ls180.v:6216$1835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6216$1835_Y + end + attribute \src "ls180.v:6217.107-6217.151" + cell $eq $eq$ls180.v:6217$1839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6217$1839_Y + end + attribute \src "ls180.v:6219.108-6219.152" + cell $eq $eq$ls180.v:6219$1842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6219$1842_Y + end + attribute \src "ls180.v:6220.111-6220.155" + cell $eq $eq$ls180.v:6220$1846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6220$1846_Y + end + attribute \src "ls180.v:6222.98-6222.142" + cell $eq $eq$ls180.v:6222$1849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6222$1849_Y + end + attribute \src "ls180.v:6223.101-6223.145" + cell $eq $eq$ls180.v:6223$1853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6223$1853_Y + end + attribute \src "ls180.v:6225.108-6225.152" + cell $eq $eq$ls180.v:6225$1856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6225$1856_Y + end + attribute \src "ls180.v:6226.111-6226.155" + cell $eq $eq$ls180.v:6226$1860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6226$1860_Y + end + attribute \src "ls180.v:6228.108-6228.152" + cell $eq $eq$ls180.v:6228$1863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6228$1863_Y + end + attribute \src "ls180.v:6229.111-6229.155" + cell $eq $eq$ls180.v:6229$1867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6229$1867_Y + end + attribute \src "ls180.v:6231.109-6231.153" + cell $eq $eq$ls180.v:6231$1870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6231$1870_Y + end + attribute \src "ls180.v:6232.112-6232.156" + cell $eq $eq$ls180.v:6232$1874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6232$1874_Y + end + attribute \src "ls180.v:6234.107-6234.151" + cell $eq $eq$ls180.v:6234$1877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6234$1877_Y + end + attribute \src "ls180.v:6235.110-6235.154" + cell $eq $eq$ls180.v:6235$1881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6235$1881_Y + end + attribute \src "ls180.v:6237.107-6237.151" + cell $eq $eq$ls180.v:6237$1884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6237$1884_Y + end + attribute \src "ls180.v:6238.110-6238.154" + cell $eq $eq$ls180.v:6238$1888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6238$1888_Y + end + attribute \src "ls180.v:6240.107-6240.151" + cell $eq $eq$ls180.v:6240$1891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6240$1891_Y + end + attribute \src "ls180.v:6241.110-6241.154" + cell $eq $eq$ls180.v:6241$1895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6241$1895_Y + end + attribute \src "ls180.v:6243.107-6243.151" + cell $eq $eq$ls180.v:6243$1898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6243$1898_Y + end + attribute \src "ls180.v:6244.110-6244.154" + cell $eq $eq$ls180.v:6244$1902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6244$1902_Y + end + attribute \src "ls180.v:6259.33-6259.79" + cell $eq $eq$ls180.v:6259$1904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [13:9] + connect \B 3'111 + connect \Y $eq$ls180.v:6259$1904_Y + end + attribute \src "ls180.v:6261.102-6261.147" + cell $eq $eq$ls180.v:6261$1906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6261$1906_Y + end + attribute \src "ls180.v:6262.105-6262.150" + cell $eq $eq$ls180.v:6262$1910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6262$1910_Y + end + attribute \src "ls180.v:6264.102-6264.147" + cell $eq $eq$ls180.v:6264$1913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6264$1913_Y + end + attribute \src "ls180.v:6265.105-6265.150" + cell $eq $eq$ls180.v:6265$1917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6265$1917_Y + end + attribute \src "ls180.v:6267.100-6267.145" + cell $eq $eq$ls180.v:6267$1920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6267$1920_Y + end + attribute \src "ls180.v:6268.103-6268.148" + cell $eq $eq$ls180.v:6268$1924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6268$1924_Y + end + attribute \src "ls180.v:6270.99-6270.144" + cell $eq $eq$ls180.v:6270$1927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6270$1927_Y + end + attribute \src "ls180.v:6271.102-6271.147" + cell $eq $eq$ls180.v:6271$1931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6271$1931_Y + end + attribute \src "ls180.v:6273.98-6273.143" + cell $eq $eq$ls180.v:6273$1934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6273$1934_Y + end + attribute \src "ls180.v:6274.101-6274.146" + cell $eq $eq$ls180.v:6274$1938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6274$1938_Y + end + attribute \src "ls180.v:6276.97-6276.142" + cell $eq $eq$ls180.v:6276$1941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6276$1941_Y + end + attribute \src "ls180.v:6277.100-6277.145" + cell $eq $eq$ls180.v:6277$1945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6277$1945_Y + end + attribute \src "ls180.v:6279.103-6279.148" + cell $eq $eq$ls180.v:6279$1948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6279$1948_Y + end + attribute \src "ls180.v:6280.106-6280.151" + cell $eq $eq$ls180.v:6280$1952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6280$1952_Y + end + attribute \src "ls180.v:6299.33-6299.79" + cell $eq $eq$ls180.v:6299$1955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [13:9] + connect \B 4'1000 + connect \Y $eq$ls180.v:6299$1955_Y + end + attribute \src "ls180.v:6301.102-6301.147" + cell $eq $eq$ls180.v:6301$1957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6301$1957_Y + end + attribute \src "ls180.v:6302.105-6302.150" + cell $eq $eq$ls180.v:6302$1961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6302$1961_Y + end + attribute \src "ls180.v:6304.102-6304.147" + cell $eq $eq$ls180.v:6304$1964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6304$1964_Y + end + attribute \src "ls180.v:6305.105-6305.150" + cell $eq $eq$ls180.v:6305$1968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6305$1968_Y + end + attribute \src "ls180.v:6307.100-6307.145" + cell $eq $eq$ls180.v:6307$1971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6307$1971_Y + end + attribute \src "ls180.v:6308.103-6308.148" + cell $eq $eq$ls180.v:6308$1975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6308$1975_Y + end + attribute \src "ls180.v:6310.99-6310.144" + cell $eq $eq$ls180.v:6310$1978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6310$1978_Y + end + attribute \src "ls180.v:6311.102-6311.147" + cell $eq $eq$ls180.v:6311$1982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6311$1982_Y + end + attribute \src "ls180.v:6313.98-6313.143" + cell $eq $eq$ls180.v:6313$1985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6313$1985_Y + end + attribute \src "ls180.v:6314.101-6314.146" + cell $eq $eq$ls180.v:6314$1989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6314$1989_Y + end + attribute \src "ls180.v:6316.97-6316.142" + cell $eq $eq$ls180.v:6316$1992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6316$1992_Y + end + attribute \src "ls180.v:6317.100-6317.145" + cell $eq $eq$ls180.v:6317$1996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6317$1996_Y + end + attribute \src "ls180.v:6319.103-6319.148" + cell $eq $eq$ls180.v:6319$1999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6319$1999_Y + end + attribute \src "ls180.v:6320.106-6320.151" + cell $eq $eq$ls180.v:6320$2003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6320$2003_Y + end + attribute \src "ls180.v:6322.106-6322.151" + cell $eq $eq$ls180.v:6322$2006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6322$2006_Y + end + attribute \src "ls180.v:6323.109-6323.154" + cell $eq $eq$ls180.v:6323$2010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6323$2010_Y + end + attribute \src "ls180.v:6325.106-6325.151" + cell $eq $eq$ls180.v:6325$2013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6325$2013_Y + end + attribute \src "ls180.v:6326.109-6326.154" + cell $eq $eq$ls180.v:6326$2017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6326$2017_Y + end + attribute \src "ls180.v:6347.33-6347.79" + cell $eq $eq$ls180.v:6347$2020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [13:9] + connect \B 2'10 + connect \Y $eq$ls180.v:6347$2020_Y + end + attribute \src "ls180.v:6349.99-6349.144" + cell $eq $eq$ls180.v:6349$2022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6349$2022_Y + end + attribute \src "ls180.v:6350.102-6350.147" + cell $eq $eq$ls180.v:6350$2026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6350$2026_Y + end + attribute \src "ls180.v:6352.99-6352.144" + cell $eq $eq$ls180.v:6352$2029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6352$2029_Y + end + attribute \src "ls180.v:6353.102-6353.147" + cell $eq $eq$ls180.v:6353$2033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6353$2033_Y + end + attribute \src "ls180.v:6355.99-6355.144" + cell $eq $eq$ls180.v:6355$2036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6355$2036_Y + end + attribute \src "ls180.v:6356.102-6356.147" + cell $eq $eq$ls180.v:6356$2040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6356$2040_Y + end + attribute \src "ls180.v:6358.99-6358.144" + cell $eq $eq$ls180.v:6358$2043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6358$2043_Y + end + attribute \src "ls180.v:6359.102-6359.147" + cell $eq $eq$ls180.v:6359$2047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6359$2047_Y + end + attribute \src "ls180.v:6361.101-6361.146" + cell $eq $eq$ls180.v:6361$2050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6361$2050_Y + end + attribute \src "ls180.v:6362.104-6362.149" + cell $eq $eq$ls180.v:6362$2054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6362$2054_Y + end + attribute \src "ls180.v:6364.101-6364.146" + cell $eq $eq$ls180.v:6364$2057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6364$2057_Y + end + attribute \src "ls180.v:6365.104-6365.149" + cell $eq $eq$ls180.v:6365$2061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6365$2061_Y + end + attribute \src "ls180.v:6367.101-6367.146" + cell $eq $eq$ls180.v:6367$2064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6367$2064_Y + end + attribute \src "ls180.v:6368.104-6368.149" + cell $eq $eq$ls180.v:6368$2068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6368$2068_Y + end + attribute \src "ls180.v:6370.101-6370.146" + cell $eq $eq$ls180.v:6370$2071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6370$2071_Y + end + attribute \src "ls180.v:6371.104-6371.149" + cell $eq $eq$ls180.v:6371$2075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6371$2075_Y + end + attribute \src "ls180.v:6373.97-6373.142" + cell $eq $eq$ls180.v:6373$2078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6373$2078_Y + end + attribute \src "ls180.v:6374.100-6374.145" + cell $eq $eq$ls180.v:6374$2082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6374$2082_Y + end + attribute \src "ls180.v:6376.107-6376.152" + cell $eq $eq$ls180.v:6376$2085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6376$2085_Y + end + attribute \src "ls180.v:6377.110-6377.155" + cell $eq $eq$ls180.v:6377$2089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6377$2089_Y + end + attribute \src "ls180.v:6379.100-6379.146" + cell $eq $eq$ls180.v:6379$2092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6379$2092_Y + end + attribute \src "ls180.v:6380.103-6380.149" + cell $eq $eq$ls180.v:6380$2096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6380$2096_Y + end + attribute \src "ls180.v:6382.100-6382.146" + cell $eq $eq$ls180.v:6382$2099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6382$2099_Y + end + attribute \src "ls180.v:6383.103-6383.149" + cell $eq $eq$ls180.v:6383$2103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6383$2103_Y + end + attribute \src "ls180.v:6385.100-6385.146" + cell $eq $eq$ls180.v:6385$2106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6385$2106_Y + end + attribute \src "ls180.v:6386.103-6386.149" + cell $eq $eq$ls180.v:6386$2110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6386$2110_Y + end + attribute \src "ls180.v:6388.100-6388.146" + cell $eq $eq$ls180.v:6388$2113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6388$2113_Y + end + attribute \src "ls180.v:6389.103-6389.149" + cell $eq $eq$ls180.v:6389$2117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6389$2117_Y + end + attribute \src "ls180.v:6391.112-6391.158" + cell $eq $eq$ls180.v:6391$2120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6391$2120_Y + end + attribute \src "ls180.v:6392.115-6392.161" + cell $eq $eq$ls180.v:6392$2124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6392$2124_Y + end + attribute \src "ls180.v:6394.113-6394.159" + cell $eq $eq$ls180.v:6394$2127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6394$2127_Y + end + attribute \src "ls180.v:6395.116-6395.162" + cell $eq $eq$ls180.v:6395$2131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6395$2131_Y + end + attribute \src "ls180.v:6397.104-6397.150" + cell $eq $eq$ls180.v:6397$2134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6397$2134_Y + end + attribute \src "ls180.v:6398.107-6398.153" + cell $eq $eq$ls180.v:6398$2138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6398$2138_Y + end + attribute \src "ls180.v:6415.33-6415.79" + cell $eq $eq$ls180.v:6415$2140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [13:9] + connect \B 3'101 + connect \Y $eq$ls180.v:6415$2140_Y + end + attribute \src "ls180.v:6417.90-6417.135" + cell $eq $eq$ls180.v:6417$2142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6417$2142_Y + end + attribute \src "ls180.v:6418.93-6418.138" + cell $eq $eq$ls180.v:6418$2146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6418$2146_Y + end + attribute \src "ls180.v:6420.100-6420.145" + cell $eq $eq$ls180.v:6420$2149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6420$2149_Y + end + attribute \src "ls180.v:6421.103-6421.148" + cell $eq $eq$ls180.v:6421$2153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6421$2153_Y + end + attribute \src "ls180.v:6423.101-6423.146" + cell $eq $eq$ls180.v:6423$2156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6423$2156_Y + end + attribute \src "ls180.v:6424.104-6424.149" + cell $eq $eq$ls180.v:6424$2160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6424$2160_Y + end + attribute \src "ls180.v:6426.105-6426.150" + cell $eq $eq$ls180.v:6426$2163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6426$2163_Y + end + attribute \src "ls180.v:6427.108-6427.153" + cell $eq $eq$ls180.v:6427$2167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6427$2167_Y + end + attribute \src "ls180.v:6429.106-6429.151" + cell $eq $eq$ls180.v:6429$2170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6429$2170_Y + end + attribute \src "ls180.v:6430.109-6430.154" + cell $eq $eq$ls180.v:6430$2174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6430$2174_Y + end + attribute \src "ls180.v:6432.104-6432.149" + cell $eq $eq$ls180.v:6432$2177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6432$2177_Y + end + attribute \src "ls180.v:6433.107-6433.152" + cell $eq $eq$ls180.v:6433$2181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6433$2181_Y + end + attribute \src "ls180.v:6435.101-6435.146" + cell $eq $eq$ls180.v:6435$2184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6435$2184_Y + end + attribute \src "ls180.v:6436.104-6436.149" + cell $eq $eq$ls180.v:6436$2188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6436$2188_Y + end + attribute \src "ls180.v:6438.100-6438.145" + cell $eq $eq$ls180.v:6438$2191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6438$2191_Y + end + attribute \src "ls180.v:6439.103-6439.148" + cell $eq $eq$ls180.v:6439$2195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6439$2195_Y + end + attribute \src "ls180.v:6449.33-6449.79" + cell $eq $eq$ls180.v:6449$2197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [13:9] + connect \B 3'100 + connect \Y $eq$ls180.v:6449$2197_Y + end + attribute \src "ls180.v:6451.106-6451.151" + cell $eq $eq$ls180.v:6451$2199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6451$2199_Y + end + attribute \src "ls180.v:6452.109-6452.154" + cell $eq $eq$ls180.v:6452$2203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6452$2203_Y + end + attribute \src "ls180.v:6454.106-6454.151" + cell $eq $eq$ls180.v:6454$2206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6454$2206_Y + end + attribute \src "ls180.v:6455.109-6455.154" + cell $eq $eq$ls180.v:6455$2210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6455$2210_Y + end + attribute \src "ls180.v:6457.106-6457.151" + cell $eq $eq$ls180.v:6457$2213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6457$2213_Y + end + attribute \src "ls180.v:6458.109-6458.154" + cell $eq $eq$ls180.v:6458$2217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6458$2217_Y + end + attribute \src "ls180.v:6460.106-6460.151" + cell $eq $eq$ls180.v:6460$2220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6460$2220_Y + end + attribute \src "ls180.v:6461.109-6461.154" + cell $eq $eq$ls180.v:6461$2224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6461$2224_Y + end + attribute \src "ls180.v:6842.41-6842.81" + cell $eq $eq$ls180.v:6842$2261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:6842$2261_Y + end + attribute \src "ls180.v:6842.144-6842.177" + cell $eq $eq$ls180.v:6842$2262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6842$2262_Y + end + attribute \src "ls180.v:6842.219-6842.252" + cell $eq $eq$ls180.v:6842$2265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6842$2265_Y + end + attribute \src "ls180.v:6842.294-6842.327" + cell $eq $eq$ls180.v:6842$2268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6842$2268_Y + end + attribute \src "ls180.v:6866.41-6866.81" + cell $eq $eq$ls180.v:6866$2277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:6866$2277_Y + end + attribute \src "ls180.v:6866.144-6866.177" + cell $eq $eq$ls180.v:6866$2278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6866$2278_Y + end + attribute \src "ls180.v:6866.219-6866.252" + cell $eq $eq$ls180.v:6866$2281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6866$2281_Y + end + attribute \src "ls180.v:6866.294-6866.327" + cell $eq $eq$ls180.v:6866$2284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6866$2284_Y + end + attribute \src "ls180.v:6890.41-6890.81" + cell $eq $eq$ls180.v:6890$2293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:6890$2293_Y + end + attribute \src "ls180.v:6890.144-6890.177" + cell $eq $eq$ls180.v:6890$2294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6890$2294_Y + end + attribute \src "ls180.v:6890.219-6890.252" + cell $eq $eq$ls180.v:6890$2297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6890$2297_Y + end + attribute \src "ls180.v:6890.294-6890.327" + cell $eq $eq$ls180.v:6890$2300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6890$2300_Y + end + attribute \src "ls180.v:6914.41-6914.81" + cell $eq $eq$ls180.v:6914$2309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:6914$2309_Y + end + attribute \src "ls180.v:6914.144-6914.177" + cell $eq $eq$ls180.v:6914$2310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6914$2310_Y + end + attribute \src "ls180.v:6914.219-6914.252" + cell $eq $eq$ls180.v:6914$2313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6914$2313_Y + end + attribute \src "ls180.v:6914.294-6914.327" + cell $eq $eq$ls180.v:6914$2316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6914$2316_Y + end + attribute \src "ls180.v:7495.8-7495.38" + cell $eq $eq$ls180.v:7495$2407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $eq$ls180.v:7495$2407_Y + end + attribute \src "ls180.v:7526.8-7526.42" + cell $eq $eq$ls180.v:7526$2415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'0 + connect \Y $eq$ls180.v:7526$2415_Y + end + attribute \src "ls180.v:7546.38-7546.74" + cell $eq $eq$ls180.v:7546$2418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $eq$ls180.v:7546$2418_Y + end + attribute \src "ls180.v:7553.7-7553.43" + cell $eq $eq$ls180.v:7553$2420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 2'10 + connect \Y $eq$ls180.v:7553$2420_Y + end + attribute \src "ls180.v:7560.7-7560.43" + cell $eq $eq$ls180.v:7560$2421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7560$2421_Y + end + attribute \src "ls180.v:7568.7-7568.43" + cell $eq $eq$ls180.v:7568$2422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7568$2422_Y + end + attribute \src "ls180.v:7620.9-7620.54" + cell $eq $eq$ls180.v:7620$2440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7620$2440_Y + end + attribute \src "ls180.v:7666.9-7666.54" + cell $eq $eq$ls180.v:7666$2456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7666$2456_Y + end + attribute \src "ls180.v:7712.9-7712.54" + cell $eq $eq$ls180.v:7712$2472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7712$2472_Y + end + attribute \src "ls180.v:7758.9-7758.54" + cell $eq $eq$ls180.v:7758$2488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7758$2488_Y + end + attribute \src "ls180.v:7908.9-7908.41" + cell $eq $eq$ls180.v:7908$2500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7908$2500_Y + end + attribute \src "ls180.v:7923.9-7923.41" + cell $eq $eq$ls180.v:7923$2503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7923$2503_Y + end + attribute \src "ls180.v:7929.49-7929.82" + cell $eq $eq$ls180.v:7929$2504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7929$2504_Y + end + attribute \src "ls180.v:7929.131-7929.164" + cell $eq $eq$ls180.v:7929$2507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7929$2507_Y + end + attribute \src "ls180.v:7929.213-7929.246" + cell $eq $eq$ls180.v:7929$2510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7929$2510_Y + end + attribute \src "ls180.v:7929.295-7929.328" + cell $eq $eq$ls180.v:7929$2513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7929$2513_Y + end + attribute \src "ls180.v:7930.50-7930.83" + cell $eq $eq$ls180.v:7930$2516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7930$2516_Y + end + attribute \src "ls180.v:7930.132-7930.165" + cell $eq $eq$ls180.v:7930$2519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7930$2519_Y + end + attribute \src "ls180.v:7930.214-7930.247" + cell $eq $eq$ls180.v:7930$2522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7930$2522_Y + end + attribute \src "ls180.v:7930.296-7930.329" + cell $eq $eq$ls180.v:7930$2525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7930$2525_Y + end + attribute \src "ls180.v:7965.9-7965.42" + cell $eq $eq$ls180.v:7965$2537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1000 + connect \Y $eq$ls180.v:7965$2537_Y + end + attribute \src "ls180.v:7968.10-7968.43" + cell $eq $eq$ls180.v:7968$2538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:7968$2538_Y + end + attribute \src "ls180.v:7994.9-7994.42" + cell $eq $eq$ls180.v:7994$2544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'0 + connect \Y $eq$ls180.v:7994$2544_Y + end + attribute \src "ls180.v:7999.10-7999.43" + cell $eq $eq$ls180.v:7999$2545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:7999$2545_Y + end + attribute \src "ls180.v:8206.9-8206.53" + cell $eq $eq$ls180.v:8206$2594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8206$2594_Y + end + attribute \src "ls180.v:8287.9-8287.54" + cell $eq $eq$ls180.v:8287$2606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8287$2606_Y + end + attribute \src "ls180.v:8366.9-8366.55" + cell $eq $eq$ls180.v:8366$2618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $eq$ls180.v:8366$2618_Y + end + attribute \src "ls180.v:8589.9-8589.49" + cell $eq $eq$ls180.v:8589$2651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_demux + connect \B 2'11 + connect \Y $eq$ls180.v:8589$2651_Y + end + attribute \src "ls180.v:8165.8-8165.54" + cell $ge $ge$ls180.v:8165$2586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B $sub$ls180.v:8165$2585_Y + connect \Y $ge$ls180.v:8165$2586_Y + end + attribute \src "ls180.v:8179.8-8179.54" + cell $ge $ge$ls180.v:8179$2590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B $sub$ls180.v:8179$2589_Y + connect \Y $ge$ls180.v:8179$2590_Y + end + attribute \src "ls180.v:5151.47-5151.83" + cell $gt $gt$ls180.v:5151$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $gt$ls180.v:5151$914_Y + end + attribute \src "ls180.v:5157.7-5157.43" + cell $lt $lt$ls180.v:5157$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1000 + connect \Y $lt$ls180.v:5157$917_Y + end + attribute \src "ls180.v:8160.8-8160.43" + cell $lt $lt$ls180.v:8160$2584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B \main_pwm0_width + connect \Y $lt$ls180.v:8160$2584_Y + end + attribute \src "ls180.v:8174.8-8174.43" + cell $lt $lt$ls180.v:8174$2588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B \main_pwm1_width + connect \Y $lt$ls180.v:8174$2588_Y + end + attribute \src "ls180.v:10055.33-10055.36" + cell $memrd $memrd$\mem$ls180.v:10055$2693 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \TRANSPARENT 0 + parameter \WIDTH 32 + connect \ADDR \memadr + connect \CLK 1'x + connect \DATA $memrd$\mem$ls180.v:10055$2693_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10066.12-10066.19" + cell $memrd $memrd$\storage$ls180.v:10066$2698 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10066$2698_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10073.68-10073.75" + cell $memrd $memrd$\storage$ls180.v:10073$2700 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10073$2700_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10080.14-10080.23" + cell $memrd $memrd$\storage_1$ls180.v:10080$2705 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10080$2705_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10087.68-10087.77" + cell $memrd $memrd$\storage_1$ls180.v:10087$2707 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10087$2707_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10094.14-10094.23" + cell $memrd $memrd$\storage_2$ls180.v:10094$2712 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10094$2712_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10101.68-10101.77" + cell $memrd $memrd$\storage_2$ls180.v:10101$2714 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10101$2714_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10108.14-10108.23" + cell $memrd $memrd$\storage_3$ls180.v:10108$2719 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10108$2719_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10115.68-10115.77" + cell $memrd $memrd$\storage_3$ls180.v:10115$2721 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10115$2721_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10123.14-10123.23" + cell $memrd $memrd$\storage_4$ls180.v:10123$2726 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10123$2726_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10128.15-10128.24" + cell $memrd $memrd$\storage_4$ls180.v:10128$2728 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10128$2728_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10140.14-10140.23" + cell $memrd $memrd$\storage_5$ls180.v:10140$2733 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10140$2733_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10145.15-10145.24" + cell $memrd $memrd$\storage_5$ls180.v:10145$2735 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10145$2735_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10156.14-10156.23" + cell $memrd $memrd$\storage_6$ls180.v:10156$2740 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10156$2740_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10163.45-10163.54" + cell $memrd $memrd$\storage_6$ls180.v:10163$2742 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10163$2742_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10170.14-10170.23" + cell $memrd $memrd$\storage_7$ls180.v:10170$2747 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10170$2747_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10177.45-10177.54" + cell $memrd $memrd$\storage_7$ls180.v:10177$2749 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10177$2749_DATA + connect \EN 1'x + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2751 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2751 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10045$1_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10045$1_DATA + connect \EN $memwr$\mem$ls180.v:10045$1_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2752 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2752 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10047$2_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10047$2_DATA + connect \EN $memwr$\mem$ls180.v:10047$2_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2753 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2753 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10049$3_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10049$3_DATA + connect \EN $memwr$\mem$ls180.v:10049$3_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2754 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2754 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10051$4_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10051$4_DATA + connect \EN $memwr$\mem$ls180.v:10051$4_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage$ls180.v:0$2755 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \PRIORITY 2755 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage$ls180.v:10065$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage$ls180.v:10065$5_DATA + connect \EN $memwr$\storage$ls180.v:10065$5_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_1$ls180.v:0$2756 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \PRIORITY 2756 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_1$ls180.v:10079$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_1$ls180.v:10079$6_DATA + connect \EN $memwr$\storage_1$ls180.v:10079$6_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_2$ls180.v:0$2757 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \PRIORITY 2757 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_2$ls180.v:10093$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_2$ls180.v:10093$7_DATA + connect \EN $memwr$\storage_2$ls180.v:10093$7_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_3$ls180.v:0$2758 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \PRIORITY 2758 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_3$ls180.v:10107$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_3$ls180.v:10107$8_DATA + connect \EN $memwr$\storage_3$ls180.v:10107$8_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_4$ls180.v:0$2759 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \PRIORITY 2759 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_4$ls180.v:10122$9_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_4$ls180.v:10122$9_DATA + connect \EN $memwr$\storage_4$ls180.v:10122$9_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_5$ls180.v:0$2760 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \PRIORITY 2760 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_5$ls180.v:10139$10_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_5$ls180.v:10139$10_DATA + connect \EN $memwr$\storage_5$ls180.v:10139$10_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_6$ls180.v:0$2761 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \PRIORITY 2761 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_6$ls180.v:10155$11_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_6$ls180.v:10155$11_DATA + connect \EN $memwr$\storage_6$ls180.v:10155$11_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_7$ls180.v:0$2762 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \PRIORITY 2762 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_7$ls180.v:10169$12_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_7$ls180.v:10169$12_DATA + connect \EN $memwr$\storage_7$ls180.v:10169$12_EN + end + attribute \src "ls180.v:2965.41-2965.71" + cell $ne $ne$ls180.v:2965$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $ne$ls180.v:2965$60_Y + end + attribute \src "ls180.v:3126.70-3126.104" + cell $ne $ne$ls180.v:3126$74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:3126$74_Y + end + attribute \src "ls180.v:3187.8-3187.142" + cell $ne $ne$ls180.v:3187$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3187$93_Y + end + attribute \src "ls180.v:3219.75-3219.133" + cell $ne $ne$ls180.v:3219$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3219$100_Y + end + attribute \src "ls180.v:3220.75-3220.133" + cell $ne $ne$ls180.v:3220$101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3220$101_Y + end + attribute \src "ls180.v:3344.8-3344.142" + cell $ne $ne$ls180.v:3344$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3344$123_Y + end + attribute \src "ls180.v:3376.75-3376.133" + cell $ne $ne$ls180.v:3376$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3376$130_Y + end + attribute \src "ls180.v:3377.75-3377.133" + cell $ne $ne$ls180.v:3377$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3377$131_Y + end + attribute \src "ls180.v:3501.8-3501.142" + cell $ne $ne$ls180.v:3501$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3501$153_Y + end + attribute \src "ls180.v:3533.75-3533.133" + cell $ne $ne$ls180.v:3533$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3533$160_Y + end + attribute \src "ls180.v:3534.75-3534.133" + cell $ne $ne$ls180.v:3534$161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3534$161_Y + end + attribute \src "ls180.v:3658.8-3658.142" + cell $ne $ne$ls180.v:3658$183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3658$183_Y + end + attribute \src "ls180.v:3690.75-3690.133" + cell $ne $ne$ls180.v:3690$190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3690$190_Y + end + attribute \src "ls180.v:3691.75-3691.133" + cell $ne $ne$ls180.v:3691$191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3691$191_Y + end + attribute \src "ls180.v:4183.47-4183.80" + cell $ne $ne$ls180.v:4183$589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4183$589_Y + end + attribute \src "ls180.v:4184.47-4184.79" + cell $ne $ne$ls180.v:4184$590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4184$590_Y + end + attribute \src "ls180.v:4213.47-4213.80" + cell $ne $ne$ls180.v:4213$600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4213$600_Y + end + attribute \src "ls180.v:4214.47-4214.79" + cell $ne $ne$ls180.v:4214$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4214$601_Y + end + attribute \src "ls180.v:4683.32-4683.89" + cell $ne $ne$ls180.v:4683$681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $ne$ls180.v:4683$681_Y + end + attribute \src "ls180.v:5330.10-5330.56" + cell $ne $ne$ls180.v:5330$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 2'10 + connect \Y $ne$ls180.v:5330$978_Y + end + attribute \src "ls180.v:5435.51-5435.87" + cell $ne $ne$ls180.v:5435$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5435$992_Y + end + attribute \src "ls180.v:5436.51-5436.86" + cell $ne $ne$ls180.v:5436$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5436$993_Y + end + attribute \src "ls180.v:5643.51-5643.87" + cell $ne $ne$ls180.v:5643$1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5643$1023_Y + end + attribute \src "ls180.v:5644.51-5644.86" + cell $ne $ne$ls180.v:5644$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5644$1024_Y + end + attribute \src "ls180.v:5675.79-5675.119" + cell $ne $ne$ls180.v:5675$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_sel + connect \B 1'0 + connect \Y $ne$ls180.v:5675$1027_Y + end + attribute \src "ls180.v:7485.7-7485.52" + cell $ne $ne$ls180.v:7485$2402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_bus_errors + connect \B 32'11111111111111111111111111111111 + connect \Y $ne$ls180.v:7485$2402_Y + end + attribute \src "ls180.v:7535.9-7535.43" + cell $ne $ne$ls180.v:7535$2416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:7535$2416_Y + end + attribute \src "ls180.v:7571.8-7571.44" + cell $ne $ne$ls180.v:7571$2423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $ne$ls180.v:7571$2423_Y + end + attribute \src "ls180.v:8509.9-8509.47" + cell $ne $ne$ls180.v:8509$2638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1010 + connect \Y $ne$ls180.v:8509$2638_Y + end + attribute \src "ls180.v:2773.45-2773.80" + cell $not $not$ls180.v:2773$14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_cyc + connect \Y $not$ls180.v:2773$14_Y + end + attribute \src "ls180.v:2812.61-2812.94" + cell $not $not$ls180.v:2812$19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$ls180.v:2812$19_Y + end + attribute \src "ls180.v:2813.61-2813.94" + cell $not $not$ls180.v:2813$20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$ls180.v:2813$20_Y + end + attribute \src "ls180.v:2833.45-2833.80" + cell $not $not$ls180.v:2833$25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_cyc + connect \Y $not$ls180.v:2833$25_Y + end + attribute \src "ls180.v:2872.61-2872.94" + cell $not $not$ls180.v:2872$30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$ls180.v:2872$30_Y + end + attribute \src "ls180.v:2873.61-2873.94" + cell $not $not$ls180.v:2873$31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$ls180.v:2873$31_Y + end + attribute \src "ls180.v:2893.45-2893.83" + cell $not $not$ls180.v:2893$36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $not$ls180.v:2893$36_Y + end + attribute \src "ls180.v:2932.61-2932.94" + cell $not $not$ls180.v:2932$41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_skip + connect \Y $not$ls180.v:2932$41_Y + end + attribute \src "ls180.v:2933.61-2933.94" + cell $not $not$ls180.v:2933$42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_skip + connect \Y $not$ls180.v:2933$42_Y + end + attribute \src "ls180.v:3075.34-3075.64" + cell $not $not$ls180.v:3075$66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [0] + connect \Y $not$ls180.v:3075$66_Y + end + attribute \src "ls180.v:3076.31-3076.61" + cell $not $not$ls180.v:3076$67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [1] + connect \Y $not$ls180.v:3076$67_Y + end + attribute \src "ls180.v:3077.32-3077.62" + cell $not $not$ls180.v:3077$68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [2] + connect \Y $not$ls180.v:3077$68_Y + end + attribute \src "ls180.v:3078.32-3078.62" + cell $not $not$ls180.v:3078$69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [3] + connect \Y $not$ls180.v:3078$69_Y + end + attribute \src "ls180.v:3120.33-3120.56" + cell $not $not$ls180.v:3120$72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:3120$72_Y + end + attribute \src "ls180.v:3221.58-3221.106" + cell $not $not$ls180.v:3221$102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:3221$102_Y + end + attribute \src "ls180.v:3275.9-3275.45" + cell $not $not$ls180.v:3275$107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_req + connect \Y $not$ls180.v:3275$107_Y + end + attribute \src "ls180.v:3378.58-3378.106" + cell $not $not$ls180.v:3378$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:3378$132_Y + end + attribute \src "ls180.v:3432.9-3432.45" + cell $not $not$ls180.v:3432$137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_refresh_req + connect \Y $not$ls180.v:3432$137_Y + end + attribute \src "ls180.v:3535.58-3535.106" + cell $not $not$ls180.v:3535$162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:3535$162_Y + end + attribute \src "ls180.v:3589.9-3589.45" + cell $not $not$ls180.v:3589$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_refresh_req + connect \Y $not$ls180.v:3589$167_Y + end + attribute \src "ls180.v:3692.58-3692.106" + cell $not $not$ls180.v:3692$192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:3692$192_Y + end + attribute \src "ls180.v:3746.9-3746.45" + cell $not $not$ls180.v:3746$197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_refresh_req + connect \Y $not$ls180.v:3746$197_Y + end + attribute \src "ls180.v:3788.149-3788.187" + cell $not $not$ls180.v:3788$200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3788$200_Y + end + attribute \src "ls180.v:3788.193-3788.230" + cell $not $not$ls180.v:3788$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3788$202_Y + end + attribute \src "ls180.v:3789.149-3789.187" + cell $not $not$ls180.v:3789$206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3789$206_Y + end + attribute \src "ls180.v:3789.193-3789.230" + cell $not $not$ls180.v:3789$208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3789$208_Y + end + attribute \src "ls180.v:3805.43-3805.73" + cell $not $not$ls180.v:3805$236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \main_sdram_interface_wdata_we + connect \Y $not$ls180.v:3805$236_Y + end + attribute \src "ls180.v:3808.205-3808.245" + cell $not $not$ls180.v:3808$239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3808$239_Y + end + attribute \src "ls180.v:3808.251-3808.290" + cell $not $not$ls180.v:3808$241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3808$241_Y + end + attribute \src "ls180.v:3808.159-3808.292" + cell $not $not$ls180.v:3808$243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3808$242_Y + connect \Y $not$ls180.v:3808$243_Y + end + attribute \src "ls180.v:3809.205-3809.245" + cell $not $not$ls180.v:3809$252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3809$252_Y + end + attribute \src "ls180.v:3809.251-3809.290" + cell $not $not$ls180.v:3809$254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3809$254_Y + end + attribute \src "ls180.v:3809.159-3809.292" + cell $not $not$ls180.v:3809$256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3809$255_Y + connect \Y $not$ls180.v:3809$256_Y + end + attribute \src "ls180.v:3810.205-3810.245" + cell $not $not$ls180.v:3810$265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3810$265_Y + end + attribute \src "ls180.v:3810.251-3810.290" + cell $not $not$ls180.v:3810$267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3810$267_Y + end + attribute \src "ls180.v:3810.159-3810.292" + cell $not $not$ls180.v:3810$269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3810$268_Y + connect \Y $not$ls180.v:3810$269_Y + end + attribute \src "ls180.v:3811.205-3811.245" + cell $not $not$ls180.v:3811$278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3811$278_Y + end + attribute \src "ls180.v:3811.251-3811.290" + cell $not $not$ls180.v:3811$280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3811$280_Y + end + attribute \src "ls180.v:3811.159-3811.292" + cell $not $not$ls180.v:3811$282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3811$281_Y + connect \Y $not$ls180.v:3811$282_Y + end + attribute \src "ls180.v:3838.71-3838.103" + cell $not $not$ls180.v:3838$293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \Y $not$ls180.v:3838$293_Y + end + attribute \src "ls180.v:3841.205-3841.245" + cell $not $not$ls180.v:3841$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3841$297_Y + end + attribute \src "ls180.v:3841.251-3841.290" + cell $not $not$ls180.v:3841$299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3841$299_Y + end + attribute \src "ls180.v:3841.159-3841.292" + cell $not $not$ls180.v:3841$301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3841$300_Y + connect \Y $not$ls180.v:3841$301_Y + end + attribute \src "ls180.v:3842.205-3842.245" + cell $not $not$ls180.v:3842$310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3842$310_Y + end + attribute \src "ls180.v:3842.251-3842.290" + cell $not $not$ls180.v:3842$312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3842$312_Y + end + attribute \src "ls180.v:3842.159-3842.292" + cell $not $not$ls180.v:3842$314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3842$313_Y + connect \Y $not$ls180.v:3842$314_Y + end + attribute \src "ls180.v:3843.205-3843.245" + cell $not $not$ls180.v:3843$323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3843$323_Y + end + attribute \src "ls180.v:3843.251-3843.290" + cell $not $not$ls180.v:3843$325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3843$325_Y + end + attribute \src "ls180.v:3843.159-3843.292" + cell $not $not$ls180.v:3843$327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3843$326_Y + connect \Y $not$ls180.v:3843$327_Y + end + attribute \src "ls180.v:3844.205-3844.245" + cell $not $not$ls180.v:3844$336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3844$336_Y + end + attribute \src "ls180.v:3844.251-3844.290" + cell $not $not$ls180.v:3844$338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3844$338_Y + end + attribute \src "ls180.v:3844.159-3844.292" + cell $not $not$ls180.v:3844$340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3844$339_Y + connect \Y $not$ls180.v:3844$340_Y + end + attribute \src "ls180.v:3907.71-3907.103" + cell $not $not$ls180.v:3907$379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \Y $not$ls180.v:3907$379_Y + end + attribute \src "ls180.v:3928.112-3928.150" + cell $not $not$ls180.v:3928$382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3928$382_Y + end + attribute \src "ls180.v:3928.156-3928.193" + cell $not $not$ls180.v:3928$384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3928$384_Y + end + attribute \src "ls180.v:3928.68-3928.195" + cell $not $not$ls180.v:3928$386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3928$385_Y + connect \Y $not$ls180.v:3928$386_Y + end + attribute \src "ls180.v:3936.11-3936.38" + cell $not $not$ls180.v:3936$389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_write_available + connect \Y $not$ls180.v:3936$389_Y + end + attribute \src "ls180.v:3966.112-3966.150" + cell $not $not$ls180.v:3966$391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3966$391_Y + end + attribute \src "ls180.v:3966.156-3966.193" + cell $not $not$ls180.v:3966$393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3966$393_Y + end + attribute \src "ls180.v:3966.68-3966.195" + cell $not $not$ls180.v:3966$395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3966$394_Y + connect \Y $not$ls180.v:3966$395_Y + end + attribute \src "ls180.v:3974.11-3974.37" + cell $not $not$ls180.v:3974$398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_read_available + connect \Y $not$ls180.v:3974$398_Y + end + attribute \src "ls180.v:3984.87-3984.331" + cell $not $not$ls180.v:3984$410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3984$409_Y + connect \Y $not$ls180.v:3984$410_Y + end + attribute \src "ls180.v:3985.35-3985.68" + cell $not $not$ls180.v:3985$413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_valid + connect \Y $not$ls180.v:3985$413_Y + end + attribute \src "ls180.v:3985.73-3985.105" + cell $not $not$ls180.v:3985$414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \Y $not$ls180.v:3985$414_Y + end + attribute \src "ls180.v:3989.87-3989.331" + cell $not $not$ls180.v:3989$426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3989$425_Y + connect \Y $not$ls180.v:3989$426_Y + end + attribute \src "ls180.v:3990.35-3990.68" + cell $not $not$ls180.v:3990$429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_valid + connect \Y $not$ls180.v:3990$429_Y + end + attribute \src "ls180.v:3990.73-3990.105" + cell $not $not$ls180.v:3990$430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \Y $not$ls180.v:3990$430_Y + end + attribute \src "ls180.v:3994.87-3994.331" + cell $not $not$ls180.v:3994$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3994$441_Y + connect \Y $not$ls180.v:3994$442_Y + end + attribute \src "ls180.v:3995.35-3995.68" + cell $not $not$ls180.v:3995$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_valid + connect \Y $not$ls180.v:3995$445_Y + end + attribute \src "ls180.v:3995.73-3995.105" + cell $not $not$ls180.v:3995$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \Y $not$ls180.v:3995$446_Y + end + attribute \src "ls180.v:3999.87-3999.331" + cell $not $not$ls180.v:3999$458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3999$457_Y + connect \Y $not$ls180.v:3999$458_Y + end + attribute \src "ls180.v:4000.35-4000.68" + cell $not $not$ls180.v:4000$461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_valid + connect \Y $not$ls180.v:4000$461_Y + end + attribute \src "ls180.v:4000.73-4000.105" + cell $not $not$ls180.v:4000$462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \Y $not$ls180.v:4000$462_Y + end + attribute \src "ls180.v:4004.128-4004.372" + cell $not $not$ls180.v:4004$475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$474_Y + connect \Y $not$ls180.v:4004$475_Y + end + attribute \src "ls180.v:4004.502-4004.746" + cell $not $not$ls180.v:4004$491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$490_Y + connect \Y $not$ls180.v:4004$491_Y + end + attribute \src "ls180.v:4004.876-4004.1120" + cell $not $not$ls180.v:4004$507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$506_Y + connect \Y $not$ls180.v:4004$507_Y + end + attribute \src "ls180.v:4004.1250-4004.1494" + cell $not $not$ls180.v:4004$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$522_Y + connect \Y $not$ls180.v:4004$523_Y + end + attribute \src "ls180.v:4026.32-4026.50" + cell $not $not$ls180.v:4026$529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_cyc + connect \Y $not$ls180.v:4026$529_Y + end + attribute \src "ls180.v:4065.30-4065.50" + cell $not $not$ls180.v:4065$534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4065$534_Y + end + attribute \src "ls180.v:4066.30-4066.50" + cell $not $not$ls180.v:4066$535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4066$535_Y + end + attribute \src "ls180.v:4091.27-4091.48" + cell $not $not$ls180.v:4091$541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \Y $not$ls180.v:4091$541_Y + end + attribute \src "ls180.v:4092.30-4092.50" + cell $not $not$ls180.v:4092$542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4092$542_Y + end + attribute \src "ls180.v:4093.80-4093.98" + cell $not $not$ls180.v:4093$544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_cmd_consumed + connect \Y $not$ls180.v:4093$544_Y + end + attribute \src "ls180.v:4094.107-4094.127" + cell $not $not$ls180.v:4094$548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wdata_consumed + connect \Y $not$ls180.v:4094$548_Y + end + attribute \src "ls180.v:4095.78-4095.103" + cell $not $not$ls180.v:4095$551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_we + connect \Y $not$ls180.v:4095$551_Y + end + attribute \src "ls180.v:4096.91-4096.111" + cell $not $not$ls180.v:4096$554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4096$554_Y + end + attribute \src "ls180.v:4112.35-4112.64" + cell $not $not$ls180.v:4112$563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4112$563_Y + end + attribute \src "ls180.v:4113.36-4113.67" + cell $not $not$ls180.v:4113$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_source_valid + connect \Y $not$ls180.v:4113$564_Y + end + attribute \src "ls180.v:4119.32-4119.61" + cell $not $not$ls180.v:4119$565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4119$565_Y + end + attribute \src "ls180.v:4125.36-4125.67" + cell $not $not$ls180.v:4125$566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4125$566_Y + end + attribute \src "ls180.v:4126.35-4126.64" + cell $not $not$ls180.v:4126$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_sink_ready + connect \Y $not$ls180.v:4126$567_Y + end + attribute \src "ls180.v:4129.32-4129.63" + cell $not $not$ls180.v:4129$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4129$570_Y + end + attribute \src "ls180.v:4167.81-4167.108" + cell $not $not$ls180.v:4167$580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_readable + connect \Y $not$ls180.v:4167$580_Y + end + attribute \src "ls180.v:4197.81-4197.108" + cell $not $not$ls180.v:4197$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_readable + connect \Y $not$ls180.v:4197$591_Y + end + attribute \src "ls180.v:4397.60-4397.85" + cell $not $not$ls180.v:4397$640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk_d + connect \Y $not$ls180.v:4397$640_Y + end + attribute \src "ls180.v:4538.54-4538.96" + cell $not $not$ls180.v:4538$654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \Y $not$ls180.v:4538$654_Y + end + attribute \src "ls180.v:4541.48-4541.86" + cell $not $not$ls180.v:4541$657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:4541$657_Y + end + attribute \src "ls180.v:4665.55-4665.98" + cell $not $not$ls180.v:4665$675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_strobe_all + connect \Y $not$ls180.v:4665$675_Y + end + attribute \src "ls180.v:4668.49-4668.88" + cell $not $not$ls180.v:4668$678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:4668$678_Y + end + attribute \src "ls180.v:4718.30-4718.58" + cell $not $not$ls180.v:4718$684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \Y $not$ls180.v:4718$684_Y + end + attribute \src "ls180.v:4799.56-4799.100" + cell $not $not$ls180.v:4799$690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_strobe_all + connect \Y $not$ls180.v:4799$690_Y + end + attribute \src "ls180.v:4802.50-4802.90" + cell $not $not$ls180.v:4802$693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:4802$693_Y + end + attribute \src "ls180.v:4918.42-4918.74" + cell $not $not$ls180.v:4918$709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_valid + connect \Y $not$ls180.v:4918$709_Y + end + attribute \src "ls180.v:5442.50-5442.88" + cell $not $not$ls180.v:5442$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_strobe_all + connect \Y $not$ls180.v:5442$994_Y + end + attribute \src "ls180.v:5454.52-5454.102" + cell $not $not$ls180.v:5454$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \Y $not$ls180.v:5454$997_Y + end + attribute \src "ls180.v:5513.38-5513.74" + cell $not $not$ls180.v:5513$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_enable_storage + connect \Y $not$ls180.v:5513$1004_Y + end + attribute \src "ls180.v:5755.69-5755.88" + cell $not $not$ls180.v:5755$1065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \Y $not$ls180.v:5755$1065_Y + end + attribute \src "ls180.v:5772.63-5772.94" + cell $not $not$ls180.v:5772$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5772$1086_Y + end + attribute \src "ls180.v:5775.65-5775.96" + cell $not $not$ls180.v:5775$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5775$1093_Y + end + attribute \src "ls180.v:5778.65-5778.96" + cell $not $not$ls180.v:5778$1100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5778$1100_Y + end + attribute \src "ls180.v:5781.65-5781.96" + cell $not $not$ls180.v:5781$1107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5781$1107_Y + end + attribute \src "ls180.v:5784.65-5784.96" + cell $not $not$ls180.v:5784$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5784$1114_Y + end + attribute \src "ls180.v:5787.68-5787.99" + cell $not $not$ls180.v:5787$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5787$1121_Y + end + attribute \src "ls180.v:5790.68-5790.99" + cell $not $not$ls180.v:5790$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5790$1128_Y + end + attribute \src "ls180.v:5793.68-5793.99" + cell $not $not$ls180.v:5793$1135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5793$1135_Y + end + attribute \src "ls180.v:5796.68-5796.99" + cell $not $not$ls180.v:5796$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5796$1142_Y + end + attribute \src "ls180.v:5810.60-5810.91" + cell $not $not$ls180.v:5810$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5810$1150_Y + end + attribute \src "ls180.v:5813.60-5813.91" + cell $not $not$ls180.v:5813$1157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5813$1157_Y + end + attribute \src "ls180.v:5816.60-5816.91" + cell $not $not$ls180.v:5816$1164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5816$1164_Y + end + attribute \src "ls180.v:5819.60-5819.91" + cell $not $not$ls180.v:5819$1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5819$1171_Y + end + attribute \src "ls180.v:5822.61-5822.92" + cell $not $not$ls180.v:5822$1178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5822$1178_Y + end + attribute \src "ls180.v:5825.61-5825.92" + cell $not $not$ls180.v:5825$1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5825$1185_Y + end + attribute \src "ls180.v:5836.59-5836.90" + cell $not $not$ls180.v:5836$1193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5836$1193_Y + end + attribute \src "ls180.v:5839.58-5839.89" + cell $not $not$ls180.v:5839$1200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5839$1200_Y + end + attribute \src "ls180.v:5850.64-5850.95" + cell $not $not$ls180.v:5850$1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5850$1208_Y + end + attribute \src "ls180.v:5853.63-5853.94" + cell $not $not$ls180.v:5853$1215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5853$1215_Y + end + attribute \src "ls180.v:5856.63-5856.94" + cell $not $not$ls180.v:5856$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5856$1222_Y + end + attribute \src "ls180.v:5859.63-5859.94" + cell $not $not$ls180.v:5859$1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5859$1229_Y + end + attribute \src "ls180.v:5862.63-5862.94" + cell $not $not$ls180.v:5862$1236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5862$1236_Y + end + attribute \src "ls180.v:5865.64-5865.95" + cell $not $not$ls180.v:5865$1243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5865$1243_Y + end + attribute \src "ls180.v:5868.64-5868.95" + cell $not $not$ls180.v:5868$1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5868$1250_Y + end + attribute \src "ls180.v:5871.64-5871.95" + cell $not $not$ls180.v:5871$1257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5871$1257_Y + end + attribute \src "ls180.v:5874.64-5874.95" + cell $not $not$ls180.v:5874$1264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5874$1264_Y + end + attribute \src "ls180.v:5887.64-5887.95" + cell $not $not$ls180.v:5887$1272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5887$1272_Y + end + attribute \src "ls180.v:5890.63-5890.94" + cell $not $not$ls180.v:5890$1279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5890$1279_Y + end + attribute \src "ls180.v:5893.63-5893.94" + cell $not $not$ls180.v:5893$1286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5893$1286_Y + end + attribute \src "ls180.v:5896.63-5896.94" + cell $not $not$ls180.v:5896$1293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5896$1293_Y + end + attribute \src "ls180.v:5899.63-5899.94" + cell $not $not$ls180.v:5899$1300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5899$1300_Y + end + attribute \src "ls180.v:5902.64-5902.95" + cell $not $not$ls180.v:5902$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5902$1307_Y + end + attribute \src "ls180.v:5905.64-5905.95" + cell $not $not$ls180.v:5905$1314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5905$1314_Y + end + attribute \src "ls180.v:5908.64-5908.95" + cell $not $not$ls180.v:5908$1321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5908$1321_Y + end + attribute \src "ls180.v:5911.64-5911.95" + cell $not $not$ls180.v:5911$1328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5911$1328_Y + end + attribute \src "ls180.v:5924.66-5924.97" + cell $not $not$ls180.v:5924$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5924$1336_Y + end + attribute \src "ls180.v:5927.66-5927.97" + cell $not $not$ls180.v:5927$1343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5927$1343_Y + end + attribute \src "ls180.v:5930.66-5930.97" + cell $not $not$ls180.v:5930$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5930$1350_Y + end + attribute \src "ls180.v:5933.66-5933.97" + cell $not $not$ls180.v:5933$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5933$1357_Y + end + attribute \src "ls180.v:5936.66-5936.97" + cell $not $not$ls180.v:5936$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5936$1364_Y + end + attribute \src "ls180.v:5939.66-5939.97" + cell $not $not$ls180.v:5939$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5939$1371_Y + end + attribute \src "ls180.v:5942.66-5942.97" + cell $not $not$ls180.v:5942$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5942$1378_Y + end + attribute \src "ls180.v:5945.66-5945.97" + cell $not $not$ls180.v:5945$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5945$1385_Y + end + attribute \src "ls180.v:5948.68-5948.99" + cell $not $not$ls180.v:5948$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5948$1392_Y + end + attribute \src "ls180.v:5951.68-5951.99" + cell $not $not$ls180.v:5951$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5951$1399_Y + end + attribute \src "ls180.v:5954.68-5954.99" + cell $not $not$ls180.v:5954$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5954$1406_Y + end + attribute \src "ls180.v:5957.68-5957.99" + cell $not $not$ls180.v:5957$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5957$1413_Y + end + attribute \src "ls180.v:5960.68-5960.99" + cell $not $not$ls180.v:5960$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5960$1420_Y + end + attribute \src "ls180.v:5963.65-5963.96" + cell $not $not$ls180.v:5963$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5963$1427_Y + end + attribute \src "ls180.v:5966.66-5966.97" + cell $not $not$ls180.v:5966$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5966$1434_Y + end + attribute \src "ls180.v:5986.70-5986.101" + cell $not $not$ls180.v:5986$1442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5986$1442_Y + end + attribute \src "ls180.v:5989.70-5989.101" + cell $not $not$ls180.v:5989$1449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5989$1449_Y + end + attribute \src "ls180.v:5992.70-5992.101" + cell $not $not$ls180.v:5992$1456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5992$1456_Y + end + attribute \src "ls180.v:5995.70-5995.101" + cell $not $not$ls180.v:5995$1463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5995$1463_Y + end + attribute \src "ls180.v:5998.69-5998.100" + cell $not $not$ls180.v:5998$1470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5998$1470_Y + end + attribute \src "ls180.v:6001.69-6001.100" + cell $not $not$ls180.v:6001$1477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6001$1477_Y + end + attribute \src "ls180.v:6004.69-6004.100" + cell $not $not$ls180.v:6004$1484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6004$1484_Y + end + attribute \src "ls180.v:6007.69-6007.100" + cell $not $not$ls180.v:6007$1491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6007$1491_Y + end + attribute \src "ls180.v:6010.60-6010.91" + cell $not $not$ls180.v:6010$1498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6010$1498_Y + end + attribute \src "ls180.v:6013.71-6013.102" + cell $not $not$ls180.v:6013$1505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6013$1505_Y + end + attribute \src "ls180.v:6016.71-6016.102" + cell $not $not$ls180.v:6016$1512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6016$1512_Y + end + attribute \src "ls180.v:6019.71-6019.102" + cell $not $not$ls180.v:6019$1519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6019$1519_Y + end + attribute \src "ls180.v:6022.71-6022.102" + cell $not $not$ls180.v:6022$1526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6022$1526_Y + end + attribute \src "ls180.v:6025.71-6025.102" + cell $not $not$ls180.v:6025$1533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6025$1533_Y + end + attribute \src "ls180.v:6028.71-6028.102" + cell $not $not$ls180.v:6028$1540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6028$1540_Y + end + attribute \src "ls180.v:6031.70-6031.101" + cell $not $not$ls180.v:6031$1547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6031$1547_Y + end + attribute \src "ls180.v:6034.70-6034.101" + cell $not $not$ls180.v:6034$1554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6034$1554_Y + end + attribute \src "ls180.v:6037.70-6037.101" + cell $not $not$ls180.v:6037$1561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6037$1561_Y + end + attribute \src "ls180.v:6040.70-6040.101" + cell $not $not$ls180.v:6040$1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6040$1568_Y + end + attribute \src "ls180.v:6043.70-6043.101" + cell $not $not$ls180.v:6043$1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6043$1575_Y + end + attribute \src "ls180.v:6046.70-6046.101" + cell $not $not$ls180.v:6046$1582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6046$1582_Y + end + attribute \src "ls180.v:6049.70-6049.101" + cell $not $not$ls180.v:6049$1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6049$1589_Y + end + attribute \src "ls180.v:6052.70-6052.101" + cell $not $not$ls180.v:6052$1596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6052$1596_Y + end + attribute \src "ls180.v:6055.70-6055.101" + cell $not $not$ls180.v:6055$1603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6055$1603_Y + end + attribute \src "ls180.v:6058.70-6058.101" + cell $not $not$ls180.v:6058$1610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6058$1610_Y + end + attribute \src "ls180.v:6061.66-6061.97" + cell $not $not$ls180.v:6061$1617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6061$1617_Y + end + attribute \src "ls180.v:6064.67-6064.98" + cell $not $not$ls180.v:6064$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6064$1624_Y + end + attribute \src "ls180.v:6067.70-6067.101" + cell $not $not$ls180.v:6067$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6067$1631_Y + end + attribute \src "ls180.v:6070.70-6070.101" + cell $not $not$ls180.v:6070$1638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6070$1638_Y + end + attribute \src "ls180.v:6073.69-6073.100" + cell $not $not$ls180.v:6073$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6073$1645_Y + end + attribute \src "ls180.v:6076.69-6076.100" + cell $not $not$ls180.v:6076$1652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6076$1652_Y + end + attribute \src "ls180.v:6079.69-6079.100" + cell $not $not$ls180.v:6079$1659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6079$1659_Y + end + attribute \src "ls180.v:6082.69-6082.100" + cell $not $not$ls180.v:6082$1666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6082$1666_Y + end + attribute \src "ls180.v:6121.66-6121.97" + cell $not $not$ls180.v:6121$1674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6121$1674_Y + end + attribute \src "ls180.v:6124.66-6124.97" + cell $not $not$ls180.v:6124$1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6124$1681_Y + end + attribute \src "ls180.v:6127.66-6127.97" + cell $not $not$ls180.v:6127$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6127$1688_Y + end + attribute \src "ls180.v:6130.66-6130.97" + cell $not $not$ls180.v:6130$1695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6130$1695_Y + end + attribute \src "ls180.v:6133.66-6133.97" + cell $not $not$ls180.v:6133$1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6133$1702_Y + end + attribute \src "ls180.v:6136.66-6136.97" + cell $not $not$ls180.v:6136$1709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6136$1709_Y + end + attribute \src "ls180.v:6139.66-6139.97" + cell $not $not$ls180.v:6139$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6139$1716_Y + end + attribute \src "ls180.v:6142.66-6142.97" + cell $not $not$ls180.v:6142$1723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6142$1723_Y + end + attribute \src "ls180.v:6145.68-6145.99" + cell $not $not$ls180.v:6145$1730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6145$1730_Y + end + attribute \src "ls180.v:6148.68-6148.99" + cell $not $not$ls180.v:6148$1737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6148$1737_Y + end + attribute \src "ls180.v:6151.68-6151.99" + cell $not $not$ls180.v:6151$1744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6151$1744_Y + end + attribute \src "ls180.v:6154.68-6154.99" + cell $not $not$ls180.v:6154$1751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6154$1751_Y + end + attribute \src "ls180.v:6157.68-6157.99" + cell $not $not$ls180.v:6157$1758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6157$1758_Y + end + attribute \src "ls180.v:6160.65-6160.96" + cell $not $not$ls180.v:6160$1765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6160$1765_Y + end + attribute \src "ls180.v:6163.66-6163.97" + cell $not $not$ls180.v:6163$1772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6163$1772_Y + end + attribute \src "ls180.v:6166.68-6166.99" + cell $not $not$ls180.v:6166$1779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6166$1779_Y + end + attribute \src "ls180.v:6169.68-6169.99" + cell $not $not$ls180.v:6169$1786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6169$1786_Y + end + attribute \src "ls180.v:6172.68-6172.99" + cell $not $not$ls180.v:6172$1793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6172$1793_Y + end + attribute \src "ls180.v:6175.68-6175.99" + cell $not $not$ls180.v:6175$1800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6175$1800_Y + end + attribute \src "ls180.v:6200.68-6200.99" + cell $not $not$ls180.v:6200$1808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6200$1808_Y + end + attribute \src "ls180.v:6203.73-6203.104" + cell $not $not$ls180.v:6203$1815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6203$1815_Y + end + attribute \src "ls180.v:6206.73-6206.104" + cell $not $not$ls180.v:6206$1822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6206$1822_Y + end + attribute \src "ls180.v:6209.66-6209.97" + cell $not $not$ls180.v:6209$1829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6209$1829_Y + end + attribute \src "ls180.v:6217.70-6217.101" + cell $not $not$ls180.v:6217$1837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6217$1837_Y + end + attribute \src "ls180.v:6220.74-6220.105" + cell $not $not$ls180.v:6220$1844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6220$1844_Y + end + attribute \src "ls180.v:6223.64-6223.95" + cell $not $not$ls180.v:6223$1851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6223$1851_Y + end + attribute \src "ls180.v:6226.74-6226.105" + cell $not $not$ls180.v:6226$1858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6226$1858_Y + end + attribute \src "ls180.v:6229.74-6229.105" + cell $not $not$ls180.v:6229$1865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6229$1865_Y + end + attribute \src "ls180.v:6232.75-6232.106" + cell $not $not$ls180.v:6232$1872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6232$1872_Y + end + attribute \src "ls180.v:6235.73-6235.104" + cell $not $not$ls180.v:6235$1879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6235$1879_Y + end + attribute \src "ls180.v:6238.73-6238.104" + cell $not $not$ls180.v:6238$1886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6238$1886_Y + end + attribute \src "ls180.v:6241.73-6241.104" + cell $not $not$ls180.v:6241$1893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6241$1893_Y + end + attribute \src "ls180.v:6244.73-6244.104" + cell $not $not$ls180.v:6244$1900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6244$1900_Y + end + attribute \src "ls180.v:6262.67-6262.99" + cell $not $not$ls180.v:6262$1908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6262$1908_Y + end + attribute \src "ls180.v:6265.67-6265.99" + cell $not $not$ls180.v:6265$1915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6265$1915_Y + end + attribute \src "ls180.v:6268.65-6268.97" + cell $not $not$ls180.v:6268$1922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6268$1922_Y + end + attribute \src "ls180.v:6271.64-6271.96" + cell $not $not$ls180.v:6271$1929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6271$1929_Y + end + attribute \src "ls180.v:6274.63-6274.95" + cell $not $not$ls180.v:6274$1936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6274$1936_Y + end + attribute \src "ls180.v:6277.62-6277.94" + cell $not $not$ls180.v:6277$1943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6277$1943_Y + end + attribute \src "ls180.v:6280.68-6280.100" + cell $not $not$ls180.v:6280$1950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6280$1950_Y + end + attribute \src "ls180.v:6302.67-6302.99" + cell $not $not$ls180.v:6302$1959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6302$1959_Y + end + attribute \src "ls180.v:6305.67-6305.99" + cell $not $not$ls180.v:6305$1966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6305$1966_Y + end + attribute \src "ls180.v:6308.65-6308.97" + cell $not $not$ls180.v:6308$1973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6308$1973_Y + end + attribute \src "ls180.v:6311.64-6311.96" + cell $not $not$ls180.v:6311$1980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6311$1980_Y + end + attribute \src "ls180.v:6314.63-6314.95" + cell $not $not$ls180.v:6314$1987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6314$1987_Y + end + attribute \src "ls180.v:6317.62-6317.94" + cell $not $not$ls180.v:6317$1994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6317$1994_Y + end + attribute \src "ls180.v:6320.68-6320.100" + cell $not $not$ls180.v:6320$2001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6320$2001_Y + end + attribute \src "ls180.v:6323.71-6323.103" + cell $not $not$ls180.v:6323$2008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6323$2008_Y + end + attribute \src "ls180.v:6326.71-6326.103" + cell $not $not$ls180.v:6326$2015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6326$2015_Y + end + attribute \src "ls180.v:6350.64-6350.96" + cell $not $not$ls180.v:6350$2024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6350$2024_Y + end + attribute \src "ls180.v:6353.64-6353.96" + cell $not $not$ls180.v:6353$2031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6353$2031_Y + end + attribute \src "ls180.v:6356.64-6356.96" + cell $not $not$ls180.v:6356$2038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6356$2038_Y + end + attribute \src "ls180.v:6359.64-6359.96" + cell $not $not$ls180.v:6359$2045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6359$2045_Y + end + attribute \src "ls180.v:6362.66-6362.98" + cell $not $not$ls180.v:6362$2052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6362$2052_Y + end + attribute \src "ls180.v:6365.66-6365.98" + cell $not $not$ls180.v:6365$2059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6365$2059_Y + end + attribute \src "ls180.v:6368.66-6368.98" + cell $not $not$ls180.v:6368$2066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6368$2066_Y + end + attribute \src "ls180.v:6371.66-6371.98" + cell $not $not$ls180.v:6371$2073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6371$2073_Y + end + attribute \src "ls180.v:6374.62-6374.94" + cell $not $not$ls180.v:6374$2080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6374$2080_Y + end + attribute \src "ls180.v:6377.72-6377.104" + cell $not $not$ls180.v:6377$2087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6377$2087_Y + end + attribute \src "ls180.v:6380.65-6380.97" + cell $not $not$ls180.v:6380$2094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6380$2094_Y + end + attribute \src "ls180.v:6383.65-6383.97" + cell $not $not$ls180.v:6383$2101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6383$2101_Y + end + attribute \src "ls180.v:6386.65-6386.97" + cell $not $not$ls180.v:6386$2108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6386$2108_Y + end + attribute \src "ls180.v:6389.65-6389.97" + cell $not $not$ls180.v:6389$2115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6389$2115_Y + end + attribute \src "ls180.v:6392.77-6392.109" + cell $not $not$ls180.v:6392$2122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6392$2122_Y + end + attribute \src "ls180.v:6395.78-6395.110" + cell $not $not$ls180.v:6395$2129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6395$2129_Y + end + attribute \src "ls180.v:6398.69-6398.101" + cell $not $not$ls180.v:6398$2136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6398$2136_Y + end + attribute \src "ls180.v:6418.55-6418.87" + cell $not $not$ls180.v:6418$2144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6418$2144_Y + end + attribute \src "ls180.v:6421.65-6421.97" + cell $not $not$ls180.v:6421$2151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6421$2151_Y + end + attribute \src "ls180.v:6424.66-6424.98" + cell $not $not$ls180.v:6424$2158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6424$2158_Y + end + attribute \src "ls180.v:6427.70-6427.102" + cell $not $not$ls180.v:6427$2165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6427$2165_Y + end + attribute \src "ls180.v:6430.71-6430.103" + cell $not $not$ls180.v:6430$2172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6430$2172_Y + end + attribute \src "ls180.v:6433.69-6433.101" + cell $not $not$ls180.v:6433$2179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6433$2179_Y + end + attribute \src "ls180.v:6436.66-6436.98" + cell $not $not$ls180.v:6436$2186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6436$2186_Y + end + attribute \src "ls180.v:6439.65-6439.97" + cell $not $not$ls180.v:6439$2193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6439$2193_Y + end + attribute \src "ls180.v:6452.71-6452.103" + cell $not $not$ls180.v:6452$2201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6452$2201_Y + end + attribute \src "ls180.v:6455.71-6455.103" + cell $not $not$ls180.v:6455$2208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6455$2208_Y + end + attribute \src "ls180.v:6458.71-6458.103" + cell $not $not$ls180.v:6458$2215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6458$2215_Y + end + attribute \src "ls180.v:6461.71-6461.103" + cell $not $not$ls180.v:6461$2222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6461$2222_Y + end + attribute \src "ls180.v:6842.86-6842.330" + cell $not $not$ls180.v:6842$2271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6842$2270_Y + connect \Y $not$ls180.v:6842$2271_Y + end + attribute \src "ls180.v:6866.86-6866.330" + cell $not $not$ls180.v:6866$2287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6866$2286_Y + connect \Y $not$ls180.v:6866$2287_Y + end + attribute \src "ls180.v:6890.86-6890.330" + cell $not $not$ls180.v:6890$2303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6890$2302_Y + connect \Y $not$ls180.v:6890$2303_Y + end + attribute \src "ls180.v:6914.86-6914.330" + cell $not $not$ls180.v:6914$2319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6914$2318_Y + connect \Y $not$ls180.v:6914$2319_Y + end + attribute \src "ls180.v:7412.18-7412.42" + cell $not $not$ls180.v:7412$2372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk0 + connect \Y $not$ls180.v:7412$2372_Y + end + attribute \src "ls180.v:7491.72-7491.101" + cell $not $not$ls180.v:7491$2405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \Y $not$ls180.v:7491$2405_Y + end + attribute \src "ls180.v:7510.8-7510.38" + cell $not $not$ls180.v:7510$2409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_zero_trigger + connect \Y $not$ls180.v:7510$2409_Y + end + attribute \src "ls180.v:7518.32-7518.55" + cell $not $not$ls180.v:7518$2411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:7518$2411_Y + end + attribute \src "ls180.v:7588.136-7588.189" + cell $not $not$ls180.v:7588$2426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7588$2426_Y + end + attribute \src "ls180.v:7594.136-7594.189" + cell $not $not$ls180.v:7594$2431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7594$2431_Y + end + attribute \src "ls180.v:7595.8-7595.61" + cell $not $not$ls180.v:7595$2433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7595$2433_Y + end + attribute \src "ls180.v:7603.8-7603.56" + cell $not $not$ls180.v:7603$2436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:7603$2436_Y + end + attribute \src "ls180.v:7618.8-7618.46" + cell $not $not$ls180.v:7618$2438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \Y $not$ls180.v:7618$2438_Y + end + attribute \src "ls180.v:7634.136-7634.189" + cell $not $not$ls180.v:7634$2442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7634$2442_Y + end + attribute \src "ls180.v:7640.136-7640.189" + cell $not $not$ls180.v:7640$2447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7640$2447_Y + end + attribute \src "ls180.v:7641.8-7641.61" + cell $not $not$ls180.v:7641$2449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7641$2449_Y + end + attribute \src "ls180.v:7649.8-7649.56" + cell $not $not$ls180.v:7649$2452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:7649$2452_Y + end + attribute \src "ls180.v:7664.8-7664.46" + cell $not $not$ls180.v:7664$2454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \Y $not$ls180.v:7664$2454_Y + end + attribute \src "ls180.v:7680.136-7680.189" + cell $not $not$ls180.v:7680$2458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7680$2458_Y + end + attribute \src "ls180.v:7686.136-7686.189" + cell $not $not$ls180.v:7686$2463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7686$2463_Y + end + attribute \src "ls180.v:7687.8-7687.61" + cell $not $not$ls180.v:7687$2465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7687$2465_Y + end + attribute \src "ls180.v:7695.8-7695.56" + cell $not $not$ls180.v:7695$2468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:7695$2468_Y + end + attribute \src "ls180.v:7710.8-7710.46" + cell $not $not$ls180.v:7710$2470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \Y $not$ls180.v:7710$2470_Y + end + attribute \src "ls180.v:7726.136-7726.189" + cell $not $not$ls180.v:7726$2474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7726$2474_Y + end + attribute \src "ls180.v:7732.136-7732.189" + cell $not $not$ls180.v:7732$2479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7732$2479_Y + end + attribute \src "ls180.v:7733.8-7733.61" + cell $not $not$ls180.v:7733$2481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7733$2481_Y + end + attribute \src "ls180.v:7741.8-7741.56" + cell $not $not$ls180.v:7741$2484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:7741$2484_Y + end + attribute \src "ls180.v:7756.8-7756.46" + cell $not $not$ls180.v:7756$2486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \Y $not$ls180.v:7756$2486_Y + end + attribute \src "ls180.v:7764.7-7764.22" + cell $not $not$ls180.v:7764$2489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en0 + connect \Y $not$ls180.v:7764$2489_Y + end + attribute \src "ls180.v:7767.8-7767.29" + cell $not $not$ls180.v:7767$2490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time0 + connect \Y $not$ls180.v:7767$2490_Y + end + attribute \src "ls180.v:7771.7-7771.22" + cell $not $not$ls180.v:7771$2492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en1 + connect \Y $not$ls180.v:7771$2492_Y + end + attribute \src "ls180.v:7774.8-7774.29" + cell $not $not$ls180.v:7774$2493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time1 + connect \Y $not$ls180.v:7774$2493_Y + end + attribute \src "ls180.v:7893.30-7893.60" + cell $not $not$ls180.v:7893$2495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed2 + connect \Y $not$ls180.v:7893$2495_Y + end + attribute \src "ls180.v:7894.30-7894.60" + cell $not $not$ls180.v:7894$2496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed3 + connect \Y $not$ls180.v:7894$2496_Y + end + attribute \src "ls180.v:7895.29-7895.59" + cell $not $not$ls180.v:7895$2497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed4 + connect \Y $not$ls180.v:7895$2497_Y + end + attribute \src "ls180.v:7906.8-7906.33" + cell $not $not$ls180.v:7906$2498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_ready + connect \Y $not$ls180.v:7906$2498_Y + end + attribute \src "ls180.v:7921.8-7921.33" + cell $not $not$ls180.v:7921$2501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_ready + connect \Y $not$ls180.v:7921$2501_Y + end + attribute \src "ls180.v:7957.36-7957.58" + cell $not $not$ls180.v:7957$2531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_busy + connect \Y $not$ls180.v:7957$2531_Y + end + attribute \src "ls180.v:7957.64-7957.89" + cell $not $not$ls180.v:7957$2533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_ready + connect \Y $not$ls180.v:7957$2533_Y + end + attribute \src "ls180.v:7986.7-7986.29" + cell $not $not$ls180.v:7986$2540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_busy + connect \Y $not$ls180.v:7986$2540_Y + end + attribute \src "ls180.v:7987.9-7987.26" + cell $not $not$ls180.v:7987$2541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx + connect \Y $not$ls180.v:7987$2541_Y + end + attribute \src "ls180.v:8020.8-8020.29" + cell $not $not$ls180.v:8020$2547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_trigger + connect \Y $not$ls180.v:8020$2547_Y + end + attribute \src "ls180.v:8027.8-8027.29" + cell $not $not$ls180.v:8027$2549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_trigger + connect \Y $not$ls180.v:8027$2549_Y + end + attribute \src "ls180.v:8037.80-8037.106" + cell $not $not$ls180.v:8037$2552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8037$2552_Y + end + attribute \src "ls180.v:8043.80-8043.106" + cell $not $not$ls180.v:8043$2557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8043$2557_Y + end + attribute \src "ls180.v:8044.8-8044.34" + cell $not $not$ls180.v:8044$2559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_do_read + connect \Y $not$ls180.v:8044$2559_Y + end + attribute \src "ls180.v:8059.80-8059.106" + cell $not $not$ls180.v:8059$2563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8059$2563_Y + end + attribute \src "ls180.v:8065.80-8065.106" + cell $not $not$ls180.v:8065$2568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8065$2568_Y + end + attribute \src "ls180.v:8066.8-8066.34" + cell $not $not$ls180.v:8066$2570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_do_read + connect \Y $not$ls180.v:8066$2570_Y + end + attribute \src "ls180.v:8097.22-8097.41" + cell $not $not$ls180.v:8097$2574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster6_cs + connect \Y $not$ls180.v:8097$2574_Y + end + attribute \src "ls180.v:8097.46-8097.73" + cell $not $not$ls180.v:8097$2575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster26_cs_enable + connect \Y $not$ls180.v:8097$2575_Y + end + attribute \src "ls180.v:8132.22-8132.40" + cell $not $not$ls180.v:8132$2579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_cs + connect \Y $not$ls180.v:8132$2579_Y + end + attribute \src "ls180.v:8132.45-8132.70" + cell $not $not$ls180.v:8132$2580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_cs_enable + connect \Y $not$ls180.v:8132$2580_Y + end + attribute \src "ls180.v:8186.7-8186.31" + cell $not $not$ls180.v:8186$2591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_stop + connect \Y $not$ls180.v:8186$2591_Y + end + attribute \src "ls180.v:8258.8-8258.46" + cell $not $not$ls180.v:8258$2603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:8258$2603_Y + end + attribute \src "ls180.v:8339.8-8339.47" + cell $not $not$ls180.v:8339$2615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:8339$2615_Y + end + attribute \src "ls180.v:8400.8-8400.48" + cell $not $not$ls180.v:8400$2627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:8400$2627_Y + end + attribute \src "ls180.v:8570.88-8570.118" + cell $not $not$ls180.v:8570$2641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8570$2641_Y + end + attribute \src "ls180.v:8576.88-8576.118" + cell $not $not$ls180.v:8576$2646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8576$2646_Y + end + attribute \src "ls180.v:8577.8-8577.38" + cell $not $not$ls180.v:8577$2648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_do_read + connect \Y $not$ls180.v:8577$2648_Y + end + attribute \src "ls180.v:8656.88-8656.118" + cell $not $not$ls180.v:8656$2663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8656$2663_Y + end + attribute \src "ls180.v:8662.88-8662.118" + cell $not $not$ls180.v:8662$2668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8662$2668_Y + end + attribute \src "ls180.v:8663.8-8663.38" + cell $not $not$ls180.v:8663$2670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_do_read + connect \Y $not$ls180.v:8663$2670_Y + end + attribute \src "ls180.v:8683.9-8683.28" + cell $not $not$ls180.v:8683$2673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [0] + connect \Y $not$ls180.v:8683$2673_Y + end + attribute \src "ls180.v:8702.9-8702.28" + cell $not $not$ls180.v:8702$2674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [1] + connect \Y $not$ls180.v:8702$2674_Y + end + attribute \src "ls180.v:8721.9-8721.28" + cell $not $not$ls180.v:8721$2675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [2] + connect \Y $not$ls180.v:8721$2675_Y + end + attribute \src "ls180.v:8740.9-8740.28" + cell $not $not$ls180.v:8740$2676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [3] + connect \Y $not$ls180.v:8740$2676_Y + end + attribute \src "ls180.v:8759.9-8759.28" + cell $not $not$ls180.v:8759$2677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [4] + connect \Y $not$ls180.v:8759$2677_Y + end + attribute \src "ls180.v:8780.8-8780.21" + cell $not $not$ls180.v:8780$2678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_done + connect \Y $not$ls180.v:8780$2678_Y + end + attribute \src "ls180.v:10279.8-10279.51" + cell $or $or$ls180.v:10279$2750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sys_rst_1 + connect \B \main_libresocsim_libresoc_reset + connect \Y $or$ls180.v:10279$2750_Y + end + attribute \src "ls180.v:2814.10-2814.96" + cell $or $or$ls180.v:2814$21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$ls180.v:2814$21_Y + end + attribute \src "ls180.v:2874.10-2874.96" + cell $or $or$ls180.v:2874$32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$ls180.v:2874$32_Y + end + attribute \src "ls180.v:2934.10-2934.96" + cell $or $or$ls180.v:2934$43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_ack + connect \B \main_libresocsim_converter2_skip + connect \Y $or$ls180.v:2934$43_Y + end + attribute \src "ls180.v:3126.39-3126.105" + cell $or $or$ls180.v:3126$75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start0 + connect \B $ne$ls180.v:3126$74_Y + connect \Y $or$ls180.v:3126$75_Y + end + attribute \src "ls180.v:3169.59-3169.140" + cell $or $or$ls180.v:3169$79 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_req_wdata_ready + connect \B \main_sdram_bankmachine0_req_rdata_valid + connect \Y $or$ls180.v:3169$79_Y + end + attribute \src "ls180.v:3170.44-3170.151" + cell $or $or$ls180.v:3170$80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $or$ls180.v:3170$80_Y + end + attribute \src "ls180.v:3178.45-3178.170" + cell $or $or$ls180.v:3178$84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3178$83_Y + connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3178$84_Y + end + attribute \src "ls180.v:3215.127-3215.245" + cell $or $or$ls180.v:3215$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3215$97_Y + end + attribute \src "ls180.v:3221.57-3221.157" + cell $or $or$ls180.v:3221$103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3221$102_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:3221$103_Y + end + attribute \src "ls180.v:3326.59-3326.140" + cell $or $or$ls180.v:3326$109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_req_wdata_ready + connect \B \main_sdram_bankmachine1_req_rdata_valid + connect \Y $or$ls180.v:3326$109_Y + end + attribute \src "ls180.v:3327.44-3327.151" + cell $or $or$ls180.v:3327$110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $or$ls180.v:3327$110_Y + end + attribute \src "ls180.v:3335.45-3335.170" + cell $or $or$ls180.v:3335$114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3335$113_Y + connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3335$114_Y + end + attribute \src "ls180.v:3372.127-3372.245" + cell $or $or$ls180.v:3372$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3372$127_Y + end + attribute \src "ls180.v:3378.57-3378.157" + cell $or $or$ls180.v:3378$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3378$132_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:3378$133_Y + end + attribute \src "ls180.v:3483.59-3483.140" + cell $or $or$ls180.v:3483$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_req_wdata_ready + connect \B \main_sdram_bankmachine2_req_rdata_valid + connect \Y $or$ls180.v:3483$139_Y + end + attribute \src "ls180.v:3484.44-3484.151" + cell $or $or$ls180.v:3484$140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $or$ls180.v:3484$140_Y + end + attribute \src "ls180.v:3492.45-3492.170" + cell $or $or$ls180.v:3492$144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3492$143_Y + connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3492$144_Y + end + attribute \src "ls180.v:3529.127-3529.245" + cell $or $or$ls180.v:3529$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3529$157_Y + end + attribute \src "ls180.v:3535.57-3535.157" + cell $or $or$ls180.v:3535$163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3535$162_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:3535$163_Y + end + attribute \src "ls180.v:3640.59-3640.140" + cell $or $or$ls180.v:3640$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_req_wdata_ready + connect \B \main_sdram_bankmachine3_req_rdata_valid + connect \Y $or$ls180.v:3640$169_Y + end + attribute \src "ls180.v:3641.44-3641.151" + cell $or $or$ls180.v:3641$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $or$ls180.v:3641$170_Y + end + attribute \src "ls180.v:3649.45-3649.170" + cell $or $or$ls180.v:3649$174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3649$173_Y + connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3649$174_Y + end + attribute \src "ls180.v:3686.127-3686.245" + cell $or $or$ls180.v:3686$187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3686$187_Y + end + attribute \src "ls180.v:3692.57-3692.157" + cell $or $or$ls180.v:3692$193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3692$192_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:3692$193_Y + end + attribute \src "ls180.v:3791.107-3791.193" + cell $or $or$ls180.v:3791$213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_is_write + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $or$ls180.v:3791$213_Y + end + attribute \src "ls180.v:3794.39-3794.204" + cell $or $or$ls180.v:3794$219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3794$217_Y + connect \B $and$ls180.v:3794$218_Y + connect \Y $or$ls180.v:3794$219_Y + end + attribute \src "ls180.v:3794.38-3794.289" + cell $or $or$ls180.v:3794$221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3794$219_Y + connect \B $and$ls180.v:3794$220_Y + connect \Y $or$ls180.v:3794$221_Y + end + attribute \src "ls180.v:3794.37-3794.374" + cell $or $or$ls180.v:3794$223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3794$221_Y + connect \B $and$ls180.v:3794$222_Y + connect \Y $or$ls180.v:3794$223_Y + end + attribute \src "ls180.v:3795.40-3795.207" + cell $or $or$ls180.v:3795$226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3795$224_Y + connect \B $and$ls180.v:3795$225_Y + connect \Y $or$ls180.v:3795$226_Y + end + attribute \src "ls180.v:3795.39-3795.293" + cell $or $or$ls180.v:3795$228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3795$226_Y + connect \B $and$ls180.v:3795$227_Y + connect \Y $or$ls180.v:3795$228_Y + end + attribute \src "ls180.v:3795.38-3795.379" + cell $or $or$ls180.v:3795$230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3795$228_Y + connect \B $and$ls180.v:3795$229_Y + connect \Y $or$ls180.v:3795$230_Y + end + attribute \src "ls180.v:3808.158-3808.332" + cell $or $or$ls180.v:3808$244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3808$243_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3808$244_Y + end + attribute \src "ls180.v:3808.75-3808.506" + cell $or $or$ls180.v:3808$249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3808$245_Y + connect \B $and$ls180.v:3808$248_Y + connect \Y $or$ls180.v:3808$249_Y + end + attribute \src "ls180.v:3809.158-3809.332" + cell $or $or$ls180.v:3809$257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3809$256_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3809$257_Y + end + attribute \src "ls180.v:3809.75-3809.506" + cell $or $or$ls180.v:3809$262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3809$258_Y + connect \B $and$ls180.v:3809$261_Y + connect \Y $or$ls180.v:3809$262_Y + end + attribute \src "ls180.v:3810.158-3810.332" + cell $or $or$ls180.v:3810$270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3810$269_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3810$270_Y + end + attribute \src "ls180.v:3810.75-3810.506" + cell $or $or$ls180.v:3810$275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3810$271_Y + connect \B $and$ls180.v:3810$274_Y + connect \Y $or$ls180.v:3810$275_Y + end + attribute \src "ls180.v:3811.158-3811.332" + cell $or $or$ls180.v:3811$283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3811$282_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3811$283_Y + end + attribute \src "ls180.v:3811.75-3811.506" + cell $or $or$ls180.v:3811$288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3811$284_Y + connect \B $and$ls180.v:3811$287_Y + connect \Y $or$ls180.v:3811$288_Y + end + attribute \src "ls180.v:3838.36-3838.104" + cell $or $or$ls180.v:3838$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_ready + connect \B $not$ls180.v:3838$293_Y + connect \Y $or$ls180.v:3838$294_Y + end + attribute \src "ls180.v:3841.158-3841.332" + cell $or $or$ls180.v:3841$302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3841$301_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3841$302_Y + end + attribute \src "ls180.v:3841.75-3841.506" + cell $or $or$ls180.v:3841$307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3841$303_Y + connect \B $and$ls180.v:3841$306_Y + connect \Y $or$ls180.v:3841$307_Y + end + attribute \src "ls180.v:3842.158-3842.332" + cell $or $or$ls180.v:3842$315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3842$314_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3842$315_Y + end + attribute \src "ls180.v:3842.75-3842.506" + cell $or $or$ls180.v:3842$320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3842$316_Y + connect \B $and$ls180.v:3842$319_Y + connect \Y $or$ls180.v:3842$320_Y + end + attribute \src "ls180.v:3843.158-3843.332" + cell $or $or$ls180.v:3843$328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3843$327_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3843$328_Y + end + attribute \src "ls180.v:3843.75-3843.506" + cell $or $or$ls180.v:3843$333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3843$329_Y + connect \B $and$ls180.v:3843$332_Y + connect \Y $or$ls180.v:3843$333_Y + end + attribute \src "ls180.v:3844.158-3844.332" + cell $or $or$ls180.v:3844$341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3844$340_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3844$341_Y + end + attribute \src "ls180.v:3844.75-3844.506" + cell $or $or$ls180.v:3844$346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3844$342_Y + connect \B $and$ls180.v:3844$345_Y + connect \Y $or$ls180.v:3844$346_Y + end + attribute \src "ls180.v:3907.36-3907.104" + cell $or $or$ls180.v:3907$380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_ready + connect \B $not$ls180.v:3907$379_Y + connect \Y $or$ls180.v:3907$380_Y + end + attribute \src "ls180.v:3928.67-3928.221" + cell $or $or$ls180.v:3928$387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3928$386_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:3928$387_Y + end + attribute \src "ls180.v:3936.10-3936.62" + cell $or $or$ls180.v:3936$390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3936$389_Y + connect \B \main_sdram_max_time1 + connect \Y $or$ls180.v:3936$390_Y + end + attribute \src "ls180.v:3966.67-3966.221" + cell $or $or$ls180.v:3966$396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3966$395_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:3966$396_Y + end + attribute \src "ls180.v:3974.10-3974.61" + cell $or $or$ls180.v:3974$399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3974$398_Y + connect \B \main_sdram_max_time0 + connect \Y $or$ls180.v:3974$399_Y + end + attribute \src "ls180.v:3984.91-3984.180" + cell $or $or$ls180.v:3984$403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:3984$402_Y + connect \Y $or$ls180.v:3984$403_Y + end + attribute \src "ls180.v:3984.90-3984.255" + cell $or $or$ls180.v:3984$406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3984$403_Y + connect \B $and$ls180.v:3984$405_Y + connect \Y $or$ls180.v:3984$406_Y + end + attribute \src "ls180.v:3984.89-3984.330" + cell $or $or$ls180.v:3984$409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3984$406_Y + connect \B $and$ls180.v:3984$408_Y + connect \Y $or$ls180.v:3984$409_Y + end + attribute \src "ls180.v:3989.91-3989.180" + cell $or $or$ls180.v:3989$419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:3989$418_Y + connect \Y $or$ls180.v:3989$419_Y + end + attribute \src "ls180.v:3989.90-3989.255" + cell $or $or$ls180.v:3989$422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3989$419_Y + connect \B $and$ls180.v:3989$421_Y + connect \Y $or$ls180.v:3989$422_Y + end + attribute \src "ls180.v:3989.89-3989.330" + cell $or $or$ls180.v:3989$425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3989$422_Y + connect \B $and$ls180.v:3989$424_Y + connect \Y $or$ls180.v:3989$425_Y + end + attribute \src "ls180.v:3994.91-3994.180" + cell $or $or$ls180.v:3994$435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:3994$434_Y + connect \Y $or$ls180.v:3994$435_Y + end + attribute \src "ls180.v:3994.90-3994.255" + cell $or $or$ls180.v:3994$438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3994$435_Y + connect \B $and$ls180.v:3994$437_Y + connect \Y $or$ls180.v:3994$438_Y + end + attribute \src "ls180.v:3994.89-3994.330" + cell $or $or$ls180.v:3994$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3994$438_Y + connect \B $and$ls180.v:3994$440_Y + connect \Y $or$ls180.v:3994$441_Y + end + attribute \src "ls180.v:3999.91-3999.180" + cell $or $or$ls180.v:3999$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:3999$450_Y + connect \Y $or$ls180.v:3999$451_Y + end + attribute \src "ls180.v:3999.90-3999.255" + cell $or $or$ls180.v:3999$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3999$451_Y + connect \B $and$ls180.v:3999$453_Y + connect \Y $or$ls180.v:3999$454_Y + end + attribute \src "ls180.v:3999.89-3999.330" + cell $or $or$ls180.v:3999$457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3999$454_Y + connect \B $and$ls180.v:3999$456_Y + connect \Y $or$ls180.v:3999$457_Y + end + attribute \src "ls180.v:4004.132-4004.221" + cell $or $or$ls180.v:4004$468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:4004$467_Y + connect \Y $or$ls180.v:4004$468_Y + end + attribute \src "ls180.v:4004.131-4004.296" + cell $or $or$ls180.v:4004$471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$468_Y + connect \B $and$ls180.v:4004$470_Y + connect \Y $or$ls180.v:4004$471_Y + end + attribute \src "ls180.v:4004.130-4004.371" + cell $or $or$ls180.v:4004$474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$471_Y + connect \B $and$ls180.v:4004$473_Y + connect \Y $or$ls180.v:4004$474_Y + end + attribute \src "ls180.v:4004.34-4004.411" + cell $or $or$ls180.v:4004$479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:4004$478_Y + connect \Y $or$ls180.v:4004$479_Y + end + attribute \src "ls180.v:4004.506-4004.595" + cell $or $or$ls180.v:4004$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:4004$483_Y + connect \Y $or$ls180.v:4004$484_Y + end + attribute \src "ls180.v:4004.505-4004.670" + cell $or $or$ls180.v:4004$487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$484_Y + connect \B $and$ls180.v:4004$486_Y + connect \Y $or$ls180.v:4004$487_Y + end + attribute \src "ls180.v:4004.504-4004.745" + cell $or $or$ls180.v:4004$490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$487_Y + connect \B $and$ls180.v:4004$489_Y + connect \Y $or$ls180.v:4004$490_Y + end + attribute \src "ls180.v:4004.33-4004.785" + cell $or $or$ls180.v:4004$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$479_Y + connect \B $and$ls180.v:4004$494_Y + connect \Y $or$ls180.v:4004$495_Y + end + attribute \src "ls180.v:4004.880-4004.969" + cell $or $or$ls180.v:4004$500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:4004$499_Y + connect \Y $or$ls180.v:4004$500_Y + end + attribute \src "ls180.v:4004.879-4004.1044" + cell $or $or$ls180.v:4004$503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$500_Y + connect \B $and$ls180.v:4004$502_Y + connect \Y $or$ls180.v:4004$503_Y + end + attribute \src "ls180.v:4004.878-4004.1119" + cell $or $or$ls180.v:4004$506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$503_Y + connect \B $and$ls180.v:4004$505_Y + connect \Y $or$ls180.v:4004$506_Y + end + attribute \src "ls180.v:4004.32-4004.1159" + cell $or $or$ls180.v:4004$511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$495_Y + connect \B $and$ls180.v:4004$510_Y + connect \Y $or$ls180.v:4004$511_Y + end + attribute \src "ls180.v:4004.1254-4004.1343" + cell $or $or$ls180.v:4004$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:4004$515_Y + connect \Y $or$ls180.v:4004$516_Y + end + attribute \src "ls180.v:4004.1253-4004.1418" + cell $or $or$ls180.v:4004$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$516_Y + connect \B $and$ls180.v:4004$518_Y + connect \Y $or$ls180.v:4004$519_Y + end + attribute \src "ls180.v:4004.1252-4004.1493" + cell $or $or$ls180.v:4004$522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$519_Y + connect \B $and$ls180.v:4004$521_Y + connect \Y $or$ls180.v:4004$522_Y + end + attribute \src "ls180.v:4004.31-4004.1533" + cell $or $or$ls180.v:4004$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4004$511_Y + connect \B $and$ls180.v:4004$526_Y + connect \Y $or$ls180.v:4004$527_Y + end + attribute \src "ls180.v:4067.10-4067.52" + cell $or $or$ls180.v:4067$536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:4067$536_Y + end + attribute \src "ls180.v:4094.35-4094.74" + cell $or $or$ls180.v:4094$546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4094$546_Y + end + attribute \src "ls180.v:4095.34-4095.73" + cell $or $or$ls180.v:4095$550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4095$550_Y + end + attribute \src "ls180.v:4096.48-4096.130" + cell $or $or$ls180.v:4096$556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4096$553_Y + connect \B $and$ls180.v:4096$555_Y + connect \Y $or$ls180.v:4096$556_Y + end + attribute \src "ls180.v:4097.24-4097.87" + cell $or $or$ls180.v:4097$559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4097$558_Y + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4097$559_Y + end + attribute \src "ls180.v:4098.26-4098.95" + cell $or $or$ls180.v:4098$561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4098$560_Y + connect \B \main_wdata_consumed + connect \Y $or$ls180.v:4098$561_Y + end + attribute \src "ls180.v:4128.42-4128.89" + cell $or $or$ls180.v:4128$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_clear + connect \B $and$ls180.v:4128$568_Y + connect \Y $or$ls180.v:4128$569_Y + end + attribute \src "ls180.v:4152.25-4152.174" + cell $or $or$ls180.v:4152$579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4152$577_Y + connect \B $and$ls180.v:4152$578_Y + connect \Y $or$ls180.v:4152$579_Y + end + attribute \src "ls180.v:4167.80-4167.132" + cell $or $or$ls180.v:4167$581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4167$580_Y + connect \B \main_uart_tx_fifo_re + connect \Y $or$ls180.v:4167$581_Y + end + attribute \src "ls180.v:4178.72-4178.135" + cell $or $or$ls180.v:4178$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_writable + connect \B \main_uart_tx_fifo_replace + connect \Y $or$ls180.v:4178$586_Y + end + attribute \src "ls180.v:4197.80-4197.132" + cell $or $or$ls180.v:4197$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4197$591_Y + connect \B \main_uart_rx_fifo_re + connect \Y $or$ls180.v:4197$592_Y + end + attribute \src "ls180.v:4208.72-4208.135" + cell $or $or$ls180.v:4208$597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_writable + connect \B \main_uart_rx_fifo_replace + connect \Y $or$ls180.v:4208$597_Y + end + attribute \src "ls180.v:4342.36-4342.111" + cell $or $or$ls180.v:4342$618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_clk + connect \B \main_sdphy_cmdw_pads_out_payload_clk + connect \Y $or$ls180.v:4342$618_Y + end + attribute \src "ls180.v:4342.35-4342.151" + cell $or $or$ls180.v:4342$619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4342$618_Y + connect \B \main_sdphy_cmdr_pads_out_payload_clk + connect \Y $or$ls180.v:4342$619_Y + end + attribute \src "ls180.v:4342.34-4342.192" + cell $or $or$ls180.v:4342$620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4342$619_Y + connect \B \main_sdphy_dataw_pads_out_payload_clk + connect \Y $or$ls180.v:4342$620_Y + end + attribute \src "ls180.v:4342.33-4342.233" + cell $or $or$ls180.v:4342$621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4342$620_Y + connect \B \main_sdphy_datar_pads_out_payload_clk + connect \Y $or$ls180.v:4342$621_Y + end + attribute \src "ls180.v:4343.39-4343.120" + cell $or $or$ls180.v:4343$622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_oe + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4343$622_Y + end + attribute \src "ls180.v:4343.38-4343.163" + cell $or $or$ls180.v:4343$623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4343$622_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4343$623_Y + end + attribute \src "ls180.v:4343.37-4343.207" + cell $or $or$ls180.v:4343$624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4343$623_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4343$624_Y + end + attribute \src "ls180.v:4343.36-4343.251" + cell $or $or$ls180.v:4343$625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4343$624_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4343$625_Y + end + attribute \src "ls180.v:4344.38-4344.117" + cell $or $or$ls180.v:4344$626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_o + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4344$626_Y + end + attribute \src "ls180.v:4344.37-4344.159" + cell $or $or$ls180.v:4344$627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4344$626_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4344$627_Y + end + attribute \src "ls180.v:4344.36-4344.202" + cell $or $or$ls180.v:4344$628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4344$627_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4344$628_Y + end + attribute \src "ls180.v:4344.35-4344.245" + cell $or $or$ls180.v:4344$629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4344$628_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4344$629_Y + end + attribute \src "ls180.v:4345.40-4345.123" + cell $or $or$ls180.v:4345$630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_data_oe + connect \B \main_sdphy_cmdw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4345$630_Y + end + attribute \src "ls180.v:4345.39-4345.167" + cell $or $or$ls180.v:4345$631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4345$630_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_oe + connect \Y $or$ls180.v:4345$631_Y + end + attribute \src "ls180.v:4345.38-4345.212" + cell $or $or$ls180.v:4345$632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4345$631_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4345$632_Y + end + attribute \src "ls180.v:4345.37-4345.257" + cell $or $or$ls180.v:4345$633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4345$632_Y + connect \B \main_sdphy_datar_pads_out_payload_data_oe + connect \Y $or$ls180.v:4345$633_Y + end + attribute \src "ls180.v:4346.39-4346.120" + cell $or $or$ls180.v:4346$634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_init_pads_out_payload_data_o + connect \B \main_sdphy_cmdw_pads_out_payload_data_o + connect \Y $or$ls180.v:4346$634_Y + end + attribute \src "ls180.v:4346.38-4346.163" + cell $or $or$ls180.v:4346$635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4346$634_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_o + connect \Y $or$ls180.v:4346$635_Y + end + attribute \src "ls180.v:4346.37-4346.207" + cell $or $or$ls180.v:4346$636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4346$635_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_o + connect \Y $or$ls180.v:4346$636_Y + end + attribute \src "ls180.v:4346.36-4346.251" + cell $or $or$ls180.v:4346$637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4346$636_Y + connect \B \main_sdphy_datar_pads_out_payload_data_o + connect \Y $or$ls180.v:4346$637_Y + end + attribute \src "ls180.v:4367.35-4367.80" + cell $or $or$ls180.v:4367$638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_stop + connect \B \main_sdphy_datar_stop + connect \Y $or$ls180.v:4367$638_Y + end + attribute \src "ls180.v:4521.91-4521.144" + cell $or $or$ls180.v:4521$652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:4521$652_Y + end + attribute \src "ls180.v:4538.53-4538.143" + cell $or $or$ls180.v:4538$655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4538$654_Y + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $or$ls180.v:4538$655_Y + end + attribute \src "ls180.v:4541.47-4541.127" + cell $or $or$ls180.v:4541$658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4541$657_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:4541$658_Y + end + attribute \src "ls180.v:4665.54-4665.146" + cell $or $or$ls180.v:4665$676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4665$675_Y + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $or$ls180.v:4665$676_Y + end + attribute \src "ls180.v:4668.48-4668.130" + cell $or $or$ls180.v:4668$679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4668$678_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:4668$679_Y + end + attribute \src "ls180.v:4799.55-4799.149" + cell $or $or$ls180.v:4799$691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4799$690_Y + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $or$ls180.v:4799$691_Y + end + attribute \src "ls180.v:4802.49-4802.133" + cell $or $or$ls180.v:4802$694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4802$693_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:4802$694_Y + end + attribute \src "ls180.v:5431.80-5431.151" + cell $or $or$ls180.v:5431$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_writable + connect \B \main_sdblock2mem_fifo_replace + connect \Y $or$ls180.v:5431$989_Y + end + attribute \src "ls180.v:5442.49-5442.131" + cell $or $or$ls180.v:5442$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:5442$994_Y + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $or$ls180.v:5442$995_Y + end + attribute \src "ls180.v:5639.80-5639.151" + cell $or $or$ls180.v:5639$1020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_writable + connect \B \main_sdmem2block_fifo_replace + connect \Y $or$ls180.v:5639$1020_Y + end + attribute \src "ls180.v:5754.33-5754.102" + cell $or $or$ls180.v:5754$1060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_err + connect \B \main_libresocsim_libresoc_xics_icp_err + connect \Y $or$ls180.v:5754$1060_Y + end + attribute \src "ls180.v:5754.32-5754.144" + cell $or $or$ls180.v:5754$1061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5754$1060_Y + connect \B \main_libresocsim_libresoc_xics_ics_err + connect \Y $or$ls180.v:5754$1061_Y + end + attribute \src "ls180.v:5754.31-5754.165" + cell $or $or$ls180.v:5754$1062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5754$1061_Y + connect \B \main_wb_sdram_err + connect \Y $or$ls180.v:5754$1062_Y + end + attribute \src "ls180.v:5754.30-5754.201" + cell $or $or$ls180.v:5754$1063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5754$1062_Y + connect \B \builder_libresocsim_wishbone_err + connect \Y $or$ls180.v:5754$1063_Y + end + attribute \src "ls180.v:5760.28-5760.97" + cell $or $or$ls180.v:5760$1068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \B \main_libresocsim_libresoc_xics_icp_ack + connect \Y $or$ls180.v:5760$1068_Y + end + attribute \src "ls180.v:5760.27-5760.139" + cell $or $or$ls180.v:5760$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5760$1068_Y + connect \B \main_libresocsim_libresoc_xics_ics_ack + connect \Y $or$ls180.v:5760$1069_Y + end + attribute \src "ls180.v:5760.26-5760.160" + cell $or $or$ls180.v:5760$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5760$1069_Y + connect \B \main_wb_sdram_ack + connect \Y $or$ls180.v:5760$1070_Y + end + attribute \src "ls180.v:5760.25-5760.196" + cell $or $or$ls180.v:5760$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5760$1070_Y + connect \B \builder_libresocsim_wishbone_ack + connect \Y $or$ls180.v:5760$1071_Y + end + attribute \src "ls180.v:5761.30-5761.169" + cell $or $or$ls180.v:5761$1074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $and$ls180.v:5761$1072_Y + connect \B $and$ls180.v:5761$1073_Y + connect \Y $or$ls180.v:5761$1074_Y + end + attribute \src "ls180.v:5761.29-5761.246" + cell $or $or$ls180.v:5761$1076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5761$1074_Y + connect \B $and$ls180.v:5761$1075_Y + connect \Y $or$ls180.v:5761$1076_Y + end + attribute \src "ls180.v:5761.28-5761.302" + cell $or $or$ls180.v:5761$1078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5761$1076_Y + connect \B $and$ls180.v:5761$1077_Y + connect \Y $or$ls180.v:5761$1078_Y + end + attribute \src "ls180.v:5761.27-5761.373" + cell $or $or$ls180.v:5761$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5761$1078_Y + connect \B $and$ls180.v:5761$1079_Y + connect \Y $or$ls180.v:5761$1080_Y + end + attribute \src "ls180.v:6515.55-6515.124" + cell $or $or$ls180.v:6515$2226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \builder_interface0_bank_bus_dat_r + connect \B \builder_interface1_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2226_Y + end + attribute \src "ls180.v:6515.54-6515.161" + cell $or $or$ls180.v:6515$2227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2226_Y + connect \B \builder_interface2_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2227_Y + end + attribute \src "ls180.v:6515.53-6515.198" + cell $or $or$ls180.v:6515$2228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2227_Y + connect \B \builder_interface3_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2228_Y + end + attribute \src "ls180.v:6515.52-6515.235" + cell $or $or$ls180.v:6515$2229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2228_Y + connect \B \builder_interface4_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2229_Y + end + attribute \src "ls180.v:6515.51-6515.272" + cell $or $or$ls180.v:6515$2230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2229_Y + connect \B \builder_interface5_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2230_Y + end + attribute \src "ls180.v:6515.50-6515.309" + cell $or $or$ls180.v:6515$2231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2230_Y + connect \B \builder_interface6_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2231_Y + end + attribute \src "ls180.v:6515.49-6515.346" + cell $or $or$ls180.v:6515$2232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2231_Y + connect \B \builder_interface7_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2232_Y + end + attribute \src "ls180.v:6515.48-6515.383" + cell $or $or$ls180.v:6515$2233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2232_Y + connect \B \builder_interface8_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2233_Y + end + attribute \src "ls180.v:6515.47-6515.420" + cell $or $or$ls180.v:6515$2234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2233_Y + connect \B \builder_interface9_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2234_Y + end + attribute \src "ls180.v:6515.46-6515.458" + cell $or $or$ls180.v:6515$2235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2234_Y + connect \B \builder_interface10_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2235_Y + end + attribute \src "ls180.v:6515.45-6515.496" + cell $or $or$ls180.v:6515$2236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2235_Y + connect \B \builder_interface11_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2236_Y + end + attribute \src "ls180.v:6515.44-6515.534" + cell $or $or$ls180.v:6515$2237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2236_Y + connect \B \builder_interface12_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2237_Y + end + attribute \src "ls180.v:6515.43-6515.572" + cell $or $or$ls180.v:6515$2238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2237_Y + connect \B \builder_interface13_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2238_Y + end + attribute \src "ls180.v:6515.42-6515.610" + cell $or $or$ls180.v:6515$2239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6515$2238_Y + connect \B \builder_interface14_bank_bus_dat_r + connect \Y $or$ls180.v:6515$2239_Y + end + attribute \src "ls180.v:6842.90-6842.179" + cell $or $or$ls180.v:6842$2264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:6842$2263_Y + connect \Y $or$ls180.v:6842$2264_Y + end + attribute \src "ls180.v:6842.89-6842.254" + cell $or $or$ls180.v:6842$2267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6842$2264_Y + connect \B $and$ls180.v:6842$2266_Y + connect \Y $or$ls180.v:6842$2267_Y + end + attribute \src "ls180.v:6842.88-6842.329" + cell $or $or$ls180.v:6842$2270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6842$2267_Y + connect \B $and$ls180.v:6842$2269_Y + connect \Y $or$ls180.v:6842$2270_Y + end + attribute \src "ls180.v:6866.90-6866.179" + cell $or $or$ls180.v:6866$2280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:6866$2279_Y + connect \Y $or$ls180.v:6866$2280_Y + end + attribute \src "ls180.v:6866.89-6866.254" + cell $or $or$ls180.v:6866$2283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6866$2280_Y + connect \B $and$ls180.v:6866$2282_Y + connect \Y $or$ls180.v:6866$2283_Y + end + attribute \src "ls180.v:6866.88-6866.329" + cell $or $or$ls180.v:6866$2286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6866$2283_Y + connect \B $and$ls180.v:6866$2285_Y + connect \Y $or$ls180.v:6866$2286_Y + end + attribute \src "ls180.v:6890.90-6890.179" + cell $or $or$ls180.v:6890$2296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:6890$2295_Y + connect \Y $or$ls180.v:6890$2296_Y + end + attribute \src "ls180.v:6890.89-6890.254" + cell $or $or$ls180.v:6890$2299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6890$2296_Y + connect \B $and$ls180.v:6890$2298_Y + connect \Y $or$ls180.v:6890$2299_Y + end + attribute \src "ls180.v:6890.88-6890.329" + cell $or $or$ls180.v:6890$2302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6890$2299_Y + connect \B $and$ls180.v:6890$2301_Y + connect \Y $or$ls180.v:6890$2302_Y + end + attribute \src "ls180.v:6914.90-6914.179" + cell $or $or$ls180.v:6914$2312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:6914$2311_Y + connect \Y $or$ls180.v:6914$2312_Y + end + attribute \src "ls180.v:6914.89-6914.254" + cell $or $or$ls180.v:6914$2315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6914$2312_Y + connect \B $and$ls180.v:6914$2314_Y + connect \Y $or$ls180.v:6914$2315_Y + end + attribute \src "ls180.v:6914.88-6914.329" + cell $or $or$ls180.v:6914$2318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6914$2315_Y + connect \B $and$ls180.v:6914$2317_Y + connect \Y $or$ls180.v:6914$2318_Y + end + attribute \src "ls180.v:7428.20-7428.71" + cell $or $or$ls180.v:7428$2375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [0] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7428$2375_Y + end + attribute \src "ls180.v:7429.20-7429.71" + cell $or $or$ls180.v:7429$2376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [1] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7429$2376_Y + end + attribute \src "ls180.v:7430.20-7430.71" + cell $or $or$ls180.v:7430$2377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [2] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7430$2377_Y + end + attribute \src "ls180.v:7431.20-7431.71" + cell $or $or$ls180.v:7431$2378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [3] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7431$2378_Y + end + attribute \src "ls180.v:7432.20-7432.71" + cell $or $or$ls180.v:7432$2379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [4] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7432$2379_Y + end + attribute \src "ls180.v:7433.20-7433.71" + cell $or $or$ls180.v:7433$2380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [5] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7433$2380_Y + end + attribute \src "ls180.v:7434.20-7434.71" + cell $or $or$ls180.v:7434$2381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [6] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7434$2381_Y + end + attribute \src "ls180.v:7435.20-7435.71" + cell $or $or$ls180.v:7435$2382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [7] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7435$2382_Y + end + attribute \src "ls180.v:7436.20-7436.71" + cell $or $or$ls180.v:7436$2383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [8] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7436$2383_Y + end + attribute \src "ls180.v:7437.20-7437.71" + cell $or $or$ls180.v:7437$2384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [9] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7437$2384_Y + end + attribute \src "ls180.v:7438.21-7438.73" + cell $or $or$ls180.v:7438$2385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [10] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7438$2385_Y + end + attribute \src "ls180.v:7439.21-7439.73" + cell $or $or$ls180.v:7439$2386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [11] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7439$2386_Y + end + attribute \src "ls180.v:7440.21-7440.73" + cell $or $or$ls180.v:7440$2387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [12] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7440$2387_Y + end + attribute \src "ls180.v:7441.21-7441.73" + cell $or $or$ls180.v:7441$2388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [13] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7441$2388_Y + end + attribute \src "ls180.v:7442.21-7442.73" + cell $or $or$ls180.v:7442$2389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [14] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7442$2389_Y + end + attribute \src "ls180.v:7443.21-7443.73" + cell $or $or$ls180.v:7443$2390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [15] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7443$2390_Y + end + attribute \src "ls180.v:7444.21-7444.73" + cell $or $or$ls180.v:7444$2391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [16] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7444$2391_Y + end + attribute \src "ls180.v:7445.21-7445.73" + cell $or $or$ls180.v:7445$2392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [17] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7445$2392_Y + end + attribute \src "ls180.v:7446.21-7446.73" + cell $or $or$ls180.v:7446$2393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [18] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7446$2393_Y + end + attribute \src "ls180.v:7447.21-7447.73" + cell $or $or$ls180.v:7447$2394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [19] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7447$2394_Y + end + attribute \src "ls180.v:7448.21-7448.73" + cell $or $or$ls180.v:7448$2395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [20] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7448$2395_Y + end + attribute \src "ls180.v:7449.21-7449.73" + cell $or $or$ls180.v:7449$2396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [21] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7449$2396_Y + end + attribute \src "ls180.v:7450.21-7450.73" + cell $or $or$ls180.v:7450$2397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [22] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7450$2397_Y + end + attribute \src "ls180.v:7451.21-7451.73" + cell $or $or$ls180.v:7451$2398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [23] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7451$2398_Y + end + attribute \src "ls180.v:7452.7-7452.93" + cell $or $or$ls180.v:7452$2399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$ls180.v:7452$2399_Y + end + attribute \src "ls180.v:7463.7-7463.93" + cell $or $or$ls180.v:7463$2400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$ls180.v:7463$2400_Y + end + attribute \src "ls180.v:7474.7-7474.93" + cell $or $or$ls180.v:7474$2401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_ack + connect \B \main_libresocsim_converter2_skip + connect \Y $or$ls180.v:7474$2401_Y + end + attribute \src "ls180.v:7603.7-7603.107" + cell $or $or$ls180.v:7603$2437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7603$2436_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:7603$2437_Y + end + attribute \src "ls180.v:7649.7-7649.107" + cell $or $or$ls180.v:7649$2453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7649$2452_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:7649$2453_Y + end + attribute \src "ls180.v:7695.7-7695.107" + cell $or $or$ls180.v:7695$2469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7695$2468_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:7695$2469_Y + end + attribute \src "ls180.v:7741.7-7741.107" + cell $or $or$ls180.v:7741$2485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7741$2484_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:7741$2485_Y + end + attribute \src "ls180.v:7929.40-7929.125" + cell $or $or$ls180.v:7929$2506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:7929$2505_Y + connect \Y $or$ls180.v:7929$2506_Y + end + attribute \src "ls180.v:7929.39-7929.207" + cell $or $or$ls180.v:7929$2509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7929$2506_Y + connect \B $and$ls180.v:7929$2508_Y + connect \Y $or$ls180.v:7929$2509_Y + end + attribute \src "ls180.v:7929.38-7929.289" + cell $or $or$ls180.v:7929$2512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7929$2509_Y + connect \B $and$ls180.v:7929$2511_Y + connect \Y $or$ls180.v:7929$2512_Y + end + attribute \src "ls180.v:7929.37-7929.371" + cell $or $or$ls180.v:7929$2515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7929$2512_Y + connect \B $and$ls180.v:7929$2514_Y + connect \Y $or$ls180.v:7929$2515_Y + end + attribute \src "ls180.v:7930.41-7930.126" + cell $or $or$ls180.v:7930$2518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:7930$2517_Y + connect \Y $or$ls180.v:7930$2518_Y + end + attribute \src "ls180.v:7930.40-7930.208" + cell $or $or$ls180.v:7930$2521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7930$2518_Y + connect \B $and$ls180.v:7930$2520_Y + connect \Y $or$ls180.v:7930$2521_Y + end + attribute \src "ls180.v:7930.39-7930.290" + cell $or $or$ls180.v:7930$2524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7930$2521_Y + connect \B $and$ls180.v:7930$2523_Y + connect \Y $or$ls180.v:7930$2524_Y + end + attribute \src "ls180.v:7930.38-7930.372" + cell $or $or$ls180.v:7930$2527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7930$2524_Y + connect \B $and$ls180.v:7930$2526_Y + connect \Y $or$ls180.v:7930$2527_Y + end + attribute \src "ls180.v:7934.7-7934.49" + cell $or $or$ls180.v:7934$2528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:7934$2528_Y + end + attribute \src "ls180.v:8097.21-8097.74" + cell $or $or$ls180.v:8097$2576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8097$2574_Y + connect \B $not$ls180.v:8097$2575_Y + connect \Y $or$ls180.v:8097$2576_Y + end + attribute \src "ls180.v:8132.21-8132.71" + cell $or $or$ls180.v:8132$2581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8132$2579_Y + connect \B $not$ls180.v:8132$2580_Y + connect \Y $or$ls180.v:8132$2581_Y + end + attribute \src "ls180.v:8200.32-8200.85" + cell $or $or$ls180.v:8200$2593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:8200$2593_Y + end + attribute \src "ls180.v:8206.8-8206.97" + cell $or $or$ls180.v:8206$2595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8206$2594_Y + connect \B \main_sdphy_cmdr_cmdr_converter_sink_last + connect \Y $or$ls180.v:8206$2595_Y + end + attribute \src "ls180.v:8223.52-8223.139" + cell $or $or$ls180.v:8223$2600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_first + connect \B \main_sdphy_cmdr_cmdr_converter_source_first + connect \Y $or$ls180.v:8223$2600_Y + end + attribute \src "ls180.v:8224.51-8224.136" + cell $or $or$ls180.v:8224$2601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_last + connect \B \main_sdphy_cmdr_cmdr_converter_source_last + connect \Y $or$ls180.v:8224$2601_Y + end + attribute \src "ls180.v:8258.7-8258.87" + cell $or $or$ls180.v:8258$2604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8258$2603_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:8258$2604_Y + end + attribute \src "ls180.v:8281.33-8281.88" + cell $or $or$ls180.v:8281$2605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_start + connect \B \main_sdphy_dataw_crcr_run + connect \Y $or$ls180.v:8281$2605_Y + end + attribute \src "ls180.v:8287.8-8287.99" + cell $or $or$ls180.v:8287$2607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8287$2606_Y + connect \B \main_sdphy_dataw_crcr_converter_sink_last + connect \Y $or$ls180.v:8287$2607_Y + end + attribute \src "ls180.v:8304.53-8304.142" + cell $or $or$ls180.v:8304$2612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_first + connect \B \main_sdphy_dataw_crcr_converter_source_first + connect \Y $or$ls180.v:8304$2612_Y + end + attribute \src "ls180.v:8305.52-8305.139" + cell $or $or$ls180.v:8305$2613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_last + connect \B \main_sdphy_dataw_crcr_converter_source_last + connect \Y $or$ls180.v:8305$2613_Y + end + attribute \src "ls180.v:8339.7-8339.89" + cell $or $or$ls180.v:8339$2616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8339$2615_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:8339$2616_Y + end + attribute \src "ls180.v:8360.34-8360.91" + cell $or $or$ls180.v:8360$2617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_start + connect \B \main_sdphy_datar_datar_run + connect \Y $or$ls180.v:8360$2617_Y + end + attribute \src "ls180.v:8366.8-8366.101" + cell $or $or$ls180.v:8366$2619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8366$2618_Y + connect \B \main_sdphy_datar_datar_converter_sink_last + connect \Y $or$ls180.v:8366$2619_Y + end + attribute \src "ls180.v:8383.54-8383.145" + cell $or $or$ls180.v:8383$2624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_first + connect \B \main_sdphy_datar_datar_converter_source_first + connect \Y $or$ls180.v:8383$2624_Y + end + attribute \src "ls180.v:8384.53-8384.142" + cell $or $or$ls180.v:8384$2625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_last + connect \B \main_sdphy_datar_datar_converter_source_last + connect \Y $or$ls180.v:8384$2625_Y + end + attribute \src "ls180.v:8400.7-8400.91" + cell $or $or$ls180.v:8400$2628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8400$2627_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:8400$2628_Y + end + attribute \src "ls180.v:8589.8-8589.89" + cell $or $or$ls180.v:8589$2652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8589$2651_Y + connect \B \main_sdblock2mem_converter_sink_last + connect \Y $or$ls180.v:8589$2652_Y + end + attribute \src "ls180.v:8606.48-8606.127" + cell $or $or$ls180.v:8606$2657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_first + connect \B \main_sdblock2mem_converter_source_first + connect \Y $or$ls180.v:8606$2657_Y + end + attribute \src "ls180.v:8607.47-8607.124" + cell $or $or$ls180.v:8607$2658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_last + connect \B \main_sdblock2mem_converter_source_last + connect \Y $or$ls180.v:8607$2658_Y + end + attribute \src "ls180.v:3178.46-3178.94" + cell $sshl $sshl$ls180.v:3178$83 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine0_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3178$83_Y + end + attribute \src "ls180.v:3335.46-3335.94" + cell $sshl $sshl$ls180.v:3335$113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine1_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3335$113_Y + end + attribute \src "ls180.v:3492.46-3492.94" + cell $sshl $sshl$ls180.v:3492$143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine2_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3492$143_Y + end + attribute \src "ls180.v:3649.46-3649.94" + cell $sshl $sshl$ls180.v:3649$173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine3_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3649$173_Y + end + attribute \src "ls180.v:3209.63-3209.122" + cell $sub $sub$ls180.v:3209$96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3209$96_Y + end + attribute \src "ls180.v:3366.63-3366.122" + cell $sub $sub$ls180.v:3366$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3366$126_Y + end + attribute \src "ls180.v:3523.63-3523.122" + cell $sub $sub$ls180.v:3523$156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3523$156_Y + end + attribute \src "ls180.v:3680.63-3680.122" + cell $sub $sub$ls180.v:3680$186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3680$186_Y + end + attribute \src "ls180.v:4086.38-4086.75" + cell $sub $sub$ls180.v:4086$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 30 + parameter \B_SIGNED 0 + parameter \B_WIDTH 31 + parameter \Y_WIDTH 31 + connect \A \main_litedram_wb_adr + connect \B 31'1001000000000000000000000000000 + connect \Y $sub$ls180.v:4086$540_Y + end + attribute \src "ls180.v:4172.36-4172.68" + cell $sub $sub$ls180.v:4172$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4172$585_Y + end + attribute \src "ls180.v:4202.36-4202.68" + cell $sub $sub$ls180.v:4202$596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4202$596_Y + end + attribute \src "ls180.v:4227.70-4227.110" + cell $sub $sub$ls180.v:4227$602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4227$602_Y + end + attribute \src "ls180.v:4228.70-4228.104" + cell $sub $sub$ls180.v:4228$604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider + connect \B 1'1 + connect \Y $sub$ls180.v:4228$604_Y + end + attribute \src "ls180.v:4255.37-4255.66" + cell $sub $sub$ls180.v:4255$608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spimaster1_length + connect \B 1'1 + connect \Y $sub$ls180.v:4255$608_Y + end + attribute \src "ls180.v:4285.67-4285.107" + cell $sub $sub$ls180.v:4285$610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4285$610_Y + end + attribute \src "ls180.v:4286.67-4286.101" + cell $sub $sub$ls180.v:4286$612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider0 + connect \B 1'1 + connect \Y $sub$ls180.v:4286$612_Y + end + attribute \src "ls180.v:4314.35-4314.64" + cell $sub $sub$ls180.v:4314$616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spisdcard_length0 + connect \B 1'1 + connect \Y $sub$ls180.v:4314$616_Y + end + attribute \src "ls180.v:4568.60-4568.90" + cell $sub $sub$ls180.v:4568$660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4568$660_Y + end + attribute \src "ls180.v:4579.62-4579.104" + cell $sub $sub$ls180.v:4579$662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_sink_payload_length + connect \B 1'1 + connect \Y $sub$ls180.v:4579$662_Y + end + attribute \src "ls180.v:4596.60-4596.90" + cell $sub $sub$ls180.v:4596$666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4596$666_Y + end + attribute \src "ls180.v:4825.62-4825.93" + cell $sub $sub$ls180.v:4825$696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4825$696_Y + end + attribute \src "ls180.v:4830.62-4830.93" + cell $sub $sub$ls180.v:4830$697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4830$697_Y + end + attribute \src "ls180.v:4841.64-4841.122" + cell $sub $sub$ls180.v:4841$700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A $add$ls180.v:4841$699_Y + connect \B 1'1 + connect \Y $sub$ls180.v:4841$700_Y + end + attribute \src "ls180.v:4862.62-4862.93" + cell $sub $sub$ls180.v:4862$703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4862$703_Y + end + attribute \src "ls180.v:5324.37-5324.75" + cell $sub $sub$ls180.v:5324$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5324$976_Y + end + attribute \src "ls180.v:5339.62-5339.100" + cell $sub $sub$ls180.v:5339$979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5339$979_Y + end + attribute \src "ls180.v:5350.39-5350.77" + cell $sub $sub$ls180.v:5350$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5350$984_Y + end + attribute \src "ls180.v:5425.40-5425.76" + cell $sub $sub$ls180.v:5425$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5425$988_Y + end + attribute \src "ls180.v:5474.56-5474.104" + cell $sub $sub$ls180.v:5474$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_length + connect \B 1'1 + connect \Y $sub$ls180.v:5474$1002_Y + end + attribute \src "ls180.v:5564.71-5564.105" + cell $sub $sub$ls180.v:5564$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_length + connect \B 1'1 + connect \Y $sub$ls180.v:5564$1008_Y + end + attribute \src "ls180.v:5633.40-5633.76" + cell $sub $sub$ls180.v:5633$1019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5633$1019_Y + end + attribute \src "ls180.v:7498.31-7498.60" + cell $sub $sub$ls180.v:7498$2408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_value + connect \B 1'1 + connect \Y $sub$ls180.v:7498$2408_Y + end + attribute \src "ls180.v:7519.31-7519.61" + cell $sub $sub$ls180.v:7519$2413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdram_timer_count1 + connect \B 1'1 + connect \Y $sub$ls180.v:7519$2413_Y + end + attribute \src "ls180.v:7525.34-7525.67" + cell $sub $sub$ls180.v:7525$2414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7525$2414_Y + end + attribute \src "ls180.v:7536.36-7536.69" + cell $sub $sub$ls180.v:7536$2417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7536$2417_Y + end + attribute \src "ls180.v:7600.59-7600.116" + cell $sub $sub$ls180.v:7600$2435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7600$2435_Y + end + attribute \src "ls180.v:7619.46-7619.90" + cell $sub $sub$ls180.v:7619$2439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7619$2439_Y + end + attribute \src "ls180.v:7646.59-7646.116" + cell $sub $sub$ls180.v:7646$2451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7646$2451_Y + end + attribute \src "ls180.v:7665.46-7665.90" + cell $sub $sub$ls180.v:7665$2455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7665$2455_Y + end + attribute \src "ls180.v:7692.59-7692.116" + cell $sub $sub$ls180.v:7692$2467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7692$2467_Y + end + attribute \src "ls180.v:7711.46-7711.90" + cell $sub $sub$ls180.v:7711$2471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7711$2471_Y + end + attribute \src "ls180.v:7738.59-7738.116" + cell $sub $sub$ls180.v:7738$2483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7738$2483_Y + end + attribute \src "ls180.v:7757.46-7757.90" + cell $sub $sub$ls180.v:7757$2487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7757$2487_Y + end + attribute \src "ls180.v:7768.25-7768.48" + cell $sub $sub$ls180.v:7768$2491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdram_time0 + connect \B 1'1 + connect \Y $sub$ls180.v:7768$2491_Y + end + attribute \src "ls180.v:7775.25-7775.48" + cell $sub $sub$ls180.v:7775$2494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_time1 + connect \B 1'1 + connect \Y $sub$ls180.v:7775$2494_Y + end + attribute \src "ls180.v:7907.33-7907.64" + cell $sub $sub$ls180.v:7907$2499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7907$2499_Y + end + attribute \src "ls180.v:7922.33-7922.64" + cell $sub $sub$ls180.v:7922$2502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7922$2502_Y + end + attribute \src "ls180.v:8049.33-8049.64" + cell $sub $sub$ls180.v:8049$2561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8049$2561_Y + end + attribute \src "ls180.v:8071.33-8071.64" + cell $sub $sub$ls180.v:8071$2572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8071$2572_Y + end + attribute \src "ls180.v:8106.34-8106.66" + cell $sub $sub$ls180.v:8106$2577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spimaster34_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8106$2577_Y + end + attribute \src "ls180.v:8141.32-8141.62" + cell $sub $sub$ls180.v:8141$2582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8141$2582_Y + end + attribute \src "ls180.v:8165.30-8165.53" + cell $sub $sub$ls180.v:8165$2585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_period + connect \B 1'1 + connect \Y $sub$ls180.v:8165$2585_Y + end + attribute \src "ls180.v:8179.30-8179.53" + cell $sub $sub$ls180.v:8179$2589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_period + connect \B 1'1 + connect \Y $sub$ls180.v:8179$2589_Y + end + attribute \src "ls180.v:8582.36-8582.70" + cell $sub $sub$ls180.v:8582$2650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8582$2650_Y + end + attribute \src "ls180.v:8668.36-8668.70" + cell $sub $sub$ls180.v:8668$2672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8668$2672_Y + end + attribute \src "ls180.v:8781.22-8781.42" + cell $sub $sub$ls180.v:8781$2679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 20 + connect \A \builder_count + connect \B 1'1 + connect \Y $sub$ls180.v:8781$2679_Y + end + attribute \src "ls180.v:4922.353-4922.425" + cell $xor $xor$ls180.v:4922$710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:4922$710_Y + end + attribute \src "ls180.v:4922.200-4922.272" + cell $xor $xor$ls180.v:4922$711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:4922$711_Y + end + attribute \src "ls180.v:4922.160-4922.273" + cell $xor $xor$ls180.v:4922$712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg0 [2] + connect \B $xor$ls180.v:4922$711_Y + connect \Y $xor$ls180.v:4922$712_Y + end + attribute \src "ls180.v:4923.353-4923.425" + cell $xor $xor$ls180.v:4923$713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:4923$713_Y + end + attribute \src "ls180.v:4923.200-4923.272" + cell $xor $xor$ls180.v:4923$714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:4923$714_Y + end + attribute \src "ls180.v:4923.160-4923.273" + cell $xor $xor$ls180.v:4923$715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg1 [2] + connect \B $xor$ls180.v:4923$714_Y + connect \Y $xor$ls180.v:4923$715_Y + end + attribute \src "ls180.v:4924.353-4924.425" + cell $xor $xor$ls180.v:4924$716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:4924$716_Y + end + attribute \src "ls180.v:4924.200-4924.272" + cell $xor $xor$ls180.v:4924$717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:4924$717_Y + end + attribute \src "ls180.v:4924.160-4924.273" + cell $xor $xor$ls180.v:4924$718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg2 [2] + connect \B $xor$ls180.v:4924$717_Y + connect \Y $xor$ls180.v:4924$718_Y + end + attribute \src "ls180.v:4925.353-4925.425" + cell $xor $xor$ls180.v:4925$719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:4925$719_Y + end + attribute \src "ls180.v:4925.200-4925.272" + cell $xor $xor$ls180.v:4925$720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:4925$720_Y + end + attribute \src "ls180.v:4925.160-4925.273" + cell $xor $xor$ls180.v:4925$721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg3 [2] + connect \B $xor$ls180.v:4925$720_Y + connect \Y $xor$ls180.v:4925$721_Y + end + attribute \src "ls180.v:4926.353-4926.425" + cell $xor $xor$ls180.v:4926$722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:4926$722_Y + end + attribute \src "ls180.v:4926.200-4926.272" + cell $xor $xor$ls180.v:4926$723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:4926$723_Y + end + attribute \src "ls180.v:4926.160-4926.273" + cell $xor $xor$ls180.v:4926$724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg4 [2] + connect \B $xor$ls180.v:4926$723_Y + connect \Y $xor$ls180.v:4926$724_Y + end + attribute \src "ls180.v:4927.353-4927.425" + cell $xor $xor$ls180.v:4927$725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:4927$725_Y + end + attribute \src "ls180.v:4927.200-4927.272" + cell $xor $xor$ls180.v:4927$726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:4927$726_Y + end + attribute \src "ls180.v:4927.160-4927.273" + cell $xor $xor$ls180.v:4927$727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg5 [2] + connect \B $xor$ls180.v:4927$726_Y + connect \Y $xor$ls180.v:4927$727_Y + end + attribute \src "ls180.v:4928.353-4928.425" + cell $xor $xor$ls180.v:4928$728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:4928$728_Y + end + attribute \src "ls180.v:4928.200-4928.272" + cell $xor $xor$ls180.v:4928$729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:4928$729_Y + end + attribute \src "ls180.v:4928.160-4928.273" + cell $xor $xor$ls180.v:4928$730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg6 [2] + connect \B $xor$ls180.v:4928$729_Y + connect \Y $xor$ls180.v:4928$730_Y + end + attribute \src "ls180.v:4929.353-4929.425" + cell $xor $xor$ls180.v:4929$731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:4929$731_Y + end + attribute \src "ls180.v:4929.200-4929.272" + cell $xor $xor$ls180.v:4929$732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:4929$732_Y + end + attribute \src "ls180.v:4929.160-4929.273" + cell $xor $xor$ls180.v:4929$733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg7 [2] + connect \B $xor$ls180.v:4929$732_Y + connect \Y $xor$ls180.v:4929$733_Y + end + attribute \src "ls180.v:4930.353-4930.425" + cell $xor $xor$ls180.v:4930$734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:4930$734_Y + end + attribute \src "ls180.v:4930.200-4930.272" + cell $xor $xor$ls180.v:4930$735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:4930$735_Y + end + attribute \src "ls180.v:4930.160-4930.273" + cell $xor $xor$ls180.v:4930$736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg8 [2] + connect \B $xor$ls180.v:4930$735_Y + connect \Y $xor$ls180.v:4930$736_Y + end + attribute \src "ls180.v:4931.354-4931.426" + cell $xor $xor$ls180.v:4931$737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:4931$737_Y + end + attribute \src "ls180.v:4931.201-4931.273" + cell $xor $xor$ls180.v:4931$738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:4931$738_Y + end + attribute \src "ls180.v:4931.161-4931.274" + cell $xor $xor$ls180.v:4931$739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg9 [2] + connect \B $xor$ls180.v:4931$738_Y + connect \Y $xor$ls180.v:4931$739_Y + end + attribute \src "ls180.v:4932.361-4932.434" + cell $xor $xor$ls180.v:4932$740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:4932$740_Y + end + attribute \src "ls180.v:4932.205-4932.278" + cell $xor $xor$ls180.v:4932$741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:4932$741_Y + end + attribute \src "ls180.v:4932.164-4932.279" + cell $xor $xor$ls180.v:4932$742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg10 [2] + connect \B $xor$ls180.v:4932$741_Y + connect \Y $xor$ls180.v:4932$742_Y + end + attribute \src "ls180.v:4933.361-4933.434" + cell $xor $xor$ls180.v:4933$743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:4933$743_Y + end + attribute \src "ls180.v:4933.205-4933.278" + cell $xor $xor$ls180.v:4933$744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:4933$744_Y + end + attribute \src "ls180.v:4933.164-4933.279" + cell $xor $xor$ls180.v:4933$745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg11 [2] + connect \B $xor$ls180.v:4933$744_Y + connect \Y $xor$ls180.v:4933$745_Y + end + attribute \src "ls180.v:4934.361-4934.434" + cell $xor $xor$ls180.v:4934$746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:4934$746_Y + end + attribute \src "ls180.v:4934.205-4934.278" + cell $xor $xor$ls180.v:4934$747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:4934$747_Y + end + attribute \src "ls180.v:4934.164-4934.279" + cell $xor $xor$ls180.v:4934$748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg12 [2] + connect \B $xor$ls180.v:4934$747_Y + connect \Y $xor$ls180.v:4934$748_Y + end + attribute \src "ls180.v:4935.361-4935.434" + cell $xor $xor$ls180.v:4935$749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:4935$749_Y + end + attribute \src "ls180.v:4935.205-4935.278" + cell $xor $xor$ls180.v:4935$750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:4935$750_Y + end + attribute \src "ls180.v:4935.164-4935.279" + cell $xor $xor$ls180.v:4935$751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg13 [2] + connect \B $xor$ls180.v:4935$750_Y + connect \Y $xor$ls180.v:4935$751_Y + end + attribute \src "ls180.v:4936.361-4936.434" + cell $xor $xor$ls180.v:4936$752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:4936$752_Y + end + attribute \src "ls180.v:4936.205-4936.278" + cell $xor $xor$ls180.v:4936$753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:4936$753_Y + end + attribute \src "ls180.v:4936.164-4936.279" + cell $xor $xor$ls180.v:4936$754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg14 [2] + connect \B $xor$ls180.v:4936$753_Y + connect \Y $xor$ls180.v:4936$754_Y + end + attribute \src "ls180.v:4937.361-4937.434" + cell $xor $xor$ls180.v:4937$755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:4937$755_Y + end + attribute \src "ls180.v:4937.205-4937.278" + cell $xor $xor$ls180.v:4937$756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:4937$756_Y + end + attribute \src "ls180.v:4937.164-4937.279" + cell $xor $xor$ls180.v:4937$757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg15 [2] + connect \B $xor$ls180.v:4937$756_Y + connect \Y $xor$ls180.v:4937$757_Y + end + attribute \src "ls180.v:4938.361-4938.434" + cell $xor $xor$ls180.v:4938$758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:4938$758_Y + end + attribute \src "ls180.v:4938.205-4938.278" + cell $xor $xor$ls180.v:4938$759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:4938$759_Y + end + attribute \src "ls180.v:4938.164-4938.279" + cell $xor $xor$ls180.v:4938$760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg16 [2] + connect \B $xor$ls180.v:4938$759_Y + connect \Y $xor$ls180.v:4938$760_Y + end + attribute \src "ls180.v:4939.361-4939.434" + cell $xor $xor$ls180.v:4939$761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:4939$761_Y + end + attribute \src "ls180.v:4939.205-4939.278" + cell $xor $xor$ls180.v:4939$762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:4939$762_Y + end + attribute \src "ls180.v:4939.164-4939.279" + cell $xor $xor$ls180.v:4939$763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg17 [2] + connect \B $xor$ls180.v:4939$762_Y + connect \Y $xor$ls180.v:4939$763_Y + end + attribute \src "ls180.v:4940.361-4940.434" + cell $xor $xor$ls180.v:4940$764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:4940$764_Y + end + attribute \src "ls180.v:4940.205-4940.278" + cell $xor $xor$ls180.v:4940$765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:4940$765_Y + end + attribute \src "ls180.v:4940.164-4940.279" + cell $xor $xor$ls180.v:4940$766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg18 [2] + connect \B $xor$ls180.v:4940$765_Y + connect \Y $xor$ls180.v:4940$766_Y + end + attribute \src "ls180.v:4941.361-4941.434" + cell $xor $xor$ls180.v:4941$767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:4941$767_Y + end + attribute \src "ls180.v:4941.205-4941.278" + cell $xor $xor$ls180.v:4941$768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:4941$768_Y + end + attribute \src "ls180.v:4941.164-4941.279" + cell $xor $xor$ls180.v:4941$769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg19 [2] + connect \B $xor$ls180.v:4941$768_Y + connect \Y $xor$ls180.v:4941$769_Y + end + attribute \src "ls180.v:4942.361-4942.434" + cell $xor $xor$ls180.v:4942$770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:4942$770_Y + end + attribute \src "ls180.v:4942.205-4942.278" + cell $xor $xor$ls180.v:4942$771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:4942$771_Y + end + attribute \src "ls180.v:4942.164-4942.279" + cell $xor $xor$ls180.v:4942$772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg20 [2] + connect \B $xor$ls180.v:4942$771_Y + connect \Y $xor$ls180.v:4942$772_Y + end + attribute \src "ls180.v:4943.361-4943.434" + cell $xor $xor$ls180.v:4943$773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:4943$773_Y + end + attribute \src "ls180.v:4943.205-4943.278" + cell $xor $xor$ls180.v:4943$774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:4943$774_Y + end + attribute \src "ls180.v:4943.164-4943.279" + cell $xor $xor$ls180.v:4943$775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg21 [2] + connect \B $xor$ls180.v:4943$774_Y + connect \Y $xor$ls180.v:4943$775_Y + end + attribute \src "ls180.v:4944.361-4944.434" + cell $xor $xor$ls180.v:4944$776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:4944$776_Y + end + attribute \src "ls180.v:4944.205-4944.278" + cell $xor $xor$ls180.v:4944$777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:4944$777_Y + end + attribute \src "ls180.v:4944.164-4944.279" + cell $xor $xor$ls180.v:4944$778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg22 [2] + connect \B $xor$ls180.v:4944$777_Y + connect \Y $xor$ls180.v:4944$778_Y + end + attribute \src "ls180.v:4945.361-4945.434" + cell $xor $xor$ls180.v:4945$779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:4945$779_Y + end + attribute \src "ls180.v:4945.205-4945.278" + cell $xor $xor$ls180.v:4945$780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:4945$780_Y + end + attribute \src "ls180.v:4945.164-4945.279" + cell $xor $xor$ls180.v:4945$781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg23 [2] + connect \B $xor$ls180.v:4945$780_Y + connect \Y $xor$ls180.v:4945$781_Y + end + attribute \src "ls180.v:4946.361-4946.434" + cell $xor $xor$ls180.v:4946$782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:4946$782_Y + end + attribute \src "ls180.v:4946.205-4946.278" + cell $xor $xor$ls180.v:4946$783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:4946$783_Y + end + attribute \src "ls180.v:4946.164-4946.279" + cell $xor $xor$ls180.v:4946$784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg24 [2] + connect \B $xor$ls180.v:4946$783_Y + connect \Y $xor$ls180.v:4946$784_Y + end + attribute \src "ls180.v:4947.361-4947.434" + cell $xor $xor$ls180.v:4947$785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:4947$785_Y + end + attribute \src "ls180.v:4947.205-4947.278" + cell $xor $xor$ls180.v:4947$786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:4947$786_Y + end + attribute \src "ls180.v:4947.164-4947.279" + cell $xor $xor$ls180.v:4947$787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg25 [2] + connect \B $xor$ls180.v:4947$786_Y + connect \Y $xor$ls180.v:4947$787_Y + end + attribute \src "ls180.v:4948.361-4948.434" + cell $xor $xor$ls180.v:4948$788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:4948$788_Y + end + attribute \src "ls180.v:4948.205-4948.278" + cell $xor $xor$ls180.v:4948$789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:4948$789_Y + end + attribute \src "ls180.v:4948.164-4948.279" + cell $xor $xor$ls180.v:4948$790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg26 [2] + connect \B $xor$ls180.v:4948$789_Y + connect \Y $xor$ls180.v:4948$790_Y + end + attribute \src "ls180.v:4949.361-4949.434" + cell $xor $xor$ls180.v:4949$791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:4949$791_Y + end + attribute \src "ls180.v:4949.205-4949.278" + cell $xor $xor$ls180.v:4949$792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:4949$792_Y + end + attribute \src "ls180.v:4949.164-4949.279" + cell $xor $xor$ls180.v:4949$793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg27 [2] + connect \B $xor$ls180.v:4949$792_Y + connect \Y $xor$ls180.v:4949$793_Y + end + attribute \src "ls180.v:4950.361-4950.434" + cell $xor $xor$ls180.v:4950$794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:4950$794_Y + end + attribute \src "ls180.v:4950.205-4950.278" + cell $xor $xor$ls180.v:4950$795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:4950$795_Y + end + attribute \src "ls180.v:4950.164-4950.279" + cell $xor $xor$ls180.v:4950$796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg28 [2] + connect \B $xor$ls180.v:4950$795_Y + connect \Y $xor$ls180.v:4950$796_Y + end + attribute \src "ls180.v:4951.361-4951.434" + cell $xor $xor$ls180.v:4951$797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:4951$797_Y + end + attribute \src "ls180.v:4951.205-4951.278" + cell $xor $xor$ls180.v:4951$798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:4951$798_Y + end + attribute \src "ls180.v:4951.164-4951.279" + cell $xor $xor$ls180.v:4951$799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg29 [2] + connect \B $xor$ls180.v:4951$798_Y + connect \Y $xor$ls180.v:4951$799_Y + end + attribute \src "ls180.v:4952.360-4952.432" + cell $xor $xor$ls180.v:4952$800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:4952$800_Y + end + attribute \src "ls180.v:4952.205-4952.277" + cell $xor $xor$ls180.v:4952$801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:4952$801_Y + end + attribute \src "ls180.v:4952.164-4952.278" + cell $xor $xor$ls180.v:4952$802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg30 [2] + connect \B $xor$ls180.v:4952$801_Y + connect \Y $xor$ls180.v:4952$802_Y + end + attribute \src "ls180.v:4953.360-4953.432" + cell $xor $xor$ls180.v:4953$803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:4953$803_Y + end + attribute \src "ls180.v:4953.205-4953.277" + cell $xor $xor$ls180.v:4953$804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:4953$804_Y + end + attribute \src "ls180.v:4953.164-4953.278" + cell $xor $xor$ls180.v:4953$805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg31 [2] + connect \B $xor$ls180.v:4953$804_Y + connect \Y $xor$ls180.v:4953$805_Y + end + attribute \src "ls180.v:4954.360-4954.432" + cell $xor $xor$ls180.v:4954$806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:4954$806_Y + end + attribute \src "ls180.v:4954.205-4954.277" + cell $xor $xor$ls180.v:4954$807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:4954$807_Y + end + attribute \src "ls180.v:4954.164-4954.278" + cell $xor $xor$ls180.v:4954$808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg32 [2] + connect \B $xor$ls180.v:4954$807_Y + connect \Y $xor$ls180.v:4954$808_Y + end + attribute \src "ls180.v:4955.360-4955.432" + cell $xor $xor$ls180.v:4955$809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:4955$809_Y + end + attribute \src "ls180.v:4955.205-4955.277" + cell $xor $xor$ls180.v:4955$810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:4955$810_Y + end + attribute \src "ls180.v:4955.164-4955.278" + cell $xor $xor$ls180.v:4955$811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg33 [2] + connect \B $xor$ls180.v:4955$810_Y + connect \Y $xor$ls180.v:4955$811_Y + end + attribute \src "ls180.v:4956.360-4956.432" + cell $xor $xor$ls180.v:4956$812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:4956$812_Y + end + attribute \src "ls180.v:4956.205-4956.277" + cell $xor $xor$ls180.v:4956$813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:4956$813_Y + end + attribute \src "ls180.v:4956.164-4956.278" + cell $xor $xor$ls180.v:4956$814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg34 [2] + connect \B $xor$ls180.v:4956$813_Y + connect \Y $xor$ls180.v:4956$814_Y + end + attribute \src "ls180.v:4957.360-4957.432" + cell $xor $xor$ls180.v:4957$815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:4957$815_Y + end + attribute \src "ls180.v:4957.205-4957.277" + cell $xor $xor$ls180.v:4957$816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:4957$816_Y + end + attribute \src "ls180.v:4957.164-4957.278" + cell $xor $xor$ls180.v:4957$817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg35 [2] + connect \B $xor$ls180.v:4957$816_Y + connect \Y $xor$ls180.v:4957$817_Y + end + attribute \src "ls180.v:4958.360-4958.432" + cell $xor $xor$ls180.v:4958$818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:4958$818_Y + end + attribute \src "ls180.v:4958.205-4958.277" + cell $xor $xor$ls180.v:4958$819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:4958$819_Y + end + attribute \src "ls180.v:4958.164-4958.278" + cell $xor $xor$ls180.v:4958$820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg36 [2] + connect \B $xor$ls180.v:4958$819_Y + connect \Y $xor$ls180.v:4958$820_Y + end + attribute \src "ls180.v:4959.360-4959.432" + cell $xor $xor$ls180.v:4959$821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:4959$821_Y + end + attribute \src "ls180.v:4959.205-4959.277" + cell $xor $xor$ls180.v:4959$822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:4959$822_Y + end + attribute \src "ls180.v:4959.164-4959.278" + cell $xor $xor$ls180.v:4959$823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg37 [2] + connect \B $xor$ls180.v:4959$822_Y + connect \Y $xor$ls180.v:4959$823_Y + end + attribute \src "ls180.v:4960.360-4960.432" + cell $xor $xor$ls180.v:4960$824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:4960$824_Y + end + attribute \src "ls180.v:4960.205-4960.277" + cell $xor $xor$ls180.v:4960$825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:4960$825_Y + end + attribute \src "ls180.v:4960.164-4960.278" + cell $xor $xor$ls180.v:4960$826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg38 [2] + connect \B $xor$ls180.v:4960$825_Y + connect \Y $xor$ls180.v:4960$826_Y + end + attribute \src "ls180.v:4961.360-4961.432" + cell $xor $xor$ls180.v:4961$827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:4961$827_Y + end + attribute \src "ls180.v:4961.205-4961.277" + cell $xor $xor$ls180.v:4961$828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:4961$828_Y + end + attribute \src "ls180.v:4961.164-4961.278" + cell $xor $xor$ls180.v:4961$829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg39 [2] + connect \B $xor$ls180.v:4961$828_Y + connect \Y $xor$ls180.v:4961$829_Y + end + attribute \src "ls180.v:4982.899-4982.983" + cell $xor $xor$ls180.v:4982$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4982$843_Y + end + attribute \src "ls180.v:4982.634-4982.718" + cell $xor $xor$ls180.v:4982$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4982$844_Y + end + attribute \src "ls180.v:4982.588-4982.719" + cell $xor $xor$ls180.v:4982$845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] + connect \B $xor$ls180.v:4982$844_Y + connect \Y $xor$ls180.v:4982$845_Y + end + attribute \src "ls180.v:4982.234-4982.318" + cell $xor $xor$ls180.v:4982$846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4982$846_Y + end + attribute \src "ls180.v:4982.187-4982.319" + cell $xor $xor$ls180.v:4982$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] + connect \B $xor$ls180.v:4982$846_Y + connect \Y $xor$ls180.v:4982$847_Y + end + attribute \src "ls180.v:4983.899-4983.983" + cell $xor $xor$ls180.v:4983$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4983$848_Y + end + attribute \src "ls180.v:4983.634-4983.718" + cell $xor $xor$ls180.v:4983$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4983$849_Y + end + attribute \src "ls180.v:4983.588-4983.719" + cell $xor $xor$ls180.v:4983$850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] + connect \B $xor$ls180.v:4983$849_Y + connect \Y $xor$ls180.v:4983$850_Y + end + attribute \src "ls180.v:4983.234-4983.318" + cell $xor $xor$ls180.v:4983$851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4983$851_Y + end + attribute \src "ls180.v:4983.187-4983.319" + cell $xor $xor$ls180.v:4983$852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] + connect \B $xor$ls180.v:4983$851_Y + connect \Y $xor$ls180.v:4983$852_Y + end + attribute \src "ls180.v:4992.899-4992.983" + cell $xor $xor$ls180.v:4992$854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4992$854_Y + end + attribute \src "ls180.v:4992.634-4992.718" + cell $xor $xor$ls180.v:4992$855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4992$855_Y + end + attribute \src "ls180.v:4992.588-4992.719" + cell $xor $xor$ls180.v:4992$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] + connect \B $xor$ls180.v:4992$855_Y + connect \Y $xor$ls180.v:4992$856_Y + end + attribute \src "ls180.v:4992.234-4992.318" + cell $xor $xor$ls180.v:4992$857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4992$857_Y + end + attribute \src "ls180.v:4992.187-4992.319" + cell $xor $xor$ls180.v:4992$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] + connect \B $xor$ls180.v:4992$857_Y + connect \Y $xor$ls180.v:4992$858_Y + end + attribute \src "ls180.v:4993.899-4993.983" + cell $xor $xor$ls180.v:4993$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4993$859_Y + end + attribute \src "ls180.v:4993.634-4993.718" + cell $xor $xor$ls180.v:4993$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4993$860_Y + end + attribute \src "ls180.v:4993.588-4993.719" + cell $xor $xor$ls180.v:4993$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] + connect \B $xor$ls180.v:4993$860_Y + connect \Y $xor$ls180.v:4993$861_Y + end + attribute \src "ls180.v:4993.234-4993.318" + cell $xor $xor$ls180.v:4993$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4993$862_Y + end + attribute \src "ls180.v:4993.187-4993.319" + cell $xor $xor$ls180.v:4993$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] + connect \B $xor$ls180.v:4993$862_Y + connect \Y $xor$ls180.v:4993$863_Y + end + attribute \src "ls180.v:5002.899-5002.983" + cell $xor $xor$ls180.v:5002$865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5002$865_Y + end + attribute \src "ls180.v:5002.634-5002.718" + cell $xor $xor$ls180.v:5002$866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5002$866_Y + end + attribute \src "ls180.v:5002.588-5002.719" + cell $xor $xor$ls180.v:5002$867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5002$866_Y + connect \Y $xor$ls180.v:5002$867_Y + end + attribute \src "ls180.v:5002.234-5002.318" + cell $xor $xor$ls180.v:5002$868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5002$868_Y + end + attribute \src "ls180.v:5002.187-5002.319" + cell $xor $xor$ls180.v:5002$869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5002$868_Y + connect \Y $xor$ls180.v:5002$869_Y + end + attribute \src "ls180.v:5003.899-5003.983" + cell $xor $xor$ls180.v:5003$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5003$870_Y + end + attribute \src "ls180.v:5003.634-5003.718" + cell $xor $xor$ls180.v:5003$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5003$871_Y + end + attribute \src "ls180.v:5003.588-5003.719" + cell $xor $xor$ls180.v:5003$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5003$871_Y + connect \Y $xor$ls180.v:5003$872_Y + end + attribute \src "ls180.v:5003.234-5003.318" + cell $xor $xor$ls180.v:5003$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5003$873_Y + end + attribute \src "ls180.v:5003.187-5003.319" + cell $xor $xor$ls180.v:5003$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5003$873_Y + connect \Y $xor$ls180.v:5003$874_Y + end + attribute \src "ls180.v:5012.899-5012.983" + cell $xor $xor$ls180.v:5012$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5012$876_Y + end + attribute \src "ls180.v:5012.634-5012.718" + cell $xor $xor$ls180.v:5012$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5012$877_Y + end + attribute \src "ls180.v:5012.588-5012.719" + cell $xor $xor$ls180.v:5012$878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5012$877_Y + connect \Y $xor$ls180.v:5012$878_Y + end + attribute \src "ls180.v:5012.234-5012.318" + cell $xor $xor$ls180.v:5012$879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5012$879_Y + end + attribute \src "ls180.v:5012.187-5012.319" + cell $xor $xor$ls180.v:5012$880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5012$879_Y + connect \Y $xor$ls180.v:5012$880_Y + end + attribute \src "ls180.v:5013.899-5013.983" + cell $xor $xor$ls180.v:5013$881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5013$881_Y + end + attribute \src "ls180.v:5013.634-5013.718" + cell $xor $xor$ls180.v:5013$882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5013$882_Y + end + attribute \src "ls180.v:5013.588-5013.719" + cell $xor $xor$ls180.v:5013$883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5013$882_Y + connect \Y $xor$ls180.v:5013$883_Y + end + attribute \src "ls180.v:5013.234-5013.318" + cell $xor $xor$ls180.v:5013$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5013$884_Y + end + attribute \src "ls180.v:5013.187-5013.319" + cell $xor $xor$ls180.v:5013$885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5013$884_Y + connect \Y $xor$ls180.v:5013$885_Y + end + attribute \src "ls180.v:5164.879-5164.961" + cell $xor $xor$ls180.v:5164$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5164$918_Y + end + attribute \src "ls180.v:5164.620-5164.702" + cell $xor $xor$ls180.v:5164$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5164$919_Y + end + attribute \src "ls180.v:5164.575-5164.703" + cell $xor $xor$ls180.v:5164$920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] + connect \B $xor$ls180.v:5164$919_Y + connect \Y $xor$ls180.v:5164$920_Y + end + attribute \src "ls180.v:5164.229-5164.311" + cell $xor $xor$ls180.v:5164$921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5164$921_Y + end + attribute \src "ls180.v:5164.183-5164.312" + cell $xor $xor$ls180.v:5164$922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] + connect \B $xor$ls180.v:5164$921_Y + connect \Y $xor$ls180.v:5164$922_Y + end + attribute \src "ls180.v:5165.879-5165.961" + cell $xor $xor$ls180.v:5165$923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5165$923_Y + end + attribute \src "ls180.v:5165.620-5165.702" + cell $xor $xor$ls180.v:5165$924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5165$924_Y + end + attribute \src "ls180.v:5165.575-5165.703" + cell $xor $xor$ls180.v:5165$925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5165$924_Y + connect \Y $xor$ls180.v:5165$925_Y + end + attribute \src "ls180.v:5165.229-5165.311" + cell $xor $xor$ls180.v:5165$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5165$926_Y + end + attribute \src "ls180.v:5165.183-5165.312" + cell $xor $xor$ls180.v:5165$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5165$926_Y + connect \Y $xor$ls180.v:5165$927_Y + end + attribute \src "ls180.v:5174.879-5174.961" + cell $xor $xor$ls180.v:5174$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5174$929_Y + end + attribute \src "ls180.v:5174.620-5174.702" + cell $xor $xor$ls180.v:5174$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5174$930_Y + end + attribute \src "ls180.v:5174.575-5174.703" + cell $xor $xor$ls180.v:5174$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] + connect \B $xor$ls180.v:5174$930_Y + connect \Y $xor$ls180.v:5174$931_Y + end + attribute \src "ls180.v:5174.229-5174.311" + cell $xor $xor$ls180.v:5174$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5174$932_Y + end + attribute \src "ls180.v:5174.183-5174.312" + cell $xor $xor$ls180.v:5174$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] + connect \B $xor$ls180.v:5174$932_Y + connect \Y $xor$ls180.v:5174$933_Y + end + attribute \src "ls180.v:5175.879-5175.961" + cell $xor $xor$ls180.v:5175$934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5175$934_Y + end + attribute \src "ls180.v:5175.620-5175.702" + cell $xor $xor$ls180.v:5175$935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5175$935_Y + end + attribute \src "ls180.v:5175.575-5175.703" + cell $xor $xor$ls180.v:5175$936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] + connect \B $xor$ls180.v:5175$935_Y + connect \Y $xor$ls180.v:5175$936_Y + end + attribute \src "ls180.v:5175.229-5175.311" + cell $xor $xor$ls180.v:5175$937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5175$937_Y + end + attribute \src "ls180.v:5175.183-5175.312" + cell $xor $xor$ls180.v:5175$938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] + connect \B $xor$ls180.v:5175$937_Y + connect \Y $xor$ls180.v:5175$938_Y + end + attribute \src "ls180.v:5184.879-5184.961" + cell $xor $xor$ls180.v:5184$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5184$940_Y + end + attribute \src "ls180.v:5184.620-5184.702" + cell $xor $xor$ls180.v:5184$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5184$941_Y + end + attribute \src "ls180.v:5184.575-5184.703" + cell $xor $xor$ls180.v:5184$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5184$941_Y + connect \Y $xor$ls180.v:5184$942_Y + end + attribute \src "ls180.v:5184.229-5184.311" + cell $xor $xor$ls180.v:5184$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5184$943_Y + end + attribute \src "ls180.v:5184.183-5184.312" + cell $xor $xor$ls180.v:5184$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5184$943_Y + connect \Y $xor$ls180.v:5184$944_Y + end + attribute \src "ls180.v:5185.879-5185.961" + cell $xor $xor$ls180.v:5185$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5185$945_Y + end + attribute \src "ls180.v:5185.620-5185.702" + cell $xor $xor$ls180.v:5185$946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5185$946_Y + end + attribute \src "ls180.v:5185.575-5185.703" + cell $xor $xor$ls180.v:5185$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5185$946_Y + connect \Y $xor$ls180.v:5185$947_Y + end + attribute \src "ls180.v:5185.229-5185.311" + cell $xor $xor$ls180.v:5185$948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5185$948_Y + end + attribute \src "ls180.v:5185.183-5185.312" + cell $xor $xor$ls180.v:5185$949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5185$948_Y + connect \Y $xor$ls180.v:5185$949_Y + end + attribute \src "ls180.v:5194.879-5194.961" + cell $xor $xor$ls180.v:5194$951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5194$951_Y + end + attribute \src "ls180.v:5194.620-5194.702" + cell $xor $xor$ls180.v:5194$952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5194$952_Y + end + attribute \src "ls180.v:5194.575-5194.703" + cell $xor $xor$ls180.v:5194$953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5194$952_Y + connect \Y $xor$ls180.v:5194$953_Y + end + attribute \src "ls180.v:5194.229-5194.311" + cell $xor $xor$ls180.v:5194$954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5194$954_Y + end + attribute \src "ls180.v:5194.183-5194.312" + cell $xor $xor$ls180.v:5194$955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5194$954_Y + connect \Y $xor$ls180.v:5194$955_Y + end + attribute \src "ls180.v:5195.879-5195.961" + cell $xor $xor$ls180.v:5195$956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5195$956_Y + end + attribute \src "ls180.v:5195.620-5195.702" + cell $xor $xor$ls180.v:5195$957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5195$957_Y + end + attribute \src "ls180.v:5195.575-5195.703" + cell $xor $xor$ls180.v:5195$958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5195$957_Y + connect \Y $xor$ls180.v:5195$958_Y + end + attribute \src "ls180.v:5195.229-5195.311" + cell $xor $xor$ls180.v:5195$959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5195$959_Y + end + attribute \src "ls180.v:5195.183-5195.312" + cell $xor $xor$ls180.v:5195$960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5195$959_Y + connect \Y $xor$ls180.v:5195$960_Y + end + attribute \module_not_derived 1 + attribute \src "ls180.v:10179.13-10553.2" + cell \test_issuer \test_issuer + connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck + connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi + connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo + connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms + connect \busy_o \main_libresocsim_libresoc0 + connect \clk \sys_clk_1 + connect \clk_sel_i \main_libresocsim_libresoc_clk_sel + connect \core_bigendian_i 1'0 + connect \dbus__ack \main_libresocsim_libresoc_dbus_ack + connect \dbus__adr \main_libresocsim_libresoc_dbus_adr + connect \dbus__bte 1'0 + connect \dbus__cti 1'0 + connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc + connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r + connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w + connect \dbus__err \main_libresocsim_libresoc_dbus_err + connect \dbus__sel \main_libresocsim_libresoc_dbus_sel + connect \dbus__stb \main_libresocsim_libresoc_dbus_stb + connect \dbus__we \main_libresocsim_libresoc_dbus_we + connect \eint_0__core__i \eint [0] + connect \eint_0__pad__i \eint_1 [0] + connect \eint_1__core__i \eint [1] + connect \eint_1__pad__i \eint_1 [1] + connect \eint_2__core__i \eint [2] + connect \eint_2__pad__i \eint_1 [2] + connect \gpio_e10__core__i \gpio_i [10] + connect \gpio_e10__core__o \gpio_o [10] + connect \gpio_e10__core__oe \gpio_oe [10] + connect \gpio_e10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [10] + connect \gpio_e10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [10] + connect \gpio_e10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [10] + connect \gpio_e11__core__i \gpio_i [11] + connect \gpio_e11__core__o \gpio_o [11] + connect \gpio_e11__core__oe \gpio_oe [11] + connect \gpio_e11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [11] + connect \gpio_e11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [11] + connect \gpio_e11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [11] + connect \gpio_e12__core__i \gpio_i [12] + connect \gpio_e12__core__o \gpio_o [12] + connect \gpio_e12__core__oe \gpio_oe [12] + connect \gpio_e12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [12] + connect \gpio_e12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [12] + connect \gpio_e12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [12] + connect \gpio_e13__core__i \gpio_i [13] + connect \gpio_e13__core__o \gpio_o [13] + connect \gpio_e13__core__oe \gpio_oe [13] + connect \gpio_e13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [13] + connect \gpio_e13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [13] + connect \gpio_e13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [13] + connect \gpio_e14__core__i \gpio_i [14] + connect \gpio_e14__core__o \gpio_o [14] + connect \gpio_e14__core__oe \gpio_oe [14] + connect \gpio_e14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [14] + connect \gpio_e14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [14] + connect \gpio_e14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [14] + connect \gpio_e15__core__i \gpio_i [15] + connect \gpio_e15__core__o \gpio_o [15] + connect \gpio_e15__core__oe \gpio_oe [15] + connect \gpio_e15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [15] + connect \gpio_e15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [15] + connect \gpio_e15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [15] + connect \gpio_e8__core__i \gpio_i [8] + connect \gpio_e8__core__o \gpio_o [8] + connect \gpio_e8__core__oe \gpio_oe [8] + connect \gpio_e8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [8] + connect \gpio_e8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [8] + connect \gpio_e8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [8] + connect \gpio_e9__core__i \gpio_i [9] + connect \gpio_e9__core__o \gpio_o [9] + connect \gpio_e9__core__oe \gpio_oe [9] + connect \gpio_e9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [9] + connect \gpio_e9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [9] + connect \gpio_e9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [9] + connect \gpio_s0__core__i \gpio_i [0] + connect \gpio_s0__core__o \gpio_o [0] + connect \gpio_s0__core__oe \gpio_oe [0] + connect \gpio_s0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [0] + connect \gpio_s0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [0] + connect \gpio_s0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [0] + connect \gpio_s1__core__i \gpio_i [1] + connect \gpio_s1__core__o \gpio_o [1] + connect \gpio_s1__core__oe \gpio_oe [1] + connect \gpio_s1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [1] + connect \gpio_s1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [1] + connect \gpio_s1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [1] + connect \gpio_s2__core__i \gpio_i [2] + connect \gpio_s2__core__o \gpio_o [2] + connect \gpio_s2__core__oe \gpio_oe [2] + connect \gpio_s2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [2] + connect \gpio_s2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [2] + connect \gpio_s2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [2] + connect \gpio_s3__core__i \gpio_i [3] + connect \gpio_s3__core__o \gpio_o [3] + connect \gpio_s3__core__oe \gpio_oe [3] + connect \gpio_s3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [3] + connect \gpio_s3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [3] + connect \gpio_s3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [3] + connect \gpio_s4__core__i \gpio_i [4] + connect \gpio_s4__core__o \gpio_o [4] + connect \gpio_s4__core__oe \gpio_oe [4] + connect \gpio_s4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [4] + connect \gpio_s4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [4] + connect \gpio_s4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [4] + connect \gpio_s5__core__i \gpio_i [5] + connect \gpio_s5__core__o \gpio_o [5] + connect \gpio_s5__core__oe \gpio_oe [5] + connect \gpio_s5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [5] + connect \gpio_s5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [5] + connect \gpio_s5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [5] + connect \gpio_s6__core__i \gpio_i [6] + connect \gpio_s6__core__o \gpio_o [6] + connect \gpio_s6__core__oe \gpio_oe [6] + connect \gpio_s6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [6] + connect \gpio_s6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [6] + connect \gpio_s6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [6] + connect \gpio_s7__core__i \gpio_i [7] + connect \gpio_s7__core__o \gpio_o [7] + connect \gpio_s7__core__oe \gpio_oe [7] + connect \gpio_s7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [7] + connect \gpio_s7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [7] + connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7] + connect \ibus__ack \main_libresocsim_libresoc_ibus_ack + connect \ibus__adr \main_libresocsim_libresoc_ibus_adr + connect \ibus__bte 1'0 + connect \ibus__cti 1'0 + connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc + connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r + connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w + connect \ibus__err \main_libresocsim_libresoc_ibus_err + connect \ibus__sel \main_libresocsim_libresoc_ibus_sel + connect \ibus__stb \main_libresocsim_libresoc_ibus_stb + connect \ibus__we \main_libresocsim_libresoc_ibus_we + connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack + connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr + connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc + connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r + connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w + connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err + connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel + connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb + connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we + connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack + connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr + connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc + connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r + connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w + connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err + connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel + connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb + connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we + connect \int_level_i \main_libresocsim_libresoc_interrupt + connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack + connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr + connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc + connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r + connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w + connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err + connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel + connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb + connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we + connect \memerr_o \main_libresocsim_libresoc1 + connect \mspi0_clk__core__o \spimaster_clk + connect \mspi0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + connect \mspi0_cs_n__core__o \spimaster_cs_n + connect \mspi0_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + connect \mspi0_miso__core__i \spimaster_miso + connect \mspi0_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + connect \mspi0_mosi__core__o \spimaster_mosi + connect \mspi0_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + connect \mspi1_clk__core__o \spisdcard_clk + connect \mspi1_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + connect \mspi1_cs_n__core__o \spisdcard_cs_n + connect \mspi1_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + connect \mspi1_miso__core__i \spisdcard_miso + connect \mspi1_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + connect \mspi1_mosi__core__o \spisdcard_mosi + connect \mspi1_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + connect \mtwi_scl__core__o \i2c_scl + connect \mtwi_scl__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + connect \mtwi_sda__core__i \i2c_sda_i + connect \mtwi_sda__core__o \i2c_sda_o + connect \mtwi_sda__core__oe \i2c_sda_oe + connect \mtwi_sda__pad__i \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + connect \mtwi_sda__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + connect \mtwi_sda__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + connect \pc_i 1'0 + connect \pc_i_ok 1'0 + connect \pc_o \main_libresocsim_libresoc2 + connect \pll_18_o \main_libresocsim_libresoc_pll_18_o + connect \pll_lck_o \main_libresocsim_libresoc_pll_lck_o + connect \pwm_0__core__o \pwm [0] + connect \pwm_0__pad__o \pwm_1 [0] + connect \pwm_1__core__o \pwm [1] + connect \pwm_1__pad__o \pwm_1 [1] + connect \rst $or$ls180.v:10279$2750_Y + connect \sd0_clk__core__o \sdcard_clk + connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + connect \sd0_cmd__core__i \sdcard_cmd_i + connect \sd0_cmd__core__o \sdcard_cmd_o + connect \sd0_cmd__core__oe \sdcard_cmd_oe + connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data0__core__i \sdcard_cmd_i + connect \sd0_data0__core__o \sdcard_cmd_o + connect \sd0_data0__core__oe \sdcard_cmd_oe + connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data1__core__i \sdcard_cmd_i + connect \sd0_data1__core__o \sdcard_cmd_o + connect \sd0_data1__core__oe \sdcard_cmd_oe + connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data2__core__i \sdcard_cmd_i + connect \sd0_data2__core__o \sdcard_cmd_o + connect \sd0_data2__core__oe \sdcard_cmd_oe + connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data3__core__i \sdcard_cmd_i + connect \sd0_data3__core__o \sdcard_cmd_o + connect \sd0_data3__core__oe \sdcard_cmd_oe + connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sdr_a_0__core__o \sdram_a [0] + connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] + connect \sdr_a_10__core__o \sdram_a [10] + connect \sdr_a_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [10] + connect \sdr_a_11__core__o \sdram_a [11] + connect \sdr_a_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [11] + connect \sdr_a_12__core__o \sdram_a [12] + connect \sdr_a_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [12] + connect \sdr_a_1__core__o \sdram_a [1] + connect \sdr_a_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [1] + connect \sdr_a_2__core__o \sdram_a [2] + connect \sdr_a_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [2] + connect \sdr_a_3__core__o \sdram_a [3] + connect \sdr_a_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [3] + connect \sdr_a_4__core__o \sdram_a [4] + connect \sdr_a_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [4] + connect \sdr_a_5__core__o \sdram_a [5] + connect \sdr_a_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [5] + connect \sdr_a_6__core__o \sdram_a [6] + connect \sdr_a_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [6] + connect \sdr_a_7__core__o \sdram_a [7] + connect \sdr_a_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [7] + connect \sdr_a_8__core__o \sdram_a [8] + connect \sdr_a_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [8] + connect \sdr_a_9__core__o \sdram_a [9] + connect \sdr_a_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [9] + connect \sdr_ba_0__core__o \sdram_ba [0] + connect \sdr_ba_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [0] + connect \sdr_ba_1__core__o \sdram_ba [1] + connect \sdr_ba_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [1] + connect \sdr_cas_n__core__o \sdram_cas_n + connect \sdr_cas_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + connect \sdr_cke__core__o \sdram_cke + connect \sdr_cke__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + connect \sdr_clock__core__o \sdram_clock + connect \sdr_clock__pad__o \sdram_clock_1 + connect \sdr_cs_n__core__o \sdram_cs_n + connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + connect \sdr_dm_0__core__o \sdram_dm [0] + connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] + connect \sdr_dm_1__core__i \sdram_dq_i [1] + connect \sdr_dm_1__core__o \sdram_dq_o [1] + connect \sdr_dm_1__core__oe \sdram_dq_oe + connect \sdr_dm_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dm_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_0__core__i \sdram_dq_i [0] + connect \sdr_dq_0__core__o \sdram_dq_o [0] + connect \sdr_dq_0__core__oe \sdram_dq_oe + connect \sdr_dq_0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] + connect \sdr_dq_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0] + connect \sdr_dq_0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_10__core__i \sdram_dq_i [10] + connect \sdr_dq_10__core__o \sdram_dq_o [10] + connect \sdr_dq_10__core__oe \sdram_dq_oe + connect \sdr_dq_10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] + connect \sdr_dq_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10] + connect \sdr_dq_10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_11__core__i \sdram_dq_i [11] + connect \sdr_dq_11__core__o \sdram_dq_o [11] + connect \sdr_dq_11__core__oe \sdram_dq_oe + connect \sdr_dq_11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] + connect \sdr_dq_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11] + connect \sdr_dq_11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_12__core__i \sdram_dq_i [12] + connect \sdr_dq_12__core__o \sdram_dq_o [12] + connect \sdr_dq_12__core__oe \sdram_dq_oe + connect \sdr_dq_12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] + connect \sdr_dq_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12] + connect \sdr_dq_12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_13__core__i \sdram_dq_i [13] + connect \sdr_dq_13__core__o \sdram_dq_o [13] + connect \sdr_dq_13__core__oe \sdram_dq_oe + connect \sdr_dq_13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] + connect \sdr_dq_13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13] + connect \sdr_dq_13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_14__core__i \sdram_dq_i [14] + connect \sdr_dq_14__core__o \sdram_dq_o [14] + connect \sdr_dq_14__core__oe \sdram_dq_oe + connect \sdr_dq_14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] + connect \sdr_dq_14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14] + connect \sdr_dq_14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_15__core__i \sdram_dq_i [15] + connect \sdr_dq_15__core__o \sdram_dq_o [15] + connect \sdr_dq_15__core__oe \sdram_dq_oe + connect \sdr_dq_15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] + connect \sdr_dq_15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15] + connect \sdr_dq_15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_1__core__i \sdram_dq_i [1] + connect \sdr_dq_1__core__o \sdram_dq_o [1] + connect \sdr_dq_1__core__oe \sdram_dq_oe + connect \sdr_dq_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dq_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dq_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_2__core__i \sdram_dq_i [2] + connect \sdr_dq_2__core__o \sdram_dq_o [2] + connect \sdr_dq_2__core__oe \sdram_dq_oe + connect \sdr_dq_2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] + connect \sdr_dq_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2] + connect \sdr_dq_2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_3__core__i \sdram_dq_i [3] + connect \sdr_dq_3__core__o \sdram_dq_o [3] + connect \sdr_dq_3__core__oe \sdram_dq_oe + connect \sdr_dq_3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] + connect \sdr_dq_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3] + connect \sdr_dq_3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_4__core__i \sdram_dq_i [4] + connect \sdr_dq_4__core__o \sdram_dq_o [4] + connect \sdr_dq_4__core__oe \sdram_dq_oe + connect \sdr_dq_4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] + connect \sdr_dq_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4] + connect \sdr_dq_4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_5__core__i \sdram_dq_i [5] + connect \sdr_dq_5__core__o \sdram_dq_o [5] + connect \sdr_dq_5__core__oe \sdram_dq_oe + connect \sdr_dq_5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] + connect \sdr_dq_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5] + connect \sdr_dq_5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_6__core__i \sdram_dq_i [6] + connect \sdr_dq_6__core__o \sdram_dq_o [6] + connect \sdr_dq_6__core__oe \sdram_dq_oe + connect \sdr_dq_6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] + connect \sdr_dq_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6] + connect \sdr_dq_6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_7__core__i \sdram_dq_i [7] + connect \sdr_dq_7__core__o \sdram_dq_o [7] + connect \sdr_dq_7__core__oe \sdram_dq_oe + connect \sdr_dq_7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] + connect \sdr_dq_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7] + connect \sdr_dq_7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_8__core__i \sdram_dq_i [8] + connect \sdr_dq_8__core__o \sdram_dq_o [8] + connect \sdr_dq_8__core__oe \sdram_dq_oe + connect \sdr_dq_8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] + connect \sdr_dq_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8] + connect \sdr_dq_8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_9__core__i \sdram_dq_i [9] + connect \sdr_dq_9__core__o \sdram_dq_o [9] + connect \sdr_dq_9__core__oe \sdram_dq_oe + connect \sdr_dq_9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] + connect \sdr_dq_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9] + connect \sdr_dq_9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_ras_n__core__o \sdram_ras_n + connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + connect \sdr_we_n__core__o \sdram_we_n + connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$3701 + sync always + sync init + end + attribute \src "ls180.v:1000.5-1000.31" + process $proc$ls180.v:1000$3130 + assign { } { } + assign $1\main_spimaster12_re[0:0] 1'0 + sync always + sync init + update \main_spimaster12_re $1\main_spimaster12_re[0:0] + end + attribute \src "ls180.v:1004.11-1004.42" + process $proc$ls180.v:1004$3131 + assign { } { } + assign $1\main_spimaster16_storage[7:0] 8'00000000 + sync always + sync init + update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] + end + attribute \src "ls180.v:10043.1-10053.4" + process $proc$ls180.v:10043$2680 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 0 + assign $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 0 + assign $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 0 + assign $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 0 + assign $0\memadr[6:0] \main_libresocsim_adr + attribute \src "ls180.v:10044.2-10045.65" + switch \main_libresocsim_we [0] + attribute \src "ls180.v:10044.6-10044.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 255 + case + end + attribute \src "ls180.v:10046.2-10047.67" + switch \main_libresocsim_we [1] + attribute \src "ls180.v:10046.6-10046.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 65280 + case + end + attribute \src "ls180.v:10048.2-10049.69" + switch \main_libresocsim_we [2] + attribute \src "ls180.v:10048.6-10048.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 16711680 + case + end + attribute \src "ls180.v:10050.2-10051.69" + switch \main_libresocsim_we [3] + attribute \src "ls180.v:10050.6-10050.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 32'11111111000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[6:0] + update $memwr$\mem$ls180.v:10045$1_ADDR $0$memwr$\mem$ls180.v:10045$1_ADDR[6:0]$2681 + update $memwr$\mem$ls180.v:10045$1_DATA $0$memwr$\mem$ls180.v:10045$1_DATA[31:0]$2682 + update $memwr$\mem$ls180.v:10045$1_EN $0$memwr$\mem$ls180.v:10045$1_EN[31:0]$2683 + update $memwr$\mem$ls180.v:10047$2_ADDR $0$memwr$\mem$ls180.v:10047$2_ADDR[6:0]$2684 + update $memwr$\mem$ls180.v:10047$2_DATA $0$memwr$\mem$ls180.v:10047$2_DATA[31:0]$2685 + update $memwr$\mem$ls180.v:10047$2_EN $0$memwr$\mem$ls180.v:10047$2_EN[31:0]$2686 + update $memwr$\mem$ls180.v:10049$3_ADDR $0$memwr$\mem$ls180.v:10049$3_ADDR[6:0]$2687 + update $memwr$\mem$ls180.v:10049$3_DATA $0$memwr$\mem$ls180.v:10049$3_DATA[31:0]$2688 + update $memwr$\mem$ls180.v:10049$3_EN $0$memwr$\mem$ls180.v:10049$3_EN[31:0]$2689 + update $memwr$\mem$ls180.v:10051$4_ADDR $0$memwr$\mem$ls180.v:10051$4_ADDR[6:0]$2690 + update $memwr$\mem$ls180.v:10051$4_DATA $0$memwr$\mem$ls180.v:10051$4_DATA[31:0]$2691 + update $memwr$\mem$ls180.v:10051$4_EN $0$memwr$\mem$ls180.v:10051$4_EN[31:0]$2692 + end + attribute \src "ls180.v:1005.5-1005.31" + process $proc$ls180.v:1005$3132 + assign { } { } + assign $1\main_spimaster17_re[0:0] 1'0 + sync always + sync init + update \main_spimaster17_re $1\main_spimaster17_re[0:0] + end + attribute \src "ls180.v:10063.1-10067.4" + process $proc$ls180.v:10063$2694 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 3'xxx + assign $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10066$2698_DATA + attribute \src "ls180.v:10064.2-10065.129" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10064.6-10064.60" + case 1'1 + assign $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:10065$5_ADDR $0$memwr$\storage$ls180.v:10065$5_ADDR[2:0]$2695 + update $memwr$\storage$ls180.v:10065$5_DATA $0$memwr$\storage$ls180.v:10065$5_DATA[24:0]$2696 + update $memwr$\storage$ls180.v:10065$5_EN $0$memwr$\storage$ls180.v:10065$5_EN[24:0]$2697 + end + attribute \src "ls180.v:10069.1-10070.4" + process $proc$ls180.v:10069$2699 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10077.1-10081.4" + process $proc$ls180.v:10077$2701 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 3'xxx + assign $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10080$2705_DATA + attribute \src "ls180.v:10078.2-10079.131" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10078.6-10078.60" + case 1'1 + assign $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[24:0] + update $memwr$\storage_1$ls180.v:10079$6_ADDR $0$memwr$\storage_1$ls180.v:10079$6_ADDR[2:0]$2702 + update $memwr$\storage_1$ls180.v:10079$6_DATA $0$memwr$\storage_1$ls180.v:10079$6_DATA[24:0]$2703 + update $memwr$\storage_1$ls180.v:10079$6_EN $0$memwr$\storage_1$ls180.v:10079$6_EN[24:0]$2704 + end + attribute \src "ls180.v:10083.1-10084.4" + process $proc$ls180.v:10083$2706 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1009.5-1009.36" + process $proc$ls180.v:1009$3133 + assign { } { } + assign $1\main_spimaster21_storage[0:0] 1'1 + sync always + sync init + update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] + end + attribute \src "ls180.v:10091.1-10095.4" + process $proc$ls180.v:10091$2708 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 3'xxx + assign $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10094$2712_DATA + attribute \src "ls180.v:10092.2-10093.131" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10092.6-10092.60" + case 1'1 + assign $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_2 $0\memdat_2[24:0] + update $memwr$\storage_2$ls180.v:10093$7_ADDR $0$memwr$\storage_2$ls180.v:10093$7_ADDR[2:0]$2709 + update $memwr$\storage_2$ls180.v:10093$7_DATA $0$memwr$\storage_2$ls180.v:10093$7_DATA[24:0]$2710 + update $memwr$\storage_2$ls180.v:10093$7_EN $0$memwr$\storage_2$ls180.v:10093$7_EN[24:0]$2711 + end + attribute \src "ls180.v:10097.1-10098.4" + process $proc$ls180.v:10097$2713 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1010.5-1010.31" + process $proc$ls180.v:1010$3134 + assign { } { } + assign $1\main_spimaster22_re[0:0] 1'0 + sync always + sync init + update \main_spimaster22_re $1\main_spimaster22_re[0:0] + end + attribute \src "ls180.v:10105.1-10109.4" + process $proc$ls180.v:10105$2715 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 3'xxx + assign $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10108$2719_DATA + attribute \src "ls180.v:10106.2-10107.131" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10106.6-10106.60" + case 1'1 + assign $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_3 $0\memdat_3[24:0] + update $memwr$\storage_3$ls180.v:10107$8_ADDR $0$memwr$\storage_3$ls180.v:10107$8_ADDR[2:0]$2716 + update $memwr$\storage_3$ls180.v:10107$8_DATA $0$memwr$\storage_3$ls180.v:10107$8_DATA[24:0]$2717 + update $memwr$\storage_3$ls180.v:10107$8_EN $0$memwr$\storage_3$ls180.v:10107$8_EN[24:0]$2718 + end + attribute \src "ls180.v:1011.5-1011.36" + process $proc$ls180.v:1011$3135 + assign { } { } + assign $1\main_spimaster23_storage[0:0] 1'0 + sync always + sync init + update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] + end + attribute \src "ls180.v:10111.1-10112.4" + process $proc$ls180.v:10111$2720 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1012.5-1012.31" + process $proc$ls180.v:1012$3136 + assign { } { } + assign $1\main_spimaster24_re[0:0] 1'0 + sync always + sync init + update \main_spimaster24_re $1\main_spimaster24_re[0:0] + end + attribute \src "ls180.v:10120.1-10124.4" + process $proc$ls180.v:10120$2722 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10123$2726_DATA + attribute \src "ls180.v:10121.2-10122.77" + switch \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:10121.6-10121.33" + case 1'1 + assign $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_4 $0\memdat_4[9:0] + update $memwr$\storage_4$ls180.v:10122$9_ADDR $0$memwr$\storage_4$ls180.v:10122$9_ADDR[3:0]$2723 + update $memwr$\storage_4$ls180.v:10122$9_DATA $0$memwr$\storage_4$ls180.v:10122$9_DATA[9:0]$2724 + update $memwr$\storage_4$ls180.v:10122$9_EN $0$memwr$\storage_4$ls180.v:10122$9_EN[9:0]$2725 + end + attribute \src "ls180.v:10126.1-10129.4" + process $proc$ls180.v:10126$2727 + assign $0\memdat_5[9:0] \memdat_5 + attribute \src "ls180.v:10127.2-10128.55" + switch \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:10127.6-10127.33" + case 1'1 + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10128$2728_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_5 $0\memdat_5[9:0] + end + attribute \src "ls180.v:1013.5-1013.39" + process $proc$ls180.v:1013$3137 + assign { } { } + assign $1\main_spimaster25_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] + end + attribute \src "ls180.v:10137.1-10141.4" + process $proc$ls180.v:10137$2729 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10140$2733_DATA + attribute \src "ls180.v:10138.2-10139.77" + switch \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:10138.6-10138.33" + case 1'1 + assign $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_6 $0\memdat_6[9:0] + update $memwr$\storage_5$ls180.v:10139$10_ADDR $0$memwr$\storage_5$ls180.v:10139$10_ADDR[3:0]$2730 + update $memwr$\storage_5$ls180.v:10139$10_DATA $0$memwr$\storage_5$ls180.v:10139$10_DATA[9:0]$2731 + update $memwr$\storage_5$ls180.v:10139$10_EN $0$memwr$\storage_5$ls180.v:10139$10_EN[9:0]$2732 + end + attribute \src "ls180.v:1014.5-1014.38" + process $proc$ls180.v:1014$3138 + assign { } { } + assign $1\main_spimaster26_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] + end + attribute \src "ls180.v:10143.1-10146.4" + process $proc$ls180.v:10143$2734 + assign $0\memdat_7[9:0] \memdat_7 + attribute \src "ls180.v:10144.2-10145.55" + switch \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:10144.6-10144.33" + case 1'1 + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10145$2735_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_7 $0\memdat_7[9:0] + end + attribute \src "ls180.v:1015.11-1015.40" + process $proc$ls180.v:1015$3139 + assign { } { } + assign $1\main_spimaster27_count[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count $1\main_spimaster27_count[2:0] + end + attribute \src "ls180.v:10153.1-10157.4" + process $proc$ls180.v:10153$2736 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10156$2740_DATA + attribute \src "ls180.v:10154.2-10155.85" + switch \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:10154.6-10154.37" + case 1'1 + assign $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_8 $0\memdat_8[9:0] + update $memwr$\storage_6$ls180.v:10155$11_ADDR $0$memwr$\storage_6$ls180.v:10155$11_ADDR[4:0]$2737 + update $memwr$\storage_6$ls180.v:10155$11_DATA $0$memwr$\storage_6$ls180.v:10155$11_DATA[9:0]$2738 + update $memwr$\storage_6$ls180.v:10155$11_EN $0$memwr$\storage_6$ls180.v:10155$11_EN[9:0]$2739 + end + attribute \src "ls180.v:10159.1-10160.4" + process $proc$ls180.v:10159$2741 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1016.5-1016.39" + process $proc$ls180.v:1016$3140 + assign { } { } + assign $1\main_spimaster28_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] + end + attribute \src "ls180.v:10167.1-10171.4" + process $proc$ls180.v:10167$2743 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10170$2747_DATA + attribute \src "ls180.v:10168.2-10169.85" + switch \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:10168.6-10168.37" + case 1'1 + assign $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_9 $0\memdat_9[9:0] + update $memwr$\storage_7$ls180.v:10169$12_ADDR $0$memwr$\storage_7$ls180.v:10169$12_ADDR[4:0]$2744 + update $memwr$\storage_7$ls180.v:10169$12_DATA $0$memwr$\storage_7$ls180.v:10169$12_DATA[9:0]$2745 + update $memwr$\storage_7$ls180.v:10169$12_EN $0$memwr$\storage_7$ls180.v:10169$12_EN[9:0]$2746 + end + attribute \src "ls180.v:1017.5-1017.39" + process $proc$ls180.v:1017$3141 + assign { } { } + assign $1\main_spimaster29_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] + end + attribute \src "ls180.v:10173.1-10174.4" + process $proc$ls180.v:10173$2748 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1018.12-1018.48" + process $proc$ls180.v:1018$3142 + assign { } { } + assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] + end + attribute \src "ls180.v:1021.11-1021.44" + process $proc$ls180.v:1021$3143 + assign { } { } + assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] + end + attribute \src "ls180.v:1022.11-1022.43" + process $proc$ls180.v:1022$3144 + assign { } { } + assign $1\main_spimaster34_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] + end + attribute \src "ls180.v:1023.11-1023.44" + process $proc$ls180.v:1023$3145 + assign { } { } + assign $1\main_spimaster35_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] + end + attribute \src "ls180.v:1026.5-1026.32" + process $proc$ls180.v:1026$3146 + assign { } { } + assign $1\main_spisdcard_done0[0:0] 1'0 + sync always + sync init + update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] + end + attribute \src "ls180.v:1027.5-1027.30" + process $proc$ls180.v:1027$3147 + assign { } { } + assign $1\main_spisdcard_irq[0:0] 1'0 + sync always + sync init + update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] + end + attribute \src "ls180.v:1029.11-1029.37" + process $proc$ls180.v:1029$3148 + assign { } { } + assign $1\main_spisdcard_miso[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] + end + attribute \src "ls180.v:1033.5-1033.33" + process $proc$ls180.v:1033$3149 + assign { } { } + assign $1\main_spisdcard_start1[0:0] 1'0 + sync always + sync init + update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:1035.12-1035.50" + process $proc$ls180.v:1035$3150 + assign { } { } + assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] + end + attribute \src "ls180.v:1036.5-1036.37" + process $proc$ls180.v:1036$3151 + assign { } { } + assign $1\main_spisdcard_control_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] + end + attribute \src "ls180.v:1040.11-1040.45" + process $proc$ls180.v:1040$3152 + assign { } { } + assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] + end + attribute \src "ls180.v:1041.5-1041.34" + process $proc$ls180.v:1041$3153 + assign { } { } + assign $1\main_spisdcard_mosi_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] + end + attribute \src "ls180.v:1045.5-1045.37" + process $proc$ls180.v:1045$3154 + assign { } { } + assign $1\main_spisdcard_cs_storage[0:0] 1'1 + sync always + sync init + update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] + end + attribute \src "ls180.v:1046.5-1046.32" + process $proc$ls180.v:1046$3155 + assign { } { } + assign $1\main_spisdcard_cs_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] + end + attribute \src "ls180.v:1047.5-1047.43" + process $proc$ls180.v:1047$3156 + assign { } { } + assign $1\main_spisdcard_loopback_storage[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] + end + attribute \src "ls180.v:1048.5-1048.38" + process $proc$ls180.v:1048$3157 + assign { } { } + assign $1\main_spisdcard_loopback_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] + end + attribute \src "ls180.v:1049.5-1049.37" + process $proc$ls180.v:1049$3158 + assign { } { } + assign $1\main_spisdcard_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] + end + attribute \src "ls180.v:1050.5-1050.36" + process $proc$ls180.v:1050$3159 + assign { } { } + assign $1\main_spisdcard_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] + end + attribute \src "ls180.v:1051.11-1051.38" + process $proc$ls180.v:1051$3160 + assign { } { } + assign $1\main_spisdcard_count[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count $1\main_spisdcard_count[2:0] + end + attribute \src "ls180.v:1052.5-1052.37" + process $proc$ls180.v:1052$3161 + assign { } { } + assign $1\main_spisdcard_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] + end + attribute \src "ls180.v:1053.5-1053.37" + process $proc$ls180.v:1053$3162 + assign { } { } + assign $1\main_spisdcard_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] + end + attribute \src "ls180.v:1054.12-1054.47" + process $proc$ls180.v:1054$3163 + assign { } { } + assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] + end + attribute \src "ls180.v:1057.11-1057.42" + process $proc$ls180.v:1057$3164 + assign { } { } + assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] + end + attribute \src "ls180.v:1058.11-1058.41" + process $proc$ls180.v:1058$3165 + assign { } { } + assign $1\main_spisdcard_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] + end + attribute \src "ls180.v:1059.11-1059.42" + process $proc$ls180.v:1059$3166 + assign { } { } + assign $1\main_spisdcard_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] + end + attribute \src "ls180.v:1060.12-1060.45" + process $proc$ls180.v:1060$3167 + assign { } { } + assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 + sync always + sync init + update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] + end + attribute \src "ls180.v:1061.5-1061.30" + process $proc$ls180.v:1061$3168 + assign { } { } + assign $1\main_spimaster1_re[0:0] 1'0 + sync always + sync init + update \main_spimaster1_re $1\main_spimaster1_re[0:0] + end + attribute \src "ls180.v:1063.12-1063.30" + process $proc$ls180.v:1063$3169 + assign { } { } + assign $1\main_dummy[23:0] 24'000000000000000000000000 + sync always + sync init + update \main_dummy $1\main_dummy[23:0] + end + attribute \src "ls180.v:1067.12-1067.37" + process $proc$ls180.v:1067$3170 + assign { } { } + assign $1\main_pwm0_counter[31:0] 0 + sync always + sync init + update \main_pwm0_counter $1\main_pwm0_counter[31:0] + end + attribute \src "ls180.v:1068.5-1068.36" + process $proc$ls180.v:1068$3171 + assign { } { } + assign $1\main_pwm0_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] + end + attribute \src "ls180.v:1069.5-1069.31" + process $proc$ls180.v:1069$3172 + assign { } { } + assign $1\main_pwm0_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] + end + attribute \src "ls180.v:1070.12-1070.43" + process $proc$ls180.v:1070$3173 + assign { } { } + assign $1\main_pwm0_width_storage[31:0] 0 + sync always + sync init + update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] + end + attribute \src "ls180.v:1071.5-1071.30" + process $proc$ls180.v:1071$3174 + assign { } { } + assign $1\main_pwm0_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + end + attribute \src "ls180.v:1072.12-1072.44" + process $proc$ls180.v:1072$3175 + assign { } { } + assign $1\main_pwm0_period_storage[31:0] 0 + sync always + sync init + update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] + end + attribute \src "ls180.v:1073.5-1073.31" + process $proc$ls180.v:1073$3176 + assign { } { } + assign $1\main_pwm0_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] + end + attribute \src "ls180.v:1077.12-1077.37" + process $proc$ls180.v:1077$3177 + assign { } { } + assign $1\main_pwm1_counter[31:0] 0 + sync always + sync init + update \main_pwm1_counter $1\main_pwm1_counter[31:0] + end + attribute \src "ls180.v:1078.5-1078.36" + process $proc$ls180.v:1078$3178 + assign { } { } + assign $1\main_pwm1_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] + end + attribute \src "ls180.v:1079.5-1079.31" + process $proc$ls180.v:1079$3179 + assign { } { } + assign $1\main_pwm1_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] + end + attribute \src "ls180.v:1080.12-1080.43" + process $proc$ls180.v:1080$3180 + assign { } { } + assign $1\main_pwm1_width_storage[31:0] 0 + sync always + sync init + update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] + end + attribute \src "ls180.v:1081.5-1081.30" + process $proc$ls180.v:1081$3181 + assign { } { } + assign $1\main_pwm1_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] + end + attribute \src "ls180.v:1082.12-1082.44" + process $proc$ls180.v:1082$3182 + assign { } { } + assign $1\main_pwm1_period_storage[31:0] 0 + sync always + sync init + update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] + end + attribute \src "ls180.v:1083.5-1083.31" + process $proc$ls180.v:1083$3183 + assign { } { } + assign $1\main_pwm1_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] + end + attribute \src "ls180.v:1087.11-1087.34" + process $proc$ls180.v:1087$3184 + assign { } { } + assign $1\main_i2c_storage[2:0] 3'000 + sync always + sync init + update \main_i2c_storage $1\main_i2c_storage[2:0] + end + attribute \src "ls180.v:1088.5-1088.23" + process $proc$ls180.v:1088$3185 + assign { } { } + assign $1\main_i2c_re[0:0] 1'0 + sync always + sync init + update \main_i2c_re $1\main_i2c_re[0:0] + end + attribute \src "ls180.v:1094.11-1094.46" + process $proc$ls180.v:1094$3186 + assign { } { } + assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 + sync always + sync init + update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] + end + attribute \src "ls180.v:1095.5-1095.33" + process $proc$ls180.v:1095$3187 + assign { } { } + assign $1\main_sdphy_clocker_re[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] + end + attribute \src "ls180.v:1097.5-1097.35" + process $proc$ls180.v:1097$3188 + assign { } { } + assign $1\main_sdphy_clocker_clk0[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] + end + attribute \src "ls180.v:1099.11-1099.41" + process $proc$ls180.v:1099$3189 + assign { } { } + assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 + sync always + sync init + update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] + end + attribute \src "ls180.v:1100.5-1100.35" + process $proc$ls180.v:1100$3190 + assign { } { } + assign $1\main_sdphy_clocker_clk1[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:1101.5-1101.36" + process $proc$ls180.v:1101$3191 + assign { } { } + assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] + end + attribute \src "ls180.v:1105.5-1105.40" + process $proc$ls180.v:1105$3192 + assign { } { } + assign $0\main_sdphy_init_initialize_w[0:0] 1'0 + sync always + update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] + sync init + end + attribute \src "ls180.v:1110.5-1110.48" + process $proc$ls180.v:1110$3193 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1111.5-1111.50" + process $proc$ls180.v:1111$3194 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1112.5-1112.51" + process $proc$ls180.v:1112$3195 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1113.11-1113.57" + process $proc$ls180.v:1113$3196 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1114.5-1114.52" + process $proc$ls180.v:1114$3197 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1115.11-1115.39" + process $proc$ls180.v:1115$3198 + assign { } { } + assign $1\main_sdphy_init_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] + end + attribute \src "ls180.v:112.5-112.49" + process $proc$ls180.v:112$2773 + assign { } { } + assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + end + attribute \src "ls180.v:1120.5-1120.48" + process $proc$ls180.v:1120$3199 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1121.5-1121.50" + process $proc$ls180.v:1121$3200 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1122.5-1122.51" + process $proc$ls180.v:1122$3201 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1123.11-1123.57" + process $proc$ls180.v:1123$3202 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1124.5-1124.52" + process $proc$ls180.v:1124$3203 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1125.5-1125.38" + process $proc$ls180.v:1125$3204 + assign { } { } + assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] + end + attribute \src "ls180.v:1126.5-1126.38" + process $proc$ls180.v:1126$3205 + assign { } { } + assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] + end + attribute \src "ls180.v:1127.5-1127.37" + process $proc$ls180.v:1127$3206 + assign { } { } + assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] + end + attribute \src "ls180.v:1128.11-1128.51" + process $proc$ls180.v:1128$3207 + assign { } { } + assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1129.5-1129.32" + process $proc$ls180.v:1129$3208 + assign { } { } + assign $1\main_sdphy_cmdw_done[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] + end + attribute \src "ls180.v:1130.11-1130.39" + process $proc$ls180.v:1130$3209 + assign { } { } + assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] + end + attribute \src "ls180.v:1133.5-1133.49" + process $proc$ls180.v:1133$3210 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1134.5-1134.48" + process $proc$ls180.v:1134$3211 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1135.5-1135.55" + process $proc$ls180.v:1135$3212 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1137.5-1137.57" + process $proc$ls180.v:1137$3213 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1138.5-1138.58" + process $proc$ls180.v:1138$3214 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:114.5-114.49" + process $proc$ls180.v:114$2774 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] + sync init + end + attribute \src "ls180.v:1140.11-1140.64" + process $proc$ls180.v:1140$3215 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1141.5-1141.59" + process $proc$ls180.v:1141$3216 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1143.5-1143.48" + process $proc$ls180.v:1143$3217 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1144.5-1144.50" + process $proc$ls180.v:1144$3218 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1145.5-1145.51" + process $proc$ls180.v:1145$3219 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1146.11-1146.57" + process $proc$ls180.v:1146$3220 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1147.5-1147.52" + process $proc$ls180.v:1147$3221 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1148.5-1148.38" + process $proc$ls180.v:1148$3222 + assign { } { } + assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] + end + attribute \src "ls180.v:1149.5-1149.38" + process $proc$ls180.v:1149$3223 + assign { } { } + assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] + end + attribute \src "ls180.v:1150.5-1150.37" + process $proc$ls180.v:1150$3224 + assign { } { } + assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] + end + attribute \src "ls180.v:1151.11-1151.53" + process $proc$ls180.v:1151$3225 + assign { } { } + assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] + end + attribute \src "ls180.v:1152.5-1152.40" + process $proc$ls180.v:1152$3226 + assign { } { } + assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] + end + attribute \src "ls180.v:1153.5-1153.40" + process $proc$ls180.v:1153$3227 + assign { } { } + assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] + end + attribute \src "ls180.v:1154.5-1154.39" + process $proc$ls180.v:1154$3228 + assign { } { } + assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] + end + attribute \src "ls180.v:1155.11-1155.53" + process $proc$ls180.v:1155$3229 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] + end + attribute \src "ls180.v:1156.11-1156.55" + process $proc$ls180.v:1156$3230 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] + end + attribute \src "ls180.v:1157.12-1157.48" + process $proc$ls180.v:1157$3231 + assign { } { } + assign $1\main_sdphy_cmdr_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] + end + attribute \src "ls180.v:1158.11-1158.39" + process $proc$ls180.v:1158$3232 + assign { } { } + assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] + end + attribute \src "ls180.v:1160.5-1160.46" + process $proc$ls180.v:1160$3233 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1171.5-1171.53" + process $proc$ls180.v:1171$3234 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1176.5-1176.36" + process $proc$ls180.v:1176$3235 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] + end + attribute \src "ls180.v:1179.5-1179.53" + process $proc$ls180.v:1179$3236 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1180.5-1180.52" + process $proc$ls180.v:1180$3237 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1184.5-1184.55" + process $proc$ls180.v:1184$3238 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + end + attribute \src "ls180.v:1185.5-1185.54" + process $proc$ls180.v:1185$3239 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + end + attribute \src "ls180.v:1186.11-1186.68" + process $proc$ls180.v:1186$3240 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1187.11-1187.81" + process $proc$ls180.v:1187$3241 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1188.11-1188.54" + process $proc$ls180.v:1188$3242 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + end + attribute \src "ls180.v:1190.5-1190.53" + process $proc$ls180.v:1190$3243 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1201.5-1201.49" + process $proc$ls180.v:1201$3244 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1203.5-1203.49" + process $proc$ls180.v:1203$3245 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + end + attribute \src "ls180.v:1204.5-1204.48" + process $proc$ls180.v:1204$3246 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + end + attribute \src "ls180.v:1205.11-1205.62" + process $proc$ls180.v:1205$3247 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1206.5-1206.38" + process $proc$ls180.v:1206$3248 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] + end + attribute \src "ls180.v:1211.5-1211.49" + process $proc$ls180.v:1211$3249 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1212.5-1212.51" + process $proc$ls180.v:1212$3250 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1213.5-1213.52" + process $proc$ls180.v:1213$3251 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1214.11-1214.58" + process $proc$ls180.v:1214$3252 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1215.5-1215.53" + process $proc$ls180.v:1215$3253 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1216.5-1216.39" + process $proc$ls180.v:1216$3254 + assign { } { } + assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] + end + attribute \src "ls180.v:1217.5-1217.39" + process $proc$ls180.v:1217$3255 + assign { } { } + assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] + end + attribute \src "ls180.v:1218.5-1218.39" + process $proc$ls180.v:1218$3256 + assign { } { } + assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] + end + attribute \src "ls180.v:1219.5-1219.38" + process $proc$ls180.v:1219$3257 + assign { } { } + assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] + end + attribute \src "ls180.v:1220.11-1220.52" + process $proc$ls180.v:1220$3258 + assign { } { } + assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1221.5-1221.33" + process $proc$ls180.v:1221$3259 + assign { } { } + assign $1\main_sdphy_dataw_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] + end + attribute \src "ls180.v:1222.11-1222.40" + process $proc$ls180.v:1222$3260 + assign { } { } + assign $1\main_sdphy_dataw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] + end + attribute \src "ls180.v:1223.5-1223.50" + process $proc$ls180.v:1223$3261 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + sync init + end + attribute \src "ls180.v:1225.5-1225.50" + process $proc$ls180.v:1225$3262 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1226.5-1226.49" + process $proc$ls180.v:1226$3263 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1227.5-1227.56" + process $proc$ls180.v:1227$3264 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1228.5-1228.58" + process $proc$ls180.v:1228$3265 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1229.5-1229.58" + process $proc$ls180.v:1229$3266 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1230.5-1230.59" + process $proc$ls180.v:1230$3267 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1231.11-1231.65" + process $proc$ls180.v:1231$3268 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + sync init + end + attribute \src "ls180.v:1232.11-1232.65" + process $proc$ls180.v:1232$3269 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1233.5-1233.60" + process $proc$ls180.v:1233$3270 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1234.5-1234.34" + process $proc$ls180.v:1234$3271 + assign { } { } + assign $1\main_sdphy_dataw_start[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] + end + attribute \src "ls180.v:1235.5-1235.34" + process $proc$ls180.v:1235$3272 + assign { } { } + assign $1\main_sdphy_dataw_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] + end + attribute \src "ls180.v:1236.5-1236.34" + process $proc$ls180.v:1236$3273 + assign { } { } + assign $1\main_sdphy_dataw_error[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] + end + attribute \src "ls180.v:1238.5-1238.47" + process $proc$ls180.v:1238$3274 + assign { } { } + assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1249.5-1249.54" + process $proc$ls180.v:1249$3275 + assign { } { } + assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1254.5-1254.37" + process $proc$ls180.v:1254$3276 + assign { } { } + assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] + end + attribute \src "ls180.v:1257.5-1257.54" + process $proc$ls180.v:1257$3277 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1258.5-1258.53" + process $proc$ls180.v:1258$3278 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1262.5-1262.56" + process $proc$ls180.v:1262$3279 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + end + attribute \src "ls180.v:1263.5-1263.55" + process $proc$ls180.v:1263$3280 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + end + attribute \src "ls180.v:1264.11-1264.69" + process $proc$ls180.v:1264$3281 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1265.11-1265.82" + process $proc$ls180.v:1265$3282 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1266.11-1266.55" + process $proc$ls180.v:1266$3283 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] + end + attribute \src "ls180.v:1268.5-1268.54" + process $proc$ls180.v:1268$3284 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1279.5-1279.50" + process $proc$ls180.v:1279$3285 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1281.5-1281.50" + process $proc$ls180.v:1281$3286 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + end + attribute \src "ls180.v:1282.5-1282.49" + process $proc$ls180.v:1282$3287 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + end + attribute \src "ls180.v:1283.11-1283.63" + process $proc$ls180.v:1283$3288 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1284.5-1284.39" + process $proc$ls180.v:1284$3289 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] + end + attribute \src "ls180.v:1287.5-1287.50" + process $proc$ls180.v:1287$3290 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1288.5-1288.49" + process $proc$ls180.v:1288$3291 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1289.5-1289.56" + process $proc$ls180.v:1289$3292 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1291.5-1291.58" + process $proc$ls180.v:1291$3293 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1292.5-1292.59" + process $proc$ls180.v:1292$3294 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1294.11-1294.65" + process $proc$ls180.v:1294$3295 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1295.5-1295.60" + process $proc$ls180.v:1295$3296 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1297.5-1297.49" + process $proc$ls180.v:1297$3297 + assign { } { } + assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1298.5-1298.51" + process $proc$ls180.v:1298$3298 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1299.5-1299.52" + process $proc$ls180.v:1299$3299 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1300.11-1300.58" + process $proc$ls180.v:1300$3300 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1301.5-1301.53" + process $proc$ls180.v:1301$3301 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1302.5-1302.39" + process $proc$ls180.v:1302$3302 + assign { } { } + assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] + end + attribute \src "ls180.v:1303.5-1303.39" + process $proc$ls180.v:1303$3303 + assign { } { } + assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] + end + attribute \src "ls180.v:1304.5-1304.38" + process $proc$ls180.v:1304$3304 + assign { } { } + assign $1\main_sdphy_datar_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] + end + attribute \src "ls180.v:1305.11-1305.61" + process $proc$ls180.v:1305$3305 + assign { } { } + assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] + end + attribute \src "ls180.v:1306.5-1306.41" + process $proc$ls180.v:1306$3306 + assign { } { } + assign $1\main_sdphy_datar_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] + end + attribute \src "ls180.v:1307.5-1307.41" + process $proc$ls180.v:1307$3307 + assign { } { } + assign $1\main_sdphy_datar_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] + end + attribute \src "ls180.v:1308.5-1308.41" + process $proc$ls180.v:1308$3308 + assign { } { } + assign $0\main_sdphy_datar_source_first[0:0] 1'0 + sync always + update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] + sync init + end + attribute \src "ls180.v:1309.5-1309.40" + process $proc$ls180.v:1309$3309 + assign { } { } + assign $1\main_sdphy_datar_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] + end + attribute \src "ls180.v:1310.11-1310.54" + process $proc$ls180.v:1310$3310 + assign { } { } + assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] + end + attribute \src "ls180.v:1311.11-1311.56" + process $proc$ls180.v:1311$3311 + assign { } { } + assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] + end + attribute \src "ls180.v:1312.5-1312.33" + process $proc$ls180.v:1312$3312 + assign { } { } + assign $1\main_sdphy_datar_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] + end + attribute \src "ls180.v:1313.12-1313.49" + process $proc$ls180.v:1313$3313 + assign { } { } + assign $1\main_sdphy_datar_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] + end + attribute \src "ls180.v:1314.11-1314.41" + process $proc$ls180.v:1314$3314 + assign { } { } + assign $1\main_sdphy_datar_count[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] + end + attribute \src "ls180.v:1316.5-1316.48" + process $proc$ls180.v:1316$3315 + assign { } { } + assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1327.5-1327.55" + process $proc$ls180.v:1327$3316 + assign { } { } + assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] + end + attribute \src "ls180.v:1332.5-1332.38" + process $proc$ls180.v:1332$3317 + assign { } { } + assign $1\main_sdphy_datar_datar_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] + end + attribute \src "ls180.v:1335.5-1335.55" + process $proc$ls180.v:1335$3318 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1336.5-1336.54" + process $proc$ls180.v:1336$3319 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1340.5-1340.57" + process $proc$ls180.v:1340$3320 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] + end + attribute \src "ls180.v:1341.5-1341.56" + process $proc$ls180.v:1341$3321 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] + end + attribute \src "ls180.v:1342.11-1342.70" + process $proc$ls180.v:1342$3322 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1343.11-1343.83" + process $proc$ls180.v:1343$3323 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + end + attribute \src "ls180.v:1344.5-1344.50" + process $proc$ls180.v:1344$3324 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] + end + attribute \src "ls180.v:1346.5-1346.55" + process $proc$ls180.v:1346$3325 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1357.5-1357.51" + process $proc$ls180.v:1357$3326 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] + end + attribute \src "ls180.v:1359.5-1359.51" + process $proc$ls180.v:1359$3327 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] + end + attribute \src "ls180.v:1360.5-1360.50" + process $proc$ls180.v:1360$3328 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] + end + attribute \src "ls180.v:1361.11-1361.64" + process $proc$ls180.v:1361$3329 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1362.5-1362.40" + process $proc$ls180.v:1362$3330 + assign { } { } + assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] + end + attribute \src "ls180.v:1364.5-1364.35" + process $proc$ls180.v:1364$3331 + assign { } { } + assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 + sync always + sync init + update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] + end + attribute \src "ls180.v:1367.11-1367.42" + process $proc$ls180.v:1367$3332 + assign { } { } + assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 + sync always + sync init + update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:1380.12-1380.52" + process $proc$ls180.v:1380$3333 + assign { } { } + assign $1\main_sdcore_cmd_argument_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] + end + attribute \src "ls180.v:1381.5-1381.39" + process $proc$ls180.v:1381$3334 + assign { } { } + assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] + end + attribute \src "ls180.v:1382.12-1382.51" + process $proc$ls180.v:1382$3335 + assign { } { } + assign $1\main_sdcore_cmd_command_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] + end + attribute \src "ls180.v:1383.5-1383.38" + process $proc$ls180.v:1383$3336 + assign { } { } + assign $1\main_sdcore_cmd_command_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] + end + attribute \src "ls180.v:1387.5-1387.34" + process $proc$ls180.v:1387$3337 + assign { } { } + assign $0\main_sdcore_cmd_send_w[0:0] 1'0 + sync always + update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] + sync init + end + attribute \src "ls180.v:1388.13-1388.53" + process $proc$ls180.v:1388$3338 + assign { } { } + assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] + end + attribute \src "ls180.v:1394.11-1394.51" + process $proc$ls180.v:1394$3339 + assign { } { } + assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 + sync always + sync init + update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] + end + attribute \src "ls180.v:1395.5-1395.39" + process $proc$ls180.v:1395$3340 + assign { } { } + assign $1\main_sdcore_block_length_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] + end + attribute \src "ls180.v:1396.12-1396.51" + process $proc$ls180.v:1396$3341 + assign { } { } + assign $1\main_sdcore_block_count_storage[31:0] 0 + sync always + sync init + update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] + end + attribute \src "ls180.v:1397.5-1397.38" + process $proc$ls180.v:1397$3342 + assign { } { } + assign $1\main_sdcore_block_count_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] + end + attribute \src "ls180.v:1398.11-1398.51" + process $proc$ls180.v:1398$3343 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + end + attribute \src "ls180.v:1440.11-1440.47" + process $proc$ls180.v:1440$3344 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:1444.5-1444.49" + process $proc$ls180.v:1444$3345 + assign { } { } + assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] + end + attribute \src "ls180.v:1448.5-1448.51" + process $proc$ls180.v:1448$3346 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] + end + attribute \src "ls180.v:1449.5-1449.51" + process $proc$ls180.v:1449$3347 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] + end + attribute \src "ls180.v:1450.5-1450.51" + process $proc$ls180.v:1450$3348 + assign { } { } + assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] + sync init + end + attribute \src "ls180.v:1451.5-1451.50" + process $proc$ls180.v:1451$3349 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] + end + attribute \src "ls180.v:1452.11-1452.64" + process $proc$ls180.v:1452$3350 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + end + attribute \src "ls180.v:1453.11-1453.48" + process $proc$ls180.v:1453$3351 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] + end + attribute \src "ls180.v:1454.12-1454.59" + process $proc$ls180.v:1454$3352 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1458.12-1458.55" + process $proc$ls180.v:1458$3353 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:1461.12-1461.59" + process $proc$ls180.v:1461$3354 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1465.12-1465.55" + process $proc$ls180.v:1465$3355 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:1468.12-1468.59" + process $proc$ls180.v:1468$3356 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1472.12-1472.55" + process $proc$ls180.v:1472$3357 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:1475.12-1475.59" + process $proc$ls180.v:1475$3358 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1479.12-1479.55" + process $proc$ls180.v:1479$3359 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:1482.12-1482.54" + process $proc$ls180.v:1482$3360 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + end + attribute \src "ls180.v:1483.12-1483.54" + process $proc$ls180.v:1483$3361 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + end + attribute \src "ls180.v:1484.12-1484.54" + process $proc$ls180.v:1484$3362 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + end + attribute \src "ls180.v:1485.12-1485.54" + process $proc$ls180.v:1485$3363 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + end + attribute \src "ls180.v:1486.5-1486.48" + process $proc$ls180.v:1486$3364 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] + end + attribute \src "ls180.v:1487.5-1487.48" + process $proc$ls180.v:1487$3365 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:1488.5-1488.48" + process $proc$ls180.v:1488$3366 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] + end + attribute \src "ls180.v:1489.5-1489.47" + process $proc$ls180.v:1489$3367 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] + end + attribute \src "ls180.v:1490.11-1490.61" + process $proc$ls180.v:1490$3368 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + end + attribute \src "ls180.v:1491.5-1491.50" + process $proc$ls180.v:1491$3369 + assign { } { } + assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:1493.5-1493.50" + process $proc$ls180.v:1493$3370 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] + sync init + end + attribute \src "ls180.v:1496.11-1496.47" + process $proc$ls180.v:1496$3371 + assign { } { } + assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] + end + attribute \src "ls180.v:1497.11-1497.47" + process $proc$ls180.v:1497$3372 + assign { } { } + assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + sync always + sync init + update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] + end + attribute \src "ls180.v:1498.12-1498.58" + process $proc$ls180.v:1498$3373 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1502.12-1502.54" + process $proc$ls180.v:1502$3374 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:1503.5-1503.46" + process $proc$ls180.v:1503$3375 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:1505.12-1505.58" + process $proc$ls180.v:1505$3376 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1509.12-1509.54" + process $proc$ls180.v:1509$3377 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:1510.5-1510.46" + process $proc$ls180.v:1510$3378 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:1512.12-1512.58" + process $proc$ls180.v:1512$3379 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1516.12-1516.54" + process $proc$ls180.v:1516$3380 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:1517.5-1517.46" + process $proc$ls180.v:1517$3381 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:1519.12-1519.58" + process $proc$ls180.v:1519$3382 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1523.12-1523.54" + process $proc$ls180.v:1523$3383 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:1524.5-1524.46" + process $proc$ls180.v:1524$3384 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:1526.12-1526.53" + process $proc$ls180.v:1526$3385 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] + end + attribute \src "ls180.v:1527.12-1527.53" + process $proc$ls180.v:1527$3386 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] + end + attribute \src "ls180.v:1528.12-1528.53" + process $proc$ls180.v:1528$3387 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] + end + attribute \src "ls180.v:1529.12-1529.53" + process $proc$ls180.v:1529$3388 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] + end + attribute \src "ls180.v:1530.5-1530.43" + process $proc$ls180.v:1530$3389 + assign { } { } + assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:1531.12-1531.51" + process $proc$ls180.v:1531$3390 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] + end + attribute \src "ls180.v:1532.12-1532.51" + process $proc$ls180.v:1532$3391 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] + end + attribute \src "ls180.v:1533.12-1533.51" + process $proc$ls180.v:1533$3392 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] + end + attribute \src "ls180.v:1534.12-1534.51" + process $proc$ls180.v:1534$3393 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] + end + attribute \src "ls180.v:1536.11-1536.39" + process $proc$ls180.v:1536$3394 + assign { } { } + assign $1\main_sdcore_cmd_count[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] + end + attribute \src "ls180.v:1537.5-1537.32" + process $proc$ls180.v:1537$3395 + assign { } { } + assign $1\main_sdcore_cmd_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] + end + attribute \src "ls180.v:1538.5-1538.33" + process $proc$ls180.v:1538$3396 + assign { } { } + assign $1\main_sdcore_cmd_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] + end + attribute \src "ls180.v:1539.5-1539.35" + process $proc$ls180.v:1539$3397 + assign { } { } + assign $1\main_sdcore_cmd_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] + end + attribute \src "ls180.v:1541.12-1541.42" + process $proc$ls180.v:1541$3398 + assign { } { } + assign $1\main_sdcore_data_count[31:0] 0 + sync always + sync init + update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] + end + attribute \src "ls180.v:1542.5-1542.33" + process $proc$ls180.v:1542$3399 + assign { } { } + assign $1\main_sdcore_data_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] + end + attribute \src "ls180.v:1543.5-1543.34" + process $proc$ls180.v:1543$3400 + assign { } { } + assign $1\main_sdcore_data_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] + end + attribute \src "ls180.v:1544.5-1544.36" + process $proc$ls180.v:1544$3401 + assign { } { } + assign $1\main_sdcore_data_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] + end + attribute \src "ls180.v:1553.11-1553.41" + process $proc$ls180.v:1553$3402 + assign { } { } + assign $0\main_interface0_bus_cti[2:0] 3'000 + sync always + update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1554.11-1554.41" + process $proc$ls180.v:1554$3403 + assign { } { } + assign $0\main_interface0_bus_bte[1:0] 2'00 + sync always + update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:1577.11-1577.45" + process $proc$ls180.v:1577$3404 + assign { } { } + assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] + end + attribute \src "ls180.v:1578.5-1578.41" + process $proc$ls180.v:1578$3405 + assign { } { } + assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 + sync always + update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1579.11-1579.47" + process $proc$ls180.v:1579$3406 + assign { } { } + assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] + end + attribute \src "ls180.v:158.12-158.71" + process $proc$ls180.v:158$2775 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1580.11-1580.47" + process $proc$ls180.v:1580$3407 + assign { } { } + assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] + end + attribute \src "ls180.v:1581.11-1581.50" + process $proc$ls180.v:1581$3408 + assign { } { } + assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:159.12-159.73" + process $proc$ls180.v:159$2776 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1601.5-1601.51" + process $proc$ls180.v:1601$3409 + assign { } { } + assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] + end + attribute \src "ls180.v:1602.5-1602.50" + process $proc$ls180.v:1602$3410 + assign { } { } + assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] + end + attribute \src "ls180.v:1603.12-1603.66" + process $proc$ls180.v:1603$3411 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] + end + attribute \src "ls180.v:1604.11-1604.77" + process $proc$ls180.v:1604$3412 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + end + attribute \src "ls180.v:1605.11-1605.50" + process $proc$ls180.v:1605$3413 + assign { } { } + assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 + sync always + sync init + update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] + end + attribute \src "ls180.v:1607.5-1607.49" + process $proc$ls180.v:1607$3414 + assign { } { } + assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] + end + attribute \src "ls180.v:161.11-161.69" + process $proc$ls180.v:161$2777 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1613.5-1613.45" + process $proc$ls180.v:1613$3415 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] + end + attribute \src "ls180.v:1615.12-1615.62" + process $proc$ls180.v:1615$3416 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] + end + attribute \src "ls180.v:1616.12-1616.60" + process $proc$ls180.v:1616$3417 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + end + attribute \src "ls180.v:1618.5-1618.57" + process $proc$ls180.v:1618$3418 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + end + attribute \src "ls180.v:162.5-162.63" + process $proc$ls180.v:162$2778 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:1622.12-1622.67" + process $proc$ls180.v:1622$3419 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + end + attribute \src "ls180.v:1623.5-1623.54" + process $proc$ls180.v:1623$3420 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + end + attribute \src "ls180.v:1624.12-1624.69" + process $proc$ls180.v:1624$3421 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + end + attribute \src "ls180.v:1625.5-1625.56" + process $proc$ls180.v:1625$3422 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + end + attribute \src "ls180.v:1626.5-1626.61" + process $proc$ls180.v:1626$3423 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + end + attribute \src "ls180.v:1627.5-1627.56" + process $proc$ls180.v:1627$3424 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + end + attribute \src "ls180.v:1628.5-1628.53" + process $proc$ls180.v:1628$3425 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + end + attribute \src "ls180.v:163.5-163.63" + process $proc$ls180.v:163$2779 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1630.5-1630.59" + process $proc$ls180.v:1630$3426 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + end + attribute \src "ls180.v:1631.5-1631.54" + process $proc$ls180.v:1631$3427 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + end + attribute \src "ls180.v:1633.12-1633.61" + process $proc$ls180.v:1633$3428 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + end + attribute \src "ls180.v:1636.12-1636.43" + process $proc$ls180.v:1636$3429 + assign { } { } + assign $1\main_interface1_bus_adr[31:0] 0 + sync always + sync init + update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] + end + attribute \src "ls180.v:1637.12-1637.45" + process $proc$ls180.v:1637$3430 + assign { } { } + assign $0\main_interface1_bus_dat_w[31:0] 0 + sync always + update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] + sync init + end + attribute \src "ls180.v:1639.11-1639.41" + process $proc$ls180.v:1639$3431 + assign { } { } + assign $1\main_interface1_bus_sel[3:0] 4'0000 + sync always + sync init + update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] + end + attribute \src "ls180.v:1640.5-1640.35" + process $proc$ls180.v:1640$3432 + assign { } { } + assign $1\main_interface1_bus_cyc[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] + end + attribute \src "ls180.v:1641.5-1641.35" + process $proc$ls180.v:1641$3433 + assign { } { } + assign $1\main_interface1_bus_stb[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] + end + attribute \src "ls180.v:1643.5-1643.34" + process $proc$ls180.v:1643$3434 + assign { } { } + assign $1\main_interface1_bus_we[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] + end + attribute \src "ls180.v:1644.11-1644.41" + process $proc$ls180.v:1644$3435 + assign { } { } + assign $0\main_interface1_bus_cti[2:0] 3'000 + sync always + update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1645.11-1645.41" + process $proc$ls180.v:1645$3436 + assign { } { } + assign $0\main_interface1_bus_bte[1:0] 2'00 + sync always + update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:165.5-165.62" + process $proc$ls180.v:165$2780 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] + end + attribute \src "ls180.v:1652.5-1652.43" + process $proc$ls180.v:1652$3437 + assign { } { } + assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] + end + attribute \src "ls180.v:1653.5-1653.43" + process $proc$ls180.v:1653$3438 + assign { } { } + assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] + end + attribute \src "ls180.v:1654.5-1654.42" + process $proc$ls180.v:1654$3439 + assign { } { } + assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] + end + attribute \src "ls180.v:1655.12-1655.61" + process $proc$ls180.v:1655$3440 + assign { } { } + assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] + end + attribute \src "ls180.v:1656.5-1656.45" + process $proc$ls180.v:1656$3441 + assign { } { } + assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] + end + attribute \src "ls180.v:1658.5-1658.45" + process $proc$ls180.v:1658$3442 + assign { } { } + assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 + sync always + update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] + sync init + end + attribute \src "ls180.v:1659.5-1659.44" + process $proc$ls180.v:1659$3443 + assign { } { } + assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] + end + attribute \src "ls180.v:166.11-166.69" + process $proc$ls180.v:166$2781 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1660.12-1660.60" + process $proc$ls180.v:1660$3444 + assign { } { } + assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] + end + attribute \src "ls180.v:1661.12-1661.45" + process $proc$ls180.v:1661$3445 + assign { } { } + assign $1\main_sdmem2block_dma_data[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] + end + attribute \src "ls180.v:1662.12-1662.53" + process $proc$ls180.v:1662$3446 + assign { } { } + assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] + end + attribute \src "ls180.v:1663.5-1663.40" + process $proc$ls180.v:1663$3447 + assign { } { } + assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] + end + attribute \src "ls180.v:1664.12-1664.55" + process $proc$ls180.v:1664$3448 + assign { } { } + assign $1\main_sdmem2block_dma_length_storage[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] + end + attribute \src "ls180.v:1665.5-1665.42" + process $proc$ls180.v:1665$3449 + assign { } { } + assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] + end + attribute \src "ls180.v:1666.5-1666.47" + process $proc$ls180.v:1666$3450 + assign { } { } + assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] + end + attribute \src "ls180.v:1667.5-1667.42" + process $proc$ls180.v:1667$3451 + assign { } { } + assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] + end + attribute \src "ls180.v:1668.5-1668.44" + process $proc$ls180.v:1668$3452 + assign { } { } + assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] + end + attribute \src "ls180.v:167.11-167.69" + process $proc$ls180.v:167$2782 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1670.5-1670.45" + process $proc$ls180.v:1670$3453 + assign { } { } + assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] + end + attribute \src "ls180.v:1671.5-1671.40" + process $proc$ls180.v:1671$3454 + assign { } { } + assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] + end + attribute \src "ls180.v:1675.12-1675.47" + process $proc$ls180.v:1675$3455 + assign { } { } + assign $1\main_sdmem2block_dma_offset[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] + end + attribute \src "ls180.v:1687.11-1687.64" + process $proc$ls180.v:1687$3456 + assign { } { } + assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1689.11-1689.48" + process $proc$ls180.v:1689$3457 + assign { } { } + assign $1\main_sdmem2block_converter_mux[1:0] 2'00 + sync always + sync init + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] + end + attribute \src "ls180.v:169.5-169.44" + process $proc$ls180.v:169$2783 + assign { } { } + assign $1\main_libresocsim_converter0_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] + end + attribute \src "ls180.v:170.5-170.47" + process $proc$ls180.v:170$2784 + assign { } { } + assign $1\main_libresocsim_converter0_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] + end + attribute \src "ls180.v:1713.11-1713.45" + process $proc$ls180.v:1713$3458 + assign { } { } + assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] + end + attribute \src "ls180.v:1714.5-1714.41" + process $proc$ls180.v:1714$3459 + assign { } { } + assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 + sync always + update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1715.11-1715.47" + process $proc$ls180.v:1715$3460 + assign { } { } + assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] + end + attribute \src "ls180.v:1716.11-1716.47" + process $proc$ls180.v:1716$3461 + assign { } { } + assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] + end + attribute \src "ls180.v:1717.11-1717.50" + process $proc$ls180.v:1717$3462 + assign { } { } + assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:172.12-172.53" + process $proc$ls180.v:172$2785 + assign { } { } + assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] + end + attribute \src "ls180.v:173.12-173.71" + process $proc$ls180.v:173$2786 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1730.5-1730.36" + process $proc$ls180.v:1730$3463 + assign { } { } + assign $1\builder_converter0_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_state $1\builder_converter0_state[0:0] + end + attribute \src "ls180.v:1731.5-1731.41" + process $proc$ls180.v:1731$3464 + assign { } { } + assign $1\builder_converter0_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] + end + attribute \src "ls180.v:1732.5-1732.69" + process $proc$ls180.v:1732$3465 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + end + attribute \src "ls180.v:1733.5-1733.72" + process $proc$ls180.v:1733$3466 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:1734.5-1734.36" + process $proc$ls180.v:1734$3467 + assign { } { } + assign $1\builder_converter1_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_state $1\builder_converter1_state[0:0] + end + attribute \src "ls180.v:1735.5-1735.41" + process $proc$ls180.v:1735$3468 + assign { } { } + assign $1\builder_converter1_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] + end + attribute \src "ls180.v:1736.5-1736.69" + process $proc$ls180.v:1736$3469 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + end + attribute \src "ls180.v:1737.5-1737.72" + process $proc$ls180.v:1737$3470 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:1738.5-1738.36" + process $proc$ls180.v:1738$3471 + assign { } { } + assign $1\builder_converter2_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_state $1\builder_converter2_state[0:0] + end + attribute \src "ls180.v:1739.5-1739.41" + process $proc$ls180.v:1739$3472 + assign { } { } + assign $1\builder_converter2_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] + end + attribute \src "ls180.v:174.12-174.73" + process $proc$ls180.v:174$2787 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1740.5-1740.69" + process $proc$ls180.v:1740$3473 + assign { } { } + assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + end + attribute \src "ls180.v:1741.5-1741.72" + process $proc$ls180.v:1741$3474 + assign { } { } + assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:1742.11-1742.41" + process $proc$ls180.v:1742$3475 + assign { } { } + assign $1\builder_refresher_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_state $1\builder_refresher_state[1:0] + end + attribute \src "ls180.v:1743.11-1743.46" + process $proc$ls180.v:1743$3476 + assign { } { } + assign $1\builder_refresher_next_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:1744.11-1744.44" + process $proc$ls180.v:1744$3477 + assign { } { } + assign $1\builder_bankmachine0_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] + end + attribute \src "ls180.v:1745.11-1745.49" + process $proc$ls180.v:1745$3478 + assign { } { } + assign $1\builder_bankmachine0_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:1746.11-1746.44" + process $proc$ls180.v:1746$3479 + assign { } { } + assign $1\builder_bankmachine1_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] + end + attribute \src "ls180.v:1747.11-1747.49" + process $proc$ls180.v:1747$3480 + assign { } { } + assign $1\builder_bankmachine1_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:1748.11-1748.44" + process $proc$ls180.v:1748$3481 + assign { } { } + assign $1\builder_bankmachine2_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] + end + attribute \src "ls180.v:1749.11-1749.49" + process $proc$ls180.v:1749$3482 + assign { } { } + assign $1\builder_bankmachine2_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:1750.11-1750.44" + process $proc$ls180.v:1750$3483 + assign { } { } + assign $1\builder_bankmachine3_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] + end + attribute \src "ls180.v:1751.11-1751.49" + process $proc$ls180.v:1751$3484 + assign { } { } + assign $1\builder_bankmachine3_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:1752.11-1752.43" + process $proc$ls180.v:1752$3485 + assign { } { } + assign $1\builder_multiplexer_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] + end + attribute \src "ls180.v:1753.11-1753.48" + process $proc$ls180.v:1753$3486 + assign { } { } + assign $1\builder_multiplexer_next_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:176.11-176.69" + process $proc$ls180.v:176$2788 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1766.5-1766.27" + process $proc$ls180.v:1766$3487 + assign { } { } + assign $0\builder_locked0[0:0] 1'0 + sync always + update \builder_locked0 $0\builder_locked0[0:0] + sync init + end + attribute \src "ls180.v:1767.5-1767.27" + process $proc$ls180.v:1767$3488 + assign { } { } + assign $0\builder_locked1[0:0] 1'0 + sync always + update \builder_locked1 $0\builder_locked1[0:0] + sync init + end + attribute \src "ls180.v:1768.5-1768.27" + process $proc$ls180.v:1768$3489 + assign { } { } + assign $0\builder_locked2[0:0] 1'0 + sync always + update \builder_locked2 $0\builder_locked2[0:0] + sync init + end + attribute \src "ls180.v:1769.5-1769.27" + process $proc$ls180.v:1769$3490 + assign { } { } + assign $0\builder_locked3[0:0] 1'0 + sync always + update \builder_locked3 $0\builder_locked3[0:0] + sync init + end + attribute \src "ls180.v:177.5-177.63" + process $proc$ls180.v:177$2789 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:1770.5-1770.42" + process $proc$ls180.v:1770$3491 + assign { } { } + assign $1\builder_new_master_wdata_ready[0:0] 1'0 + sync always + sync init + update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] + end + attribute \src "ls180.v:1771.5-1771.43" + process $proc$ls180.v:1771$3492 + assign { } { } + assign $1\builder_new_master_rdata_valid0[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] + end + attribute \src "ls180.v:1772.5-1772.43" + process $proc$ls180.v:1772$3493 + assign { } { } + assign $1\builder_new_master_rdata_valid1[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] + end + attribute \src "ls180.v:1773.5-1773.43" + process $proc$ls180.v:1773$3494 + assign { } { } + assign $1\builder_new_master_rdata_valid2[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] + end + attribute \src "ls180.v:1774.5-1774.43" + process $proc$ls180.v:1774$3495 + assign { } { } + assign $1\builder_new_master_rdata_valid3[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] + end + attribute \src "ls180.v:1775.5-1775.35" + process $proc$ls180.v:1775$3496 + assign { } { } + assign $1\builder_converter_state[0:0] 1'0 + sync always + sync init + update \builder_converter_state $1\builder_converter_state[0:0] + end + attribute \src "ls180.v:1776.5-1776.40" + process $proc$ls180.v:1776$3497 + assign { } { } + assign $1\builder_converter_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter_next_state $1\builder_converter_next_state[0:0] + end + attribute \src "ls180.v:1777.5-1777.55" + process $proc$ls180.v:1777$3498 + assign { } { } + assign $1\main_converter_counter_converter_next_value[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] + end + attribute \src "ls180.v:1778.5-1778.58" + process $proc$ls180.v:1778$3499 + assign { } { } + assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:1779.11-1779.42" + process $proc$ls180.v:1779$3500 + assign { } { } + assign $1\builder_spimaster0_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] + end + attribute \src "ls180.v:178.5-178.63" + process $proc$ls180.v:178$2790 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1780.11-1780.47" + process $proc$ls180.v:1780$3501 + assign { } { } + assign $1\builder_spimaster0_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] + end + attribute \src "ls180.v:1781.11-1781.62" + process $proc$ls180.v:1781$3502 + assign { } { } + assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] + end + attribute \src "ls180.v:1782.5-1782.59" + process $proc$ls180.v:1782$3503 + assign { } { } + assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:1783.11-1783.42" + process $proc$ls180.v:1783$3504 + assign { } { } + assign $1\builder_spimaster1_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] + end + attribute \src "ls180.v:1784.11-1784.47" + process $proc$ls180.v:1784$3505 + assign { } { } + assign $1\builder_spimaster1_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] + end + attribute \src "ls180.v:1785.11-1785.60" + process $proc$ls180.v:1785$3506 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] + end + attribute \src "ls180.v:1786.5-1786.57" + process $proc$ls180.v:1786$3507 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:1787.5-1787.41" + process $proc$ls180.v:1787$3508 + assign { } { } + assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] + end + attribute \src "ls180.v:1788.5-1788.46" + process $proc$ls180.v:1788$3509 + assign { } { } + assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] + end + attribute \src "ls180.v:1789.11-1789.66" + process $proc$ls180.v:1789$3510 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + end + attribute \src "ls180.v:1790.5-1790.63" + process $proc$ls180.v:1790$3511 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:1791.11-1791.47" + process $proc$ls180.v:1791$3512 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] + end + attribute \src "ls180.v:1792.11-1792.52" + process $proc$ls180.v:1792$3513 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] + end + attribute \src "ls180.v:1793.11-1793.66" + process $proc$ls180.v:1793$3514 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + end + attribute \src "ls180.v:1794.5-1794.63" + process $proc$ls180.v:1794$3515 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:1795.11-1795.47" + process $proc$ls180.v:1795$3516 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] + end + attribute \src "ls180.v:1796.11-1796.52" + process $proc$ls180.v:1796$3517 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] + end + attribute \src "ls180.v:1797.11-1797.67" + process $proc$ls180.v:1797$3518 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + end + attribute \src "ls180.v:1798.5-1798.64" + process $proc$ls180.v:1798$3519 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + end + attribute \src "ls180.v:1799.12-1799.71" + process $proc$ls180.v:1799$3520 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + end + attribute \src "ls180.v:180.5-180.62" + process $proc$ls180.v:180$2791 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] + end + attribute \src "ls180.v:1800.5-1800.66" + process $proc$ls180.v:1800$3521 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + end + attribute \src "ls180.v:1801.5-1801.66" + process $proc$ls180.v:1801$3522 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + end + attribute \src "ls180.v:1802.5-1802.69" + process $proc$ls180.v:1802$3523 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:1803.5-1803.41" + process $proc$ls180.v:1803$3524 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] + end + attribute \src "ls180.v:1804.5-1804.46" + process $proc$ls180.v:1804$3525 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] + end + attribute \src "ls180.v:1805.5-1805.66" + process $proc$ls180.v:1805$3526 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + end + attribute \src "ls180.v:1806.5-1806.69" + process $proc$ls180.v:1806$3527 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:1807.11-1807.41" + process $proc$ls180.v:1807$3528 + assign { } { } + assign $1\builder_sdphy_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] + end + attribute \src "ls180.v:1808.11-1808.46" + process $proc$ls180.v:1808$3529 + assign { } { } + assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] + end + attribute \src "ls180.v:1809.11-1809.61" + process $proc$ls180.v:1809$3530 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + end + attribute \src "ls180.v:181.11-181.69" + process $proc$ls180.v:181$2792 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1810.5-1810.58" + process $proc$ls180.v:1810$3531 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1811.11-1811.48" + process $proc$ls180.v:1811$3532 + assign { } { } + assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] + end + attribute \src "ls180.v:1812.11-1812.53" + process $proc$ls180.v:1812$3533 + assign { } { } + assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] + end + attribute \src "ls180.v:1813.11-1813.70" + process $proc$ls180.v:1813$3534 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + end + attribute \src "ls180.v:1814.5-1814.66" + process $proc$ls180.v:1814$3535 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + end + attribute \src "ls180.v:1815.12-1815.73" + process $proc$ls180.v:1815$3536 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + end + attribute \src "ls180.v:1816.5-1816.68" + process $proc$ls180.v:1816$3537 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + end + attribute \src "ls180.v:1817.5-1817.69" + process $proc$ls180.v:1817$3538 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + end + attribute \src "ls180.v:1818.5-1818.72" + process $proc$ls180.v:1818$3539 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:1819.5-1819.52" + process $proc$ls180.v:1819$3540 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] + end + attribute \src "ls180.v:182.11-182.69" + process $proc$ls180.v:182$2793 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1820.5-1820.57" + process $proc$ls180.v:1820$3541 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + end + attribute \src "ls180.v:1821.12-1821.93" + process $proc$ls180.v:1821$3542 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + end + attribute \src "ls180.v:1822.5-1822.88" + process $proc$ls180.v:1822$3543 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + end + attribute \src "ls180.v:1823.12-1823.93" + process $proc$ls180.v:1823$3544 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + end + attribute \src "ls180.v:1824.5-1824.88" + process $proc$ls180.v:1824$3545 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + end + attribute \src "ls180.v:1825.12-1825.93" + process $proc$ls180.v:1825$3546 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + end + attribute \src "ls180.v:1826.5-1826.88" + process $proc$ls180.v:1826$3547 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + end + attribute \src "ls180.v:1827.12-1827.93" + process $proc$ls180.v:1827$3548 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + end + attribute \src "ls180.v:1828.5-1828.88" + process $proc$ls180.v:1828$3549 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + end + attribute \src "ls180.v:1829.11-1829.87" + process $proc$ls180.v:1829$3550 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + end + attribute \src "ls180.v:1830.5-1830.84" + process $proc$ls180.v:1830$3551 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:1831.11-1831.42" + process $proc$ls180.v:1831$3552 + assign { } { } + assign $1\builder_sdcore_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] + end + attribute \src "ls180.v:1832.11-1832.47" + process $proc$ls180.v:1832$3553 + assign { } { } + assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] + end + attribute \src "ls180.v:1833.5-1833.55" + process $proc$ls180.v:1833$3554 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + end + attribute \src "ls180.v:1834.5-1834.58" + process $proc$ls180.v:1834$3555 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + end + attribute \src "ls180.v:1835.5-1835.56" + process $proc$ls180.v:1835$3556 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + end + attribute \src "ls180.v:1836.5-1836.59" + process $proc$ls180.v:1836$3557 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + end + attribute \src "ls180.v:1837.11-1837.62" + process $proc$ls180.v:1837$3558 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + end + attribute \src "ls180.v:1838.5-1838.59" + process $proc$ls180.v:1838$3559 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + end + attribute \src "ls180.v:1839.12-1839.65" + process $proc$ls180.v:1839$3560 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + end + attribute \src "ls180.v:184.5-184.44" + process $proc$ls180.v:184$2794 + assign { } { } + assign $1\main_libresocsim_converter1_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] + end + attribute \src "ls180.v:1840.5-1840.60" + process $proc$ls180.v:1840$3561 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + end + attribute \src "ls180.v:1841.5-1841.56" + process $proc$ls180.v:1841$3562 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + end + attribute \src "ls180.v:1842.5-1842.59" + process $proc$ls180.v:1842$3563 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + end + attribute \src "ls180.v:1843.5-1843.58" + process $proc$ls180.v:1843$3564 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + end + attribute \src "ls180.v:1844.5-1844.61" + process $proc$ls180.v:1844$3565 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + end + attribute \src "ls180.v:1845.5-1845.57" + process $proc$ls180.v:1845$3566 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + end + attribute \src "ls180.v:1846.5-1846.60" + process $proc$ls180.v:1846$3567 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + end + attribute \src "ls180.v:1847.5-1847.59" + process $proc$ls180.v:1847$3568 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + end + attribute \src "ls180.v:1848.5-1848.62" + process $proc$ls180.v:1848$3569 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + end + attribute \src "ls180.v:1849.13-1849.76" + process $proc$ls180.v:1849$3570 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + end + attribute \src "ls180.v:185.5-185.47" + process $proc$ls180.v:185$2795 + assign { } { } + assign $1\main_libresocsim_converter1_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] + end + attribute \src "ls180.v:1850.5-1850.69" + process $proc$ls180.v:1850$3571 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:1851.11-1851.46" + process $proc$ls180.v:1851$3572 + assign { } { } + assign $1\builder_sdblock2memdma_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] + end + attribute \src "ls180.v:1852.11-1852.51" + process $proc$ls180.v:1852$3573 + assign { } { } + assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] + end + attribute \src "ls180.v:1853.12-1853.87" + process $proc$ls180.v:1853$3574 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + end + attribute \src "ls180.v:1854.5-1854.82" + process $proc$ls180.v:1854$3575 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:1855.5-1855.44" + process $proc$ls180.v:1855$3576 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] + end + attribute \src "ls180.v:1856.5-1856.49" + process $proc$ls180.v:1856$3577 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] + end + attribute \src "ls180.v:1857.12-1857.75" + process $proc$ls180.v:1857$3578 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + end + attribute \src "ls180.v:1858.5-1858.70" + process $proc$ls180.v:1858$3579 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1859.11-1859.60" + process $proc$ls180.v:1859$3580 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] + end + attribute \src "ls180.v:1860.11-1860.65" + process $proc$ls180.v:1860$3581 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + end + attribute \src "ls180.v:1861.12-1861.87" + process $proc$ls180.v:1861$3582 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + end + attribute \src "ls180.v:1862.5-1862.82" + process $proc$ls180.v:1862$3583 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:1863.12-1863.43" + process $proc$ls180.v:1863$3584 + assign { } { } + assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] + end + attribute \src "ls180.v:1864.5-1864.34" + process $proc$ls180.v:1864$3585 + assign { } { } + assign $1\builder_libresocsim_we[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] + end + attribute \src "ls180.v:1865.11-1865.43" + process $proc$ls180.v:1865$3586 + assign { } { } + assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] + end + attribute \src "ls180.v:1869.12-1869.54" + process $proc$ls180.v:1869$3587 + assign { } { } + assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 + sync always + sync init + update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] + end + attribute \src "ls180.v:187.12-187.53" + process $proc$ls180.v:187$2796 + assign { } { } + assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] + end + attribute \src "ls180.v:1873.5-1873.44" + process $proc$ls180.v:1873$3588 + assign { } { } + assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] + end + attribute \src "ls180.v:1877.5-1877.44" + process $proc$ls180.v:1877$3589 + assign { } { } + assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] + sync init + end + attribute \src "ls180.v:188.12-188.71" + process $proc$ls180.v:188$2797 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1880.12-1880.40" + process $proc$ls180.v:1880$3590 + assign { } { } + assign $1\builder_shared_dat_r[31:0] 0 + sync always + sync init + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] + end + attribute \src "ls180.v:1884.5-1884.30" + process $proc$ls180.v:1884$3591 + assign { } { } + assign $1\builder_shared_ack[0:0] 1'0 + sync always + sync init + update \builder_shared_ack $1\builder_shared_ack[0:0] + end + attribute \src "ls180.v:189.12-189.73" + process $proc$ls180.v:189$2798 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1890.11-1890.31" + process $proc$ls180.v:1890$3592 + assign { } { } + assign $1\builder_grant[2:0] 3'000 + sync always + sync init + update \builder_grant $1\builder_grant[2:0] + end + attribute \src "ls180.v:1891.11-1891.35" + process $proc$ls180.v:1891$3593 + assign { } { } + assign $1\builder_slave_sel[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel $1\builder_slave_sel[4:0] + end + attribute \src "ls180.v:1892.11-1892.37" + process $proc$ls180.v:1892$3594 + assign { } { } + assign $1\builder_slave_sel_r[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] + end + attribute \src "ls180.v:1893.5-1893.25" + process $proc$ls180.v:1893$3595 + assign { } { } + assign $1\builder_error[0:0] 1'0 + sync always + sync init + update \builder_error $1\builder_error[0:0] + end + attribute \src "ls180.v:1896.12-1896.39" + process $proc$ls180.v:1896$3596 + assign { } { } + assign $1\builder_count[19:0] 20'11110100001001000000 + sync always + sync init + update \builder_count $1\builder_count[19:0] + end + attribute \src "ls180.v:1900.11-1900.51" + process $proc$ls180.v:1900$3597 + assign { } { } + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:191.11-191.69" + process $proc$ls180.v:191$2799 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] + end + attribute \src "ls180.v:192.5-192.63" + process $proc$ls180.v:192$2800 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:193.5-193.63" + process $proc$ls180.v:193$2801 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1941.11-1941.51" + process $proc$ls180.v:1941$3598 + assign { } { } + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:195.5-195.62" + process $proc$ls180.v:195$2802 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] + end + attribute \src "ls180.v:196.11-196.69" + process $proc$ls180.v:196$2803 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:197.11-197.69" + process $proc$ls180.v:197$2804 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1970.11-1970.51" + process $proc$ls180.v:1970$3599 + assign { } { } + assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:1983.11-1983.51" + process $proc$ls180.v:1983$3600 + assign { } { } + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:199.5-199.44" + process $proc$ls180.v:199$2805 + assign { } { } + assign $1\main_libresocsim_converter2_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] + end + attribute \src "ls180.v:200.5-200.47" + process $proc$ls180.v:200$2806 + assign { } { } + assign $1\main_libresocsim_converter2_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] + end + attribute \src "ls180.v:202.12-202.53" + process $proc$ls180.v:202$2807 + assign { } { } + assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] + end + attribute \src "ls180.v:2024.11-2024.51" + process $proc$ls180.v:2024$3601 + assign { } { } + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2065.11-2065.51" + process $proc$ls180.v:2065$3602 + assign { } { } + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:209.5-209.40" + process $proc$ls180.v:209$2808 + assign { } { } + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] + end + attribute \src "ls180.v:213.5-213.40" + process $proc$ls180.v:213$2809 + assign { } { } + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:2130.11-2130.51" + process $proc$ls180.v:2130$3603 + assign { } { } + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:216.11-216.37" + process $proc$ls180.v:216$2810 + assign { } { } + assign $1\main_libresocsim_we[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_we $1\main_libresocsim_we[3:0] + end + attribute \src "ls180.v:218.12-218.49" + process $proc$ls180.v:218$2811 + assign { } { } + assign $1\main_libresocsim_load_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + end + attribute \src "ls180.v:219.5-219.36" + process $proc$ls180.v:219$2812 + assign { } { } + assign $1\main_libresocsim_load_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] + end + attribute \src "ls180.v:220.12-220.51" + process $proc$ls180.v:220$2813 + assign { } { } + assign $1\main_libresocsim_reload_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] + end + attribute \src "ls180.v:221.5-221.38" + process $proc$ls180.v:221$2814 + assign { } { } + assign $1\main_libresocsim_reload_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] + end + attribute \src "ls180.v:222.5-222.39" + process $proc$ls180.v:222$2815 + assign { } { } + assign $1\main_libresocsim_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + end + attribute \src "ls180.v:223.5-223.34" + process $proc$ls180.v:223$2816 + assign { } { } + assign $1\main_libresocsim_en_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + end + attribute \src "ls180.v:224.5-224.49" + process $proc$ls180.v:224$2817 + assign { } { } + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] + end + attribute \src "ls180.v:225.5-225.44" + process $proc$ls180.v:225$2818 + assign { } { } + assign $1\main_libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:226.12-226.49" + process $proc$ls180.v:226$2819 + assign { } { } + assign $1\main_libresocsim_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + end + attribute \src "ls180.v:2263.11-2263.51" + process $proc$ls180.v:2263$3604 + assign { } { } + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:230.5-230.41" + process $proc$ls180.v:230$2820 + assign { } { } + assign $1\main_libresocsim_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + end + attribute \src "ls180.v:232.5-232.39" + process $proc$ls180.v:232$2821 + assign { } { } + assign $1\main_libresocsim_zero_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:233.5-233.45" + process $proc$ls180.v:233$2822 + assign { } { } + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:2344.11-2344.51" + process $proc$ls180.v:2344$3605 + assign { } { } + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2361.11-2361.51" + process $proc$ls180.v:2361$3606 + assign { } { } + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2402.11-2402.52" + process $proc$ls180.v:2402$3607 + assign { } { } + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:242.5-242.49" + process $proc$ls180.v:242$2823 + assign { } { } + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + end + attribute \src "ls180.v:243.5-243.44" + process $proc$ls180.v:243$2824 + assign { } { } + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + end + attribute \src "ls180.v:2435.11-2435.52" + process $proc$ls180.v:2435$3608 + assign { } { } + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:244.12-244.42" + process $proc$ls180.v:244$2825 + assign { } { } + assign $1\main_libresocsim_value[31:0] 0 + sync always + sync init + update \main_libresocsim_value $1\main_libresocsim_value[31:0] + end + attribute \src "ls180.v:2476.11-2476.52" + process $proc$ls180.v:2476$3609 + assign { } { } + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:248.5-248.24" + process $proc$ls180.v:248$2826 + assign { } { } + assign $1\main_int_rst[0:0] 1'1 + sync always + sync init + update \main_int_rst $1\main_int_rst[0:0] + end + attribute \src "ls180.v:2541.11-2541.52" + process $proc$ls180.v:2541$3610 + assign { } { } + assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2566.11-2566.52" + process $proc$ls180.v:2566$3611 + assign { } { } + assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2588.11-2588.31" + process $proc$ls180.v:2588$3612 + assign { } { } + assign $1\builder_state[1:0] 2'00 + sync always + sync init + update \builder_state $1\builder_state[1:0] + end + attribute \src "ls180.v:2589.11-2589.36" + process $proc$ls180.v:2589$3613 + assign { } { } + assign $1\builder_next_state[1:0] 2'00 + sync always + sync init + update \builder_next_state $1\builder_next_state[1:0] + end + attribute \src "ls180.v:2590.11-2590.55" + process $proc$ls180.v:2590$3614 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] + end + attribute \src "ls180.v:2591.5-2591.52" + process $proc$ls180.v:2591$3615 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + end + attribute \src "ls180.v:2592.12-2592.55" + process $proc$ls180.v:2592$3616 + assign { } { } + assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] + end + attribute \src "ls180.v:2593.5-2593.50" + process $proc$ls180.v:2593$3617 + assign { } { } + assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] + end + attribute \src "ls180.v:2594.5-2594.46" + process $proc$ls180.v:2594$3618 + assign { } { } + assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] + end + attribute \src "ls180.v:2595.5-2595.49" + process $proc$ls180.v:2595$3619 + assign { } { } + assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:2596.5-2596.41" + process $proc$ls180.v:2596$3620 + assign { } { } + assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:2597.12-2597.49" + process $proc$ls180.v:2597$3621 + assign { } { } + assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2598.11-2598.47" + process $proc$ls180.v:2598$3622 + assign { } { } + assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:2599.5-2599.41" + process $proc$ls180.v:2599$3623 + assign { } { } + assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2600.5-2600.41" + process $proc$ls180.v:2600$3624 + assign { } { } + assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2601.5-2601.41" + process $proc$ls180.v:2601$3625 + assign { } { } + assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2602.5-2602.39" + process $proc$ls180.v:2602$3626 + assign { } { } + assign $1\builder_comb_t_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:2603.5-2603.39" + process $proc$ls180.v:2603$3627 + assign { } { } + assign $1\builder_comb_t_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:2604.5-2604.39" + process $proc$ls180.v:2604$3628 + assign { } { } + assign $1\builder_comb_t_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:2605.5-2605.41" + process $proc$ls180.v:2605$3629 + assign { } { } + assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2606.12-2606.49" + process $proc$ls180.v:2606$3630 + assign { } { } + assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:2607.11-2607.47" + process $proc$ls180.v:2607$3631 + assign { } { } + assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:2608.5-2608.41" + process $proc$ls180.v:2608$3632 + assign { } { } + assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:2609.5-2609.42" + process $proc$ls180.v:2609$3633 + assign { } { } + assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:2610.5-2610.42" + process $proc$ls180.v:2610$3634 + assign { } { } + assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:2611.5-2611.39" + process $proc$ls180.v:2611$3635 + assign { } { } + assign $1\builder_comb_t_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:2612.5-2612.39" + process $proc$ls180.v:2612$3636 + assign { } { } + assign $1\builder_comb_t_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:2613.5-2613.39" + process $proc$ls180.v:2613$3637 + assign { } { } + assign $1\builder_comb_t_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:2614.12-2614.50" + process $proc$ls180.v:2614$3638 + assign { } { } + assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:2615.5-2615.42" + process $proc$ls180.v:2615$3639 + assign { } { } + assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:2616.5-2616.42" + process $proc$ls180.v:2616$3640 + assign { } { } + assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:2617.12-2617.50" + process $proc$ls180.v:2617$3641 + assign { } { } + assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:2618.5-2618.42" + process $proc$ls180.v:2618$3642 + assign { } { } + assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:2619.5-2619.42" + process $proc$ls180.v:2619$3643 + assign { } { } + assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:2620.12-2620.50" + process $proc$ls180.v:2620$3644 + assign { } { } + assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:2621.5-2621.42" + process $proc$ls180.v:2621$3645 + assign { } { } + assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:2622.5-2622.42" + process $proc$ls180.v:2622$3646 + assign { } { } + assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:2623.12-2623.50" + process $proc$ls180.v:2623$3647 + assign { } { } + assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:2624.5-2624.42" + process $proc$ls180.v:2624$3648 + assign { } { } + assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:2625.5-2625.42" + process $proc$ls180.v:2625$3649 + assign { } { } + assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:2626.12-2626.50" + process $proc$ls180.v:2626$3650 + assign { } { } + assign $1\builder_comb_rhs_array_muxed24[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:2627.12-2627.50" + process $proc$ls180.v:2627$3651 + assign { } { } + assign $1\builder_comb_rhs_array_muxed25[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] + end + attribute \src "ls180.v:2628.11-2628.48" + process $proc$ls180.v:2628$3652 + assign { } { } + assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 + sync always + sync init + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] + end + attribute \src "ls180.v:2629.5-2629.42" + process $proc$ls180.v:2629$3653 + assign { } { } + assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:263.12-263.38" + process $proc$ls180.v:263$2827 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + end + attribute \src "ls180.v:2630.5-2630.42" + process $proc$ls180.v:2630$3654 + assign { } { } + assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:2631.5-2631.42" + process $proc$ls180.v:2631$3655 + assign { } { } + assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:2632.11-2632.48" + process $proc$ls180.v:2632$3656 + assign { } { } + assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 + sync always + sync init + update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:2633.11-2633.48" + process $proc$ls180.v:2633$3657 + assign { } { } + assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:2634.11-2634.47" + process $proc$ls180.v:2634$3658 + assign { } { } + assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 + sync always + sync init + update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:2635.12-2635.49" + process $proc$ls180.v:2635$3659 + assign { } { } + assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2636.5-2636.41" + process $proc$ls180.v:2636$3660 + assign { } { } + assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:2637.5-2637.41" + process $proc$ls180.v:2637$3661 + assign { } { } + assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2638.5-2638.41" + process $proc$ls180.v:2638$3662 + assign { } { } + assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2639.5-2639.41" + process $proc$ls180.v:2639$3663 + assign { } { } + assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:264.5-264.36" + process $proc$ls180.v:264$2828 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:2640.5-2640.41" + process $proc$ls180.v:2640$3664 + assign { } { } + assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2641.5-2641.39" + process $proc$ls180.v:2641$3665 + assign { } { } + assign $1\builder_sync_f_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:2642.5-2642.39" + process $proc$ls180.v:2642$3666 + assign { } { } + assign $1\builder_sync_f_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:265.11-265.32" + process $proc$ls180.v:265$2829 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] + end + attribute \src "ls180.v:268.5-268.36" + process $proc$ls180.v:268$2830 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + end + attribute \src "ls180.v:269.5-269.35" + process $proc$ls180.v:269$2831 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + end + attribute \src "ls180.v:2699.32-2699.66" + process $proc$ls180.v:2699$3667 + assign { } { } + assign $1\builder_multiregimpl0_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] + end + attribute \src "ls180.v:270.5-270.36" + process $proc$ls180.v:270$2832 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + end + attribute \src "ls180.v:2700.32-2700.66" + process $proc$ls180.v:2700$3668 + assign { } { } + assign $1\builder_multiregimpl0_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] + end + attribute \src "ls180.v:2701.32-2701.66" + process $proc$ls180.v:2701$3669 + assign { } { } + assign $1\builder_multiregimpl1_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] + end + attribute \src "ls180.v:2702.32-2702.66" + process $proc$ls180.v:2702$3670 + assign { } { } + assign $1\builder_multiregimpl1_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] + end + attribute \src "ls180.v:2703.32-2703.66" + process $proc$ls180.v:2703$3671 + assign { } { } + assign $1\builder_multiregimpl2_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] + end + attribute \src "ls180.v:2704.32-2704.66" + process $proc$ls180.v:2704$3672 + assign { } { } + assign $1\builder_multiregimpl2_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] + end + attribute \src "ls180.v:2705.32-2705.66" + process $proc$ls180.v:2705$3673 + assign { } { } + assign $1\builder_multiregimpl3_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] + end + attribute \src "ls180.v:2706.32-2706.66" + process $proc$ls180.v:2706$3674 + assign { } { } + assign $1\builder_multiregimpl3_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] + end + attribute \src "ls180.v:2707.32-2707.66" + process $proc$ls180.v:2707$3675 + assign { } { } + assign $1\builder_multiregimpl4_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] + end + attribute \src "ls180.v:2708.32-2708.66" + process $proc$ls180.v:2708$3676 + assign { } { } + assign $1\builder_multiregimpl4_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] + end + attribute \src "ls180.v:2709.32-2709.66" + process $proc$ls180.v:2709$3677 + assign { } { } + assign $1\builder_multiregimpl5_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] + end + attribute \src "ls180.v:271.5-271.35" + process $proc$ls180.v:271$2833 + assign { } { } + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:2710.32-2710.66" + process $proc$ls180.v:2710$3678 + assign { } { } + assign $1\builder_multiregimpl5_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] + end + attribute \src "ls180.v:2711.32-2711.66" + process $proc$ls180.v:2711$3679 + assign { } { } + assign $1\builder_multiregimpl6_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] + end + attribute \src "ls180.v:2712.32-2712.66" + process $proc$ls180.v:2712$3680 + assign { } { } + assign $1\builder_multiregimpl6_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] + end + attribute \src "ls180.v:2713.32-2713.66" + process $proc$ls180.v:2713$3681 + assign { } { } + assign $1\builder_multiregimpl7_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] + end + attribute \src "ls180.v:2714.32-2714.66" + process $proc$ls180.v:2714$3682 + assign { } { } + assign $1\builder_multiregimpl7_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] + end + attribute \src "ls180.v:2715.32-2715.66" + process $proc$ls180.v:2715$3683 + assign { } { } + assign $1\builder_multiregimpl8_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] + end + attribute \src "ls180.v:2716.32-2716.66" + process $proc$ls180.v:2716$3684 + assign { } { } + assign $1\builder_multiregimpl8_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] + end + attribute \src "ls180.v:2717.32-2717.66" + process $proc$ls180.v:2717$3685 + assign { } { } + assign $1\builder_multiregimpl9_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] + end + attribute \src "ls180.v:2718.32-2718.66" + process $proc$ls180.v:2718$3686 + assign { } { } + assign $1\builder_multiregimpl9_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] + end + attribute \src "ls180.v:2719.32-2719.67" + process $proc$ls180.v:2719$3687 + assign { } { } + assign $1\builder_multiregimpl10_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] + end + attribute \src "ls180.v:2720.32-2720.67" + process $proc$ls180.v:2720$3688 + assign { } { } + assign $1\builder_multiregimpl10_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] + end + attribute \src "ls180.v:2721.32-2721.67" + process $proc$ls180.v:2721$3689 + assign { } { } + assign $1\builder_multiregimpl11_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] + end + attribute \src "ls180.v:2722.32-2722.67" + process $proc$ls180.v:2722$3690 + assign { } { } + assign $1\builder_multiregimpl11_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] + end + attribute \src "ls180.v:2723.32-2723.67" + process $proc$ls180.v:2723$3691 + assign { } { } + assign $1\builder_multiregimpl12_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] + end + attribute \src "ls180.v:2724.32-2724.67" + process $proc$ls180.v:2724$3692 + assign { } { } + assign $1\builder_multiregimpl12_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] + end + attribute \src "ls180.v:2725.32-2725.67" + process $proc$ls180.v:2725$3693 + assign { } { } + assign $1\builder_multiregimpl13_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] + end + attribute \src "ls180.v:2726.32-2726.67" + process $proc$ls180.v:2726$3694 + assign { } { } + assign $1\builder_multiregimpl13_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] + end + attribute \src "ls180.v:2727.32-2727.67" + process $proc$ls180.v:2727$3695 + assign { } { } + assign $1\builder_multiregimpl14_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] + end + attribute \src "ls180.v:2728.32-2728.67" + process $proc$ls180.v:2728$3696 + assign { } { } + assign $1\builder_multiregimpl14_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] + end + attribute \src "ls180.v:2729.32-2729.67" + process $proc$ls180.v:2729$3697 + assign { } { } + assign $1\builder_multiregimpl15_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] + end + attribute \src "ls180.v:2730.32-2730.67" + process $proc$ls180.v:2730$3698 + assign { } { } + assign $1\builder_multiregimpl15_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] + end + attribute \src "ls180.v:2731.32-2731.67" + process $proc$ls180.v:2731$3699 + assign { } { } + assign $1\builder_multiregimpl16_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] + end + attribute \src "ls180.v:2732.32-2732.67" + process $proc$ls180.v:2732$3700 + assign { } { } + assign $1\builder_multiregimpl16_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:275.5-275.36" + process $proc$ls180.v:275$2834 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:2767.1-2772.4" + process $proc$ls180.v:2767$13 + assign { } { } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 + assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq + assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq + sync always + update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:2774.1-2784.4" + process $proc$ls180.v:2774$15 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2776.2-2783.9" + switch \main_libresocsim_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:2786.1-2832.4" + process $proc$ls180.v:2786$16 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + assign $0\main_libresocsim_converter0_skip[0:0] 1'0 + assign { } { } + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign $0\builder_converter0_next_state[0:0] \builder_converter0_state + attribute \src "ls180.v:2798.2-2831.9" + switch \builder_converter0_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } + attribute \src "ls180.v:2801.4-2808.11" + switch \main_libresocsim_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] + case + end + attribute \src "ls180.v:2809.4-2822.7" + switch $and$ls180.v:2809$17_Y + attribute \src "ls180.v:2809.8-2809.81" + case 1'1 + assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2810$18_Y + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2812$19_Y + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2813$20_Y + attribute \src "ls180.v:2814.5-2821.8" + switch $or$ls180.v:2814$21_Y + attribute \src "ls180.v:2814.9-2814.97" + case 1'1 + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2815$22_Y + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2817.6-2820.9" + switch $eq$ls180.v:2817$23_Y + attribute \src "ls180.v:2817.10-2817.55" + case 1'1 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 + assign $0\builder_converter0_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2827.4-2829.7" + switch $and$ls180.v:2827$24_Y + attribute \src "ls180.v:2827.8-2827.81" + case 1'1 + assign $0\builder_converter0_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] + update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] + update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] + update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] + update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] + update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] + update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:280.12-280.45" + process $proc$ls180.v:280$2835 + assign { } { } + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + end + attribute \src "ls180.v:281.5-281.43" + process $proc$ls180.v:281$2836 + assign { } { } + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:2834.1-2844.4" + process $proc$ls180.v:2834$26 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2836.2-2843.9" + switch \main_libresocsim_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:2846.1-2892.4" + process $proc$ls180.v:2846$27 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_converter1_skip[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign { } { } + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign $0\builder_converter1_next_state[0:0] \builder_converter1_state + attribute \src "ls180.v:2858.2-2891.9" + switch \builder_converter1_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } + attribute \src "ls180.v:2861.4-2868.11" + switch \main_libresocsim_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] + case + end + attribute \src "ls180.v:2869.4-2882.7" + switch $and$ls180.v:2869$28_Y + attribute \src "ls180.v:2869.8-2869.81" + case 1'1 + assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2870$29_Y + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2872$30_Y + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2873$31_Y + attribute \src "ls180.v:2874.5-2881.8" + switch $or$ls180.v:2874$32_Y + attribute \src "ls180.v:2874.9-2874.97" + case 1'1 + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2875$33_Y + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2877.6-2880.9" + switch $eq$ls180.v:2877$34_Y + attribute \src "ls180.v:2877.10-2877.55" + case 1'1 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 + assign $0\builder_converter1_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2887.4-2889.7" + switch $and$ls180.v:2887$35_Y + attribute \src "ls180.v:2887.8-2887.81" + case 1'1 + assign $0\builder_converter1_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] + update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] + update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] + update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] + update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] + update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] + update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:2894.1-2904.4" + process $proc$ls180.v:2894$37 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2896.2-2903.9" + switch \main_libresocsim_converter2_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:2906.1-2952.4" + process $proc$ls180.v:2906$38 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_converter2_skip[0:0] 1'0 + assign $0\builder_converter2_next_state[0:0] \builder_converter2_state + attribute \src "ls180.v:2918.2-2951.9" + switch \builder_converter2_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } + attribute \src "ls180.v:2921.4-2928.11" + switch \main_libresocsim_converter2_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] + case + end + attribute \src "ls180.v:2929.4-2942.7" + switch $and$ls180.v:2929$39_Y + attribute \src "ls180.v:2929.8-2929.87" + case 1'1 + assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2930$40_Y + assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2932$41_Y + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2933$42_Y + attribute \src "ls180.v:2934.5-2941.8" + switch $or$ls180.v:2934$43_Y + attribute \src "ls180.v:2934.9-2934.97" + case 1'1 + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2935$44_Y + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2937.6-2940.9" + switch $eq$ls180.v:2937$45_Y + attribute \src "ls180.v:2937.10-2937.55" + case 1'1 + assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 + assign $0\builder_converter2_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2947.4-2949.7" + switch $and$ls180.v:2947$46_Y + attribute \src "ls180.v:2947.8-2947.87" + case 1'1 + assign $0\builder_converter2_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_jtag_wb_ack $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] + update \main_libresocsim_interface2_converted_interface_adr $0\main_libresocsim_interface2_converted_interface_adr[29:0] + update \main_libresocsim_interface2_converted_interface_sel $0\main_libresocsim_interface2_converted_interface_sel[3:0] + update \main_libresocsim_interface2_converted_interface_cyc $0\main_libresocsim_interface2_converted_interface_cyc[0:0] + update \main_libresocsim_interface2_converted_interface_stb $0\main_libresocsim_interface2_converted_interface_stb[0:0] + update \main_libresocsim_interface2_converted_interface_we $0\main_libresocsim_interface2_converted_interface_we[0:0] + update \main_libresocsim_converter2_skip $0\main_libresocsim_converter2_skip[0:0] + update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] + update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] + update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:2955.1-2961.4" + process $proc$ls180.v:2955$47 + assign { } { } + assign { } { } + assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2957$50_Y + assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2958$53_Y + assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2959$56_Y + assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2960$59_Y + sync always + update \main_libresocsim_we $0\main_libresocsim_we[3:0] + end + attribute \src "ls180.v:296.12-296.46" + process $proc$ls180.v:296$2837 + assign { } { } + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + end + attribute \src "ls180.v:2967.1-2972.4" + process $proc$ls180.v:2967$61 + assign { } { } + assign $0\main_libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:2969.2-2971.5" + switch $and$ls180.v:2969$62_Y + attribute \src "ls180.v:2969.6-2969.90" + case 1'1 + assign $0\main_libresocsim_zero_clear[0:0] 1'1 + case + end + sync always + update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:297.5-297.44" + process $proc$ls180.v:297$2838 + assign { } { } + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:298.12-298.48" + process $proc$ls180.v:298$2839 + assign { } { } + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + end + attribute \src "ls180.v:299.11-299.43" + process $proc$ls180.v:299$2840 + assign { } { } + assign $1\main_sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] + end + attribute \src "ls180.v:300.5-300.38" + process $proc$ls180.v:300$2841 + assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + end + attribute \src "ls180.v:301.5-301.37" + process $proc$ls180.v:301$2842 + assign { } { } + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] + end + attribute \src "ls180.v:3011.1-3065.4" + process $proc$ls180.v:3011$64 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_act_n[0:0] 1'1 + assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_master_p0_bank[1:0] 2'00 + assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_master_p0_we_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cke[0:0] 1'0 + assign $0\main_sdram_master_p0_odt[0:0] 1'0 + assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + attribute \src "ls180.v:3030.2-3064.5" + switch \main_sdram_sel + attribute \src "ls180.v:3030.6-3030.20" + case 1'1 + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en + assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:3047.6-3047.10" + case + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en + assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + end + sync always + update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] + update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] + update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] + update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] + update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] + update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] + update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] + update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] + update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] + update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] + update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] + update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] + update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] + update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] + update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:302.5-302.38" + process $proc$ls180.v:302$2843 + assign { } { } + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] + end + attribute \src "ls180.v:303.5-303.37" + process $proc$ls180.v:303$2844 + assign { } { } + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] + end + attribute \src "ls180.v:304.5-304.36" + process $proc$ls180.v:304$2845 + assign { } { } + assign $1\main_sdram_master_p0_cke[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] + end + attribute \src "ls180.v:305.5-305.36" + process $proc$ls180.v:305$2846 + assign { } { } + assign $1\main_sdram_master_p0_odt[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + end + attribute \src "ls180.v:306.5-306.40" + process $proc$ls180.v:306$2847 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "ls180.v:3069.1-3085.4" + process $proc$ls180.v:3069$65 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + attribute \src "ls180.v:3074.2-3084.5" + switch \main_sdram_command_issue_re + attribute \src "ls180.v:3074.6-3074.33" + case 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3075$66_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3076$67_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3077$68_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3078$69_Y + attribute \src "ls180.v:3079.6-3079.10" + case + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + end + sync always + update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] + update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] + update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] + update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:307.5-307.38" + process $proc$ls180.v:307$2848 + assign { } { } + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "ls180.v:308.12-308.47" + process $proc$ls180.v:308$2849 + assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "ls180.v:309.5-309.42" + process $proc$ls180.v:309$2850 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:310.11-310.50" + process $proc$ls180.v:310$2851 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:311.5-311.42" + process $proc$ls180.v:311$2852 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:3128.1-3158.4" + process $proc$ls180.v:3128$78 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_cmd_last[0:0] 1'0 + assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign { } { } + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\builder_refresher_next_state[1:0] \builder_refresher_state + attribute \src "ls180.v:3134.2-3157.9" + switch \builder_refresher_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3137.4-3140.7" + switch \main_sdram_cmd_ready + attribute \src "ls180.v:3137.8-3137.28" + case 1'1 + assign $0\main_sdram_sequencer_start0[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3144.4-3148.7" + switch \main_sdram_sequencer_done0 + attribute \src "ls180.v:3144.8-3144.34" + case 1'1 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\main_sdram_cmd_last[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3151.4-3155.7" + switch 1'1 + attribute \src "ls180.v:3151.8-3151.12" + case 1'1 + attribute \src "ls180.v:3152.5-3154.8" + switch \main_sdram_wants_refresh + attribute \src "ls180.v:3152.9-3152.33" + case 1'1 + assign $0\builder_refresher_next_state[1:0] 2'01 + case + end + case + end + end + sync always + update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] + update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] + update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] + update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:3173.1-3180.4" + process $proc$ls180.v:3173$82 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3175.2-3179.5" + switch \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:3175.6-3175.48" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3177.6-3177.10" + case + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3178$84_Y + end + sync always + update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:318.11-318.36" + process $proc$ls180.v:318$2853 + assign { } { } + assign $1\main_sdram_storage[3:0] 4'0001 + sync always + sync init + update \main_sdram_storage $1\main_sdram_storage[3:0] + end + attribute \src "ls180.v:3184.1-3191.4" + process $proc$ls180.v:3184$91 + assign { } { } + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3186.2-3190.5" + switch $and$ls180.v:3186$92_Y + attribute \src "ls180.v:3186.6-3186.115" + case 1'1 + attribute \src "ls180.v:3187.3-3189.6" + switch $ne$ls180.v:3187$93_Y + attribute \src "ls180.v:3187.7-3187.143" + case 1'1 + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3188$94_Y + case + end + case + end + sync always + update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:319.5-319.25" + process $proc$ls180.v:319$2854 + assign { } { } + assign $1\main_sdram_re[0:0] 1'0 + sync always + sync init + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "ls180.v:320.11-320.44" + process $proc$ls180.v:320$2855 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "ls180.v:3206.1-3213.4" + process $proc$ls180.v:3206$95 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3208.2-3212.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3208.6-3208.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3209$96_Y + attribute \src "ls180.v:3210.6-3210.10" + case + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:321.5-321.33" + process $proc$ls180.v:321$2856 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:3222.1-3315.4" + process $proc$ls180.v:3222$104 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state + attribute \src "ls180.v:3238.2-3314.9" + switch \builder_bankmachine0_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3240.4-3248.7" + switch $and$ls180.v:3240$105_Y + attribute \src "ls180.v:3240.8-3240.87" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3242.5-3244.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3242.9-3242.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3252.4-3254.7" + switch $and$ls180.v:3252$106_Y + attribute \src "ls180.v:3252.8-3252.87" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3258.4-3267.7" + switch \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:3258.8-3258.44" + case 1'1 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3263.5-3265.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3263.9-3263.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3270.4-3272.7" + switch \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:3270.8-3270.45" + case 1'1 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3275.4-3277.7" + switch $not$ls180.v:3275$107_Y + attribute \src "ls180.v:3275.8-3275.46" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3286.4-3312.7" + switch \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:3286.8-3286.43" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'100 + attribute \src "ls180.v:3288.8-3288.12" + case + attribute \src "ls180.v:3289.5-3311.8" + switch \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:3289.9-3289.56" + case 1'1 + attribute \src "ls180.v:3290.6-3310.9" + switch \main_sdram_bankmachine0_row_opened + attribute \src "ls180.v:3290.10-3290.44" + case 1'1 + attribute \src "ls180.v:3291.7-3307.10" + switch \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:3291.11-3291.42" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3293.8-3300.11" + switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:3293.12-3293.64" + case 1'1 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3297.12-3297.16" + case + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3302.8-3304.11" + switch $and$ls180.v:3302$108_Y + attribute \src "ls180.v:3302.12-3302.88" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3305.11-3305.15" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3308.10-3308.14" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] + update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] + update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:325.5-325.38" + process $proc$ls180.v:325$2857 + assign { } { } + assign $0\main_sdram_command_issue_w[0:0] 1'0 + sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] + sync init + end + attribute \src "ls180.v:326.12-326.46" + process $proc$ls180.v:326$2858 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:327.5-327.33" + process $proc$ls180.v:327$2859 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "ls180.v:328.11-328.45" + process $proc$ls180.v:328$2860 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:329.5-329.34" + process $proc$ls180.v:329$2861 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:330.12-330.45" + process $proc$ls180.v:330$2862 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:331.5-331.32" + process $proc$ls180.v:331$2863 + assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:332.12-332.37" + process $proc$ls180.v:332$2864 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "ls180.v:3330.1-3337.4" + process $proc$ls180.v:3330$112 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3332.2-3336.5" + switch \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:3332.6-3332.48" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3334.6-3334.10" + case + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3335$114_Y + end + sync always + update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3341.1-3348.4" + process $proc$ls180.v:3341$121 + assign { } { } + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3343.2-3347.5" + switch $and$ls180.v:3343$122_Y + attribute \src "ls180.v:3343.6-3343.115" + case 1'1 + attribute \src "ls180.v:3344.3-3346.6" + switch $ne$ls180.v:3344$123_Y + attribute \src "ls180.v:3344.7-3344.143" + case 1'1 + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3345$124_Y + case + end + case + end + sync always + update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:3363.1-3370.4" + process $proc$ls180.v:3363$125 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3365.2-3369.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3365.6-3365.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3366$126_Y + attribute \src "ls180.v:3367.6-3367.10" + case + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3379.1-3472.4" + process $proc$ls180.v:3379$134 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state + attribute \src "ls180.v:3395.2-3471.9" + switch \builder_bankmachine1_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3397.4-3405.7" + switch $and$ls180.v:3397$135_Y + attribute \src "ls180.v:3397.8-3397.87" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3399.5-3401.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3399.9-3399.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3409.4-3411.7" + switch $and$ls180.v:3409$136_Y + attribute \src "ls180.v:3409.8-3409.87" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3415.4-3424.7" + switch \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:3415.8-3415.44" + case 1'1 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3420.5-3422.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3420.9-3420.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3427.4-3429.7" + switch \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:3427.8-3427.45" + case 1'1 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3432.4-3434.7" + switch $not$ls180.v:3432$137_Y + attribute \src "ls180.v:3432.8-3432.46" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3443.4-3469.7" + switch \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:3443.8-3443.43" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'100 + attribute \src "ls180.v:3445.8-3445.12" + case + attribute \src "ls180.v:3446.5-3468.8" + switch \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:3446.9-3446.56" + case 1'1 + attribute \src "ls180.v:3447.6-3467.9" + switch \main_sdram_bankmachine1_row_opened + attribute \src "ls180.v:3447.10-3447.44" + case 1'1 + attribute \src "ls180.v:3448.7-3464.10" + switch \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:3448.11-3448.42" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3450.8-3457.11" + switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:3450.12-3450.64" + case 1'1 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3454.12-3454.16" + case + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3459.8-3461.11" + switch $and$ls180.v:3459$138_Y + attribute \src "ls180.v:3459.12-3459.88" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3462.11-3462.15" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3465.10-3465.14" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] + update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:3487.1-3494.4" + process $proc$ls180.v:3487$142 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3489.2-3493.5" + switch \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:3489.6-3489.48" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3491.6-3491.10" + case + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3492$144_Y + end + sync always + update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3498.1-3505.4" + process $proc$ls180.v:3498$151 + assign { } { } + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3500.2-3504.5" + switch $and$ls180.v:3500$152_Y + attribute \src "ls180.v:3500.6-3500.115" + case 1'1 + attribute \src "ls180.v:3501.3-3503.6" + switch $ne$ls180.v:3501$153_Y + attribute \src "ls180.v:3501.7-3501.143" + case 1'1 + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3502$154_Y + case + end + case + end + sync always + update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:3520.1-3527.4" + process $proc$ls180.v:3520$155 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3522.2-3526.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3522.6-3522.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3523$156_Y + attribute \src "ls180.v:3524.6-3524.10" + case + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3536.1-3629.4" + process $proc$ls180.v:3536$164 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state + attribute \src "ls180.v:3552.2-3628.9" + switch \builder_bankmachine2_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3554.4-3562.7" + switch $and$ls180.v:3554$165_Y + attribute \src "ls180.v:3554.8-3554.87" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3556.5-3558.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3556.9-3556.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3566.4-3568.7" + switch $and$ls180.v:3566$166_Y + attribute \src "ls180.v:3566.8-3566.87" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3572.4-3581.7" + switch \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:3572.8-3572.44" + case 1'1 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3577.5-3579.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3577.9-3577.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3584.4-3586.7" + switch \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:3584.8-3584.45" + case 1'1 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3589.4-3591.7" + switch $not$ls180.v:3589$167_Y + attribute \src "ls180.v:3589.8-3589.46" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3600.4-3626.7" + switch \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:3600.8-3600.43" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'100 + attribute \src "ls180.v:3602.8-3602.12" + case + attribute \src "ls180.v:3603.5-3625.8" + switch \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:3603.9-3603.56" + case 1'1 + attribute \src "ls180.v:3604.6-3624.9" + switch \main_sdram_bankmachine2_row_opened + attribute \src "ls180.v:3604.10-3604.44" + case 1'1 + attribute \src "ls180.v:3605.7-3621.10" + switch \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:3605.11-3605.42" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3607.8-3614.11" + switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:3607.12-3607.64" + case 1'1 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3611.12-3611.16" + case + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3616.8-3618.11" + switch $and$ls180.v:3616$168_Y + attribute \src "ls180.v:3616.12-3616.88" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3619.11-3619.15" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3622.10-3622.14" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] + update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] + update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] + update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:362.12-362.46" + process $proc$ls180.v:362$2865 + assign { } { } + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + end + attribute \src "ls180.v:363.11-363.47" + process $proc$ls180.v:363$2866 + assign { } { } + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:3644.1-3651.4" + process $proc$ls180.v:3644$172 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3646.2-3650.5" + switch \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:3646.6-3646.48" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3648.6-3648.10" + case + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3649$174_Y + end + sync always + update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:365.12-365.45" + process $proc$ls180.v:365$2867 + assign { } { } + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + end + attribute \src "ls180.v:3655.1-3662.4" + process $proc$ls180.v:3655$181 + assign { } { } + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3657.2-3661.5" + switch $and$ls180.v:3657$182_Y + attribute \src "ls180.v:3657.6-3657.115" + case 1'1 + attribute \src "ls180.v:3658.3-3660.6" + switch $ne$ls180.v:3658$183_Y + attribute \src "ls180.v:3658.7-3658.143" + case 1'1 + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3659$184_Y + case + end + case + end + sync always + update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:366.11-366.40" + process $proc$ls180.v:366$2868 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:367.5-367.35" + process $proc$ls180.v:367$2869 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + end + attribute \src "ls180.v:3677.1-3684.4" + process $proc$ls180.v:3677$185 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3679.2-3683.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3679.6-3679.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3680$186_Y + attribute \src "ls180.v:3681.6-3681.10" + case + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:368.5-368.34" + process $proc$ls180.v:368$2870 + assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "ls180.v:369.5-369.35" + process $proc$ls180.v:369$2871 + assign { } { } + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + end + attribute \src "ls180.v:3693.1-3786.4" + process $proc$ls180.v:3693$194 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state + attribute \src "ls180.v:3709.2-3785.9" + switch \builder_bankmachine3_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3711.4-3719.7" + switch $and$ls180.v:3711$195_Y + attribute \src "ls180.v:3711.8-3711.87" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3713.5-3715.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3713.9-3713.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3723.4-3725.7" + switch $and$ls180.v:3723$196_Y + attribute \src "ls180.v:3723.8-3723.87" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3729.4-3738.7" + switch \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:3729.8-3729.44" + case 1'1 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3734.5-3736.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3734.9-3734.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3741.4-3743.7" + switch \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:3741.8-3741.45" + case 1'1 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3746.4-3748.7" + switch $not$ls180.v:3746$197_Y + attribute \src "ls180.v:3746.8-3746.46" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3757.4-3783.7" + switch \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:3757.8-3757.43" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'100 + attribute \src "ls180.v:3759.8-3759.12" + case + attribute \src "ls180.v:3760.5-3782.8" + switch \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:3760.9-3760.56" + case 1'1 + attribute \src "ls180.v:3761.6-3781.9" + switch \main_sdram_bankmachine3_row_opened + attribute \src "ls180.v:3761.10-3761.44" + case 1'1 + attribute \src "ls180.v:3762.7-3778.10" + switch \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:3762.11-3762.42" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3764.8-3771.11" + switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:3764.12-3764.64" + case 1'1 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3768.12-3768.16" + case + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3773.8-3775.11" + switch $and$ls180.v:3773$198_Y + attribute \src "ls180.v:3773.12-3773.88" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3776.11-3776.15" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3779.10-3779.14" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] + update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] + update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] + update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:370.5-370.34" + process $proc$ls180.v:370$2872 + assign { } { } + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + end + attribute \src "ls180.v:374.5-374.35" + process $proc$ls180.v:374$2873 + assign { } { } + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:376.5-376.39" + process $proc$ls180.v:376$2874 + assign { } { } + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:378.5-378.39" + process $proc$ls180.v:378$2875 + assign { } { } + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + end + attribute \src "ls180.v:3806.1-3812.4" + process $proc$ls180.v:3806$237 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3808$250_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3809$263_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3810$276_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3811$289_Y + sync always + update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:381.5-381.32" + process $proc$ls180.v:381$2876 + assign { } { } + assign $1\main_sdram_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + end + attribute \src "ls180.v:382.5-382.32" + process $proc$ls180.v:382$2877 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + end + attribute \src "ls180.v:3820.1-3825.4" + process $proc$ls180.v:3820$290 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3822.2-3824.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3822.6-3822.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3826.1-3831.4" + process $proc$ls180.v:3826$291 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3828.2-3830.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3828.6-3828.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:383.5-383.31" + process $proc$ls180.v:383$2878 + assign { } { } + assign $1\main_sdram_cmd_last[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] + end + attribute \src "ls180.v:3832.1-3837.4" + process $proc$ls180.v:3832$292 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3834.2-3836.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3834.6-3834.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3839.1-3845.4" + process $proc$ls180.v:3839$295 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3841$308_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3842$321_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3843$334_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3844$347_Y + sync always + update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:384.12-384.44" + process $proc$ls180.v:384$2879 + assign { } { } + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + end + attribute \src "ls180.v:385.11-385.43" + process $proc$ls180.v:385$2880 + assign { } { } + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + end + attribute \src "ls180.v:3853.1-3858.4" + process $proc$ls180.v:3853$348 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3855.2-3857.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3855.6-3855.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3859.1-3864.4" + process $proc$ls180.v:3859$349 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3861.2-3863.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3861.6-3861.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:386.5-386.38" + process $proc$ls180.v:386$2881 + assign { } { } + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3865.1-3870.4" + process $proc$ls180.v:3865$350 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3867.2-3869.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3867.6-3867.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:387.5-387.38" + process $proc$ls180.v:387$2882 + assign { } { } + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3871.1-3879.4" + process $proc$ls180.v:3871$351 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3873.2-3875.5" + switch $and$ls180.v:3873$354_Y + attribute \src "ls180.v:3873.6-3873.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3876.2-3878.5" + switch $and$ls180.v:3876$357_Y + attribute \src "ls180.v:3876.6-3876.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:388.5-388.37" + process $proc$ls180.v:388$2883 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3880.1-3888.4" + process $proc$ls180.v:3880$358 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3882.2-3884.5" + switch $and$ls180.v:3882$361_Y + attribute \src "ls180.v:3882.6-3882.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3885.2-3887.5" + switch $and$ls180.v:3885$364_Y + attribute \src "ls180.v:3885.6-3885.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:3889.1-3897.4" + process $proc$ls180.v:3889$365 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3891.2-3893.5" + switch $and$ls180.v:3891$368_Y + attribute \src "ls180.v:3891.6-3891.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3894.2-3896.5" + switch $and$ls180.v:3894$371_Y + attribute \src "ls180.v:3894.6-3894.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:389.5-389.42" + process $proc$ls180.v:389$2884 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init + end + attribute \src "ls180.v:3898.1-3906.4" + process $proc$ls180.v:3898$372 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3900.2-3902.5" + switch $and$ls180.v:3900$375_Y + attribute \src "ls180.v:3900.6-3900.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3903.2-3905.5" + switch $and$ls180.v:3903$378_Y + attribute \src "ls180.v:3903.6-3903.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:390.5-390.43" + process $proc$ls180.v:390$2885 + assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] + sync init + end + attribute \src "ls180.v:3911.1-3983.4" + process $proc$ls180.v:3911$381 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdram_en0[0:0] 1'0 + assign $0\main_sdram_en1[0:0] 1'0 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 + assign $0\main_sdram_cmd_ready[0:0] 1'0 + assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed + assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state + attribute \src "ls180.v:3923.2-3982.9" + switch \builder_multiplexer_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_en1[0:0] 1'1 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:3927.4-3933.7" + switch 1'1 + attribute \src "ls180.v:3927.8-3927.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3928$388_Y + case + end + attribute \src "ls180.v:3935.4-3939.7" + switch \main_sdram_read_available + attribute \src "ls180.v:3935.8-3935.33" + case 1'1 + attribute \src "ls180.v:3936.5-3938.8" + switch $or$ls180.v:3936$390_Y + attribute \src "ls180.v:3936.9-3936.63" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'011 + case + end + case + end + attribute \src "ls180.v:3940.4-3942.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:3940.8-3940.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_steerer_sel[1:0] 2'11 + assign $0\main_sdram_cmd_ready[0:0] 1'1 + attribute \src "ls180.v:3947.4-3949.7" + switch \main_sdram_cmd_last + attribute \src "ls180.v:3947.8-3947.27" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3952.4-3954.7" + switch \main_sdram_twtrcon_ready + attribute \src "ls180.v:3952.8-3952.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_multiplexer_next_state[2:0] 3'101 + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_multiplexer_next_state[2:0] 3'001 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_en0[0:0] 1'1 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:3965.4-3971.7" + switch 1'1 + attribute \src "ls180.v:3965.8-3965.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3966$397_Y + case + end + attribute \src "ls180.v:3973.4-3977.7" + switch \main_sdram_write_available + attribute \src "ls180.v:3973.8-3973.34" + case 1'1 + attribute \src "ls180.v:3974.5-3976.8" + switch $or$ls180.v:3974$399_Y + attribute \src "ls180.v:3974.9-3974.62" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'100 + case + end + case + end + attribute \src "ls180.v:3978.4-3980.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:3978.8-3978.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + end + sync always + update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] + update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] + update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] + update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] + update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] + update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] + update \main_sdram_en0 $0\main_sdram_en0[0:0] + update \main_sdram_en1 $0\main_sdram_en1[0:0] + update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:396.11-396.44" + process $proc$ls180.v:396$2886 + assign { } { } + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + end + attribute \src "ls180.v:398.5-398.38" + process $proc$ls180.v:398$2887 + assign { } { } + assign $1\main_sdram_postponer_req_o[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + end + attribute \src "ls180.v:399.5-399.38" + process $proc$ls180.v:399$2888 + assign { } { } + assign $1\main_sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + end + attribute \src "ls180.v:400.5-400.39" + process $proc$ls180.v:400$2889 + assign { } { } + assign $1\main_sdram_sequencer_start0[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + end + attribute \src "ls180.v:4007.1-4020.4" + process $proc$ls180.v:4007$528 + assign { } { } + assign { } { } + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + attribute \src "ls180.v:4010.2-4019.9" + switch \builder_new_master_wdata_ready + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data + assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + end + sync always + update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] + update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:4027.1-4037.4" + process $proc$ls180.v:4027$530 + assign { } { } + assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + attribute \src "ls180.v:4029.2-4036.9" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] + case + end + sync always + update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:403.5-403.38" + process $proc$ls180.v:403$2890 + assign { } { } + assign $1\main_sdram_sequencer_done1[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + end + attribute \src "ls180.v:4039.1-4085.4" + process $proc$ls180.v:4039$531 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_litedram_wb_we[0:0] 1'0 + assign $0\main_converter_skip[0:0] 1'0 + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign { } { } + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 + assign $0\main_litedram_wb_sel[1:0] 2'00 + assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign $0\main_litedram_wb_stb[0:0] 1'0 + assign $0\builder_converter_next_state[0:0] \builder_converter_state + attribute \src "ls180.v:4051.2-4084.9" + switch \builder_converter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } + attribute \src "ls180.v:4054.4-4061.11" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] + case + end + attribute \src "ls180.v:4062.4-4075.7" + switch $and$ls180.v:4062$532_Y + attribute \src "ls180.v:4062.8-4062.47" + case 1'1 + assign $0\main_converter_skip[0:0] $eq$ls180.v:4063$533_Y + assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4065$534_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4066$535_Y + attribute \src "ls180.v:4067.5-4074.8" + switch $or$ls180.v:4067$536_Y + attribute \src "ls180.v:4067.9-4067.53" + case 1'1 + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4068$537_Y + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4070.6-4073.9" + switch $eq$ls180.v:4070$538_Y + attribute \src "ls180.v:4070.10-4070.42" + case 1'1 + assign $0\main_wb_sdram_ack[0:0] 1'1 + assign $0\builder_converter_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4080.4-4082.7" + switch $and$ls180.v:4080$539_Y + attribute \src "ls180.v:4080.8-4080.47" + case 1'1 + assign $0\builder_converter_next_state[0:0] 1'1 + case + end + end + sync always + update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] + update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] + update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] + update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] + update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] + update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] + update \main_converter_skip $0\main_converter_skip[0:0] + update \builder_converter_next_state $0\builder_converter_next_state[0:0] + update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] + update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:404.11-404.46" + process $proc$ls180.v:404$2891 + assign { } { } + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + sync always + sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + end + attribute \src "ls180.v:405.5-405.38" + process $proc$ls180.v:405$2892 + assign { } { } + assign $1\main_sdram_sequencer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + end + attribute \src "ls180.v:411.5-411.51" + process $proc$ls180.v:411$2893 + assign { } { } + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:412.5-412.51" + process $proc$ls180.v:412$2894 + assign { } { } + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + end + attribute \src "ls180.v:4130.1-4135.4" + process $proc$ls180.v:4130$571 + assign { } { } + assign $0\main_uart_tx_clear[0:0] 1'0 + attribute \src "ls180.v:4132.2-4134.5" + switch $and$ls180.v:4132$572_Y + attribute \src "ls180.v:4132.6-4132.79" + case 1'1 + assign $0\main_uart_tx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:4136.1-4140.4" + process $proc$ls180.v:4136$573 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status + assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status + sync always + update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:414.5-414.47" + process $proc$ls180.v:414$2895 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:4141.1-4146.4" + process $proc$ls180.v:4141$574 + assign { } { } + assign $0\main_uart_rx_clear[0:0] 1'0 + attribute \src "ls180.v:4143.2-4145.5" + switch $and$ls180.v:4143$575_Y + attribute \src "ls180.v:4143.6-4143.79" + case 1'1 + assign $0\main_uart_rx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:4147.1-4151.4" + process $proc$ls180.v:4147$576 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending + assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending + sync always + update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:415.5-415.45" + process $proc$ls180.v:415$2896 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:416.5-416.45" + process $proc$ls180.v:416$2897 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:4169.1-4176.4" + process $proc$ls180.v:4169$584 + assign { } { } + assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4171.2-4175.5" + switch \main_uart_tx_fifo_replace + attribute \src "ls180.v:4171.6-4171.31" + case 1'1 + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4172$585_Y + attribute \src "ls180.v:4173.6-4173.10" + case + assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce + end + sync always + update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:417.12-417.57" + process $proc$ls180.v:417$2898 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:419.5-419.51" + process $proc$ls180.v:419$2899 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:4199.1-4206.4" + process $proc$ls180.v:4199$595 + assign { } { } + assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4201.2-4205.5" + switch \main_uart_rx_fifo_replace + attribute \src "ls180.v:4201.6-4201.31" + case 1'1 + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4202$596_Y + attribute \src "ls180.v:4203.6-4203.10" + case + assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce + end + sync always + update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:420.5-420.51" + process $proc$ls180.v:420$2900 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:421.5-421.50" + process $proc$ls180.v:421$2901 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:422.5-422.54" + process $proc$ls180.v:422$2902 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:4229.1-4277.4" + process $proc$ls180.v:4229$606 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spimaster25_clk_enable[0:0] 1'0 + assign $0\main_spimaster26_cs_enable[0:0] 1'0 + assign { } { } + assign $0\main_spimaster28_mosi_latch[0:0] 1'0 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 + assign $0\main_spimaster29_miso_latch[0:0] 1'0 + assign $0\main_spimaster3_irq[0:0] 1'0 + assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state + attribute \src "ls180.v:4240.2-4276.9" + switch \builder_spimaster0_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4244.4-4247.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4244.8-4244.33" + case 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spimaster25_clk_enable[0:0] 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4252.4-4258.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4252.8-4252.33" + case 1'1 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4253$607_Y + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4255.5-4257.8" + switch $eq$ls180.v:4255$609_Y + attribute \src "ls180.v:4255.9-4255.68" + case 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4262.4-4266.7" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:4262.8-4262.33" + case 1'1 + assign $0\main_spimaster29_miso_latch[0:0] 1'1 + assign $0\main_spimaster3_irq[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spimaster2_done[0:0] 1'1 + attribute \src "ls180.v:4270.4-4274.7" + switch \main_spimaster0_start + attribute \src "ls180.v:4270.8-4270.29" + case 1'1 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster28_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spimaster2_done $0\main_spimaster2_done[0:0] + update \main_spimaster3_irq $0\main_spimaster3_irq[0:0] + update \main_spimaster25_clk_enable $0\main_spimaster25_clk_enable[0:0] + update \main_spimaster26_cs_enable $0\main_spimaster26_cs_enable[0:0] + update \main_spimaster28_mosi_latch $0\main_spimaster28_mosi_latch[0:0] + update \main_spimaster29_miso_latch $0\main_spimaster29_miso_latch[0:0] + update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] + update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] + update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:423.5-423.55" + process $proc$ls180.v:423$2903 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:424.5-424.56" + process $proc$ls180.v:424$2904 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:425.5-425.50" + process $proc$ls180.v:425$2905 + assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:428.5-428.67" + process $proc$ls180.v:428$2906 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:4288.1-4336.4" + process $proc$ls180.v:4288$614 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + assign $0\main_spisdcard_clk_enable[0:0] 1'0 + assign $0\main_spisdcard_cs_enable[0:0] 1'0 + assign $0\main_spisdcard_mosi_latch[0:0] 1'0 + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_miso_latch[0:0] 1'0 + assign $0\main_spisdcard_irq[0:0] 1'0 + assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state + attribute \src "ls180.v:4299.2-4335.9" + switch \builder_spimaster1_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4303.4-4306.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4303.8-4303.31" + case 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spisdcard_clk_enable[0:0] 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4311.4-4317.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4311.8-4311.31" + case 1'1 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4312$615_Y + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4314.5-4316.8" + switch $eq$ls180.v:4314$617_Y + attribute \src "ls180.v:4314.9-4314.66" + case 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4321.4-4325.7" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:4321.8-4321.31" + case 1'1 + assign $0\main_spisdcard_miso_latch[0:0] 1'1 + assign $0\main_spisdcard_irq[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spisdcard_done0[0:0] 1'1 + attribute \src "ls180.v:4329.4-4333.7" + switch \main_spisdcard_start0 + attribute \src "ls180.v:4329.8-4329.29" + case 1'1 + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spisdcard_done0 $0\main_spisdcard_done0[0:0] + update \main_spisdcard_irq $0\main_spisdcard_irq[0:0] + update \main_spisdcard_clk_enable $0\main_spisdcard_clk_enable[0:0] + update \main_spisdcard_cs_enable $0\main_spisdcard_cs_enable[0:0] + update \main_spisdcard_mosi_latch $0\main_spisdcard_mosi_latch[0:0] + update \main_spisdcard_miso_latch $0\main_spisdcard_miso_latch[0:0] + update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] + update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] + update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:429.5-429.66" + process $proc$ls180.v:429$2907 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4368.1-4396.4" + process $proc$ls180.v:4368$639 + assign { } { } + assign $0\main_sdphy_clocker_clk1[0:0] 1'0 + attribute \src "ls180.v:4370.2-4395.9" + switch \main_sdphy_clocker_storage + attribute \src "ls180.v:0.0-0.0" + case 9'000000100 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] + attribute \src "ls180.v:0.0-0.0" + case 9'000001000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] + attribute \src "ls180.v:0.0-0.0" + case 9'000010000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] + attribute \src "ls180.v:0.0-0.0" + case 9'000100000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] + attribute \src "ls180.v:0.0-0.0" + case 9'001000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] + attribute \src "ls180.v:0.0-0.0" + case 9'010000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] + attribute \src "ls180.v:0.0-0.0" + case 9'100000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] + end + sync always + update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:4398.1-4431.4" + process $proc$ls180.v:4398$642 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:4408.2-4430.9" + switch \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4415.4-4421.7" + switch \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:4415.8-4415.38" + case 1'1 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4416$643_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4418.5-4420.8" + switch $eq$ls180.v:4418$644_Y + attribute \src "ls180.v:4418.9-4418.41" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4426.4-4428.7" + switch \main_sdphy_init_initialize_re + attribute \src "ls180.v:4426.8-4426.37" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] + update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] + update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:4432.1-4508.4" + process $proc$ls180.v:4432$645 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 + assign $0\main_sdphy_cmdw_done[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:4442.2-4507.9" + switch \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + attribute \src "ls180.v:4446.4-4471.11" + switch \main_sdphy_cmdw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] + attribute \src "ls180.v:0.0-0.0" + case 8'00000010 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] + attribute \src "ls180.v:0.0-0.0" + case 8'00000011 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000100 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] + attribute \src "ls180.v:0.0-0.0" + case 8'00000101 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] + attribute \src "ls180.v:0.0-0.0" + case 8'00000110 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] + attribute \src "ls180.v:0.0-0.0" + case 8'00000111 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] + case + end + attribute \src "ls180.v:4472.4-4483.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4472.8-4472.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4473$646_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4475.5-4482.8" + switch $eq$ls180.v:4475$647_Y + attribute \src "ls180.v:4475.9-4475.40" + case 1'1 + attribute \src "ls180.v:4476.6-4481.9" + switch \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:4476.10-4476.35" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 + attribute \src "ls180.v:4478.10-4478.14" + case + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4489.4-4496.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4489.8-4489.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4490$648_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4492.5-4495.8" + switch $eq$ls180.v:4492$649_Y + attribute \src "ls180.v:4492.9-4492.40" + case 1'1 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4501.4-4505.7" + switch $and$ls180.v:4501$650_Y + attribute \src "ls180.v:4501.8-4501.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 + attribute \src "ls180.v:4503.8-4503.12" + case + assign $0\main_sdphy_cmdw_done[0:0] 1'1 + end + end + sync always + update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] + update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] + update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:444.11-444.68" + process $proc$ls180.v:444$2908 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:445.5-445.64" + process $proc$ls180.v:445$2909 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:446.11-446.70" + process $proc$ls180.v:446$2910 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:447.11-447.70" + process $proc$ls180.v:447$2911 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:448.11-448.73" + process $proc$ls180.v:448$2912 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:4542.1-4635.4" + process $proc$ls180.v:4542$659 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign { } { } + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:4560.2-4634.9" + switch \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4568$660_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4565.4-4567.7" + switch \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:4565.8-4565.49" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4570.4-4573.7" + switch $eq$ls180.v:4570$661_Y + attribute \src "ls180.v:4570.8-4570.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4579$663_Y + assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4596$666_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4581.4-4595.7" + switch $and$ls180.v:4581$664_Y + attribute \src "ls180.v:4581.8-4581.69" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4583$665_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4585.5-4594.8" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:4585.9-4585.36" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4587.6-4593.9" + switch \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:4587.10-4587.35" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 + attribute \src "ls180.v:4591.10-4591.14" + case + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + end + case + end + case + end + attribute \src "ls180.v:4598.4-4601.7" + switch $eq$ls180.v:4598$667_Y + attribute \src "ls180.v:4598.8-4598.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4607.4-4613.7" + switch \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:4607.8-4607.38" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4608$668_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4610.5-4612.8" + switch $eq$ls180.v:4610$669_Y + attribute \src "ls180.v:4610.9-4610.40" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 + attribute \src "ls180.v:4619.4-4621.7" + switch $and$ls180.v:4619$670_Y + attribute \src "ls180.v:4619.8-4619.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4628.4-4632.7" + switch $and$ls180.v:4628$672_Y + attribute \src "ls180.v:4628.8-4628.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] + update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] + update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] + update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] + update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] + update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:4669.1-4696.4" + process $proc$ls180.v:4669$680 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_dataw_error[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:4677.2-4695.9" + switch \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 + attribute \src "ls180.v:4682.4-4686.7" + switch \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:4682.8-4682.50" + case 1'1 + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4683$681_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4684$682_Y + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:4689.4-4693.7" + switch \main_sdphy_dataw_start + attribute \src "ls180.v:4689.8-4689.30" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] + update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] + update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:469.5-469.59" + process $proc$ls180.v:469$2913 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:4697.1-4769.4" + process $proc$ls180.v:4697$683 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 + assign $0\main_sdphy_dataw_start[0:0] 1'0 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state + attribute \src "ls180.v:4708.2-4768.9" + switch \builder_sdphy_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + attribute \src "ls180.v:4713.4-4715.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4713.8-4713.39" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4718$684_Y + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + attribute \src "ls180.v:4721.4-4728.11" + switch \main_sdphy_dataw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] + case + end + attribute \src "ls180.v:4729.4-4741.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4729.8-4729.39" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4730$685_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4732.5-4740.8" + switch $eq$ls180.v:4732$686_Y + attribute \src "ls180.v:4732.9-4732.41" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4735.6-4739.9" + switch \main_sdphy_dataw_sink_last + attribute \src "ls180.v:4735.10-4735.36" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:4737.10-4737.14" + case + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4747.4-4750.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4747.8-4747.39" + case 1'1 + assign $0\main_sdphy_dataw_start[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4754.4-4759.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4754.8-4754.39" + case 1'1 + attribute \src "ls180.v:4755.5-4758.8" + switch \main_sdphy_dataw_pads_in_payload_data_i [0] + attribute \src "ls180.v:4755.9-4755.51" + case 1'1 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4764.4-4766.7" + switch $and$ls180.v:4764$687_Y + attribute \src "ls180.v:4764.8-4764.71" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] + update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] + update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] + update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:471.5-471.59" + process $proc$ls180.v:471$2914 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:472.5-472.58" + process $proc$ls180.v:472$2915 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:473.5-473.64" + process $proc$ls180.v:473$2916 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:474.12-474.74" + process $proc$ls180.v:474$2917 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:475.12-475.47" + process $proc$ls180.v:475$2918 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] + end + attribute \src "ls180.v:476.5-476.46" + process $proc$ls180.v:476$2919 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + end + attribute \src "ls180.v:478.5-478.44" + process $proc$ls180.v:478$2920 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:479.5-479.45" + process $proc$ls180.v:479$2921 + assign { } { } + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + end + attribute \src "ls180.v:480.5-480.54" + process $proc$ls180.v:480$2922 + assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:4803.1-4904.4" + process $proc$ls180.v:4803$695 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_datar_source_last[0:0] 1'0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:4820.2-4903.9" + switch \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4830$697_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4827.4-4829.7" + switch \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:4827.8-4827.51" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4832.4-4835.7" + switch $eq$ls180.v:4832$698_Y + attribute \src "ls180.v:4832.8-4832.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4841$701_Y + assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4862$703_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4843.4-4861.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:4843.8-4843.37" + case 1'1 + attribute \src "ls180.v:4844.5-4860.8" + switch \main_sdphy_datar_source_ready + attribute \src "ls180.v:4844.9-4844.38" + case 1'1 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4846$702_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4848.6-4857.9" + switch \main_sdphy_datar_source_last + attribute \src "ls180.v:4848.10-4848.38" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4850.7-4856.10" + switch \main_sdphy_datar_sink_last + attribute \src "ls180.v:4850.11-4850.37" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 + attribute \src "ls180.v:4854.11-4854.15" + case + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + end + case + end + attribute \src "ls180.v:4858.9-4858.13" + case + assign $0\main_sdphy_datar_stop[0:0] 1'1 + end + case + end + attribute \src "ls180.v:4864.4-4867.7" + switch $eq$ls180.v:4864$704_Y + attribute \src "ls180.v:4864.8-4864.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4871.4-4877.7" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4871.8-4871.39" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4872$705_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4874.5-4876.8" + switch $eq$ls180.v:4874$706_Y + attribute \src "ls180.v:4874.9-4874.42" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_source_valid[0:0] 1'1 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_datar_source_last[0:0] 1'1 + attribute \src "ls180.v:4883.4-4885.7" + switch $and$ls180.v:4883$707_Y + attribute \src "ls180.v:4883.8-4883.71" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4890.4-4901.7" + switch $and$ls180.v:4890$708_Y + attribute \src "ls180.v:4890.8-4890.71" + case 1'1 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4892.5-4900.8" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4892.9-4892.40" + case 1'1 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 + case + end + case + end + end + sync always + update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] + update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] + update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] + update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] + update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] + update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] + update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] + update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] + update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:482.32-482.76" + process $proc$ls180.v:482$2923 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + end + attribute \src "ls180.v:483.11-483.55" + process $proc$ls180.v:483$2924 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "ls180.v:485.32-485.75" + process $proc$ls180.v:485$2925 + assign { } { } + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:487.32-487.76" + process $proc$ls180.v:487$2926 + assign { } { } + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:493.5-493.51" + process $proc$ls180.v:493$2927 + assign { } { } + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "ls180.v:494.5-494.51" + process $proc$ls180.v:494$2928 + assign { } { } + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "ls180.v:496.5-496.47" + process $proc$ls180.v:496$2929 + assign { } { } + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + end + attribute \src "ls180.v:4962.1-4969.4" + process $proc$ls180.v:4962$830 + assign { } { } + assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + attribute \src "ls180.v:4964.2-4968.5" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:4964.6-4964.38" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:4966.6-4966.10" + case + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 + end + sync always + update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:497.5-497.45" + process $proc$ls180.v:497$2930 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:498.5-498.45" + process $proc$ls180.v:498$2931 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:4984.1-4991.4" + process $proc$ls180.v:4984$853 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4986.2-4990.5" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:4986.6-4986.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:4988.6-4988.10" + case + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:499.12-499.57" + process $proc$ls180.v:499$2932 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:4994.1-5001.4" + process $proc$ls180.v:4994$864 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4996.2-5000.5" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:4996.6-4996.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:4998.6-4998.10" + case + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:5004.1-5011.4" + process $proc$ls180.v:5004$875 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5006.2-5010.5" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:5006.6-5006.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:5008.6-5008.10" + case + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:501.5-501.51" + process $proc$ls180.v:501$2933 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:5014.1-5021.4" + process $proc$ls180.v:5014$886 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5016.2-5020.5" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:5016.6-5016.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:5018.6-5018.10" + case + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:502.5-502.51" + process $proc$ls180.v:502$2934 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:5022.1-5101.4" + process $proc$ls180.v:5022$887 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:5039.2-5100.9" + switch \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 + attribute \src "ls180.v:5043.4-5045.7" + switch $eq$ls180.v:5043$888_Y + attribute \src "ls180.v:5043.8-5043.48" + case 1'1 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 + case + end + attribute \src "ls180.v:5046.4-5071.11" + switch \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } + case + end + attribute \src "ls180.v:5072.4-5079.7" + switch \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:5072.8-5072.47" + case 1'1 + attribute \src "ls180.v:5073.5-5078.8" + switch $eq$ls180.v:5073$889_Y + attribute \src "ls180.v:5073.9-5073.49" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + attribute \src "ls180.v:5075.9-5075.13" + case + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5076$890_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5094.4-5098.7" + switch $and$ls180.v:5094$892_Y + attribute \src "ls180.v:5094.8-5094.128" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + case + end + end + sync always + update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] + update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] + update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] + update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:503.5-503.50" + process $proc$ls180.v:503$2935 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "ls180.v:504.5-504.54" + process $proc$ls180.v:504$2936 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:505.5-505.55" + process $proc$ls180.v:505$2937 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:506.5-506.56" + process $proc$ls180.v:506$2938 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:507.5-507.50" + process $proc$ls180.v:507$2939 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:510.5-510.67" + process $proc$ls180.v:510$2940 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:5102.1-5107.4" + process $proc$ls180.v:5102$893 + assign { } { } + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 + attribute \src "ls180.v:5104.2-5106.5" + switch $and$ls180.v:5104$900_Y + attribute \src "ls180.v:5104.6-5104.301" + case 1'1 + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:511.5-511.66" + process $proc$ls180.v:511$2941 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:5110.1-5117.4" + process $proc$ls180.v:5110$902 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + attribute \src "ls180.v:5112.2-5116.5" + switch $eq$ls180.v:5112$903_Y + attribute \src "ls180.v:5112.6-5112.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 + attribute \src "ls180.v:5114.6-5114.10" + case + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:5120.1-5127.4" + process $proc$ls180.v:5120$905 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + attribute \src "ls180.v:5122.2-5126.5" + switch $eq$ls180.v:5122$906_Y + attribute \src "ls180.v:5122.6-5122.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 + attribute \src "ls180.v:5124.6-5124.10" + case + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:5130.1-5137.4" + process $proc$ls180.v:5130$908 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + attribute \src "ls180.v:5132.2-5136.5" + switch $eq$ls180.v:5132$909_Y + attribute \src "ls180.v:5132.6-5132.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 + attribute \src "ls180.v:5134.6-5134.10" + case + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:5140.1-5147.4" + process $proc$ls180.v:5140$911 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + attribute \src "ls180.v:5142.2-5146.5" + switch $eq$ls180.v:5142$912_Y + attribute \src "ls180.v:5142.6-5142.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 + attribute \src "ls180.v:5144.6-5144.10" + case + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:5149.1-5154.4" + process $proc$ls180.v:5149$913 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + attribute \src "ls180.v:5151.2-5153.5" + switch $and$ls180.v:5151$915_Y + attribute \src "ls180.v:5151.6-5151.85" + case 1'1 + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:5155.1-5162.4" + process $proc$ls180.v:5155$916 + assign { } { } + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + attribute \src "ls180.v:5157.2-5161.5" + switch $lt$ls180.v:5157$917_Y + attribute \src "ls180.v:5157.6-5157.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 + attribute \src "ls180.v:5159.6-5159.10" + case + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready + end + sync always + update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:5166.1-5173.4" + process $proc$ls180.v:5166$928 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5168.2-5172.5" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:5168.6-5168.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:5170.6-5170.10" + case + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:5176.1-5183.4" + process $proc$ls180.v:5176$939 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5178.2-5182.5" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:5178.6-5178.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:5180.6-5180.10" + case + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:5186.1-5193.4" + process $proc$ls180.v:5186$950 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5188.2-5192.5" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:5188.6-5188.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:5190.6-5190.10" + case + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:5196.1-5203.4" + process $proc$ls180.v:5196$961 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5198.2-5202.5" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:5198.6-5198.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:5200.6-5200.10" + case + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:5204.1-5394.4" + process $proc$ls180.v:5204$962 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 + assign $0\main_sdphy_datar_sink_last[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_source_ready[0:0] 1'0 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state + attribute \src "ls180.v:5245.2-5393.9" + switch \builder_sdcore_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 + attribute \src "ls180.v:5248.4-5268.11" + switch \main_sdcore_cmd_count + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5266$963_Y + case + end + attribute \src "ls180.v:5269.4-5281.7" + switch $and$ls180.v:5269$964_Y + attribute \src "ls180.v:5269.8-5269.65" + case 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5270$965_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + attribute \src "ls180.v:5272.5-5280.8" + switch $eq$ls180.v:5272$966_Y + attribute \src "ls180.v:5272.9-5272.40" + case 1'1 + attribute \src "ls180.v:5273.6-5279.9" + switch $eq$ls180.v:5273$967_Y + attribute \src "ls180.v:5273.10-5273.40" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5277.10-5277.14" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5285$968_Y + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 + attribute \src "ls180.v:5286.4-5290.7" + switch $eq$ls180.v:5286$969_Y + attribute \src "ls180.v:5286.8-5286.38" + case 1'1 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 + attribute \src "ls180.v:5288.8-5288.12" + case + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 + end + attribute \src "ls180.v:5292.4-5313.7" + switch \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:5292.8-5292.36" + case 1'1 + attribute \src "ls180.v:5293.5-5312.8" + switch $eq$ls180.v:5293$970_Y + attribute \src "ls180.v:5293.9-5293.56" + case 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5297.9-5297.13" + case + attribute \src "ls180.v:5298.6-5311.9" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:5298.10-5298.37" + case 1'1 + attribute \src "ls180.v:5299.7-5307.10" + switch $eq$ls180.v:5299$971_Y + attribute \src "ls180.v:5299.11-5299.42" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:5301.11-5301.15" + case + attribute \src "ls180.v:5302.8-5306.11" + switch $eq$ls180.v:5302$972_Y + attribute \src "ls180.v:5302.12-5302.43" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + attribute \src "ls180.v:5304.12-5304.16" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + end + end + attribute \src "ls180.v:5308.10-5308.14" + case + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready + assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first + assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last + assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + attribute \src "ls180.v:5321.4-5327.7" + switch $and$ls180.v:5321$974_Y + attribute \src "ls180.v:5321.8-5321.98" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5322$975_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5324.5-5326.8" + switch $eq$ls180.v:5324$977_Y + attribute \src "ls180.v:5324.9-5324.77" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:5329.4-5334.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5329.8-5329.37" + case 1'1 + attribute \src "ls180.v:5330.5-5333.8" + switch $ne$ls180.v:5330$978_Y + attribute \src "ls180.v:5330.9-5330.57" + case 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5339$980_Y + attribute \src "ls180.v:5340.4-5366.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5340.8-5340.37" + case 1'1 + attribute \src "ls180.v:5341.5-5365.8" + switch $eq$ls180.v:5341$981_Y + attribute \src "ls180.v:5341.9-5341.57" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid + assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready + assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first + assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:5347.6-5355.9" + switch $and$ls180.v:5347$982_Y + attribute \src "ls180.v:5347.10-5347.72" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5348$983_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5350.7-5354.10" + switch $eq$ls180.v:5350$985_Y + attribute \src "ls180.v:5350.11-5350.79" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5352.11-5352.15" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + end + case + end + attribute \src "ls180.v:5356.9-5356.13" + case + attribute \src "ls180.v:5357.6-5364.9" + switch $eq$ls180.v:5357$986_Y + attribute \src "ls180.v:5357.10-5357.58" + case 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5377.4-5391.7" + switch \main_sdcore_cmd_send_re + attribute \src "ls180.v:5377.8-5377.31" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] + update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] + update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] + update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] + update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] + update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] + update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] + update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] + update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] + update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] + update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] + update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] + update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] + update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] + update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] + update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] + update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] + update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] + update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] + update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:526.11-526.68" + process $proc$ls180.v:526$2942 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:527.5-527.64" + process $proc$ls180.v:527$2943 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:528.11-528.70" + process $proc$ls180.v:528$2944 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:529.11-529.70" + process $proc$ls180.v:529$2945 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:530.11-530.73" + process $proc$ls180.v:530$2946 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:5422.1-5429.4" + process $proc$ls180.v:5422$987 + assign { } { } + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5424.2-5428.5" + switch \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:5424.6-5424.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5425$988_Y + attribute \src "ls180.v:5426.6-5426.10" + case + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce + end + sync always + update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:5455.1-5494.4" + process $proc$ls180.v:5455$998 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign { } { } + assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state + attribute \src "ls180.v:5465.2-5493.9" + switch \builder_sdblock2memdma_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid + assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5469$999_Y + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:5471.4-5482.7" + switch $and$ls180.v:5471$1000_Y + attribute \src "ls180.v:5471.8-5471.103" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5472$1001_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5474.5-5481.8" + switch $eq$ls180.v:5474$1003_Y + attribute \src "ls180.v:5474.9-5474.106" + case 1'1 + attribute \src "ls180.v:5475.6-5480.9" + switch \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:5475.10-5475.57" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5478.10-5478.14" + case + assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 + end + sync always + update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] + update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:55.5-55.42" + process $proc$ls180.v:55$2763 + assign { } { } + assign $1\main_libresocsim_reset_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + end + attribute \src "ls180.v:551.5-551.59" + process $proc$ls180.v:551$2947 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:5514.1-5551.4" + process $proc$ls180.v:5514$1005 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_interface1_bus_adr[31:0] 0 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 + assign $0\main_interface1_bus_sel[3:0] 4'0000 + assign $0\main_interface1_bus_cyc[0:0] 1'0 + assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 + assign { } { } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:5528.2-5550.9" + switch \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last + assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data + attribute \src "ls180.v:5533.4-5536.7" + switch \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:5533.8-5533.41" + case 1'1 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_interface1_bus_sel[3:0] 4'1111 + assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:5544.4-5548.7" + switch $and$ls180.v:5544$1006_Y + attribute \src "ls180.v:5544.8-5544.59" + case 1'1 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 + case + end + end + sync always + update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] + update \main_interface1_bus_sel $0\main_interface1_bus_sel[3:0] + update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] + update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] + update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] + update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] + update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] + update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] + update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[31:0] + update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:553.5-553.59" + process $proc$ls180.v:553$2948 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:554.5-554.58" + process $proc$ls180.v:554$2949 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:555.5-555.64" + process $proc$ls180.v:555$2950 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:5552.1-5588.4" + process $proc$ls180.v:5552$1007 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign { } { } + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:5561.2-5587.9" + switch \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5564$1009_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5565$1010_Y + attribute \src "ls180.v:5566.4-5577.7" + switch \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:5566.8-5566.39" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5567$1011_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5569.5-5576.8" + switch \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:5569.9-5569.39" + case 1'1 + attribute \src "ls180.v:5570.6-5575.9" + switch \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:5570.10-5570.43" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5573.10-5573.14" + case + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 + end + sync always + update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] + update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] + update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] + update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] + update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:556.12-556.74" + process $proc$ls180.v:556$2951 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:557.12-557.47" + process $proc$ls180.v:557$2952 + assign { } { } + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + end + attribute \src "ls180.v:558.5-558.46" + process $proc$ls180.v:558$2953 + assign { } { } + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + end + attribute \src "ls180.v:56.5-56.37" + process $proc$ls180.v:56$2764 + assign { } { } + assign $1\main_libresocsim_reset_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + end + attribute \src "ls180.v:560.5-560.44" + process $proc$ls180.v:560$2954 + assign { } { } + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + end + attribute \src "ls180.v:5600.1-5616.4" + process $proc$ls180.v:5600$1017 + assign { } { } + assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + attribute \src "ls180.v:5602.2-5615.9" + switch \main_sdmem2block_converter_mux + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] + end + sync always + update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:561.5-561.45" + process $proc$ls180.v:561$2955 + assign { } { } + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] + end + attribute \src "ls180.v:562.5-562.54" + process $proc$ls180.v:562$2956 + assign { } { } + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:5630.1-5637.4" + process $proc$ls180.v:5630$1018 + assign { } { } + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5632.2-5636.5" + switch \main_sdmem2block_fifo_replace + attribute \src "ls180.v:5632.6-5632.35" + case 1'1 + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5633$1019_Y + attribute \src "ls180.v:5634.6-5634.10" + case + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce + end + sync always + update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:564.32-564.76" + process $proc$ls180.v:564$2957 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + end + attribute \src "ls180.v:5645.1-5681.4" + process $proc$ls180.v:5645$1025 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign { } { } + assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_next_state[1:0] \builder_state + attribute \src "ls180.v:5656.2-5680.9" + switch \builder_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'10 + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } + assign $0\builder_next_state[1:0] 2'00 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5672.4-5678.7" + switch $and$ls180.v:5672$1026_Y + attribute \src "ls180.v:5672.8-5672.77" + case 1'1 + assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5675$1028_Y + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'01 + case + end + end + sync always + update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] + update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] + update \builder_next_state $0\builder_next_state[1:0] + update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] + update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] + update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] + update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] + update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:565.11-565.55" + process $proc$ls180.v:565$2958 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + end + attribute \src "ls180.v:567.32-567.75" + process $proc$ls180.v:567$2959 + assign { } { } + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:569.32-569.76" + process $proc$ls180.v:569$2960 + assign { } { } + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:57.12-57.60" + process $proc$ls180.v:57$2765 + assign { } { } + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:5706.1-5713.4" + process $proc$ls180.v:5706$1049 + assign { } { } + assign { } { } + assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5708$1050_Y + assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5709$1051_Y + assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5710$1052_Y + assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5711$1053_Y + assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5712$1054_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[4:0] + end + attribute \src "ls180.v:575.5-575.51" + process $proc$ls180.v:575$2961 + assign { } { } + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + end + attribute \src "ls180.v:5756.1-5767.4" + process $proc$ls180.v:5756$1067 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_error[0:0] 1'0 + assign $0\builder_shared_ack[0:0] $or$ls180.v:5760$1071_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5761$1080_Y + attribute \src "ls180.v:5762.2-5766.5" + switch \builder_done + attribute \src "ls180.v:5762.6-5762.18" + case 1'1 + assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\builder_shared_ack[0:0] 1'1 + assign $0\builder_error[0:0] 1'1 + case + end + sync always + update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] + update \builder_shared_ack $0\builder_shared_ack[0:0] + update \builder_error $0\builder_error[0:0] + end + attribute \src "ls180.v:576.5-576.51" + process $proc$ls180.v:576$2962 + assign { } { } + assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + end + attribute \src "ls180.v:578.5-578.47" + process $proc$ls180.v:578$2963 + assign { } { } + assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + end + attribute \src "ls180.v:579.5-579.45" + process $proc$ls180.v:579$2964 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + end + attribute \src "ls180.v:58.5-58.39" + process $proc$ls180.v:58$2766 + assign { } { } + assign $1\main_libresocsim_scratch_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + end + attribute \src "ls180.v:580.5-580.45" + process $proc$ls180.v:580$2965 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:581.12-581.57" + process $proc$ls180.v:581$2966 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:583.5-583.51" + process $proc$ls180.v:583$2967 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:584.5-584.51" + process $proc$ls180.v:584$2968 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:585.5-585.50" + process $proc$ls180.v:585$2969 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + end + attribute \src "ls180.v:586.5-586.54" + process $proc$ls180.v:586$2970 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:587.5-587.55" + process $proc$ls180.v:587$2971 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:588.5-588.56" + process $proc$ls180.v:588$2972 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:589.5-589.50" + process $proc$ls180.v:589$2973 + assign { } { } + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:592.5-592.67" + process $proc$ls180.v:592$2974 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:593.5-593.66" + process $proc$ls180.v:593$2975 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:608.11-608.68" + process $proc$ls180.v:608$2976 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:609.5-609.64" + process $proc$ls180.v:609$2977 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:610.11-610.70" + process $proc$ls180.v:610$2978 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:611.11-611.70" + process $proc$ls180.v:611$2979 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:612.11-612.73" + process $proc$ls180.v:612$2980 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:6281.1-6286.4" + process $proc$ls180.v:6281$1954 + assign { } { } + assign $0\main_spimaster9_start[0:0] 1'0 + attribute \src "ls180.v:6283.2-6285.5" + switch \main_spimaster12_re + attribute \src "ls180.v:6283.6-6283.25" + case 1'1 + assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] + case + end + sync always + update \main_spimaster9_start $0\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:63.12-63.47" + process $proc$ls180.v:63$2767 + assign { } { } + assign $1\main_libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:6327.1-6332.4" + process $proc$ls180.v:6327$2019 + assign { } { } + assign $0\main_spisdcard_start1[0:0] 1'0 + attribute \src "ls180.v:6329.2-6331.5" + switch \main_spisdcard_control_re + attribute \src "ls180.v:6329.6-6329.31" + case 1'1 + assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] + case + end + sync always + update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:633.5-633.59" + process $proc$ls180.v:633$2981 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:635.5-635.59" + process $proc$ls180.v:635$2982 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:636.5-636.58" + process $proc$ls180.v:636$2983 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:637.5-637.64" + process $proc$ls180.v:637$2984 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:638.12-638.74" + process $proc$ls180.v:638$2985 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:639.12-639.47" + process $proc$ls180.v:639$2986 + assign { } { } + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + end + attribute \src "ls180.v:640.5-640.46" + process $proc$ls180.v:640$2987 + assign { } { } + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + end + attribute \src "ls180.v:642.5-642.44" + process $proc$ls180.v:642$2988 + assign { } { } + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:643.5-643.45" + process $proc$ls180.v:643$2989 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:644.5-644.54" + process $proc$ls180.v:644$2990 + assign { } { } + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:646.32-646.76" + process $proc$ls180.v:646$2991 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "ls180.v:647.11-647.55" + process $proc$ls180.v:647$2992 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:649.32-649.75" + process $proc$ls180.v:649$2993 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:65.12-65.55" + process $proc$ls180.v:65$2768 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:651.32-651.76" + process $proc$ls180.v:651$2994 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:6516.1-6532.4" + process $proc$ls180.v:6516$2240 + assign { } { } + assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6518.2-6531.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:6533.1-6549.4" + process $proc$ls180.v:6533$2241 + assign { } { } + assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:6535.2-6548.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:6550.1-6566.4" + process $proc$ls180.v:6550$2242 + assign { } { } + assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 + attribute \src "ls180.v:6552.2-6565.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:6567.1-6583.4" + process $proc$ls180.v:6567$2243 + assign { } { } + assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6569.2-6582.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:657.5-657.51" + process $proc$ls180.v:657$2995 + assign { } { } + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + end + attribute \src "ls180.v:658.5-658.51" + process $proc$ls180.v:658$2996 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "ls180.v:6584.1-6600.4" + process $proc$ls180.v:6584$2244 + assign { } { } + assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6586.2-6599.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:660.5-660.47" + process $proc$ls180.v:660$2997 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "ls180.v:6601.1-6617.4" + process $proc$ls180.v:6601$2245 + assign { } { } + assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6603.2-6616.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:661.5-661.45" + process $proc$ls180.v:661$2998 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "ls180.v:6618.1-6634.4" + process $proc$ls180.v:6618$2246 + assign { } { } + assign $0\builder_comb_t_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6620.2-6633.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:662.5-662.45" + process $proc$ls180.v:662$2999 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:663.12-663.57" + process $proc$ls180.v:663$3000 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:6635.1-6651.4" + process $proc$ls180.v:6635$2247 + assign { } { } + assign $0\builder_comb_t_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:6637.2-6650.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:665.5-665.51" + process $proc$ls180.v:665$3001 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:6652.1-6668.4" + process $proc$ls180.v:6652$2248 + assign { } { } + assign $0\builder_comb_t_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:6654.2-6667.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:666.5-666.51" + process $proc$ls180.v:666$3002 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:6669.1-6685.4" + process $proc$ls180.v:6669$2249 + assign { } { } + assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:6671.2-6684.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:667.5-667.50" + process $proc$ls180.v:667$3003 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "ls180.v:668.5-668.54" + process $proc$ls180.v:668$3004 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:6686.1-6702.4" + process $proc$ls180.v:6686$2250 + assign { } { } + assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + attribute \src "ls180.v:6688.2-6701.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:669.5-669.55" + process $proc$ls180.v:669$3005 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:670.5-670.56" + process $proc$ls180.v:670$3006 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:6703.1-6719.4" + process $proc$ls180.v:6703$2251 + assign { } { } + assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 + attribute \src "ls180.v:6705.2-6718.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:671.5-671.50" + process $proc$ls180.v:671$3007 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:6720.1-6736.4" + process $proc$ls180.v:6720$2252 + assign { } { } + assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 + attribute \src "ls180.v:6722.2-6735.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:6737.1-6753.4" + process $proc$ls180.v:6737$2253 + assign { } { } + assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 + attribute \src "ls180.v:6739.2-6752.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:674.5-674.67" + process $proc$ls180.v:674$3008 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:675.5-675.66" + process $proc$ls180.v:675$3009 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6754.1-6770.4" + process $proc$ls180.v:6754$2254 + assign { } { } + assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 + attribute \src "ls180.v:6756.2-6769.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:6771.1-6787.4" + process $proc$ls180.v:6771$2255 + assign { } { } + assign $0\builder_comb_t_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6773.2-6786.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:6788.1-6804.4" + process $proc$ls180.v:6788$2256 + assign { } { } + assign $0\builder_comb_t_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6790.2-6803.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:6805.1-6821.4" + process $proc$ls180.v:6805$2257 + assign { } { } + assign $0\builder_comb_t_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6807.2-6820.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:6822.1-6829.4" + process $proc$ls180.v:6822$2258 + assign { } { } + assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6824.2-6828.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:6830.1-6837.4" + process $proc$ls180.v:6830$2259 + assign { } { } + assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 + attribute \src "ls180.v:6832.2-6836.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:6838.1-6845.4" + process $proc$ls180.v:6838$2260 + assign { } { } + assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 + attribute \src "ls180.v:6840.2-6844.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6842$2273_Y + end + sync always + update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:6846.1-6853.4" + process $proc$ls180.v:6846$2274 + assign { } { } + assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6848.2-6852.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:6854.1-6861.4" + process $proc$ls180.v:6854$2275 + assign { } { } + assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 + attribute \src "ls180.v:6856.2-6860.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:6862.1-6869.4" + process $proc$ls180.v:6862$2276 + assign { } { } + assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 + attribute \src "ls180.v:6864.2-6868.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6866$2289_Y + end + sync always + update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:6870.1-6877.4" + process $proc$ls180.v:6870$2290 + assign { } { } + assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6872.2-6876.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:6878.1-6885.4" + process $proc$ls180.v:6878$2291 + assign { } { } + assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 + attribute \src "ls180.v:6880.2-6884.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:6886.1-6893.4" + process $proc$ls180.v:6886$2292 + assign { } { } + assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 + attribute \src "ls180.v:6888.2-6892.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6890$2305_Y + end + sync always + update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:6894.1-6901.4" + process $proc$ls180.v:6894$2306 + assign { } { } + assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6896.2-6900.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:690.11-690.68" + process $proc$ls180.v:690$3010 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:6902.1-6909.4" + process $proc$ls180.v:6902$2307 + assign { } { } + assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 + attribute \src "ls180.v:6904.2-6908.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:691.5-691.64" + process $proc$ls180.v:691$3011 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:6910.1-6917.4" + process $proc$ls180.v:6910$2308 + assign { } { } + assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 + attribute \src "ls180.v:6912.2-6916.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6914$2321_Y + end + sync always + update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:6918.1-6937.4" + process $proc$ls180.v:6918$2322 + assign { } { } + assign $0\builder_comb_rhs_array_muxed24[31:0] 0 + attribute \src "ls180.v:6920.2-6936.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface2_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr + end + sync always + update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:692.11-692.70" + process $proc$ls180.v:692$3012 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:693.11-693.70" + process $proc$ls180.v:693$3013 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:6938.1-6957.4" + process $proc$ls180.v:6938$2323 + assign { } { } + assign $0\builder_comb_rhs_array_muxed25[31:0] 0 + attribute \src "ls180.v:6940.2-6956.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface2_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface0_bus_dat_w + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface1_bus_dat_w + end + sync always + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] + end + attribute \src "ls180.v:694.11-694.73" + process $proc$ls180.v:694$3014 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:6958.1-6977.4" + process $proc$ls180.v:6958$2324 + assign { } { } + assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 + attribute \src "ls180.v:6960.2-6976.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface2_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface0_bus_sel + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface1_bus_sel + end + sync always + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] + end + attribute \src "ls180.v:6978.1-6997.4" + process $proc$ls180.v:6978$2325 + assign { } { } + assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 + attribute \src "ls180.v:6980.2-6996.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface2_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc + end + sync always + update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:6998.1-7017.4" + process $proc$ls180.v:6998$2326 + assign { } { } + assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 + attribute \src "ls180.v:7000.2-7016.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface2_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb + end + sync always + update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:7018.1-7037.4" + process $proc$ls180.v:7018$2327 + assign { } { } + assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 + attribute \src "ls180.v:7020.2-7036.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface2_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we + end + sync always + update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:7038.1-7057.4" + process $proc$ls180.v:7038$2328 + assign { } { } + assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 + attribute \src "ls180.v:7040.2-7056.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface2_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti + end + sync always + update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:7058.1-7077.4" + process $proc$ls180.v:7058$2329 + assign { } { } + assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 + attribute \src "ls180.v:7060.2-7076.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface2_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte + end + sync always + update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:7078.1-7094.4" + process $proc$ls180.v:7078$2330 + assign { } { } + assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 + attribute \src "ls180.v:7080.2-7093.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba + end + sync always + update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:7095.1-7111.4" + process $proc$ls180.v:7095$2331 + assign { } { } + assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:7097.2-7110.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a + end + sync always + update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:7112.1-7128.4" + process $proc$ls180.v:7112$2332 + assign { } { } + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:7114.2-7127.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7119$2334_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7122$2336_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7125$2338_Y + end + sync always + update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:7129.1-7145.4" + process $proc$ls180.v:7129$2339 + assign { } { } + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:7131.2-7144.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7136$2341_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7139$2343_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7142$2345_Y + end + sync always + update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:7146.1-7162.4" + process $proc$ls180.v:7146$2346 + assign { } { } + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:7148.2-7161.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7153$2348_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7156$2350_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7159$2352_Y + end + sync always + update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:715.5-715.59" + process $proc$ls180.v:715$3015 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:7163.1-7179.4" + process $proc$ls180.v:7163$2353 + assign { } { } + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:7165.2-7178.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7170$2355_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7173$2357_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7176$2359_Y + end + sync always + update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:717.5-717.59" + process $proc$ls180.v:717$3016 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:718.5-718.58" + process $proc$ls180.v:718$3017 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:7180.1-7196.4" + process $proc$ls180.v:7180$2360 + assign { } { } + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:7182.2-7195.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7187$2362_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7190$2364_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7193$2366_Y + end + sync always + update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:719.5-719.64" + process $proc$ls180.v:719$3018 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:7197.1-7225.4" + process $proc$ls180.v:7197$2367 + assign { } { } + assign $0\builder_sync_f_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:7199.2-7224.9" + switch \main_spimaster34_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:72.5-72.46" + process $proc$ls180.v:72$2769 + assign { } { } + assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] + end + attribute \src "ls180.v:720.12-720.74" + process $proc$ls180.v:720$3019 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:721.12-721.47" + process $proc$ls180.v:721$3020 + assign { } { } + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] + end + attribute \src "ls180.v:722.5-722.46" + process $proc$ls180.v:722$3021 + assign { } { } + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] + end + attribute \src "ls180.v:7226.1-7254.4" + process $proc$ls180.v:7226$2368 + assign { } { } + assign $0\builder_sync_f_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:7228.2-7253.9" + switch \main_spisdcard_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:724.5-724.44" + process $proc$ls180.v:724$3022 + assign { } { } + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] + end + attribute \src "ls180.v:725.5-725.45" + process $proc$ls180.v:725$3023 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] + end + attribute \src "ls180.v:726.5-726.54" + process $proc$ls180.v:726$3024 + assign { } { } + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:728.32-728.76" + process $proc$ls180.v:728$3025 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + end + attribute \src "ls180.v:729.11-729.55" + process $proc$ls180.v:729$3026 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] + end + attribute \src "ls180.v:731.32-731.75" + process $proc$ls180.v:731$3027 + assign { } { } + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:7312.1-7330.4" + process $proc$ls180.v:7312$2369 + assign { } { } + assign { } { } + assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 + assign $0\main_gpio_status[15:0] [1] \builder_multiregimpl2_regs1 + assign $0\main_gpio_status[15:0] [2] \builder_multiregimpl3_regs1 + assign $0\main_gpio_status[15:0] [3] \builder_multiregimpl4_regs1 + assign $0\main_gpio_status[15:0] [4] \builder_multiregimpl5_regs1 + assign $0\main_gpio_status[15:0] [5] \builder_multiregimpl6_regs1 + assign $0\main_gpio_status[15:0] [6] \builder_multiregimpl7_regs1 + assign $0\main_gpio_status[15:0] [7] \builder_multiregimpl8_regs1 + assign $0\main_gpio_status[15:0] [8] \builder_multiregimpl9_regs1 + assign $0\main_gpio_status[15:0] [9] \builder_multiregimpl10_regs1 + assign $0\main_gpio_status[15:0] [10] \builder_multiregimpl11_regs1 + assign $0\main_gpio_status[15:0] [11] \builder_multiregimpl12_regs1 + assign $0\main_gpio_status[15:0] [12] \builder_multiregimpl13_regs1 + assign $0\main_gpio_status[15:0] [13] \builder_multiregimpl14_regs1 + assign $0\main_gpio_status[15:0] [14] \builder_multiregimpl15_regs1 + assign $0\main_gpio_status[15:0] [15] \builder_multiregimpl16_regs1 + sync always + update \main_gpio_status $0\main_gpio_status[15:0] + end + attribute \src "ls180.v:733.32-733.76" + process $proc$ls180.v:733$3028 + assign { } { } + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:7351.1-7353.4" + process $proc$ls180.v:7351$2370 + assign { } { } + assign $0\main_int_rst[0:0] \sys_rst + sync posedge \por_clk + update \main_int_rst $0\main_int_rst[0:0] + end + attribute \src "ls180.v:7355.1-7425.4" + process $proc$ls180.v:7355$2371 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] + assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] + assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] + assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] + assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] + assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] + assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] + assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] + assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] + assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] + assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] + assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] + assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] + assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] + assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] + assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n + assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n + assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n + assign $0\sdram_cke[0:0] \main_dfi_p0_cke + assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n + assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] + assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] + assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] + assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] + assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] + assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] + assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] + assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] + assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] + assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] + assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] + assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] + assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] + assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] + assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] + assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] + assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] + assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] + assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] + assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] + assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] + assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] + assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] + assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] + assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] + assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] + assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] + assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] + assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] + assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] + assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] + assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] + assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] + assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] + assign $0\sdram_clock[0:0] \sys_clk_1 + assign $0\sdcard_clk[0:0] $and$ls180.v:7412$2373_Y + assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe + assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o + assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i + assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe + assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] + assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] + assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] + assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] + assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] + assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] + assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] + assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] + sync posedge \sdrio_clk + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] + update \sdram_a $0\sdram_a[12:0] + update \sdram_dq_o $0\sdram_dq_o[15:0] + update \sdram_dq_oe $0\sdram_dq_oe[0:0] + update \sdram_we_n $0\sdram_we_n[0:0] + update \sdram_ras_n $0\sdram_ras_n[0:0] + update \sdram_cas_n $0\sdram_cas_n[0:0] + update \sdram_cs_n $0\sdram_cs_n[0:0] + update \sdram_cke $0\sdram_cke[0:0] + update \sdram_ba $0\sdram_ba[1:0] + update \sdram_dm $0\sdram_dm[1:0] + update \sdram_clock $0\sdram_clock[0:0] + update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] + update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] + update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:736.5-736.44" + process $proc$ls180.v:736$3029 + assign { } { } + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] + sync init + end + attribute \src "ls180.v:737.5-737.45" + process $proc$ls180.v:737$3030 + assign { } { } + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + sync init + end + attribute \src "ls180.v:738.5-738.43" + process $proc$ls180.v:738$3031 + assign { } { } + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] + sync init + end + attribute \src "ls180.v:739.5-739.48" + process $proc$ls180.v:739$3032 + assign { } { } + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] + sync init + end + attribute \src "ls180.v:74.5-74.46" + process $proc$ls180.v:74$2770 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] + sync init + end + attribute \src "ls180.v:741.5-741.43" + process $proc$ls180.v:741$3033 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + sync init + end + attribute \src "ls180.v:7427.1-10039.4" + process $proc$ls180.v:7427$2374 + assign $0\spimaster_clk[0:0] \spimaster_clk + assign $0\spimaster_mosi[0:0] \spimaster_mosi + assign { } { } + assign $0\spisdcard_clk[0:0] \spisdcard_clk + assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + assign { } { } + assign $0\uart_tx[0:0] \uart_tx + assign $0\pwm[1:0] \pwm + assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage + assign { } { } + assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage + assign { } { } + assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r + assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter + assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_converter2_dat_r + assign { } { } + assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage + assign { } { } + assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage + assign { } { } + assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage + assign { } { } + assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage + assign { } { } + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status + assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending + assign { } { } + assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage + assign { } { } + assign $0\main_libresocsim_value[31:0] \main_libresocsim_value + assign { } { } + assign { } { } + assign $0\main_sdram_storage[3:0] \main_sdram_storage + assign { } { } + assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage + assign { } { } + assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage + assign { } { } + assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage + assign { } { } + assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage + assign { } { } + assign $0\main_sdram_status[15:0] \main_sdram_status + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 + assign { } { } + assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count + assign { } { } + assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter + assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row + assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row + assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row + assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row + assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count + assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant + assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant + assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready + assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count + assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready + assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count + assign $0\main_sdram_time0[4:0] \main_sdram_time0 + assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_converter_counter[0:0] \main_converter_counter + assign $0\main_converter_dat_r[31:0] \main_converter_dat_r + assign $0\main_cmd_consumed[0:0] \main_cmd_consumed + assign $0\main_wdata_consumed[0:0] \main_wdata_consumed + assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage + assign { } { } + assign { } { } + assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen + assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg + assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount + assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy + assign { } { } + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data + assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen + assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx + assign { } { } + assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount + assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy + assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending + assign { } { } + assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending + assign { } { } + assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage + assign { } { } + assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable + assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 + assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce + assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume + assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable + assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 + assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce + assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume + assign $0\main_gpio_oe_storage[15:0] \main_gpio_oe_storage + assign { } { } + assign $0\main_gpio_out_storage[15:0] \main_gpio_out_storage + assign { } { } + assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso + assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage + assign { } { } + assign $0\main_spimaster16_storage[7:0] \main_spimaster16_storage + assign { } { } + assign $0\main_spimaster21_storage[0:0] \main_spimaster21_storage + assign { } { } + assign $0\main_spimaster23_storage[0:0] \main_spimaster23_storage + assign { } { } + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count + assign { } { } + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster33_mosi_data + assign $0\main_spimaster34_mosi_sel[2:0] \main_spimaster34_mosi_sel + assign $0\main_spimaster35_miso_data[7:0] \main_spimaster35_miso_data + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso + assign $0\main_spisdcard_control_storage[15:0] \main_spisdcard_control_storage + assign { } { } + assign $0\main_spisdcard_mosi_storage[7:0] \main_spisdcard_mosi_storage + assign { } { } + assign $0\main_spisdcard_cs_storage[0:0] \main_spisdcard_cs_storage + assign { } { } + assign $0\main_spisdcard_loopback_storage[0:0] \main_spisdcard_loopback_storage + assign { } { } + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count + assign { } { } + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi_data + assign $0\main_spisdcard_mosi_sel[2:0] \main_spisdcard_mosi_sel + assign $0\main_spisdcard_miso_data[7:0] \main_spisdcard_miso_data + assign $0\main_spimaster1_storage[15:0] \main_spimaster1_storage + assign { } { } + assign { } { } + assign $0\main_pwm0_counter[31:0] \main_pwm0_counter + assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage + assign { } { } + assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage + assign { } { } + assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage + assign { } { } + assign $0\main_pwm1_counter[31:0] \main_pwm1_counter + assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage + assign { } { } + assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage + assign { } { } + assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage + assign { } { } + assign $0\main_i2c_storage[2:0] \main_i2c_storage + assign { } { } + assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage + assign { } { } + assign { } { } + assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks + assign { } { } + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count + assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count + assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count + assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count + assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset + assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage + assign { } { } + assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage + assign { } { } + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status + assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage + assign { } { } + assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage + assign { } { } + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 + assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val + assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout + assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level + assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce + assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] \main_sdblock2mem_converter_source_payload_data + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] \main_sdblock2mem_converter_source_payload_valid_token_count + assign $0\main_sdblock2mem_converter_demux[1:0] \main_sdblock2mem_converter_demux + assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset + assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data + assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage + assign { } { } + assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage + assign { } { } + assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage + assign { } { } + assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage + assign { } { } + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset + assign $0\main_sdmem2block_converter_mux[1:0] \main_sdmem2block_converter_mux + assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level + assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce + assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w + assign $0\builder_grant[2:0] \builder_grant + assign { } { } + assign $0\builder_count[19:0] \builder_count + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_dummy[23:0] [0] $or$ls180.v:7428$2375_Y + assign $0\main_dummy[23:0] [1] $or$ls180.v:7429$2376_Y + assign $0\main_dummy[23:0] [2] $or$ls180.v:7430$2377_Y + assign $0\main_dummy[23:0] [3] $or$ls180.v:7431$2378_Y + assign $0\main_dummy[23:0] [4] $or$ls180.v:7432$2379_Y + assign $0\main_dummy[23:0] [5] $or$ls180.v:7433$2380_Y + assign $0\main_dummy[23:0] [6] $or$ls180.v:7434$2381_Y + assign $0\main_dummy[23:0] [7] $or$ls180.v:7435$2382_Y + assign $0\main_dummy[23:0] [8] $or$ls180.v:7436$2383_Y + assign $0\main_dummy[23:0] [9] $or$ls180.v:7437$2384_Y + assign $0\main_dummy[23:0] [10] $or$ls180.v:7438$2385_Y + assign $0\main_dummy[23:0] [11] $or$ls180.v:7439$2386_Y + assign $0\main_dummy[23:0] [12] $or$ls180.v:7440$2387_Y + assign $0\main_dummy[23:0] [13] $or$ls180.v:7441$2388_Y + assign $0\main_dummy[23:0] [14] $or$ls180.v:7442$2389_Y + assign $0\main_dummy[23:0] [15] $or$ls180.v:7443$2390_Y + assign $0\main_dummy[23:0] [16] $or$ls180.v:7444$2391_Y + assign $0\main_dummy[23:0] [17] $or$ls180.v:7445$2392_Y + assign $0\main_dummy[23:0] [18] $or$ls180.v:7446$2393_Y + assign $0\main_dummy[23:0] [19] $or$ls180.v:7447$2394_Y + assign $0\main_dummy[23:0] [20] $or$ls180.v:7448$2395_Y + assign $0\main_dummy[23:0] [21] $or$ls180.v:7449$2396_Y + assign $0\main_dummy[23:0] [22] $or$ls180.v:7450$2397_Y + assign $0\main_dummy[23:0] [23] $or$ls180.v:7451$2398_Y + assign $0\builder_converter0_state[0:0] \builder_converter0_next_state + assign $0\builder_converter1_state[0:0] \builder_converter1_next_state + assign $0\builder_converter2_state[0:0] \builder_converter2_next_state + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger + assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } + assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\builder_refresher_state[1:0] \builder_refresher_next_state + assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state + assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state + assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state + assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 + assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 + assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7893$2495_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7894$2496_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7895$2497_Y + assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 + assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7929$2515_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7930$2527_Y + assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 + assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 + assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 + assign $0\builder_converter_state[0:0] \builder_converter_next_state + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx + assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger + assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8088$2573_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8097$2576_Y + assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8123$2578_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8132$2581_Y + assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state + assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 + assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 + assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state + assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state + assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state + assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state + assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state + assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state + assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state + assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state + assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state + assign $0\builder_state[1:0] \builder_next_state + assign $0\builder_slave_sel_r[4:0] \builder_slave_sel + assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re + assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re + assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re + assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re + assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re + assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re + assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re + assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re + assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re + assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re + assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re + assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re + assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re + assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re + assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re + assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re + assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re + assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re + assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re + assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re + assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re + assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re + assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re + assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re + assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re + assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re + assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spimaster12_re[0:0] \builder_csrbank10_control0_re + assign $0\main_spimaster17_re[0:0] \builder_csrbank10_mosi0_re + assign $0\main_spimaster22_re[0:0] \builder_csrbank10_cs0_re + assign $0\main_spimaster24_re[0:0] \builder_csrbank10_loopback0_re + assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spisdcard_control_re[0:0] \builder_csrbank11_control0_re + assign $0\main_spisdcard_mosi_re[0:0] \builder_csrbank11_mosi0_re + assign $0\main_spisdcard_cs_re[0:0] \builder_csrbank11_cs0_re + assign $0\main_spisdcard_loopback_re[0:0] \builder_csrbank11_loopback0_re + assign $0\main_spimaster1_re[0:0] \builder_csrbank11_clk_divider0_re + assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re + assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re + assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re + assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re + assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re + assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re + assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re + assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx + assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 + assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0] + assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 + assign $0\builder_multiregimpl2_regs0[0:0] \main_gpio_pads_i [1] + assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 + assign $0\builder_multiregimpl3_regs0[0:0] \main_gpio_pads_i [2] + assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 + assign $0\builder_multiregimpl4_regs0[0:0] \main_gpio_pads_i [3] + assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 + assign $0\builder_multiregimpl5_regs0[0:0] \main_gpio_pads_i [4] + assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 + assign $0\builder_multiregimpl6_regs0[0:0] \main_gpio_pads_i [5] + assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 + assign $0\builder_multiregimpl7_regs0[0:0] \main_gpio_pads_i [6] + assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 + assign $0\builder_multiregimpl8_regs0[0:0] \main_gpio_pads_i [7] + assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 + assign $0\builder_multiregimpl9_regs0[0:0] \main_gpio_pads_i [8] + assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 + assign $0\builder_multiregimpl10_regs0[0:0] \main_gpio_pads_i [9] + assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 + assign $0\builder_multiregimpl11_regs0[0:0] \main_gpio_pads_i [10] + assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 + assign $0\builder_multiregimpl12_regs0[0:0] \main_gpio_pads_i [11] + assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 + assign $0\builder_multiregimpl13_regs0[0:0] \main_gpio_pads_i [12] + assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 + assign $0\builder_multiregimpl14_regs0[0:0] \main_gpio_pads_i [13] + assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 + assign $0\builder_multiregimpl15_regs0[0:0] \main_gpio_pads_i [14] + assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 + assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] + assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 + attribute \src "ls180.v:7452.2-7454.5" + switch $or$ls180.v:7452$2399_Y + attribute \src "ls180.v:7452.6-7452.94" + case 1'1 + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r + case + end + attribute \src "ls180.v:7456.2-7458.5" + switch \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:7456.6-7456.66" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value + case + end + attribute \src "ls180.v:7459.2-7462.5" + switch \main_libresocsim_converter0_reset + attribute \src "ls180.v:7459.6-7459.39" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7463.2-7465.5" + switch $or$ls180.v:7463$2400_Y + attribute \src "ls180.v:7463.6-7463.94" + case 1'1 + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r + case + end + attribute \src "ls180.v:7467.2-7469.5" + switch \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:7467.6-7467.66" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value + case + end + attribute \src "ls180.v:7470.2-7473.5" + switch \main_libresocsim_converter1_reset + attribute \src "ls180.v:7470.6-7470.39" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7474.2-7476.5" + switch $or$ls180.v:7474$2401_Y + attribute \src "ls180.v:7474.6-7474.94" + case 1'1 + assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r + case + end + attribute \src "ls180.v:7478.2-7480.5" + switch \main_libresocsim_converter2_counter_converter2_next_value_ce + attribute \src "ls180.v:7478.6-7478.66" + case 1'1 + assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value + case + end + attribute \src "ls180.v:7481.2-7484.5" + switch \main_libresocsim_converter2_reset + attribute \src "ls180.v:7481.6-7481.39" + case 1'1 + assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7485.2-7489.5" + switch $ne$ls180.v:7485$2402_Y + attribute \src "ls180.v:7485.6-7485.53" + case 1'1 + attribute \src "ls180.v:7486.3-7488.6" + switch \main_libresocsim_bus_error + attribute \src "ls180.v:7486.7-7486.33" + case 1'1 + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7487$2403_Y + case + end + case + end + attribute \src "ls180.v:7491.2-7493.5" + switch $and$ls180.v:7491$2406_Y + attribute \src "ls180.v:7491.6-7491.103" + case 1'1 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7494.2-7502.5" + switch \main_libresocsim_en_storage + attribute \src "ls180.v:7494.6-7494.33" + case 1'1 + attribute \src "ls180.v:7495.3-7499.6" + switch $eq$ls180.v:7495$2407_Y + attribute \src "ls180.v:7495.7-7495.39" + case 1'1 + assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage + attribute \src "ls180.v:7497.7-7497.11" + case + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7498$2408_Y + end + attribute \src "ls180.v:7500.6-7500.10" + case + assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage + end + attribute \src "ls180.v:7503.2-7505.5" + switch \main_libresocsim_update_value_re + attribute \src "ls180.v:7503.6-7503.38" + case 1'1 + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value + case + end + attribute \src "ls180.v:7506.2-7508.5" + switch \main_libresocsim_zero_clear + attribute \src "ls180.v:7506.6-7506.33" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7510.2-7512.5" + switch $and$ls180.v:7510$2410_Y + attribute \src "ls180.v:7510.6-7510.76" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7515.2-7517.5" + switch \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:7515.6-7515.37" + case 1'1 + assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata + case + end + attribute \src "ls180.v:7518.2-7522.5" + switch $and$ls180.v:7518$2412_Y + attribute \src "ls180.v:7518.6-7518.57" + case 1'1 + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7519$2413_Y + attribute \src "ls180.v:7520.6-7520.10" + case + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + end + attribute \src "ls180.v:7524.2-7530.5" + switch \main_sdram_postponer_req_i + attribute \src "ls180.v:7524.6-7524.32" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7525$2414_Y + attribute \src "ls180.v:7526.3-7529.6" + switch $eq$ls180.v:7526$2415_Y + attribute \src "ls180.v:7526.7-7526.43" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_postponer_req_o[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:7531.2-7539.5" + switch \main_sdram_sequencer_start0 + attribute \src "ls180.v:7531.6-7531.33" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + attribute \src "ls180.v:7533.6-7533.10" + case + attribute \src "ls180.v:7534.3-7538.6" + switch \main_sdram_sequencer_done1 + attribute \src "ls180.v:7534.7-7534.33" + case 1'1 + attribute \src "ls180.v:7535.4-7537.7" + switch $ne$ls180.v:7535$2416_Y + attribute \src "ls180.v:7535.8-7535.44" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7536$2417_Y + case + end + case + end + end + attribute \src "ls180.v:7546.2-7552.5" + switch $and$ls180.v:7546$2419_Y + attribute \src "ls180.v:7546.6-7546.76" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'1 + case + end + attribute \src "ls180.v:7553.2-7559.5" + switch $eq$ls180.v:7553$2420_Y + attribute \src "ls180.v:7553.6-7553.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + case + end + attribute \src "ls180.v:7560.2-7567.5" + switch $eq$ls180.v:7560$2421_Y + attribute \src "ls180.v:7560.6-7560.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'1 + case + end + attribute \src "ls180.v:7568.2-7578.5" + switch $eq$ls180.v:7568$2422_Y + attribute \src "ls180.v:7568.6-7568.44" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + attribute \src "ls180.v:7570.6-7570.10" + case + attribute \src "ls180.v:7571.3-7577.6" + switch $ne$ls180.v:7571$2423_Y + attribute \src "ls180.v:7571.7-7571.45" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7572$2424_Y + attribute \src "ls180.v:7573.7-7573.11" + case + attribute \src "ls180.v:7574.4-7576.7" + switch \main_sdram_sequencer_start1 + attribute \src "ls180.v:7574.8-7574.35" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0001 + case + end + end + end + attribute \src "ls180.v:7580.2-7587.5" + switch \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:7580.6-7580.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + attribute \src "ls180.v:7582.6-7582.10" + case + attribute \src "ls180.v:7583.3-7586.6" + switch \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:7583.7-7583.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7588.2-7590.5" + switch $and$ls180.v:7588$2427_Y + attribute \src "ls180.v:7588.6-7588.191" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7589$2428_Y + case + end + attribute \src "ls180.v:7591.2-7593.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7591.6-7591.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7592$2429_Y + case + end + attribute \src "ls180.v:7594.2-7602.5" + switch $and$ls180.v:7594$2432_Y + attribute \src "ls180.v:7594.6-7594.191" + case 1'1 + attribute \src "ls180.v:7595.3-7597.6" + switch $not$ls180.v:7595$2433_Y + attribute \src "ls180.v:7595.7-7595.62" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7596$2434_Y + case + end + attribute \src "ls180.v:7598.6-7598.10" + case + attribute \src "ls180.v:7599.3-7601.6" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7599.7-7599.59" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7600$2435_Y + case + end + end + attribute \src "ls180.v:7603.2-7609.5" + switch $or$ls180.v:7603$2437_Y + attribute \src "ls180.v:7603.6-7603.108" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7610.2-7624.5" + switch \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:7610.6-7610.43" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7612.3-7616.6" + switch 1'0 + attribute \src "ls180.v:7614.7-7614.11" + case + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7617.6-7617.10" + case + attribute \src "ls180.v:7618.3-7623.6" + switch $not$ls180.v:7618$2438_Y + attribute \src "ls180.v:7618.7-7618.47" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7619$2439_Y + attribute \src "ls180.v:7620.4-7622.7" + switch $eq$ls180.v:7620$2440_Y + attribute \src "ls180.v:7620.8-7620.55" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7626.2-7633.5" + switch \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:7626.6-7626.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + attribute \src "ls180.v:7628.6-7628.10" + case + attribute \src "ls180.v:7629.3-7632.6" + switch \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:7629.7-7629.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7634.2-7636.5" + switch $and$ls180.v:7634$2443_Y + attribute \src "ls180.v:7634.6-7634.191" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7635$2444_Y + case + end + attribute \src "ls180.v:7637.2-7639.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7637.6-7637.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7638$2445_Y + case + end + attribute \src "ls180.v:7640.2-7648.5" + switch $and$ls180.v:7640$2448_Y + attribute \src "ls180.v:7640.6-7640.191" + case 1'1 + attribute \src "ls180.v:7641.3-7643.6" + switch $not$ls180.v:7641$2449_Y + attribute \src "ls180.v:7641.7-7641.62" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7642$2450_Y + case + end + attribute \src "ls180.v:7644.6-7644.10" + case + attribute \src "ls180.v:7645.3-7647.6" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7645.7-7645.59" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7646$2451_Y + case + end + end + attribute \src "ls180.v:7649.2-7655.5" + switch $or$ls180.v:7649$2453_Y + attribute \src "ls180.v:7649.6-7649.108" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7656.2-7670.5" + switch \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:7656.6-7656.43" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7658.3-7662.6" + switch 1'0 + attribute \src "ls180.v:7660.7-7660.11" + case + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7663.6-7663.10" + case + attribute \src "ls180.v:7664.3-7669.6" + switch $not$ls180.v:7664$2454_Y + attribute \src "ls180.v:7664.7-7664.47" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7665$2455_Y + attribute \src "ls180.v:7666.4-7668.7" + switch $eq$ls180.v:7666$2456_Y + attribute \src "ls180.v:7666.8-7666.55" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7672.2-7679.5" + switch \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:7672.6-7672.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + attribute \src "ls180.v:7674.6-7674.10" + case + attribute \src "ls180.v:7675.3-7678.6" + switch \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:7675.7-7675.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7680.2-7682.5" + switch $and$ls180.v:7680$2459_Y + attribute \src "ls180.v:7680.6-7680.191" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7681$2460_Y + case + end + attribute \src "ls180.v:7683.2-7685.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7683.6-7683.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7684$2461_Y + case + end + attribute \src "ls180.v:7686.2-7694.5" + switch $and$ls180.v:7686$2464_Y + attribute \src "ls180.v:7686.6-7686.191" + case 1'1 + attribute \src "ls180.v:7687.3-7689.6" + switch $not$ls180.v:7687$2465_Y + attribute \src "ls180.v:7687.7-7687.62" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7688$2466_Y + case + end + attribute \src "ls180.v:7690.6-7690.10" + case + attribute \src "ls180.v:7691.3-7693.6" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7691.7-7691.59" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7692$2467_Y + case + end + end + attribute \src "ls180.v:7695.2-7701.5" + switch $or$ls180.v:7695$2469_Y + attribute \src "ls180.v:7695.6-7695.108" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7702.2-7716.5" + switch \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:7702.6-7702.43" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7704.3-7708.6" + switch 1'0 + attribute \src "ls180.v:7706.7-7706.11" + case + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7709.6-7709.10" + case + attribute \src "ls180.v:7710.3-7715.6" + switch $not$ls180.v:7710$2470_Y + attribute \src "ls180.v:7710.7-7710.47" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7711$2471_Y + attribute \src "ls180.v:7712.4-7714.7" + switch $eq$ls180.v:7712$2472_Y + attribute \src "ls180.v:7712.8-7712.55" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7718.2-7725.5" + switch \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:7718.6-7718.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + attribute \src "ls180.v:7720.6-7720.10" + case + attribute \src "ls180.v:7721.3-7724.6" + switch \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:7721.7-7721.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7726.2-7728.5" + switch $and$ls180.v:7726$2475_Y + attribute \src "ls180.v:7726.6-7726.191" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7727$2476_Y + case + end + attribute \src "ls180.v:7729.2-7731.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7729.6-7729.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7730$2477_Y + case + end + attribute \src "ls180.v:7732.2-7740.5" + switch $and$ls180.v:7732$2480_Y + attribute \src "ls180.v:7732.6-7732.191" + case 1'1 + attribute \src "ls180.v:7733.3-7735.6" + switch $not$ls180.v:7733$2481_Y + attribute \src "ls180.v:7733.7-7733.62" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7734$2482_Y + case + end + attribute \src "ls180.v:7736.6-7736.10" + case + attribute \src "ls180.v:7737.3-7739.6" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7737.7-7737.59" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7738$2483_Y + case + end + end + attribute \src "ls180.v:7741.2-7747.5" + switch $or$ls180.v:7741$2485_Y + attribute \src "ls180.v:7741.6-7741.108" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7748.2-7762.5" + switch \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:7748.6-7748.43" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7750.3-7754.6" + switch 1'0 + attribute \src "ls180.v:7752.7-7752.11" + case + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7755.6-7755.10" + case + attribute \src "ls180.v:7756.3-7761.6" + switch $not$ls180.v:7756$2486_Y + attribute \src "ls180.v:7756.7-7756.47" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7757$2487_Y + attribute \src "ls180.v:7758.4-7760.7" + switch $eq$ls180.v:7758$2488_Y + attribute \src "ls180.v:7758.8-7758.55" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7764.2-7770.5" + switch $not$ls180.v:7764$2489_Y + attribute \src "ls180.v:7764.6-7764.23" + case 1'1 + assign $0\main_sdram_time0[4:0] 5'11111 + attribute \src "ls180.v:7766.6-7766.10" + case + attribute \src "ls180.v:7767.3-7769.6" + switch $not$ls180.v:7767$2490_Y + attribute \src "ls180.v:7767.7-7767.30" + case 1'1 + assign $0\main_sdram_time0[4:0] $sub$ls180.v:7768$2491_Y + case + end + end + attribute \src "ls180.v:7771.2-7777.5" + switch $not$ls180.v:7771$2492_Y + attribute \src "ls180.v:7771.6-7771.23" + case 1'1 + assign $0\main_sdram_time1[3:0] 4'1111 + attribute \src "ls180.v:7773.6-7773.10" + case + attribute \src "ls180.v:7774.3-7776.6" + switch $not$ls180.v:7774$2493_Y + attribute \src "ls180.v:7774.7-7774.30" + case 1'1 + assign $0\main_sdram_time1[3:0] $sub$ls180.v:7775$2494_Y + case + end + end + attribute \src "ls180.v:7778.2-7833.5" + switch \main_sdram_choose_cmd_ce + attribute \src "ls180.v:7778.6-7778.30" + case 1'1 + attribute \src "ls180.v:7779.3-7832.10" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:7781.5-7791.8" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7781.9-7781.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7783.9-7783.13" + case + attribute \src "ls180.v:7784.6-7790.9" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7784.10-7784.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7786.10-7786.14" + case + attribute \src "ls180.v:7787.7-7789.10" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7787.11-7787.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:7794.5-7804.8" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7794.9-7794.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7796.9-7796.13" + case + attribute \src "ls180.v:7797.6-7803.9" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7797.10-7797.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7799.10-7799.14" + case + attribute \src "ls180.v:7800.7-7802.10" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7800.11-7800.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:7807.5-7817.8" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7807.9-7807.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7809.9-7809.13" + case + attribute \src "ls180.v:7810.6-7816.9" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7810.10-7810.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7812.10-7812.14" + case + attribute \src "ls180.v:7813.7-7815.10" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7813.11-7813.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:7820.5-7830.8" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7820.9-7820.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7822.9-7822.13" + case + attribute \src "ls180.v:7823.6-7829.9" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7823.10-7823.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7825.10-7825.14" + case + attribute \src "ls180.v:7826.7-7828.10" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7826.11-7826.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:7834.2-7889.5" + switch \main_sdram_choose_req_ce + attribute \src "ls180.v:7834.6-7834.30" + case 1'1 + attribute \src "ls180.v:7835.3-7888.10" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:7837.5-7847.8" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7837.9-7837.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:7839.9-7839.13" + case + attribute \src "ls180.v:7840.6-7846.9" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7840.10-7840.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:7842.10-7842.14" + case + attribute \src "ls180.v:7843.7-7845.10" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7843.11-7843.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:7850.5-7860.8" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7850.9-7850.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:7852.9-7852.13" + case + attribute \src "ls180.v:7853.6-7859.9" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7853.10-7853.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:7855.10-7855.14" + case + attribute \src "ls180.v:7856.7-7858.10" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7856.11-7856.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:7863.5-7873.8" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7863.9-7863.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:7865.9-7865.13" + case + attribute \src "ls180.v:7866.6-7872.9" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7866.10-7866.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:7868.10-7868.14" + case + attribute \src "ls180.v:7869.7-7871.10" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7869.11-7869.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:7876.5-7886.8" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7876.9-7876.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:7878.9-7878.13" + case + attribute \src "ls180.v:7879.6-7885.9" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7879.10-7879.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:7881.10-7881.14" + case + attribute \src "ls180.v:7882.7-7884.10" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7882.11-7882.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:7898.2-7912.5" + switch \main_sdram_tccdcon_valid + attribute \src "ls180.v:7898.6-7898.30" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + attribute \src "ls180.v:7900.3-7904.6" + switch 1'1 + attribute \src "ls180.v:7900.7-7900.11" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:7905.6-7905.10" + case + attribute \src "ls180.v:7906.3-7911.6" + switch $not$ls180.v:7906$2498_Y + attribute \src "ls180.v:7906.7-7906.34" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7907$2499_Y + attribute \src "ls180.v:7908.4-7910.7" + switch $eq$ls180.v:7908$2500_Y + attribute \src "ls180.v:7908.8-7908.42" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7913.2-7927.5" + switch \main_sdram_twtrcon_valid + attribute \src "ls180.v:7913.6-7913.30" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] 3'100 + attribute \src "ls180.v:7915.3-7919.6" + switch 1'0 + attribute \src "ls180.v:7917.7-7917.11" + case + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7920.6-7920.10" + case + attribute \src "ls180.v:7921.3-7926.6" + switch $not$ls180.v:7921$2501_Y + attribute \src "ls180.v:7921.7-7921.34" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7922$2502_Y + attribute \src "ls180.v:7923.4-7925.7" + switch $eq$ls180.v:7923$2503_Y + attribute \src "ls180.v:7923.8-7923.42" + case 1'1 + assign $0\main_sdram_twtrcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7934.2-7936.5" + switch $or$ls180.v:7934$2528_Y + attribute \src "ls180.v:7934.6-7934.50" + case 1'1 + assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r + case + end + attribute \src "ls180.v:7938.2-7940.5" + switch \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:7938.6-7938.52" + case 1'1 + assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value + case + end + attribute \src "ls180.v:7941.2-7944.5" + switch \main_converter_reset + attribute \src "ls180.v:7941.6-7941.26" + case 1'1 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7945.2-7955.5" + switch \main_litedram_wb_ack + attribute \src "ls180.v:7945.6-7945.26" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + attribute \src "ls180.v:7948.6-7948.10" + case + attribute \src "ls180.v:7949.3-7951.6" + switch $and$ls180.v:7949$2529_Y + attribute \src "ls180.v:7949.7-7949.50" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'1 + case + end + attribute \src "ls180.v:7952.3-7954.6" + switch $and$ls180.v:7952$2530_Y + attribute \src "ls180.v:7952.7-7952.54" + case 1'1 + assign $0\main_wdata_consumed[0:0] 1'1 + case + end + end + attribute \src "ls180.v:7957.2-7978.5" + switch $and$ls180.v:7957$2534_Y + attribute \src "ls180.v:7957.6-7957.91" + case 1'1 + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data + assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 + assign $0\main_uart_phy_tx_busy[0:0] 1'1 + assign $0\uart_tx[0:0] 1'0 + attribute \src "ls180.v:7962.6-7962.10" + case + attribute \src "ls180.v:7963.3-7977.6" + switch $and$ls180.v:7963$2535_Y + attribute \src "ls180.v:7963.7-7963.60" + case 1'1 + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7964$2536_Y + attribute \src "ls180.v:7965.4-7976.7" + switch $eq$ls180.v:7965$2537_Y + attribute \src "ls180.v:7965.8-7965.43" + case 1'1 + assign $0\uart_tx[0:0] 1'1 + attribute \src "ls180.v:7967.8-7967.12" + case + attribute \src "ls180.v:7968.5-7975.8" + switch $eq$ls180.v:7968$2538_Y + attribute \src "ls180.v:7968.9-7968.44" + case 1'1 + assign $0\uart_tx[0:0] 1'1 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'1 + attribute \src "ls180.v:7972.9-7972.13" + case + assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] + assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:7979.2-7983.5" + switch \main_uart_phy_tx_busy + attribute \src "ls180.v:7979.6-7979.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7980$2539_Y + attribute \src "ls180.v:7981.6-7981.10" + case + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } + end + attribute \src "ls180.v:7986.2-8010.5" + switch $not$ls180.v:7986$2540_Y + attribute \src "ls180.v:7986.6-7986.30" + case 1'1 + attribute \src "ls180.v:7987.3-7990.6" + switch $and$ls180.v:7987$2542_Y + attribute \src "ls180.v:7987.7-7987.49" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 + case + end + attribute \src "ls180.v:7991.6-7991.10" + case + attribute \src "ls180.v:7992.3-8009.6" + switch \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:7992.7-7992.34" + case 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:7993$2543_Y + attribute \src "ls180.v:7994.4-8008.7" + switch $eq$ls180.v:7994$2544_Y + attribute \src "ls180.v:7994.8-7994.43" + case 1'1 + attribute \src "ls180.v:7995.5-7997.8" + switch \main_uart_phy_rx + attribute \src "ls180.v:7995.9-7995.25" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + case + end + attribute \src "ls180.v:7998.8-7998.12" + case + attribute \src "ls180.v:7999.5-8007.8" + switch $eq$ls180.v:7999$2545_Y + attribute \src "ls180.v:7999.9-7999.44" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + attribute \src "ls180.v:8001.6-8004.9" + switch \main_uart_phy_rx + attribute \src "ls180.v:8001.10-8001.26" + case 1'1 + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_source_valid[0:0] 1'1 + case + end + attribute \src "ls180.v:8005.9-8005.13" + case + assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:8011.2-8015.5" + switch \main_uart_phy_rx_busy + attribute \src "ls180.v:8011.6-8011.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8012$2546_Y + attribute \src "ls180.v:8013.6-8013.10" + case + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 + end + attribute \src "ls180.v:8016.2-8018.5" + switch \main_uart_tx_clear + attribute \src "ls180.v:8016.6-8016.24" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8020.2-8022.5" + switch $and$ls180.v:8020$2548_Y + attribute \src "ls180.v:8020.6-8020.58" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8023.2-8025.5" + switch \main_uart_rx_clear + attribute \src "ls180.v:8023.6-8023.24" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8027.2-8029.5" + switch $and$ls180.v:8027$2550_Y + attribute \src "ls180.v:8027.6-8027.58" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8030.2-8036.5" + switch \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:8030.6-8030.35" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8032.6-8032.10" + case + attribute \src "ls180.v:8033.3-8035.6" + switch \main_uart_tx_fifo_re + attribute \src "ls180.v:8033.7-8033.27" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8037.2-8039.5" + switch $and$ls180.v:8037$2553_Y + attribute \src "ls180.v:8037.6-8037.108" + case 1'1 + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8038$2554_Y + case + end + attribute \src "ls180.v:8040.2-8042.5" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8040.6-8040.31" + case 1'1 + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8041$2555_Y + case + end + attribute \src "ls180.v:8043.2-8051.5" + switch $and$ls180.v:8043$2558_Y + attribute \src "ls180.v:8043.6-8043.108" + case 1'1 + attribute \src "ls180.v:8044.3-8046.6" + switch $not$ls180.v:8044$2559_Y + attribute \src "ls180.v:8044.7-8044.35" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8045$2560_Y + case + end + attribute \src "ls180.v:8047.6-8047.10" + case + attribute \src "ls180.v:8048.3-8050.6" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8048.7-8048.32" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8049$2561_Y + case + end + end + attribute \src "ls180.v:8052.2-8058.5" + switch \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:8052.6-8052.35" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8054.6-8054.10" + case + attribute \src "ls180.v:8055.3-8057.6" + switch \main_uart_rx_fifo_re + attribute \src "ls180.v:8055.7-8055.27" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8059.2-8061.5" + switch $and$ls180.v:8059$2564_Y + attribute \src "ls180.v:8059.6-8059.108" + case 1'1 + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8060$2565_Y + case + end + attribute \src "ls180.v:8062.2-8064.5" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8062.6-8062.31" + case 1'1 + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8063$2566_Y + case + end + attribute \src "ls180.v:8065.2-8073.5" + switch $and$ls180.v:8065$2569_Y + attribute \src "ls180.v:8065.6-8065.108" + case 1'1 + attribute \src "ls180.v:8066.3-8068.6" + switch $not$ls180.v:8066$2570_Y + attribute \src "ls180.v:8066.7-8066.35" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8067$2571_Y + case + end + attribute \src "ls180.v:8069.6-8069.10" + case + attribute \src "ls180.v:8070.3-8072.6" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8070.7-8070.32" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8071$2572_Y + case + end + end + attribute \src "ls180.v:8074.2-8087.5" + switch \main_uart_reset + attribute \src "ls180.v:8074.6-8074.21" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + case + end + attribute \src "ls180.v:8089.2-8096.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8089.6-8089.31" + case 1'1 + assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable + attribute \src "ls180.v:8091.6-8091.10" + case + attribute \src "ls180.v:8092.3-8095.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8092.7-8092.32" + case 1'1 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\spisdcard_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8098.2-8108.5" + switch \main_spimaster28_mosi_latch + attribute \src "ls180.v:8098.6-8098.33" + case 1'1 + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi + assign $0\main_spimaster34_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8101.6-8101.10" + case + attribute \src "ls180.v:8102.3-8107.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8102.7-8102.32" + case 1'1 + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8106$2577_Y + attribute \src "ls180.v:8103.4-8105.7" + switch \main_spimaster26_cs_enable + attribute \src "ls180.v:8103.8-8103.34" + case 1'1 + assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 + case + end + case + end + end + attribute \src "ls180.v:8109.2-8115.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8109.6-8109.31" + case 1'1 + attribute \src "ls180.v:8110.3-8114.6" + switch \main_spimaster7_loopback + attribute \src "ls180.v:8110.7-8110.31" + case 1'1 + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } + attribute \src "ls180.v:8112.7-8112.11" + case + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } + end + case + end + attribute \src "ls180.v:8116.2-8118.5" + switch \main_spimaster29_miso_latch + attribute \src "ls180.v:8116.6-8116.33" + case 1'1 + assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data + case + end + attribute \src "ls180.v:8120.2-8122.5" + switch \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:8120.6-8120.53" + case 1'1 + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value + case + end + attribute \src "ls180.v:8124.2-8131.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8124.6-8124.29" + case 1'1 + assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable + attribute \src "ls180.v:8126.6-8126.10" + case + attribute \src "ls180.v:8127.3-8130.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8127.7-8127.30" + case 1'1 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\spimaster_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8133.2-8143.5" + switch \main_spisdcard_mosi_latch + attribute \src "ls180.v:8133.6-8133.31" + case 1'1 + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi + assign $0\main_spisdcard_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8136.6-8136.10" + case + attribute \src "ls180.v:8137.3-8142.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8137.7-8137.30" + case 1'1 + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8141$2582_Y + attribute \src "ls180.v:8138.4-8140.7" + switch \main_spisdcard_cs_enable + attribute \src "ls180.v:8138.8-8138.32" + case 1'1 + assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 + case + end + case + end + end + attribute \src "ls180.v:8144.2-8150.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8144.6-8144.29" + case 1'1 + attribute \src "ls180.v:8145.3-8149.6" + switch \main_spisdcard_loopback + attribute \src "ls180.v:8145.7-8145.30" + case 1'1 + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } + attribute \src "ls180.v:8147.7-8147.11" + case + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } + end + case + end + attribute \src "ls180.v:8151.2-8153.5" + switch \main_spisdcard_miso_latch + attribute \src "ls180.v:8151.6-8151.31" + case 1'1 + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data + case + end + attribute \src "ls180.v:8155.2-8157.5" + switch \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:8155.6-8155.51" + case 1'1 + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value + case + end + attribute \src "ls180.v:8158.2-8171.5" + switch \main_pwm0_enable + attribute \src "ls180.v:8158.6-8158.22" + case 1'1 + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8159$2583_Y + attribute \src "ls180.v:8160.3-8164.6" + switch $lt$ls180.v:8160$2584_Y + attribute \src "ls180.v:8160.7-8160.44" + case 1'1 + assign $0\pwm[1:0] [0] 1'1 + attribute \src "ls180.v:8162.7-8162.11" + case + assign $0\pwm[1:0] [0] 1'0 + end + attribute \src "ls180.v:8165.3-8167.6" + switch $ge$ls180.v:8165$2586_Y + attribute \src "ls180.v:8165.7-8165.55" + case 1'1 + assign $0\main_pwm0_counter[31:0] 0 + case + end + attribute \src "ls180.v:8168.6-8168.10" + case + assign $0\main_pwm0_counter[31:0] 0 + assign $0\pwm[1:0] [0] 1'0 + end + attribute \src "ls180.v:8172.2-8185.5" + switch \main_pwm1_enable + attribute \src "ls180.v:8172.6-8172.22" + case 1'1 + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8173$2587_Y + attribute \src "ls180.v:8174.3-8178.6" + switch $lt$ls180.v:8174$2588_Y + attribute \src "ls180.v:8174.7-8174.44" + case 1'1 + assign $0\pwm[1:0] [1] 1'1 + attribute \src "ls180.v:8176.7-8176.11" + case + assign $0\pwm[1:0] [1] 1'0 + end + attribute \src "ls180.v:8179.3-8181.6" + switch $ge$ls180.v:8179$2590_Y + attribute \src "ls180.v:8179.7-8179.55" + case 1'1 + assign $0\main_pwm1_counter[31:0] 0 + case + end + attribute \src "ls180.v:8182.6-8182.10" + case + assign $0\main_pwm1_counter[31:0] 0 + assign $0\pwm[1:0] [1] 1'0 + end + attribute \src "ls180.v:8186.2-8188.5" + switch $not$ls180.v:8186$2591_Y + attribute \src "ls180.v:8186.6-8186.32" + case 1'1 + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8187$2592_Y + case + end + attribute \src "ls180.v:8192.2-8194.5" + switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:8192.6-8192.57" + case 1'1 + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value + case + end + attribute \src "ls180.v:8196.2-8198.5" + switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:8196.6-8196.57" + case 1'1 + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + case + end + attribute \src "ls180.v:8199.2-8201.5" + switch \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:8199.6-8199.40" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8200$2593_Y + case + end + attribute \src "ls180.v:8202.2-8204.5" + switch \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:8202.6-8202.49" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8205.2-8212.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8205.6-8205.46" + case 1'1 + attribute \src "ls180.v:8206.3-8211.6" + switch $or$ls180.v:8206$2595_Y + attribute \src "ls180.v:8206.7-8206.98" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8209.7-8209.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8210$2596_Y + end + case + end + attribute \src "ls180.v:8213.2-8226.5" + switch $and$ls180.v:8213$2597_Y + attribute \src "ls180.v:8213.6-8213.97" + case 1'1 + attribute \src "ls180.v:8214.3-8220.6" + switch $and$ls180.v:8214$2598_Y + attribute \src "ls180.v:8214.7-8214.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:8217.7-8217.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8221.6-8221.10" + case + attribute \src "ls180.v:8222.3-8225.6" + switch $and$ls180.v:8222$2599_Y + attribute \src "ls180.v:8222.7-8222.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8223$2600_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8224$2601_Y + case + end + end + attribute \src "ls180.v:8227.2-8254.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8227.6-8227.46" + case 1'1 + attribute \src "ls180.v:8228.3-8253.10" + switch \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8255.2-8257.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8255.6-8255.46" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8256$2602_Y + case + end + attribute \src "ls180.v:8258.2-8263.5" + switch $or$ls180.v:8258$2604_Y + attribute \src "ls180.v:8258.6-8258.88" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8264.2-8269.5" + switch \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:8264.6-8264.32" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8271.2-8273.5" + switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:8271.6-8271.58" + case 1'1 + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + case + end + attribute \src "ls180.v:8274.2-8276.5" + switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:8274.6-8274.60" + case 1'1 + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + case + end + attribute \src "ls180.v:8277.2-8279.5" + switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:8277.6-8277.63" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + case + end + attribute \src "ls180.v:8280.2-8282.5" + switch \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:8280.6-8280.41" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8281$2605_Y + case + end + attribute \src "ls180.v:8283.2-8285.5" + switch \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:8283.6-8283.50" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8286.2-8293.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8286.6-8286.47" + case 1'1 + attribute \src "ls180.v:8287.3-8292.6" + switch $or$ls180.v:8287$2607_Y + attribute \src "ls180.v:8287.7-8287.100" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8290.7-8290.11" + case + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8291$2608_Y + end + case + end + attribute \src "ls180.v:8294.2-8307.5" + switch $and$ls180.v:8294$2609_Y + attribute \src "ls180.v:8294.6-8294.99" + case 1'1 + attribute \src "ls180.v:8295.3-8301.6" + switch $and$ls180.v:8295$2610_Y + attribute \src "ls180.v:8295.7-8295.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:8298.7-8298.11" + case + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8302.6-8302.10" + case + attribute \src "ls180.v:8303.3-8306.6" + switch $and$ls180.v:8303$2611_Y + attribute \src "ls180.v:8303.7-8303.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8304$2612_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8305$2613_Y + case + end + end + attribute \src "ls180.v:8308.2-8335.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8308.6-8308.47" + case 1'1 + attribute \src "ls180.v:8309.3-8334.10" + switch \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8336.2-8338.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8336.6-8336.47" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8337$2614_Y + case + end + attribute \src "ls180.v:8339.2-8344.5" + switch $or$ls180.v:8339$2616_Y + attribute \src "ls180.v:8339.6-8339.90" + case 1'1 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8345.2-8350.5" + switch \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:8345.6-8345.33" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8352.2-8354.5" + switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:8352.6-8352.63" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + case + end + attribute \src "ls180.v:8356.2-8358.5" + switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:8356.6-8356.52" + case 1'1 + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value + case + end + attribute \src "ls180.v:8359.2-8361.5" + switch \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:8359.6-8359.42" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8360$2617_Y + case + end + attribute \src "ls180.v:8362.2-8364.5" + switch \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:8362.6-8362.51" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8365.2-8372.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8365.6-8365.48" + case 1'1 + attribute \src "ls180.v:8366.3-8371.6" + switch $or$ls180.v:8366$2619_Y + attribute \src "ls180.v:8366.7-8366.102" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8369.7-8369.11" + case + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8370$2620_Y + end + case + end + attribute \src "ls180.v:8373.2-8386.5" + switch $and$ls180.v:8373$2621_Y + attribute \src "ls180.v:8373.6-8373.101" + case 1'1 + attribute \src "ls180.v:8374.3-8380.6" + switch $and$ls180.v:8374$2622_Y + attribute \src "ls180.v:8374.7-8374.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:8377.7-8377.11" + case + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8381.6-8381.10" + case + attribute \src "ls180.v:8382.3-8385.6" + switch $and$ls180.v:8382$2623_Y + attribute \src "ls180.v:8382.7-8382.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8383$2624_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8384$2625_Y + case + end + end + attribute \src "ls180.v:8387.2-8396.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8387.6-8387.48" + case 1'1 + attribute \src "ls180.v:8388.3-8395.10" + switch \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8397.2-8399.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8397.6-8397.48" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8398$2626_Y + case + end + attribute \src "ls180.v:8400.2-8405.5" + switch $or$ls180.v:8400$2628_Y + attribute \src "ls180.v:8400.6-8400.92" + case 1'1 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data + case + end + attribute \src "ls180.v:8406.2-8411.5" + switch \main_sdphy_datar_datar_reset + attribute \src "ls180.v:8406.6-8406.34" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8413.2-8415.5" + switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:8413.6-8413.60" + case 1'1 + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + case + end + attribute \src "ls180.v:8416.2-8418.5" + switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:8416.6-8416.62" + case 1'1 + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + case + end + attribute \src "ls180.v:8419.2-8421.5" + switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:8419.6-8419.66" + case 1'1 + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + case + end + attribute \src "ls180.v:8422.2-8428.5" + switch \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:8422.6-8422.35" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + attribute \src "ls180.v:8424.6-8424.10" + case + attribute \src "ls180.v:8425.3-8427.6" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:8425.7-8425.39" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 + case + end + end + attribute \src "ls180.v:8429.2-8435.5" + switch \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:8429.6-8429.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8431.6-8431.10" + case + attribute \src "ls180.v:8432.3-8434.6" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:8432.7-8432.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8436.2-8442.5" + switch \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:8436.6-8436.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8438.6-8438.10" + case + attribute \src "ls180.v:8439.3-8441.6" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:8439.7-8439.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8443.2-8449.5" + switch \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:8443.6-8443.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8445.6-8445.10" + case + attribute \src "ls180.v:8446.3-8448.6" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:8446.7-8446.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8450.2-8456.5" + switch \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:8450.6-8450.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8452.6-8452.10" + case + attribute \src "ls180.v:8453.3-8455.6" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:8453.7-8453.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8458.2-8460.5" + switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:8458.6-8458.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + case + end + attribute \src "ls180.v:8461.2-8463.5" + switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:8461.6-8461.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + case + end + attribute \src "ls180.v:8464.2-8466.5" + switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:8464.6-8464.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + case + end + attribute \src "ls180.v:8467.2-8469.5" + switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:8467.6-8467.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + case + end + attribute \src "ls180.v:8470.2-8472.5" + switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:8470.6-8470.78" + case 1'1 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + case + end + attribute \src "ls180.v:8473.2-8475.5" + switch $and$ls180.v:8473$2629_Y + attribute \src "ls180.v:8473.6-8473.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc + case + end + attribute \src "ls180.v:8476.2-8478.5" + switch $and$ls180.v:8476$2630_Y + attribute \src "ls180.v:8476.6-8476.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc + case + end + attribute \src "ls180.v:8479.2-8481.5" + switch $and$ls180.v:8479$2631_Y + attribute \src "ls180.v:8479.6-8479.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc + case + end + attribute \src "ls180.v:8482.2-8484.5" + switch $and$ls180.v:8482$2632_Y + attribute \src "ls180.v:8482.6-8482.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc + case + end + attribute \src "ls180.v:8485.2-8489.5" + switch $and$ls180.v:8485$2633_Y + attribute \src "ls180.v:8485.6-8485.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } + assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] + case + end + attribute \src "ls180.v:8490.2-8494.5" + switch $and$ls180.v:8490$2634_Y + attribute \src "ls180.v:8490.6-8490.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } + assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] + case + end + attribute \src "ls180.v:8495.2-8499.5" + switch $and$ls180.v:8495$2635_Y + attribute \src "ls180.v:8495.6-8495.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } + assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] + case + end + attribute \src "ls180.v:8500.2-8504.5" + switch $and$ls180.v:8500$2636_Y + attribute \src "ls180.v:8500.6-8500.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } + assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] + case + end + attribute \src "ls180.v:8505.2-8513.5" + switch $and$ls180.v:8505$2637_Y + attribute \src "ls180.v:8505.6-8505.83" + case 1'1 + attribute \src "ls180.v:8506.3-8512.6" + switch \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:8506.7-8506.42" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + attribute \src "ls180.v:8508.7-8508.11" + case + attribute \src "ls180.v:8509.4-8511.7" + switch $ne$ls180.v:8509$2638_Y + attribute \src "ls180.v:8509.8-8509.48" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8510$2639_Y + case + end + end + case + end + attribute \src "ls180.v:8514.2-8520.5" + switch \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:8514.6-8514.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8516.6-8516.10" + case + attribute \src "ls180.v:8517.3-8519.6" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:8517.7-8517.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8521.2-8527.5" + switch \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:8521.6-8521.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8523.6-8523.10" + case + attribute \src "ls180.v:8524.3-8526.6" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:8524.7-8524.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8528.2-8534.5" + switch \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:8528.6-8528.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8530.6-8530.10" + case + attribute \src "ls180.v:8531.3-8533.6" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:8531.7-8531.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8535.2-8541.5" + switch \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:8535.6-8535.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8537.6-8537.10" + case + attribute \src "ls180.v:8538.3-8540.6" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:8538.7-8538.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8543.2-8545.5" + switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:8543.6-8543.52" + case 1'1 + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 + case + end + attribute \src "ls180.v:8546.2-8548.5" + switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:8546.6-8546.53" + case 1'1 + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 + case + end + attribute \src "ls180.v:8549.2-8551.5" + switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:8549.6-8549.53" + case 1'1 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 + case + end + attribute \src "ls180.v:8552.2-8554.5" + switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:8552.6-8552.54" + case 1'1 + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 + case + end + attribute \src "ls180.v:8555.2-8557.5" + switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:8555.6-8555.53" + case 1'1 + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 + case + end + attribute \src "ls180.v:8558.2-8560.5" + switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:8558.6-8558.55" + case 1'1 + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + case + end + attribute \src "ls180.v:8561.2-8563.5" + switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:8561.6-8561.54" + case 1'1 + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 + case + end + attribute \src "ls180.v:8564.2-8566.5" + switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:8564.6-8564.56" + case 1'1 + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 + case + end + attribute \src "ls180.v:8567.2-8569.5" + switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:8567.6-8567.63" + case 1'1 + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + case + end + attribute \src "ls180.v:8570.2-8572.5" + switch $and$ls180.v:8570$2642_Y + attribute \src "ls180.v:8570.6-8570.120" + case 1'1 + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8571$2643_Y + case + end + attribute \src "ls180.v:8573.2-8575.5" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8573.6-8573.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8574$2644_Y + case + end + attribute \src "ls180.v:8576.2-8584.5" + switch $and$ls180.v:8576$2647_Y + attribute \src "ls180.v:8576.6-8576.120" + case 1'1 + attribute \src "ls180.v:8577.3-8579.6" + switch $not$ls180.v:8577$2648_Y + attribute \src "ls180.v:8577.7-8577.39" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8578$2649_Y + case + end + attribute \src "ls180.v:8580.6-8580.10" + case + attribute \src "ls180.v:8581.3-8583.6" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8581.7-8581.36" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8582$2650_Y + case + end + end + attribute \src "ls180.v:8585.2-8587.5" + switch \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:8585.6-8585.45" + case 1'1 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8588.2-8595.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8588.6-8588.42" + case 1'1 + attribute \src "ls180.v:8589.3-8594.6" + switch $or$ls180.v:8589$2652_Y + attribute \src "ls180.v:8589.7-8589.90" + case 1'1 + assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8592.7-8592.11" + case + assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8593$2653_Y + end + case + end + attribute \src "ls180.v:8596.2-8609.5" + switch $and$ls180.v:8596$2654_Y + attribute \src "ls180.v:8596.6-8596.89" + case 1'1 + attribute \src "ls180.v:8597.3-8603.6" + switch $and$ls180.v:8597$2655_Y + attribute \src "ls180.v:8597.7-8597.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:8600.7-8600.11" + case + assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 + assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8604.6-8604.10" + case + attribute \src "ls180.v:8605.3-8608.6" + switch $and$ls180.v:8605$2656_Y + attribute \src "ls180.v:8605.7-8605.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8606$2657_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8607$2658_Y + case + end + end + attribute \src "ls180.v:8610.2-8625.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8610.6-8610.42" + case 1'1 + attribute \src "ls180.v:8611.3-8624.10" + switch \main_sdblock2mem_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8626.2-8628.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8626.6-8626.42" + case 1'1 + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8627$2659_Y + case + end + attribute \src "ls180.v:8630.2-8632.5" + switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:8630.6-8630.76" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + case + end + attribute \src "ls180.v:8633.2-8636.5" + switch \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:8633.6-8633.46" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8638.2-8640.5" + switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:8638.6-8638.64" + case 1'1 + assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + case + end + attribute \src "ls180.v:8642.2-8644.5" + switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:8642.6-8642.76" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + case + end + attribute \src "ls180.v:8645.2-8648.5" + switch \main_sdmem2block_dma_reset + attribute \src "ls180.v:8645.6-8645.32" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8649.2-8655.5" + switch $and$ls180.v:8649$2660_Y + attribute \src "ls180.v:8649.6-8649.89" + case 1'1 + attribute \src "ls180.v:8650.3-8654.6" + switch \main_sdmem2block_converter_last + attribute \src "ls180.v:8650.7-8650.38" + case 1'1 + assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + attribute \src "ls180.v:8652.7-8652.11" + case + assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8653$2661_Y + end + case + end + attribute \src "ls180.v:8656.2-8658.5" + switch $and$ls180.v:8656$2664_Y + attribute \src "ls180.v:8656.6-8656.120" + case 1'1 + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8657$2665_Y + case + end + attribute \src "ls180.v:8659.2-8661.5" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8659.6-8659.35" + case 1'1 + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8660$2666_Y + case + end + attribute \src "ls180.v:8662.2-8670.5" + switch $and$ls180.v:8662$2669_Y + attribute \src "ls180.v:8662.6-8662.120" + case 1'1 + attribute \src "ls180.v:8663.3-8665.6" + switch $not$ls180.v:8663$2670_Y + attribute \src "ls180.v:8663.7-8663.39" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8664$2671_Y + case + end + attribute \src "ls180.v:8666.6-8666.10" + case + attribute \src "ls180.v:8667.3-8669.6" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8667.7-8667.36" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8668$2672_Y + case + end + end + attribute \src "ls180.v:8672.2-8674.5" + switch \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:8672.6-8672.46" + case 1'1 + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 + case + end + attribute \src "ls180.v:8675.2-8677.5" + switch \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:8675.6-8675.44" + case 1'1 + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 + case + end + attribute \src "ls180.v:8678.2-8680.5" + switch \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:8678.6-8678.43" + case 1'1 + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 + case + end + attribute \src "ls180.v:8681.2-8777.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + attribute \src "ls180.v:8683.4-8699.7" + switch $not$ls180.v:8683$2673_Y + attribute \src "ls180.v:8683.8-8683.29" + case 1'1 + attribute \src "ls180.v:8684.5-8698.8" + switch \builder_request [1] + attribute \src "ls180.v:8684.9-8684.27" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8686.9-8686.13" + case + attribute \src "ls180.v:8687.6-8697.9" + switch \builder_request [2] + attribute \src "ls180.v:8687.10-8687.28" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8689.10-8689.14" + case + attribute \src "ls180.v:8690.7-8696.10" + switch \builder_request [3] + attribute \src "ls180.v:8690.11-8690.29" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8692.11-8692.15" + case + attribute \src "ls180.v:8693.8-8695.11" + switch \builder_request [4] + attribute \src "ls180.v:8693.12-8693.30" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'001 + attribute \src "ls180.v:8702.4-8718.7" + switch $not$ls180.v:8702$2674_Y + attribute \src "ls180.v:8702.8-8702.29" + case 1'1 + attribute \src "ls180.v:8703.5-8717.8" + switch \builder_request [2] + attribute \src "ls180.v:8703.9-8703.27" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8705.9-8705.13" + case + attribute \src "ls180.v:8706.6-8716.9" + switch \builder_request [3] + attribute \src "ls180.v:8706.10-8706.28" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8708.10-8708.14" + case + attribute \src "ls180.v:8709.7-8715.10" + switch \builder_request [4] + attribute \src "ls180.v:8709.11-8709.29" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8711.11-8711.15" + case + attribute \src "ls180.v:8712.8-8714.11" + switch \builder_request [0] + attribute \src "ls180.v:8712.12-8712.30" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + attribute \src "ls180.v:8721.4-8737.7" + switch $not$ls180.v:8721$2675_Y + attribute \src "ls180.v:8721.8-8721.29" + case 1'1 + attribute \src "ls180.v:8722.5-8736.8" + switch \builder_request [3] + attribute \src "ls180.v:8722.9-8722.27" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8724.9-8724.13" + case + attribute \src "ls180.v:8725.6-8735.9" + switch \builder_request [4] + attribute \src "ls180.v:8725.10-8725.28" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8727.10-8727.14" + case + attribute \src "ls180.v:8728.7-8734.10" + switch \builder_request [0] + attribute \src "ls180.v:8728.11-8728.29" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8730.11-8730.15" + case + attribute \src "ls180.v:8731.8-8733.11" + switch \builder_request [1] + attribute \src "ls180.v:8731.12-8731.30" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:8740.4-8756.7" + switch $not$ls180.v:8740$2676_Y + attribute \src "ls180.v:8740.8-8740.29" + case 1'1 + attribute \src "ls180.v:8741.5-8755.8" + switch \builder_request [4] + attribute \src "ls180.v:8741.9-8741.27" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8743.9-8743.13" + case + attribute \src "ls180.v:8744.6-8754.9" + switch \builder_request [0] + attribute \src "ls180.v:8744.10-8744.28" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8746.10-8746.14" + case + attribute \src "ls180.v:8747.7-8753.10" + switch \builder_request [1] + attribute \src "ls180.v:8747.11-8747.29" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8749.11-8749.15" + case + attribute \src "ls180.v:8750.8-8752.11" + switch \builder_request [2] + attribute \src "ls180.v:8750.12-8750.30" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + attribute \src "ls180.v:8759.4-8775.7" + switch $not$ls180.v:8759$2677_Y + attribute \src "ls180.v:8759.8-8759.29" + case 1'1 + attribute \src "ls180.v:8760.5-8774.8" + switch \builder_request [0] + attribute \src "ls180.v:8760.9-8760.27" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8762.9-8762.13" + case + attribute \src "ls180.v:8763.6-8773.9" + switch \builder_request [1] + attribute \src "ls180.v:8763.10-8763.28" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8765.10-8765.14" + case + attribute \src "ls180.v:8766.7-8772.10" + switch \builder_request [2] + attribute \src "ls180.v:8766.11-8766.29" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8768.11-8768.15" + case + attribute \src "ls180.v:8769.8-8771.11" + switch \builder_request [3] + attribute \src "ls180.v:8769.12-8769.30" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + case + end + end + end + end + case + end + case + end + attribute \src "ls180.v:8779.2-8785.5" + switch \builder_wait + attribute \src "ls180.v:8779.6-8779.18" + case 1'1 + attribute \src "ls180.v:8780.3-8782.6" + switch $not$ls180.v:8780$2678_Y + attribute \src "ls180.v:8780.7-8780.22" + case 1'1 + assign $0\builder_count[19:0] $sub$ls180.v:8781$2679_Y + case + end + attribute \src "ls180.v:8783.6-8783.10" + case + assign $0\builder_count[19:0] 20'11110100001001000000 + end + attribute \src "ls180.v:8787.2-8817.5" + switch \builder_csrbank0_sel + attribute \src "ls180.v:8787.6-8787.26" + case 1'1 + attribute \src "ls180.v:8788.3-8816.10" + switch \builder_interface0_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w + case + end + case + end + attribute \src "ls180.v:8818.2-8820.5" + switch \builder_csrbank0_reset0_re + attribute \src "ls180.v:8818.6-8818.32" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r + case + end + attribute \src "ls180.v:8822.2-8824.5" + switch \builder_csrbank0_scratch3_re + attribute \src "ls180.v:8822.6-8822.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r + case + end + attribute \src "ls180.v:8825.2-8827.5" + switch \builder_csrbank0_scratch2_re + attribute \src "ls180.v:8825.6-8825.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r + case + end + attribute \src "ls180.v:8828.2-8830.5" + switch \builder_csrbank0_scratch1_re + attribute \src "ls180.v:8828.6-8828.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r + case + end + attribute \src "ls180.v:8831.2-8833.5" + switch \builder_csrbank0_scratch0_re + attribute \src "ls180.v:8831.6-8831.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r + case + end + attribute \src "ls180.v:8836.2-8857.5" + switch \builder_csrbank1_sel + attribute \src "ls180.v:8836.6-8836.26" + case 1'1 + attribute \src "ls180.v:8837.3-8856.10" + switch \builder_interface1_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w + case + end + case + end + attribute \src "ls180.v:8858.2-8860.5" + switch \builder_csrbank1_oe1_re + attribute \src "ls180.v:8858.6-8858.29" + case 1'1 + assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r + case + end + attribute \src "ls180.v:8861.2-8863.5" + switch \builder_csrbank1_oe0_re + attribute \src "ls180.v:8861.6-8861.29" + case 1'1 + assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r + case + end + attribute \src "ls180.v:8865.2-8867.5" + switch \builder_csrbank1_out1_re + attribute \src "ls180.v:8865.6-8865.30" + case 1'1 + assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r + case + end + attribute \src "ls180.v:8868.2-8870.5" + switch \builder_csrbank1_out0_re + attribute \src "ls180.v:8868.6-8868.30" + case 1'1 + assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r + case + end + attribute \src "ls180.v:8873.2-8882.5" + switch \builder_csrbank2_sel + attribute \src "ls180.v:8873.6-8873.26" + case 1'1 + attribute \src "ls180.v:8874.3-8881.10" + switch \builder_interface2_bank_bus_adr [0] + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } + case + end + case + end + attribute \src "ls180.v:8883.2-8885.5" + switch \builder_csrbank2_w0_re + attribute \src "ls180.v:8883.6-8883.28" + case 1'1 + assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r + case + end + attribute \src "ls180.v:8888.2-8918.5" + switch \builder_csrbank3_sel + attribute \src "ls180.v:8888.6-8888.26" + case 1'1 + attribute \src "ls180.v:8889.3-8917.10" + switch \builder_interface3_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w + case + end + case + end + attribute \src "ls180.v:8919.2-8921.5" + switch \builder_csrbank3_enable0_re + attribute \src "ls180.v:8919.6-8919.33" + case 1'1 + assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r + case + end + attribute \src "ls180.v:8923.2-8925.5" + switch \builder_csrbank3_width3_re + attribute \src "ls180.v:8923.6-8923.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r + case + end + attribute \src "ls180.v:8926.2-8928.5" + switch \builder_csrbank3_width2_re + attribute \src "ls180.v:8926.6-8926.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r + case + end + attribute \src "ls180.v:8929.2-8931.5" + switch \builder_csrbank3_width1_re + attribute \src "ls180.v:8929.6-8929.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r + case + end + attribute \src "ls180.v:8932.2-8934.5" + switch \builder_csrbank3_width0_re + attribute \src "ls180.v:8932.6-8932.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r + case + end + attribute \src "ls180.v:8936.2-8938.5" + switch \builder_csrbank3_period3_re + attribute \src "ls180.v:8936.6-8936.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r + case + end + attribute \src "ls180.v:8939.2-8941.5" + switch \builder_csrbank3_period2_re + attribute \src "ls180.v:8939.6-8939.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r + case + end + attribute \src "ls180.v:8942.2-8944.5" + switch \builder_csrbank3_period1_re + attribute \src "ls180.v:8942.6-8942.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r + case + end + attribute \src "ls180.v:8945.2-8947.5" + switch \builder_csrbank3_period0_re + attribute \src "ls180.v:8945.6-8945.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r + case + end + attribute \src "ls180.v:8950.2-8980.5" + switch \builder_csrbank4_sel + attribute \src "ls180.v:8950.6-8950.26" + case 1'1 + attribute \src "ls180.v:8951.3-8979.10" + switch \builder_interface4_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w + case + end + case + end + attribute \src "ls180.v:8981.2-8983.5" + switch \builder_csrbank4_enable0_re + attribute \src "ls180.v:8981.6-8981.33" + case 1'1 + assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r + case + end + attribute \src "ls180.v:8985.2-8987.5" + switch \builder_csrbank4_width3_re + attribute \src "ls180.v:8985.6-8985.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r + case + end + attribute \src "ls180.v:8988.2-8990.5" + switch \builder_csrbank4_width2_re + attribute \src "ls180.v:8988.6-8988.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r + case + end + attribute \src "ls180.v:8991.2-8993.5" + switch \builder_csrbank4_width1_re + attribute \src "ls180.v:8991.6-8991.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r + case + end + attribute \src "ls180.v:8994.2-8996.5" + switch \builder_csrbank4_width0_re + attribute \src "ls180.v:8994.6-8994.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r + case + end + attribute \src "ls180.v:8998.2-9000.5" + switch \builder_csrbank4_period3_re + attribute \src "ls180.v:8998.6-8998.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r + case + end + attribute \src "ls180.v:9001.2-9003.5" + switch \builder_csrbank4_period2_re + attribute \src "ls180.v:9001.6-9001.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r + case + end + attribute \src "ls180.v:9004.2-9006.5" + switch \builder_csrbank4_period1_re + attribute \src "ls180.v:9004.6-9004.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r + case + end + attribute \src "ls180.v:9007.2-9009.5" + switch \builder_csrbank4_period0_re + attribute \src "ls180.v:9007.6-9007.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r + case + end + attribute \src "ls180.v:9012.2-9060.5" + switch \builder_csrbank5_sel + attribute \src "ls180.v:9012.6-9012.26" + case 1'1 + attribute \src "ls180.v:9013.3-9059.10" + switch \builder_interface5_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 4'1010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } + case + end + case + end + attribute \src "ls180.v:9061.2-9063.5" + switch \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:9061.6-9061.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r + case + end + attribute \src "ls180.v:9064.2-9066.5" + switch \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:9064.6-9064.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r + case + end + attribute \src "ls180.v:9067.2-9069.5" + switch \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:9067.6-9067.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r + case + end + attribute \src "ls180.v:9070.2-9072.5" + switch \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:9070.6-9070.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r + case + end + attribute \src "ls180.v:9073.2-9075.5" + switch \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:9073.6-9073.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r + case + end + attribute \src "ls180.v:9076.2-9078.5" + switch \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:9076.6-9076.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r + case + end + attribute \src "ls180.v:9079.2-9081.5" + switch \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:9079.6-9079.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r + case + end + attribute \src "ls180.v:9082.2-9084.5" + switch \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:9082.6-9082.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r + case + end + attribute \src "ls180.v:9086.2-9088.5" + switch \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:9086.6-9086.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r + case + end + attribute \src "ls180.v:9089.2-9091.5" + switch \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:9089.6-9089.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r + case + end + attribute \src "ls180.v:9092.2-9094.5" + switch \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:9092.6-9092.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r + case + end + attribute \src "ls180.v:9095.2-9097.5" + switch \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:9095.6-9095.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r + case + end + attribute \src "ls180.v:9099.2-9101.5" + switch \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:9099.6-9099.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r + case + end + attribute \src "ls180.v:9103.2-9105.5" + switch \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:9103.6-9103.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r + case + end + attribute \src "ls180.v:9108.2-9210.5" + switch \builder_csrbank6_sel + attribute \src "ls180.v:9108.6-9108.26" + case 1'1 + attribute \src "ls180.v:9109.3-9209.10" + switch \builder_interface6_bank_bus_adr [5:0] + attribute \src "ls180.v:0.0-0.0" + case 6'000000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:0.0-0.0" + case 6'000100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:0.0-0.0" + case 6'001000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } + attribute \src "ls180.v:0.0-0.0" + case 6'001001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:0.0-0.0" + case 6'001010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:0.0-0.0" + case 6'001011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:0.0-0.0" + case 6'001100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:0.0-0.0" + case 6'001101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:0.0-0.0" + case 6'001110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:0.0-0.0" + case 6'001111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:0.0-0.0" + case 6'010000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:0.0-0.0" + case 6'010001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:0.0-0.0" + case 6'010010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:0.0-0.0" + case 6'010011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:0.0-0.0" + case 6'010100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:0.0-0.0" + case 6'010101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:0.0-0.0" + case 6'010110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:0.0-0.0" + case 6'010111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:0.0-0.0" + case 6'011000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w + attribute \src "ls180.v:0.0-0.0" + case 6'011110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w + attribute \src "ls180.v:0.0-0.0" + case 6'011111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w + attribute \src "ls180.v:0.0-0.0" + case 6'100000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w + case + end + case + end + attribute \src "ls180.v:9211.2-9213.5" + switch \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:9211.6-9211.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r + case + end + attribute \src "ls180.v:9214.2-9216.5" + switch \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:9214.6-9214.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r + case + end + attribute \src "ls180.v:9217.2-9219.5" + switch \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:9217.6-9217.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r + case + end + attribute \src "ls180.v:9220.2-9222.5" + switch \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:9220.6-9220.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r + case + end + attribute \src "ls180.v:9224.2-9226.5" + switch \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:9224.6-9224.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r + case + end + attribute \src "ls180.v:9227.2-9229.5" + switch \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:9227.6-9227.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r + case + end + attribute \src "ls180.v:9230.2-9232.5" + switch \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:9230.6-9230.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r + case + end + attribute \src "ls180.v:9233.2-9235.5" + switch \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:9233.6-9233.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r + case + end + attribute \src "ls180.v:9237.2-9239.5" + switch \builder_csrbank6_block_length1_re + attribute \src "ls180.v:9237.6-9237.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r + case + end + attribute \src "ls180.v:9240.2-9242.5" + switch \builder_csrbank6_block_length0_re + attribute \src "ls180.v:9240.6-9240.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r + case + end + attribute \src "ls180.v:9244.2-9246.5" + switch \builder_csrbank6_block_count3_re + attribute \src "ls180.v:9244.6-9244.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r + case + end + attribute \src "ls180.v:9247.2-9249.5" + switch \builder_csrbank6_block_count2_re + attribute \src "ls180.v:9247.6-9247.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r + case + end + attribute \src "ls180.v:9250.2-9252.5" + switch \builder_csrbank6_block_count1_re + attribute \src "ls180.v:9250.6-9250.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r + case + end + attribute \src "ls180.v:9253.2-9255.5" + switch \builder_csrbank6_block_count0_re + attribute \src "ls180.v:9253.6-9253.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r + case + end + attribute \src "ls180.v:9258.2-9318.5" + switch \builder_csrbank7_sel + attribute \src "ls180.v:9258.6-9258.26" + case 1'1 + attribute \src "ls180.v:9259.3-9317.10" + switch \builder_interface7_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:0.0-0.0" + case 5'10001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:0.0-0.0" + case 5'10010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w + case + end + case + end + attribute \src "ls180.v:9319.2-9321.5" + switch \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:9319.6-9319.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r + case + end + attribute \src "ls180.v:9322.2-9324.5" + switch \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:9322.6-9322.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r + case + end + attribute \src "ls180.v:9325.2-9327.5" + switch \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:9325.6-9325.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r + case + end + attribute \src "ls180.v:9328.2-9330.5" + switch \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:9328.6-9328.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r + case + end + attribute \src "ls180.v:9331.2-9333.5" + switch \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:9331.6-9331.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r + case + end + attribute \src "ls180.v:9334.2-9336.5" + switch \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:9334.6-9334.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r + case + end + attribute \src "ls180.v:9337.2-9339.5" + switch \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:9337.6-9337.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r + case + end + attribute \src "ls180.v:9340.2-9342.5" + switch \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:9340.6-9340.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r + case + end + attribute \src "ls180.v:9344.2-9346.5" + switch \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:9344.6-9344.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r + case + end + attribute \src "ls180.v:9347.2-9349.5" + switch \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:9347.6-9347.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r + case + end + attribute \src "ls180.v:9350.2-9352.5" + switch \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:9350.6-9350.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r + case + end + attribute \src "ls180.v:9353.2-9355.5" + switch \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:9353.6-9353.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r + case + end + attribute \src "ls180.v:9357.2-9359.5" + switch \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:9357.6-9357.37" + case 1'1 + assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r + case + end + attribute \src "ls180.v:9361.2-9363.5" + switch \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:9361.6-9361.35" + case 1'1 + assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r + case + end + attribute \src "ls180.v:9366.2-9381.5" + switch \builder_csrbank8_sel + attribute \src "ls180.v:9366.6-9366.26" + case 1'1 + attribute \src "ls180.v:9367.3-9380.10" + switch \builder_interface8_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } + case + end + case + end + attribute \src "ls180.v:9382.2-9384.5" + switch \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:9382.6-9382.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r + case + end + attribute \src "ls180.v:9385.2-9387.5" + switch \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:9385.6-9385.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r + case + end + attribute \src "ls180.v:9390.2-9423.5" + switch \builder_csrbank9_sel + attribute \src "ls180.v:9390.6-9390.26" + case 1'1 + attribute \src "ls180.v:9391.3-9422.10" + switch \builder_interface9_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w + case + end + case + end + attribute \src "ls180.v:9424.2-9426.5" + switch \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:9424.6-9424.39" + case 1'1 + assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r + case + end + attribute \src "ls180.v:9428.2-9430.5" + switch \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:9428.6-9428.43" + case 1'1 + assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r + case + end + attribute \src "ls180.v:9432.2-9434.5" + switch \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:9432.6-9432.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r + case + end + attribute \src "ls180.v:9435.2-9437.5" + switch \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:9435.6-9435.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r + case + end + attribute \src "ls180.v:9439.2-9441.5" + switch \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:9439.6-9439.44" + case 1'1 + assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r + case + end + attribute \src "ls180.v:9443.2-9445.5" + switch \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:9443.6-9443.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r + case + end + attribute \src "ls180.v:9446.2-9448.5" + switch \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:9446.6-9446.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r + case + end + attribute \src "ls180.v:9451.2-9475.5" + switch \builder_csrbank10_sel + attribute \src "ls180.v:9451.6-9451.27" + case 1'1 + attribute \src "ls180.v:9452.3-9474.10" + switch \builder_interface10_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } + case + end + case + end + attribute \src "ls180.v:9476.2-9478.5" + switch \builder_csrbank10_control1_re + attribute \src "ls180.v:9476.6-9476.35" + case 1'1 + assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r + case + end + attribute \src "ls180.v:9479.2-9481.5" + switch \builder_csrbank10_control0_re + attribute \src "ls180.v:9479.6-9479.35" + case 1'1 + assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r + case + end + attribute \src "ls180.v:9483.2-9485.5" + switch \builder_csrbank10_mosi0_re + attribute \src "ls180.v:9483.6-9483.32" + case 1'1 + assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r + case + end + attribute \src "ls180.v:9487.2-9489.5" + switch \builder_csrbank10_cs0_re + attribute \src "ls180.v:9487.6-9487.30" + case 1'1 + assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r + case + end + attribute \src "ls180.v:9491.2-9493.5" + switch \builder_csrbank10_loopback0_re + attribute \src "ls180.v:9491.6-9491.36" + case 1'1 + assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r + case + end + attribute \src "ls180.v:9496.2-9526.5" + switch \builder_csrbank11_sel + attribute \src "ls180.v:9496.6-9496.27" + case 1'1 + attribute \src "ls180.v:9497.3-9525.10" + switch \builder_interface11_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w + case + end + case + end + attribute \src "ls180.v:9527.2-9529.5" + switch \builder_csrbank11_control1_re + attribute \src "ls180.v:9527.6-9527.35" + case 1'1 + assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r + case + end + attribute \src "ls180.v:9530.2-9532.5" + switch \builder_csrbank11_control0_re + attribute \src "ls180.v:9530.6-9530.35" + case 1'1 + assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r + case + end + attribute \src "ls180.v:9534.2-9536.5" + switch \builder_csrbank11_mosi0_re + attribute \src "ls180.v:9534.6-9534.32" + case 1'1 + assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r + case + end + attribute \src "ls180.v:9538.2-9540.5" + switch \builder_csrbank11_cs0_re + attribute \src "ls180.v:9538.6-9538.30" + case 1'1 + assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r + case + end + attribute \src "ls180.v:9542.2-9544.5" + switch \builder_csrbank11_loopback0_re + attribute \src "ls180.v:9542.6-9542.36" + case 1'1 + assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r + case + end + attribute \src "ls180.v:9546.2-9548.5" + switch \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:9546.6-9546.39" + case 1'1 + assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r + case + end + attribute \src "ls180.v:9549.2-9551.5" + switch \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:9549.6-9549.39" + case 1'1 + assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r + case + end + attribute \src "ls180.v:9554.2-9608.5" + switch \builder_csrbank12_sel + attribute \src "ls180.v:9554.6-9554.27" + case 1'1 + attribute \src "ls180.v:9555.3-9607.10" + switch \builder_interface12_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } + case + end + case + end + attribute \src "ls180.v:9609.2-9611.5" + switch \builder_csrbank12_load3_re + attribute \src "ls180.v:9609.6-9609.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r + case + end + attribute \src "ls180.v:9612.2-9614.5" + switch \builder_csrbank12_load2_re + attribute \src "ls180.v:9612.6-9612.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r + case + end + attribute \src "ls180.v:9615.2-9617.5" + switch \builder_csrbank12_load1_re + attribute \src "ls180.v:9615.6-9615.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r + case + end + attribute \src "ls180.v:9618.2-9620.5" + switch \builder_csrbank12_load0_re + attribute \src "ls180.v:9618.6-9618.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r + case + end + attribute \src "ls180.v:9622.2-9624.5" + switch \builder_csrbank12_reload3_re + attribute \src "ls180.v:9622.6-9622.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r + case + end + attribute \src "ls180.v:9625.2-9627.5" + switch \builder_csrbank12_reload2_re + attribute \src "ls180.v:9625.6-9625.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r + case + end + attribute \src "ls180.v:9628.2-9630.5" + switch \builder_csrbank12_reload1_re + attribute \src "ls180.v:9628.6-9628.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r + case + end + attribute \src "ls180.v:9631.2-9633.5" + switch \builder_csrbank12_reload0_re + attribute \src "ls180.v:9631.6-9631.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r + case + end + attribute \src "ls180.v:9635.2-9637.5" + switch \builder_csrbank12_en0_re + attribute \src "ls180.v:9635.6-9635.30" + case 1'1 + assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r + case + end + attribute \src "ls180.v:9639.2-9641.5" + switch \builder_csrbank12_update_value0_re + attribute \src "ls180.v:9639.6-9639.40" + case 1'1 + assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r + case + end + attribute \src "ls180.v:9643.2-9645.5" + switch \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:9643.6-9643.37" + case 1'1 + assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r + case + end + attribute \src "ls180.v:9648.2-9675.5" + switch \builder_csrbank13_sel + attribute \src "ls180.v:9648.6-9648.27" + case 1'1 + attribute \src "ls180.v:9649.3-9674.10" + switch \builder_interface13_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } + case + end + case + end + attribute \src "ls180.v:9676.2-9678.5" + switch \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:9676.6-9676.37" + case 1'1 + assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r + case + end + attribute \src "ls180.v:9681.2-9696.5" + switch \builder_csrbank14_sel + attribute \src "ls180.v:9681.6-9681.27" + case 1'1 + attribute \src "ls180.v:9682.3-9695.10" + switch \builder_interface14_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w + case + end + case + end + attribute \src "ls180.v:9697.2-9699.5" + switch \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:9697.6-9697.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r + case + end + attribute \src "ls180.v:9700.2-9702.5" + switch \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:9700.6-9700.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r + case + end + attribute \src "ls180.v:9703.2-9705.5" + switch \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:9703.6-9703.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r + case + end + attribute \src "ls180.v:9706.2-9708.5" + switch \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:9706.6-9706.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r + case + end + attribute \src "ls180.v:9710.2-10004.5" + switch \sys_rst_1 + attribute \src "ls180.v:9710.6-9710.15" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] 1'0 + assign $0\main_libresocsim_reset_re[0:0] 1'0 + assign $0\main_libresocsim_scratch_storage[31:0] 305419896 + assign $0\main_libresocsim_scratch_re[0:0] 1'0 + assign $0\main_libresocsim_bus_errors[31:0] 0 + assign $0\spimaster_clk[0:0] 1'0 + assign $0\spimaster_mosi[0:0] 1'0 + assign $0\spimaster_cs_n[0:0] 1'0 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\uart_tx[0:0] 1'1 + assign $0\pwm[1:0] 2'00 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_load_storage[31:0] 0 + assign $0\main_libresocsim_load_re[0:0] 1'0 + assign $0\main_libresocsim_reload_storage[31:0] 0 + assign $0\main_libresocsim_reload_re[0:0] 1'0 + assign $0\main_libresocsim_en_storage[0:0] 1'0 + assign $0\main_libresocsim_en_re[0:0] 1'0 + assign $0\main_libresocsim_update_value_storage[0:0] 1'0 + assign $0\main_libresocsim_update_value_re[0:0] 1'0 + assign $0\main_libresocsim_value_status[31:0] 0 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $0\main_libresocsim_value[31:0] 0 + assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $0\main_rddata_en[2:0] 3'000 + assign $0\main_sdram_storage[3:0] 4'0001 + assign $0\main_sdram_re[0:0] 1'0 + assign $0\main_sdram_command_storage[5:0] 6'000000 + assign $0\main_sdram_command_re[0:0] 1'0 + assign $0\main_sdram_address_re[0:0] 1'0 + assign $0\main_sdram_baddress_re[0:0] 1'0 + assign $0\main_sdram_wrdata_re[0:0] 1'0 + assign $0\main_sdram_status[15:0] 16'0000000000000000 + assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + assign $0\main_sdram_tccdcon_ready[0:0] 1'0 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + assign $0\main_sdram_twtrcon_count[2:0] 3'000 + assign $0\main_sdram_time0[4:0] 5'00000 + assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + assign $0\main_uart_phy_storage[31:0] 9895604 + assign $0\main_uart_phy_re[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] 1'0 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_eventmanager_storage[1:0] 2'00 + assign $0\main_uart_eventmanager_re[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + assign $0\main_gpio_oe_storage[15:0] 16'0000000000000000 + assign $0\main_gpio_oe_re[0:0] 1'0 + assign $0\main_gpio_out_storage[15:0] 16'0000000000000000 + assign $0\main_gpio_out_re[0:0] 1'0 + assign $0\main_spimaster5_miso[7:0] 8'00000000 + assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 + assign $0\main_spimaster12_re[0:0] 1'0 + assign $0\main_spimaster17_re[0:0] 1'0 + assign $0\main_spimaster21_storage[0:0] 1'1 + assign $0\main_spimaster22_re[0:0] 1'0 + assign $0\main_spimaster23_storage[0:0] 1'0 + assign $0\main_spimaster24_re[0:0] 1'0 + assign $0\main_spimaster27_count[2:0] 3'000 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\main_spimaster33_mosi_data[7:0] 8'00000000 + assign $0\main_spimaster34_mosi_sel[2:0] 3'000 + assign $0\main_spimaster35_miso_data[7:0] 8'00000000 + assign $0\main_spisdcard_miso[7:0] 8'00000000 + assign $0\main_spisdcard_control_storage[15:0] 16'0000000000000000 + assign $0\main_spisdcard_control_re[0:0] 1'0 + assign $0\main_spisdcard_mosi_re[0:0] 1'0 + assign $0\main_spisdcard_cs_storage[0:0] 1'1 + assign $0\main_spisdcard_cs_re[0:0] 1'0 + assign $0\main_spisdcard_loopback_storage[0:0] 1'0 + assign $0\main_spisdcard_loopback_re[0:0] 1'0 + assign $0\main_spisdcard_count[2:0] 3'000 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\main_spisdcard_mosi_data[7:0] 8'00000000 + assign $0\main_spisdcard_mosi_sel[2:0] 3'000 + assign $0\main_spisdcard_miso_data[7:0] 8'00000000 + assign $0\main_spimaster1_storage[15:0] 16'0000000001111101 + assign $0\main_spimaster1_re[0:0] 1'0 + assign $0\main_dummy[23:0] 24'000000000000000000000000 + assign $0\main_pwm0_enable_storage[0:0] 1'0 + assign $0\main_pwm0_enable_re[0:0] 1'0 + assign $0\main_pwm0_width_re[0:0] 1'0 + assign $0\main_pwm0_period_re[0:0] 1'0 + assign $0\main_pwm1_enable_storage[0:0] 1'0 + assign $0\main_pwm1_enable_re[0:0] 1'0 + assign $0\main_pwm1_width_re[0:0] 1'0 + assign $0\main_pwm1_period_re[0:0] 1'0 + assign $0\main_i2c_storage[2:0] 3'000 + assign $0\main_i2c_re[0:0] 1'0 + assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 + assign $0\main_sdphy_clocker_re[0:0] 1'0 + assign $0\main_sdphy_clocker_clk0[0:0] 1'0 + assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 + assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 + assign $0\main_sdphy_init_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_timeout[31:0] 500000 + assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + assign $0\main_sdphy_dataw_count[7:0] 8'00000000 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 + assign $0\main_sdphy_datar_timeout[31:0] 500000 + assign $0\main_sdphy_datar_count[9:0] 10'0000000000 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 + assign $0\main_sdcore_cmd_argument_storage[31:0] 0 + assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 + assign $0\main_sdcore_cmd_command_storage[31:0] 0 + assign $0\main_sdcore_cmd_command_re[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 + assign $0\main_sdcore_block_length_re[0:0] 1'0 + assign $0\main_sdcore_block_count_storage[31:0] 0 + assign $0\main_sdcore_block_count_re[0:0] 1'0 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + assign $0\main_sdcore_cmd_count[2:0] 3'000 + assign $0\main_sdcore_cmd_done[0:0] 1'0 + assign $0\main_sdcore_cmd_error[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout[0:0] 1'0 + assign $0\main_sdcore_data_count[31:0] 0 + assign $0\main_sdcore_data_done[0:0] 1'0 + assign $0\main_sdcore_data_error[0:0] 1'0 + assign $0\main_sdcore_data_timeout[0:0] 1'0 + assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 + assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 + assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 + assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\main_sdmem2block_dma_data[31:0] 0 + assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_length_storage[31:0] 0 + assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 + assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 + assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 + assign $0\builder_converter0_state[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + assign $0\builder_refresher_state[1:0] 2'00 + assign $0\builder_bankmachine0_state[2:0] 3'000 + assign $0\builder_bankmachine1_state[2:0] 3'000 + assign $0\builder_bankmachine2_state[2:0] 3'000 + assign $0\builder_bankmachine3_state[2:0] 3'000 + assign $0\builder_multiplexer_state[2:0] 3'000 + assign $0\builder_new_master_wdata_ready[0:0] 1'0 + assign $0\builder_new_master_rdata_valid0[0:0] 1'0 + assign $0\builder_new_master_rdata_valid1[0:0] 1'0 + assign $0\builder_new_master_rdata_valid2[0:0] 1'0 + assign $0\builder_new_master_rdata_valid3[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + assign $0\builder_spimaster0_state[1:0] 2'00 + assign $0\builder_spimaster1_state[1:0] 2'00 + assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 + assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 + assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 + assign $0\builder_sdphy_fsm_state[2:0] 3'000 + assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + assign $0\builder_sdcore_fsm_state[2:0] 3'000 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + assign $0\builder_libresocsim_we[0:0] 1'0 + assign $0\builder_grant[2:0] 3'000 + assign $0\builder_slave_sel_r[4:0] 5'00000 + assign $0\builder_count[19:0] 20'11110100001001000000 + assign $0\builder_state[1:0] 2'00 + case + end + sync posedge \sys_clk_1 + update \spimaster_clk $0\spimaster_clk[0:0] + update \spimaster_mosi $0\spimaster_mosi[0:0] + update \spimaster_cs_n $0\spimaster_cs_n[0:0] + update \spisdcard_clk $0\spisdcard_clk[0:0] + update \spisdcard_mosi $0\spisdcard_mosi[0:0] + update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \uart_tx $0\uart_tx[0:0] + update \pwm $0\pwm[1:0] + update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] + update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] + update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] + update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] + update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] + update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] + update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] + update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] + update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] + update \main_libresocsim_converter2_counter $0\main_libresocsim_converter2_counter[0:0] + update \main_libresocsim_converter2_dat_r $0\main_libresocsim_converter2_dat_r[63:0] + update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] + update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] + update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] + update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] + update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] + update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] + update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] + update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] + update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] + update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] + update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] + update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] + update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] + update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] + update \main_libresocsim_value $0\main_libresocsim_value[31:0] + update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] + update \main_rddata_en $0\main_rddata_en[2:0] + update \main_sdram_storage $0\main_sdram_storage[3:0] + update \main_sdram_re $0\main_sdram_re[0:0] + update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] + update \main_sdram_command_re $0\main_sdram_command_re[0:0] + update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] + update \main_sdram_address_re $0\main_sdram_address_re[0:0] + update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] + update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] + update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] + update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] + update \main_sdram_status $0\main_sdram_status[15:0] + update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] + update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] + update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] + update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] + update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] + update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] + update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] + update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] + update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] + update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] + update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] + update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] + update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] + update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] + update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] + update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] + update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] + update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] + update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] + update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] + update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] + update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] + update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] + update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] + update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] + update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] + update \main_sdram_time0 $0\main_sdram_time0[4:0] + update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_converter_counter $0\main_converter_counter[0:0] + update \main_converter_dat_r $0\main_converter_dat_r[31:0] + update \main_cmd_consumed $0\main_cmd_consumed[0:0] + update \main_wdata_consumed $0\main_wdata_consumed[0:0] + update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] + update \main_uart_phy_re $0\main_uart_phy_re[0:0] + update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] + update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] + update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] + update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] + update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] + update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] + update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] + update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] + update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] + update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] + update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] + update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] + update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] + update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] + update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] + update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] + update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] + update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] + update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] + update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] + update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] + update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] + update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] + update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] + update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] + update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] + update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] + update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] + update \main_gpio_oe_storage $0\main_gpio_oe_storage[15:0] + update \main_gpio_oe_re $0\main_gpio_oe_re[0:0] + update \main_gpio_out_storage $0\main_gpio_out_storage[15:0] + update \main_gpio_out_re $0\main_gpio_out_re[0:0] + update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] + update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] + update \main_spimaster12_re $0\main_spimaster12_re[0:0] + update \main_spimaster16_storage $0\main_spimaster16_storage[7:0] + update \main_spimaster17_re $0\main_spimaster17_re[0:0] + update \main_spimaster21_storage $0\main_spimaster21_storage[0:0] + update \main_spimaster22_re $0\main_spimaster22_re[0:0] + update \main_spimaster23_storage $0\main_spimaster23_storage[0:0] + update \main_spimaster24_re $0\main_spimaster24_re[0:0] + update \main_spimaster27_count $0\main_spimaster27_count[2:0] + update \main_spimaster30_clk_divider $0\main_spimaster30_clk_divider[15:0] + update \main_spimaster33_mosi_data $0\main_spimaster33_mosi_data[7:0] + update \main_spimaster34_mosi_sel $0\main_spimaster34_mosi_sel[2:0] + update \main_spimaster35_miso_data $0\main_spimaster35_miso_data[7:0] + update \main_spisdcard_miso $0\main_spisdcard_miso[7:0] + update \main_spisdcard_control_storage $0\main_spisdcard_control_storage[15:0] + update \main_spisdcard_control_re $0\main_spisdcard_control_re[0:0] + update \main_spisdcard_mosi_storage $0\main_spisdcard_mosi_storage[7:0] + update \main_spisdcard_mosi_re $0\main_spisdcard_mosi_re[0:0] + update \main_spisdcard_cs_storage $0\main_spisdcard_cs_storage[0:0] + update \main_spisdcard_cs_re $0\main_spisdcard_cs_re[0:0] + update \main_spisdcard_loopback_storage $0\main_spisdcard_loopback_storage[0:0] + update \main_spisdcard_loopback_re $0\main_spisdcard_loopback_re[0:0] + update \main_spisdcard_count $0\main_spisdcard_count[2:0] + update \main_spisdcard_clk_divider1 $0\main_spisdcard_clk_divider1[15:0] + update \main_spisdcard_mosi_data $0\main_spisdcard_mosi_data[7:0] + update \main_spisdcard_mosi_sel $0\main_spisdcard_mosi_sel[2:0] + update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0] + update \main_spimaster1_storage $0\main_spimaster1_storage[15:0] + update \main_spimaster1_re $0\main_spimaster1_re[0:0] + update \main_dummy $0\main_dummy[23:0] + update \main_pwm0_counter $0\main_pwm0_counter[31:0] + update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] + update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] + update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] + update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] + update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] + update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] + update \main_pwm1_counter $0\main_pwm1_counter[31:0] + update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] + update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] + update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] + update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] + update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] + update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] + update \main_i2c_storage $0\main_i2c_storage[2:0] + update \main_i2c_re $0\main_i2c_re[0:0] + update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] + update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] + update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] + update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] + update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] + update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] + update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] + update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] + update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] + update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] + update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] + update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] + update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] + update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] + update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] + update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] + update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] + update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] + update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] + update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] + update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] + update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] + update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] + update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] + update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] + update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] + update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] + update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] + update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] + update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] + update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] + update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] + update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] + update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] + update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] + update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] + update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] + update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] + update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] + update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] + update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] + update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] + update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] + update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] + update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] + update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] + update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] + update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] + update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] + update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] + update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] + update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] + update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] + update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] + update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] + update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] + update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] + update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[31:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[1:0] + update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] + update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[31:0] + update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] + update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] + update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] + update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] + update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] + update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] + update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] + update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] + update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] + update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[1:0] + update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] + update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] + update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] + update \builder_converter0_state $0\builder_converter0_state[0:0] + update \builder_converter1_state $0\builder_converter1_state[0:0] + update \builder_converter2_state $0\builder_converter2_state[0:0] + update \builder_refresher_state $0\builder_refresher_state[1:0] + update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] + update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] + update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] + update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] + update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] + update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] + update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] + update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] + update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] + update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] + update \builder_converter_state $0\builder_converter_state[0:0] + update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] + update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] + update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] + update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] + update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] + update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] + update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] + update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] + update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] + update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] + update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] + update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] + update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] + update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] + update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] + update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] + update \builder_grant $0\builder_grant[2:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[4:0] + update \builder_count $0\builder_count[19:0] + update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] + update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] + update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] + update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] + update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] + update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] + update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] + update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] + update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] + update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] + update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] + update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] + update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] + update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] + update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] + update \builder_state $0\builder_state[1:0] + update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] + update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] + update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] + update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] + update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] + update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] + update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] + update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] + update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] + update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] + update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] + update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] + update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] + update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] + update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] + update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] + update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] + update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] + update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] + update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] + update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] + update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] + update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] + update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] + update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] + update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] + update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] + update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] + update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] + update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] + update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] + update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] + update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] + update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:744.5-744.49" + process $proc$ls180.v:744$3034 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:745.5-745.49" + process $proc$ls180.v:745$3035 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:746.5-746.48" + process $proc$ls180.v:746$3036 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:750.11-750.46" + process $proc$ls180.v:750$3037 + assign { } { } + assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:752.11-752.45" + process $proc$ls180.v:752$3038 + assign { } { } + assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + end + attribute \src "ls180.v:754.5-754.44" + process $proc$ls180.v:754$3039 + assign { } { } + assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] + end + attribute \src "ls180.v:755.5-755.45" + process $proc$ls180.v:755$3040 + assign { } { } + assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] + end + attribute \src "ls180.v:757.5-757.48" + process $proc$ls180.v:757$3041 + assign { } { } + assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] + end + attribute \src "ls180.v:759.5-759.43" + process $proc$ls180.v:759$3042 + assign { } { } + assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] + end + attribute \src "ls180.v:762.5-762.49" + process $proc$ls180.v:762$3043 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:763.5-763.49" + process $proc$ls180.v:763$3044 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:764.5-764.48" + process $proc$ls180.v:764$3045 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:768.11-768.46" + process $proc$ls180.v:768$3046 + assign { } { } + assign $1\main_sdram_choose_req_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:770.11-770.45" + process $proc$ls180.v:770$3047 + assign { } { } + assign $1\main_sdram_choose_req_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] + end + attribute \src "ls180.v:772.12-772.36" + process $proc$ls180.v:772$3048 + assign { } { } + assign $0\main_sdram_nop_a[12:0] 13'0000000000000 + sync always + update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] + sync init + end + attribute \src "ls180.v:773.11-773.35" + process $proc$ls180.v:773$3049 + assign { } { } + assign $0\main_sdram_nop_ba[1:0] 2'00 + sync always + update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] + sync init + end + attribute \src "ls180.v:774.11-774.40" + process $proc$ls180.v:774$3050 + assign { } { } + assign $1\main_sdram_steerer_sel[1:0] 2'00 + sync always + sync init + update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] + end + attribute \src "ls180.v:775.5-775.31" + process $proc$ls180.v:775$3051 + assign { } { } + assign $0\main_sdram_steerer0[0:0] 1'1 + sync always + update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] + sync init + end + attribute \src "ls180.v:776.5-776.31" + process $proc$ls180.v:776$3052 + assign { } { } + assign $0\main_sdram_steerer1[0:0] 1'1 + sync always + update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] + sync init + end + attribute \src "ls180.v:778.32-778.63" + process $proc$ls180.v:778$3053 + assign { } { } + assign $0\main_sdram_trrdcon_ready[0:0] 1'1 + sync always + update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] + sync init + end + attribute \src "ls180.v:780.32-780.63" + process $proc$ls180.v:780$3054 + assign { } { } + assign $0\main_sdram_tfawcon_ready[0:0] 1'1 + sync always + update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] + sync init + end + attribute \src "ls180.v:782.32-782.63" + process $proc$ls180.v:782$3055 + assign { } { } + assign $1\main_sdram_tccdcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] + end + attribute \src "ls180.v:783.5-783.36" + process $proc$ls180.v:783$3056 + assign { } { } + assign $1\main_sdram_tccdcon_count[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] + end + attribute \src "ls180.v:785.32-785.63" + process $proc$ls180.v:785$3057 + assign { } { } + assign $1\main_sdram_twtrcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] + end + attribute \src "ls180.v:786.11-786.42" + process $proc$ls180.v:786$3058 + assign { } { } + assign $1\main_sdram_twtrcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] + end + attribute \src "ls180.v:789.5-789.26" + process $proc$ls180.v:789$3059 + assign { } { } + assign $1\main_sdram_en0[0:0] 1'0 + sync always + sync init + update \main_sdram_en0 $1\main_sdram_en0[0:0] + end + attribute \src "ls180.v:791.11-791.34" + process $proc$ls180.v:791$3060 + assign { } { } + assign $1\main_sdram_time0[4:0] 5'00000 + sync always + sync init + update \main_sdram_time0 $1\main_sdram_time0[4:0] + end + attribute \src "ls180.v:792.5-792.26" + process $proc$ls180.v:792$3061 + assign { } { } + assign $1\main_sdram_en1[0:0] 1'0 + sync always + sync init + update \main_sdram_en1 $1\main_sdram_en1[0:0] + end + attribute \src "ls180.v:794.11-794.34" + process $proc$ls180.v:794$3062 + assign { } { } + assign $1\main_sdram_time1[3:0] 4'0000 + sync always + sync init + update \main_sdram_time1 $1\main_sdram_time1[3:0] + end + attribute \src "ls180.v:81.5-81.46" + process $proc$ls180.v:81$2771 + assign { } { } + assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] + end + attribute \src "ls180.v:815.5-815.29" + process $proc$ls180.v:815$3063 + assign { } { } + assign $1\main_wb_sdram_ack[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] + end + attribute \src "ls180.v:819.5-819.29" + process $proc$ls180.v:819$3064 + assign { } { } + assign $0\main_wb_sdram_err[0:0] 1'0 + sync always + update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] + sync init + end + attribute \src "ls180.v:820.12-820.40" + process $proc$ls180.v:820$3065 + assign { } { } + assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] + end + attribute \src "ls180.v:821.12-821.42" + process $proc$ls180.v:821$3066 + assign { } { } + assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + sync always + sync init + update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:823.11-823.38" + process $proc$ls180.v:823$3067 + assign { } { } + assign $1\main_litedram_wb_sel[1:0] 2'00 + sync always + sync init + update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] + end + attribute \src "ls180.v:824.5-824.32" + process $proc$ls180.v:824$3068 + assign { } { } + assign $1\main_litedram_wb_cyc[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] + end + attribute \src "ls180.v:825.5-825.32" + process $proc$ls180.v:825$3069 + assign { } { } + assign $1\main_litedram_wb_stb[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] + end + attribute \src "ls180.v:827.5-827.31" + process $proc$ls180.v:827$3070 + assign { } { } + assign $1\main_litedram_wb_we[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] + end + attribute \src "ls180.v:828.5-828.31" + process $proc$ls180.v:828$3071 + assign { } { } + assign $1\main_converter_skip[0:0] 1'0 + sync always + sync init + update \main_converter_skip $1\main_converter_skip[0:0] + end + attribute \src "ls180.v:829.5-829.34" + process $proc$ls180.v:829$3072 + assign { } { } + assign $1\main_converter_counter[0:0] 1'0 + sync always + sync init + update \main_converter_counter $1\main_converter_counter[0:0] + end + attribute \src "ls180.v:83.5-83.46" + process $proc$ls180.v:83$2772 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] + sync init + end + attribute \src "ls180.v:831.12-831.40" + process $proc$ls180.v:831$3073 + assign { } { } + assign $1\main_converter_dat_r[31:0] 0 + sync always + sync init + update \main_converter_dat_r $1\main_converter_dat_r[31:0] + end + attribute \src "ls180.v:832.5-832.29" + process $proc$ls180.v:832$3074 + assign { } { } + assign $1\main_cmd_consumed[0:0] 1'0 + sync always + sync init + update \main_cmd_consumed $1\main_cmd_consumed[0:0] + end + attribute \src "ls180.v:833.5-833.31" + process $proc$ls180.v:833$3075 + assign { } { } + assign $1\main_wdata_consumed[0:0] 1'0 + sync always + sync init + update \main_wdata_consumed $1\main_wdata_consumed[0:0] + end + attribute \src "ls180.v:837.12-837.47" + process $proc$ls180.v:837$3076 + assign { } { } + assign $1\main_uart_phy_storage[31:0] 9895604 + sync always + sync init + update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] + end + attribute \src "ls180.v:838.5-838.28" + process $proc$ls180.v:838$3077 + assign { } { } + assign $1\main_uart_phy_re[0:0] 1'0 + sync always + sync init + update \main_uart_phy_re $1\main_uart_phy_re[0:0] + end + attribute \src "ls180.v:840.5-840.36" + process $proc$ls180.v:840$3078 + assign { } { } + assign $1\main_uart_phy_sink_ready[0:0] 1'0 + sync always + sync init + update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] + end + attribute \src "ls180.v:844.5-844.39" + process $proc$ls180.v:844$3079 + assign { } { } + assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 + sync always + sync init + update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] + end + attribute \src "ls180.v:845.12-845.54" + process $proc$ls180.v:845$3080 + assign { } { } + assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 + sync always + sync init + update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] + end + attribute \src "ls180.v:846.11-846.38" + process $proc$ls180.v:846$3081 + assign { } { } + assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] + end + attribute \src "ls180.v:847.11-847.43" + process $proc$ls180.v:847$3082 + assign { } { } + assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] + end + attribute \src "ls180.v:848.5-848.33" + process $proc$ls180.v:848$3083 + assign { } { } + assign $1\main_uart_phy_tx_busy[0:0] 1'0 + sync always + sync init + update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] + end + attribute \src "ls180.v:849.5-849.38" + process $proc$ls180.v:849$3084 + assign { } { } + assign $1\main_uart_phy_source_valid[0:0] 1'0 + sync always + sync init + update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] + end + attribute \src "ls180.v:851.5-851.38" + process $proc$ls180.v:851$3085 + assign { } { } + assign $0\main_uart_phy_source_first[0:0] 1'0 + sync always + update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] + sync init + end + attribute \src "ls180.v:852.5-852.37" + process $proc$ls180.v:852$3086 + assign { } { } + assign $0\main_uart_phy_source_last[0:0] 1'0 + sync always + update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] + sync init + end + attribute \src "ls180.v:853.11-853.51" + process $proc$ls180.v:853$3087 + assign { } { } + assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] + end + attribute \src "ls180.v:854.5-854.39" + process $proc$ls180.v:854$3088 + assign { } { } + assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 + sync always + sync init + update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] + end + attribute \src "ls180.v:855.12-855.54" + process $proc$ls180.v:855$3089 + assign { } { } + assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 + sync always + sync init + update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] + end + attribute \src "ls180.v:857.5-857.30" + process $proc$ls180.v:857$3090 + assign { } { } + assign $1\main_uart_phy_rx_r[0:0] 1'0 + sync always + sync init + update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] + end + attribute \src "ls180.v:858.11-858.38" + process $proc$ls180.v:858$3091 + assign { } { } + assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] + end + attribute \src "ls180.v:859.11-859.43" + process $proc$ls180.v:859$3092 + assign { } { } + assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] + end + attribute \src "ls180.v:860.5-860.33" + process $proc$ls180.v:860$3093 + assign { } { } + assign $1\main_uart_phy_rx_busy[0:0] 1'0 + sync always + sync init + update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] + end + attribute \src "ls180.v:871.5-871.32" + process $proc$ls180.v:871$3094 + assign { } { } + assign $1\main_uart_tx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] + end + attribute \src "ls180.v:873.5-873.30" + process $proc$ls180.v:873$3095 + assign { } { } + assign $1\main_uart_tx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:874.5-874.36" + process $proc$ls180.v:874$3096 + assign { } { } + assign $1\main_uart_tx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] + end + attribute \src "ls180.v:876.5-876.32" + process $proc$ls180.v:876$3097 + assign { } { } + assign $1\main_uart_rx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] + end + attribute \src "ls180.v:878.5-878.30" + process $proc$ls180.v:878$3098 + assign { } { } + assign $1\main_uart_rx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:879.5-879.36" + process $proc$ls180.v:879$3099 + assign { } { } + assign $1\main_uart_rx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] + end + attribute \src "ls180.v:883.11-883.49" + process $proc$ls180.v:883$3100 + assign { } { } + assign $1\main_uart_eventmanager_status_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:887.11-887.50" + process $proc$ls180.v:887$3101 + assign { } { } + assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:888.11-888.48" + process $proc$ls180.v:888$3102 + assign { } { } + assign $1\main_uart_eventmanager_storage[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] + end + attribute \src "ls180.v:889.5-889.37" + process $proc$ls180.v:889$3103 + assign { } { } + assign $1\main_uart_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] + end + attribute \src "ls180.v:906.5-906.40" + process $proc$ls180.v:906$3104 + assign { } { } + assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] + sync init + end + attribute \src "ls180.v:907.5-907.39" + process $proc$ls180.v:907$3105 + assign { } { } + assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] + sync init + end + attribute \src "ls180.v:915.5-915.38" + process $proc$ls180.v:915$3106 + assign { } { } + assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] + end + attribute \src "ls180.v:922.11-922.42" + process $proc$ls180.v:922$3107 + assign { } { } + assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] + end + attribute \src "ls180.v:923.5-923.37" + process $proc$ls180.v:923$3108 + assign { } { } + assign $0\main_uart_tx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:924.11-924.43" + process $proc$ls180.v:924$3109 + assign { } { } + assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] + end + attribute \src "ls180.v:925.11-925.43" + process $proc$ls180.v:925$3110 + assign { } { } + assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] + end + attribute \src "ls180.v:926.11-926.46" + process $proc$ls180.v:926$3111 + assign { } { } + assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:952.5-952.38" + process $proc$ls180.v:952$3112 + assign { } { } + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] + end + attribute \src "ls180.v:959.11-959.42" + process $proc$ls180.v:959$3113 + assign { } { } + assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] + end + attribute \src "ls180.v:960.5-960.37" + process $proc$ls180.v:960$3114 + assign { } { } + assign $0\main_uart_rx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:961.11-961.43" + process $proc$ls180.v:961$3115 + assign { } { } + assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] + end + attribute \src "ls180.v:962.11-962.43" + process $proc$ls180.v:962$3116 + assign { } { } + assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] + end + attribute \src "ls180.v:963.11-963.46" + process $proc$ls180.v:963$3117 + assign { } { } + assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:978.5-978.27" + process $proc$ls180.v:978$3118 + assign { } { } + assign $0\main_uart_reset[0:0] 1'0 + sync always + update \main_uart_reset $0\main_uart_reset[0:0] + sync init + end + attribute \src "ls180.v:979.12-979.40" + process $proc$ls180.v:979$3119 + assign { } { } + assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] + end + attribute \src "ls180.v:980.5-980.27" + process $proc$ls180.v:980$3120 + assign { } { } + assign $1\main_gpio_oe_re[0:0] 1'0 + sync always + sync init + update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] + end + attribute \src "ls180.v:981.12-981.36" + process $proc$ls180.v:981$3121 + assign { } { } + assign $1\main_gpio_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_status $1\main_gpio_status[15:0] + end + attribute \src "ls180.v:983.12-983.41" + process $proc$ls180.v:983$3122 + assign { } { } + assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] + end + attribute \src "ls180.v:984.5-984.28" + process $proc$ls180.v:984$3123 + assign { } { } + assign $1\main_gpio_out_re[0:0] 1'0 + sync always + sync init + update \main_gpio_out_re $1\main_gpio_out_re[0:0] + end + attribute \src "ls180.v:990.5-990.32" + process $proc$ls180.v:990$3124 + assign { } { } + assign $1\main_spimaster2_done[0:0] 1'0 + sync always + sync init + update \main_spimaster2_done $1\main_spimaster2_done[0:0] + end + attribute \src "ls180.v:991.5-991.31" + process $proc$ls180.v:991$3125 + assign { } { } + assign $1\main_spimaster3_irq[0:0] 1'0 + sync always + sync init + update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] + end + attribute \src "ls180.v:993.11-993.38" + process $proc$ls180.v:993$3126 + assign { } { } + assign $1\main_spimaster5_miso[7:0] 8'00000000 + sync always + sync init + update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] + end + attribute \src "ls180.v:996.12-996.47" + process $proc$ls180.v:996$3127 + assign { } { } + assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 + sync always + update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] + sync init + end + attribute \src "ls180.v:997.5-997.33" + process $proc$ls180.v:997$3128 + assign { } { } + assign $1\main_spimaster9_start[0:0] 1'0 + sync always + sync init + update \main_spimaster9_start $1\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:999.12-999.44" + process $proc$ls180.v:999$3129 + assign { } { } + assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] + end + connect \main_libresocsim_libresoc_reset \main_libresocsim_reset + connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i + connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o + connect \sys_pll_lck_o \main_libresocsim_libresoc_pll_lck_o + connect \main_libresocsim_libresoc_jtag_tck \jtag_tck + connect \main_libresocsim_libresoc_jtag_tms \jtag_tms + connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi + connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo + connect \main_nc \nc + connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid + connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 + connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first + connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last + connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data + connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 + connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready + connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 + connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 + connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 + connect \main_libresocsim_bus_error \builder_error + connect \main_libresocsim_converter0_reset $not$ls180.v:2773$14_Y + connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } + connect \main_libresocsim_converter1_reset $not$ls180.v:2833$25_Y + connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } + connect \main_libresocsim_converter2_reset $not$ls180.v:2893$36_Y + connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } + connect \main_libresocsim_reset \main_libresocsim_reset_re + connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] + connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r + connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w + connect \main_libresocsim_zero_trigger $ne$ls180.v:2965$60_Y + connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status + connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending + connect \main_libresocsim_irq $and$ls180.v:2974$63_Y + connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger + connect \sys_clk_1 \sys_clk + connect \por_clk \sys_clk + connect \sys_rst_1 \main_int_rst + connect \main_dfi_p0_address \main_sdram_master_p0_address + connect \main_dfi_p0_bank \main_sdram_master_p0_bank + connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n + connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n + connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n + connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n + connect \main_dfi_p0_cke \main_sdram_master_p0_cke + connect \main_dfi_p0_odt \main_sdram_master_p0_odt + connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n + connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n + connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata + connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en + connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask + connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en + connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata + connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid + connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address + connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank + connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n + connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n + connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n + connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n + connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke + connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt + connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n + connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n + connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata + connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en + connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask + connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en + connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata + connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid + connect \main_sdram_inti_p0_cke \main_sdram_cke + connect \main_sdram_inti_p0_odt \main_sdram_odt + connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n + connect \main_sdram_inti_p0_address \main_sdram_address_storage + connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3088$70_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3089$71_Y + connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage + connect \main_sdram_inti_p0_wrdata_mask 2'00 + connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid + connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready + connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we + connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr + connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock + connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready + connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid + connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid + connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready + connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we + connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr + connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock + connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready + connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid + connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid + connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready + connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we + connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr + connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock + connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready + connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid + connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid + connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready + connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we + connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr + connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock + connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready + connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid + connect \main_sdram_timer_wait $not$ls180.v:3120$72_Y + connect \main_sdram_postponer_req_i \main_sdram_timer_done0 + connect \main_sdram_wants_refresh \main_sdram_postponer_req_o + connect \main_sdram_timer_done1 $eq$ls180.v:3123$73_Y + connect \main_sdram_timer_done0 \main_sdram_timer_done1 + connect \main_sdram_timer_count0 \main_sdram_timer_count1 + connect \main_sdram_sequencer_start1 $or$ls180.v:3126$75_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3127$77_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid + connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr + connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3169$79_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3170$80_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3171$81_Y + connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3181$86_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3182$88_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3183$90_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3215$98_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3216$99_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3219$100_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3220$101_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3221$103_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid + connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr + connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3326$109_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3327$110_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3328$111_Y + connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3338$116_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3339$118_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3340$120_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3372$128_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3373$129_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3376$130_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3377$131_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3378$133_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid + connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr + connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3483$139_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3484$140_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3485$141_Y + connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3495$146_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3496$148_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3497$150_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3529$158_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3530$159_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3533$160_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3534$161_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3535$163_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid + connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr + connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3640$169_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3641$170_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3642$171_Y + connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3652$176_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3653$178_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3654$180_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3686$188_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3687$189_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3690$190_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3691$191_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3692$193_Y + connect \main_sdram_choose_req_want_cmds 1'1 + connect \main_sdram_trrdcon_valid $and$ls180.v:3788$204_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3789$210_Y + connect \main_sdram_ras_allowed $and$ls180.v:3790$211_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3791$214_Y + connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready + connect \main_sdram_twtrcon_valid $and$ls180.v:3793$216_Y + connect \main_sdram_read_available $or$ls180.v:3794$223_Y + connect \main_sdram_write_available $or$ls180.v:3795$230_Y + connect \main_sdram_max_time0 $eq$ls180.v:3796$231_Y + connect \main_sdram_max_time1 $eq$ls180.v:3797$232_Y + connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid + connect \main_sdram_go_to_refresh $and$ls180.v:3802$235_Y + connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata + connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3805$236_Y + connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids + connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 + connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 + connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 + connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 + connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 + connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 + connect \main_sdram_choose_cmd_ce $or$ls180.v:3838$294_Y + connect \main_sdram_choose_req_request \main_sdram_choose_req_valids + connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 + connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 + connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 + connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 + connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 + connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 + connect \main_sdram_choose_req_ce $or$ls180.v:3907$380_Y + connect \main_sdram_dfi_p0_reset_n 1'1 + connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 + connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 + connect \builder_roundrobin0_request $and$ls180.v:3984$412_Y + connect \builder_roundrobin0_ce $and$ls180.v:3985$415_Y + connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 + connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 + connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 + connect \builder_roundrobin1_request $and$ls180.v:3989$428_Y + connect \builder_roundrobin1_ce $and$ls180.v:3990$431_Y + connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 + connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 + connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 + connect \builder_roundrobin2_request $and$ls180.v:3994$444_Y + connect \builder_roundrobin2_ce $and$ls180.v:3995$447_Y + connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 + connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 + connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 + connect \builder_roundrobin3_request $and$ls180.v:3999$460_Y + connect \builder_roundrobin3_ce $and$ls180.v:4000$463_Y + connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 + connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 + connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 + connect \main_port_cmd_ready $or$ls180.v:4004$527_Y + connect \main_port_wdata_ready \builder_new_master_wdata_ready + connect \main_port_rdata_valid \builder_new_master_rdata_valid3 + connect \main_port_rdata_payload_data \main_sdram_interface_rdata + connect \builder_roundrobin0_grant 1'0 + connect \builder_roundrobin1_grant 1'0 + connect \builder_roundrobin2_grant 1'0 + connect \builder_roundrobin3_grant 1'0 + connect \main_converter_reset $not$ls180.v:4026$529_Y + connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } + connect \main_port_cmd_payload_addr $sub$ls180.v:4086$540_Y [23:0] + connect \main_port_cmd_payload_we \main_litedram_wb_we + connect \main_port_wdata_payload_data \main_litedram_wb_dat_w + connect \main_port_wdata_payload_we \main_litedram_wb_sel + connect \main_litedram_wb_dat_r \main_port_rdata_payload_data + connect \main_port_flush $not$ls180.v:4091$541_Y + connect \main_port_cmd_last $not$ls180.v:4092$542_Y + connect \main_port_cmd_valid $and$ls180.v:4093$545_Y + connect \main_port_wdata_valid $and$ls180.v:4094$549_Y + connect \main_port_rdata_ready $and$ls180.v:4095$552_Y + connect \main_litedram_wb_ack $and$ls180.v:4096$557_Y + connect \main_ack_cmd $or$ls180.v:4097$559_Y + connect \main_ack_wdata $or$ls180.v:4098$561_Y + connect \main_ack_rdata $and$ls180.v:4099$562_Y + connect \main_uart_uart_sink_valid \main_uart_phy_source_valid + connect \main_uart_phy_source_ready \main_uart_uart_sink_ready + connect \main_uart_uart_sink_first \main_uart_phy_source_first + connect \main_uart_uart_sink_last \main_uart_phy_source_last + connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data + connect \main_uart_phy_sink_valid \main_uart_uart_source_valid + connect \main_uart_uart_source_ready \main_uart_phy_sink_ready + connect \main_uart_phy_sink_first \main_uart_uart_source_first + connect \main_uart_phy_sink_last \main_uart_uart_source_last + connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data + connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re + connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r + connect \main_uart_txfull_status $not$ls180.v:4112$563_Y + connect \main_uart_txempty_status $not$ls180.v:4113$564_Y + connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid + connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready + connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first + connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last + connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data + connect \main_uart_tx_trigger $not$ls180.v:4119$565_Y + connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid + connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready + connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first + connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last + connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data + connect \main_uart_rxempty_status $not$ls180.v:4125$566_Y + connect \main_uart_rxfull_status $not$ls180.v:4126$567_Y + connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4128$569_Y + connect \main_uart_rx_trigger $not$ls180.v:4129$570_Y + connect \main_uart_irq $or$ls180.v:4152$579_Y + connect \main_uart_tx_status \main_uart_tx_trigger + connect \main_uart_rx_status \main_uart_rx_trigger + connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } + connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout + connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable + connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid + connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first + connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last + connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data + connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable + connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first + connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last + connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data + connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4167$582_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4168$583_Y + connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4178$587_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4179$588_Y + connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume + connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r + connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4183$589_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4184$590_Y + connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } + connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout + connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable + connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid + connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first + connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last + connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data + connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable + connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first + connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last + connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data + connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4197$593_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4198$594_Y + connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4208$598_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4209$599_Y + connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume + connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r + connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4213$600_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4214$601_Y + connect \main_gpio_pads_i \gpio_i + connect \gpio_o \main_gpio_pads_o + connect \gpio_oe \main_gpio_pads_oe + connect \main_gpio_pads_oe \main_gpio_oe_storage + connect \main_gpio_pads_o \main_gpio_out_storage + connect \main_spimaster0_start \main_spimaster9_start + connect \main_spimaster1_length \main_spimaster10_length + connect \main_spimaster4_mosi \main_spimaster16_storage + connect \main_spimaster13_done \main_spimaster2_done + connect \main_spimaster18_status \main_spimaster5_miso + connect \main_spimaster6_cs \main_spimaster21_storage + connect \main_spimaster7_loopback \main_spimaster23_storage + connect \main_spimaster31_clk_rise $eq$ls180.v:4227$603_Y + connect \main_spimaster32_clk_fall $eq$ls180.v:4228$605_Y + connect \main_spisdcard_start0 \main_spisdcard_start1 + connect \main_spisdcard_length0 \main_spisdcard_length1 + connect \main_spisdcard_mosi \main_spisdcard_mosi_storage + connect \main_spisdcard_done1 \main_spisdcard_done0 + connect \main_spisdcard_miso_status \main_spisdcard_miso + connect \main_spisdcard_cs \main_spisdcard_cs_storage + connect \main_spisdcard_loopback \main_spisdcard_loopback_storage + connect \main_spisdcard_clk_rise $eq$ls180.v:4285$611_Y + connect \main_spisdcard_clk_fall $eq$ls180.v:4286$613_Y + connect \main_spisdcard_clk_divider0 \main_spimaster1_storage + connect \i2c_scl \main_i2c_scl + connect \i2c_sda_oe \main_i2c_oe + connect \i2c_sda_o \main_i2c_sda0 + connect \main_i2c_sda1 \i2c_sda_i + connect \main_sdphy_status 1'0 + connect \main_sdphy_sdpads_clk $or$ls180.v:4342$621_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4343$625_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4344$629_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4345$633_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4346$637_Y + connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_clocker_stop $or$ls180.v:4367$638_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4397$641_Y + connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid + connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready + connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first + connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last + connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4520$651_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4521$653_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 + connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready + connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 + connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 + connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 + connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid + connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 + connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data + connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid + connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 + connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4538$655_Y + connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4540$656_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4541$658_Y + connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid + connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready + connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first + connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last + connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i + connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o + connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4647$673_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4648$674_Y + connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 + connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready + connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 + connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 + connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 + connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid + connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 + connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first + connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data + connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid + connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 + connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first + connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4665$676_Y + connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4667$677_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4668$679_Y + connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid + connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready + connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first + connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last + connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk + connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i + connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o + connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe + connect \main_sdphy_datar_datar_start $eq$ls180.v:4781$688_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4782$689_Y + connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i + connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 + connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready + connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 + connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 + connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 + connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid + connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 + connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first + connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last + connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data + connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid + connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 + connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first + connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last + connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4799$691_Y + connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4801$692_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4802$694_Y + connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid + connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready + connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first + connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last + connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data + connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid + connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready + connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first + connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last + connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data + connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] + connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] + connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } + connect \main_sdcore_data_event_status { $not$ls180.v:4918$709_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } + connect \main_sdcore_crc7_inserter_clr 1'1 + connect \main_sdcore_crc7_inserter_enable 1'1 + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4922$712_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4922$710_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4923$715_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4923$713_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4924$718_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4924$716_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4925$721_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4925$719_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4926$724_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4926$722_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4927$727_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4927$725_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4928$730_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4928$728_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4929$733_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4929$731_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4930$736_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4930$734_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4931$739_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4931$737_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4932$742_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4932$740_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4933$745_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4933$743_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4934$748_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4934$746_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4935$751_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4935$749_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4936$754_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4936$752_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4937$757_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4937$755_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4938$760_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4938$758_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4939$763_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4939$761_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4940$766_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4940$764_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4941$769_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4941$767_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4942$772_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4942$770_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4943$775_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4943$773_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4944$778_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4944$776_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4945$781_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4945$779_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4946$784_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4946$782_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4947$787_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4947$785_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4948$790_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4948$788_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4949$793_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4949$791_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4950$796_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4950$794_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4951$799_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4951$797_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4952$802_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4952$800_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4953$805_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4953$803_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4954$808_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4954$806_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4955$811_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4955$809_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4956$814_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4956$812_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4957$817_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4957$815_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4958$820_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4958$818_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4959$823_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4959$821_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4960$826_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4960$824_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4961$829_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4961$827_Y } + connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4971$832_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4972$833_Y + connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4974$835_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4975$836_Y + connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4977$838_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4978$839_Y + connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4980$841_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4981$842_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4982$847_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4982$845_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4982$843_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4983$852_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4983$850_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4983$848_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4992$858_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4992$856_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4992$854_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4993$863_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4993$861_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4993$859_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5002$869_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5002$867_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5002$865_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5003$874_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5003$872_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5003$870_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5012$880_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5012$878_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5012$876_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5013$885_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5013$883_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5013$881_Y } + connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5109$901_Y + connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5119$904_Y + connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5129$907_Y + connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5139$910_Y + connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val + connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5164$922_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5164$920_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5164$918_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5165$927_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5165$925_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5165$923_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5174$933_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5174$931_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5174$929_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5175$938_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5175$936_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5175$934_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5184$944_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5184$942_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5184$940_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5185$949_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5185$947_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5185$945_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5194$955_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5194$953_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5194$951_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5195$960_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5195$958_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5195$956_Y } + connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 + connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready + connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first + connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last + connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 + connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid + connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready + connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first + connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last + connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data + connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid + connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first + connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last + connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data + connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } + connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout + connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable + connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid + connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first + connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last + connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data + connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable + connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first + connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last + connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data + connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready + connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5431$990_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5432$991_Y + connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume + connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5435$992_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5436$993_Y + connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid + connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready + connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first + connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last + connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5442$995_Y + connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5444$996_Y + connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_we 1'1 + connect \main_interface0_bus_sel 4'1111 + connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address + connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] } + connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack + connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] + connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5454$997_Y + connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid + connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready + connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first + connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last + connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data + connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 + connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready + connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 + connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 + connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 + connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid + connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 + connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first + connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last + connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data + connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] + connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } + connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset + connect \main_sdmem2block_dma_reset $not$ls180.v:5513$1004_Y + connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid + connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 + connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first + connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last + connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data + connect \main_sdmem2block_converter_first $eq$ls180.v:5594$1012_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5595$1013_Y + connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid + connect \main_sdmem2block_converter_source_first $and$ls180.v:5597$1014_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5598$1015_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5599$1016_Y + connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last + connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } + connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout + connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable + connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid + connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first + connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last + connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data + connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable + connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first + connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last + connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data + connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready + connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5639$1021_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5640$1022_Y + connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume + connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5643$1023_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5644$1024_Y + connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 + connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 + connect \builder_shared_stb \builder_comb_rhs_array_muxed28 + connect \builder_shared_we \builder_comb_rhs_array_muxed29 + connect \builder_shared_cti \builder_comb_rhs_array_muxed30 + connect \builder_shared_bte \builder_comb_rhs_array_muxed31 + connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r + connect \main_interface0_bus_dat_r \builder_shared_dat_r + connect \main_interface1_bus_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5695$1030_Y + connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5696$1032_Y + connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5697$1034_Y + connect \main_interface0_bus_ack $and$ls180.v:5698$1036_Y + connect \main_interface1_bus_ack $and$ls180.v:5699$1038_Y + connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5700$1040_Y + connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5701$1042_Y + connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5702$1044_Y + connect \main_interface0_bus_err $and$ls180.v:5703$1046_Y + connect \main_interface1_bus_err $and$ls180.v:5704$1048_Y + connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } + connect \main_libresocsim_ram_bus_adr \builder_shared_adr + connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w + connect \main_libresocsim_ram_bus_sel \builder_shared_sel + connect \main_libresocsim_ram_bus_stb \builder_shared_stb + connect \main_libresocsim_ram_bus_we \builder_shared_we + connect \main_libresocsim_ram_bus_cti \builder_shared_cti + connect \main_libresocsim_ram_bus_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte + connect \main_wb_sdram_adr \builder_shared_adr + connect \main_wb_sdram_dat_w \builder_shared_dat_w + connect \main_wb_sdram_sel \builder_shared_sel + connect \main_wb_sdram_stb \builder_shared_stb + connect \main_wb_sdram_we \builder_shared_we + connect \main_wb_sdram_cti \builder_shared_cti + connect \main_wb_sdram_bte \builder_shared_bte + connect \builder_libresocsim_wishbone_adr \builder_shared_adr + connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w + connect \builder_libresocsim_wishbone_sel \builder_shared_sel + connect \builder_libresocsim_wishbone_stb \builder_shared_stb + connect \builder_libresocsim_wishbone_we \builder_shared_we + connect \builder_libresocsim_wishbone_cti \builder_shared_cti + connect \builder_libresocsim_wishbone_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5749$1055_Y + connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5750$1056_Y + connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5751$1057_Y + connect \main_wb_sdram_cyc $and$ls180.v:5752$1058_Y + connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5753$1059_Y + connect \builder_shared_err $or$ls180.v:5754$1063_Y + connect \builder_wait $and$ls180.v:5755$1066_Y + connect \builder_done $eq$ls180.v:5768$1081_Y + connect \builder_csrbank0_sel $eq$ls180.v:5769$1082_Y + connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] + connect \builder_csrbank0_reset0_re $and$ls180.v:5771$1085_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:5772$1089_Y + connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch3_re $and$ls180.v:5774$1092_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:5775$1096_Y + connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch2_re $and$ls180.v:5777$1099_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:5778$1103_Y + connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch1_re $and$ls180.v:5780$1106_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:5781$1110_Y + connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch0_re $and$ls180.v:5783$1113_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:5784$1117_Y + connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5786$1120_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5787$1124_Y + connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5789$1127_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5790$1131_Y + connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5792$1134_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5793$1138_Y + connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5795$1141_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5796$1145_Y + connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage + connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] + connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] + connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] + connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] + connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] + connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] + connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] + connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] + connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we + connect \builder_csrbank1_sel $eq$ls180.v:5807$1146_Y + connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe1_re $and$ls180.v:5809$1149_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:5810$1153_Y + connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe0_re $and$ls180.v:5812$1156_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:5813$1160_Y + connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in1_re $and$ls180.v:5815$1163_Y + connect \builder_csrbank1_in1_we $and$ls180.v:5816$1167_Y + connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in0_re $and$ls180.v:5818$1170_Y + connect \builder_csrbank1_in0_we $and$ls180.v:5819$1174_Y + connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out1_re $and$ls180.v:5821$1177_Y + connect \builder_csrbank1_out1_we $and$ls180.v:5822$1181_Y + connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out0_re $and$ls180.v:5824$1184_Y + connect \builder_csrbank1_out0_we $and$ls180.v:5825$1188_Y + connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] + connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] + connect \builder_csrbank1_in1_w \main_gpio_status [15:8] + connect \builder_csrbank1_in0_w \main_gpio_status [7:0] + connect \main_gpio_we \builder_csrbank1_in0_we + connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] + connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] + connect \builder_csrbank2_sel $eq$ls180.v:5833$1189_Y + connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] + connect \builder_csrbank2_w0_re $and$ls180.v:5835$1192_Y + connect \builder_csrbank2_w0_we $and$ls180.v:5836$1196_Y + connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] + connect \builder_csrbank2_r_re $and$ls180.v:5838$1199_Y + connect \builder_csrbank2_r_we $and$ls180.v:5839$1203_Y + connect \main_i2c_scl \main_i2c_storage [0] + connect \main_i2c_oe \main_i2c_storage [1] + connect \main_i2c_sda0 \main_i2c_storage [2] + connect \builder_csrbank2_w0_w \main_i2c_storage + connect \main_i2c_status \main_i2c_sda1 + connect \builder_csrbank2_r_w \main_i2c_status + connect \main_i2c_we \builder_csrbank2_r_we + connect \builder_csrbank3_sel $eq$ls180.v:5847$1204_Y + connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] + connect \builder_csrbank3_enable0_re $and$ls180.v:5849$1207_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:5850$1211_Y + connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width3_re $and$ls180.v:5852$1214_Y + connect \builder_csrbank3_width3_we $and$ls180.v:5853$1218_Y + connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width2_re $and$ls180.v:5855$1221_Y + connect \builder_csrbank3_width2_we $and$ls180.v:5856$1225_Y + connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width1_re $and$ls180.v:5858$1228_Y + connect \builder_csrbank3_width1_we $and$ls180.v:5859$1232_Y + connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width0_re $and$ls180.v:5861$1235_Y + connect \builder_csrbank3_width0_we $and$ls180.v:5862$1239_Y + connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period3_re $and$ls180.v:5864$1242_Y + connect \builder_csrbank3_period3_we $and$ls180.v:5865$1246_Y + connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period2_re $and$ls180.v:5867$1249_Y + connect \builder_csrbank3_period2_we $and$ls180.v:5868$1253_Y + connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period1_re $and$ls180.v:5870$1256_Y + connect \builder_csrbank3_period1_we $and$ls180.v:5871$1260_Y + connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period0_re $and$ls180.v:5873$1263_Y + connect \builder_csrbank3_period0_we $and$ls180.v:5874$1267_Y + connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage + connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] + connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] + connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] + connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] + connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] + connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] + connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] + connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] + connect \builder_csrbank4_sel $eq$ls180.v:5884$1268_Y + connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_enable0_re $and$ls180.v:5886$1271_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:5887$1275_Y + connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width3_re $and$ls180.v:5889$1278_Y + connect \builder_csrbank4_width3_we $and$ls180.v:5890$1282_Y + connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width2_re $and$ls180.v:5892$1285_Y + connect \builder_csrbank4_width2_we $and$ls180.v:5893$1289_Y + connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width1_re $and$ls180.v:5895$1292_Y + connect \builder_csrbank4_width1_we $and$ls180.v:5896$1296_Y + connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width0_re $and$ls180.v:5898$1299_Y + connect \builder_csrbank4_width0_we $and$ls180.v:5899$1303_Y + connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period3_re $and$ls180.v:5901$1306_Y + connect \builder_csrbank4_period3_we $and$ls180.v:5902$1310_Y + connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period2_re $and$ls180.v:5904$1313_Y + connect \builder_csrbank4_period2_we $and$ls180.v:5905$1317_Y + connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period1_re $and$ls180.v:5907$1320_Y + connect \builder_csrbank4_period1_we $and$ls180.v:5908$1324_Y + connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period0_re $and$ls180.v:5910$1327_Y + connect \builder_csrbank4_period0_we $and$ls180.v:5911$1331_Y + connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage + connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] + connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] + connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] + connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] + connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] + connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] + connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] + connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] + connect \builder_csrbank5_sel $eq$ls180.v:5921$1332_Y + connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base7_re $and$ls180.v:5923$1335_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:5924$1339_Y + connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base6_re $and$ls180.v:5926$1342_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:5927$1346_Y + connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base5_re $and$ls180.v:5929$1349_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:5930$1353_Y + connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base4_re $and$ls180.v:5932$1356_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:5933$1360_Y + connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base3_re $and$ls180.v:5935$1363_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:5936$1367_Y + connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base2_re $and$ls180.v:5938$1370_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:5939$1374_Y + connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base1_re $and$ls180.v:5941$1377_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:5942$1381_Y + connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base0_re $and$ls180.v:5944$1384_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:5945$1388_Y + connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length3_re $and$ls180.v:5947$1391_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:5948$1395_Y + connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length2_re $and$ls180.v:5950$1398_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:5951$1402_Y + connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length1_re $and$ls180.v:5953$1405_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:5954$1409_Y + connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length0_re $and$ls180.v:5956$1412_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:5957$1416_Y + connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5959$1419_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5960$1423_Y + connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_done_re $and$ls180.v:5962$1426_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:5963$1430_Y + connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5965$1433_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5966$1437_Y + connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] + connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] + connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] + connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] + connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] + connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] + connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] + connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] + connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] + connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] + connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] + connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] + connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status + connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we + connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage + connect \builder_csrbank6_sel $eq$ls180.v:5983$1438_Y + connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5985$1441_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5986$1445_Y + connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5988$1448_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5989$1452_Y + connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5991$1455_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5992$1459_Y + connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5994$1462_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5995$1466_Y + connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:5997$1469_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:5998$1473_Y + connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6000$1476_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6001$1480_Y + connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6003$1483_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6004$1487_Y + connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6006$1490_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6007$1494_Y + connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] + connect \main_sdcore_cmd_send_re $and$ls180.v:6009$1497_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:6010$1501_Y + connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6012$1504_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6013$1508_Y + connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6015$1511_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6016$1515_Y + connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6018$1518_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6019$1522_Y + connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6021$1525_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6022$1529_Y + connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6024$1532_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6025$1536_Y + connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6027$1539_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6028$1543_Y + connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6030$1546_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6031$1550_Y + connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6033$1553_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6034$1557_Y + connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6036$1560_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6037$1564_Y + connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6039$1567_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6040$1571_Y + connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6042$1574_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6043$1578_Y + connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6045$1581_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6046$1585_Y + connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6048$1588_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6049$1592_Y + connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6051$1595_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6052$1599_Y + connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6054$1602_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6055$1606_Y + connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6057$1609_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6058$1613_Y + connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6060$1616_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6061$1620_Y + connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_data_event_re $and$ls180.v:6063$1623_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6064$1627_Y + connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] + connect \builder_csrbank6_block_length1_re $and$ls180.v:6066$1630_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6067$1634_Y + connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_length0_re $and$ls180.v:6069$1637_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6070$1641_Y + connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count3_re $and$ls180.v:6072$1644_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6073$1648_Y + connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count2_re $and$ls180.v:6075$1651_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6076$1655_Y + connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count1_re $and$ls180.v:6078$1658_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6079$1662_Y + connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count0_re $and$ls180.v:6081$1665_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6082$1669_Y + connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] + connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] + connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] + connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] + connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] + connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] + connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] + connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] + connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] + connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] + connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] + connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] + connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] + connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] + connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] + connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] + connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] + connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] + connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] + connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] + connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] + connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] + connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] + connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] + connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we + connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status + connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we + connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status + connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we + connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] + connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] + connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] + connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] + connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] + connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] + connect \builder_csrbank7_sel $eq$ls180.v:6118$1670_Y + connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6120$1673_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6121$1677_Y + connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6123$1680_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6124$1684_Y + connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6126$1687_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6127$1691_Y + connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6129$1694_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6130$1698_Y + connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6132$1701_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6133$1705_Y + connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6135$1708_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6136$1712_Y + connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6138$1715_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6139$1719_Y + connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6141$1722_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6142$1726_Y + connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6144$1729_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6145$1733_Y + connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6147$1736_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6148$1740_Y + connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6150$1743_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6151$1747_Y + connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6153$1750_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6154$1754_Y + connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6156$1757_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6157$1761_Y + connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_done_re $and$ls180.v:6159$1764_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6160$1768_Y + connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6162$1771_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6163$1775_Y + connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6165$1778_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6166$1782_Y + connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6168$1785_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6169$1789_Y + connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6171$1792_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6172$1796_Y + connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6174$1799_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6175$1803_Y + connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] + connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] + connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] + connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] + connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] + connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] + connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] + connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] + connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] + connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] + connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] + connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] + connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage + connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status + connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we + connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage + connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] + connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] + connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] + connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] + connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we + connect \builder_csrbank8_sel $eq$ls180.v:6197$1804_Y + connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_card_detect_re $and$ls180.v:6199$1807_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6200$1811_Y + connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6202$1814_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6203$1818_Y + connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6205$1821_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6206$1825_Y + connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] + connect \main_sdphy_init_initialize_re $and$ls180.v:6208$1828_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6209$1832_Y + connect \builder_csrbank8_card_detect_w \main_sdphy_status + connect \main_sdphy_we \builder_csrbank8_card_detect_we + connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] + connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] + connect \builder_csrbank9_sel $eq$ls180.v:6214$1833_Y + connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6216$1836_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6217$1840_Y + connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6219$1843_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6220$1847_Y + connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] + connect \main_sdram_command_issue_re $and$ls180.v:6222$1850_Y + connect \main_sdram_command_issue_we $and$ls180.v:6223$1854_Y + connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6225$1857_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6226$1861_Y + connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6228$1864_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6229$1868_Y + connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6231$1871_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6232$1875_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6234$1878_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6235$1882_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6237$1885_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6238$1889_Y + connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6240$1892_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6241$1896_Y + connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6243$1899_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6244$1903_Y + connect \main_sdram_sel \main_sdram_storage [0] + connect \main_sdram_cke \main_sdram_storage [1] + connect \main_sdram_odt \main_sdram_storage [2] + connect \main_sdram_reset_n \main_sdram_storage [3] + connect \builder_csrbank9_dfii_control0_w \main_sdram_storage + connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage + connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] + connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] + connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage + connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] + connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] + connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] + connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] + connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we + connect \builder_csrbank10_sel $eq$ls180.v:6259$1904_Y + connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control1_re $and$ls180.v:6261$1907_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6262$1911_Y + connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control0_re $and$ls180.v:6264$1914_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6265$1918_Y + connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_status_re $and$ls180.v:6267$1921_Y + connect \builder_csrbank10_status_we $and$ls180.v:6268$1925_Y + connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_mosi0_re $and$ls180.v:6270$1928_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6271$1932_Y + connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_miso_re $and$ls180.v:6273$1935_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6274$1939_Y + connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_cs0_re $and$ls180.v:6276$1942_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6277$1946_Y + connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_loopback0_re $and$ls180.v:6279$1949_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6280$1953_Y + connect \main_spimaster10_length \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] + connect \main_spimaster14_status \main_spimaster13_done + connect \builder_csrbank10_status_w \main_spimaster14_status + connect \main_spimaster15_we \builder_csrbank10_status_we + connect \builder_csrbank10_mosi0_w \main_spimaster16_storage + connect \builder_csrbank10_miso_w \main_spimaster18_status + connect \main_spimaster19_we \builder_csrbank10_miso_we + connect \main_spimaster20_sel \main_spimaster21_storage + connect \builder_csrbank10_cs0_w \main_spimaster21_storage + connect \builder_csrbank10_loopback0_w \main_spimaster23_storage + connect \builder_csrbank11_sel $eq$ls180.v:6299$1955_Y + connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control1_re $and$ls180.v:6301$1958_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6302$1962_Y + connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control0_re $and$ls180.v:6304$1965_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6305$1969_Y + connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_status_re $and$ls180.v:6307$1972_Y + connect \builder_csrbank11_status_we $and$ls180.v:6308$1976_Y + connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_mosi0_re $and$ls180.v:6310$1979_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6311$1983_Y + connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_miso_re $and$ls180.v:6313$1986_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6314$1990_Y + connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_cs0_re $and$ls180.v:6316$1993_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6317$1997_Y + connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_loopback0_re $and$ls180.v:6319$2000_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6320$2004_Y + connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6322$2007_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6323$2011_Y + connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6325$2014_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6326$2018_Y + connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] + connect \main_spisdcard_status_status \main_spisdcard_done1 + connect \builder_csrbank11_status_w \main_spisdcard_status_status + connect \main_spisdcard_status_we \builder_csrbank11_status_we + connect \builder_csrbank11_mosi0_w \main_spisdcard_mosi_storage + connect \builder_csrbank11_miso_w \main_spisdcard_miso_status + connect \main_spisdcard_miso_we \builder_csrbank11_miso_we + connect \main_spisdcard_sel \main_spisdcard_cs_storage + connect \builder_csrbank11_cs0_w \main_spisdcard_cs_storage + connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage + connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] + connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] + connect \builder_csrbank12_sel $eq$ls180.v:6347$2020_Y + connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load3_re $and$ls180.v:6349$2023_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6350$2027_Y + connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load2_re $and$ls180.v:6352$2030_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6353$2034_Y + connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load1_re $and$ls180.v:6355$2037_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6356$2041_Y + connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load0_re $and$ls180.v:6358$2044_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6359$2048_Y + connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload3_re $and$ls180.v:6361$2051_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6362$2055_Y + connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload2_re $and$ls180.v:6364$2058_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6365$2062_Y + connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload1_re $and$ls180.v:6367$2065_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6368$2069_Y + connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload0_re $and$ls180.v:6370$2072_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6371$2076_Y + connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_en0_re $and$ls180.v:6373$2079_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6374$2083_Y + connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_update_value0_re $and$ls180.v:6376$2086_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6377$2090_Y + connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value3_re $and$ls180.v:6379$2093_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6380$2097_Y + connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value2_re $and$ls180.v:6382$2100_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6383$2104_Y + connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value1_re $and$ls180.v:6385$2107_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6386$2111_Y + connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value0_re $and$ls180.v:6388$2114_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6389$2118_Y + connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6391$2121_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6392$2125_Y + connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6394$2128_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6395$2132_Y + connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6397$2135_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6398$2139_Y + connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] + connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] + connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] + connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] + connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] + connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] + connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] + connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] + connect \builder_csrbank12_en0_w \main_libresocsim_en_storage + connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage + connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] + connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] + connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] + connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] + connect \main_libresocsim_value_we \builder_csrbank12_value0_we + connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage + connect \builder_csrbank13_sel $eq$ls180.v:6415$2140_Y + connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w + connect \main_uart_rxtx_re $and$ls180.v:6417$2143_Y + connect \main_uart_rxtx_we $and$ls180.v:6418$2147_Y + connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txfull_re $and$ls180.v:6420$2150_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6421$2154_Y + connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxempty_re $and$ls180.v:6423$2157_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6424$2161_Y + connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_status_re $and$ls180.v:6426$2164_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6427$2168_Y + connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_pending_re $and$ls180.v:6429$2171_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6430$2175_Y + connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6432$2178_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6433$2182_Y + connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txempty_re $and$ls180.v:6435$2185_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6436$2189_Y + connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxfull_re $and$ls180.v:6438$2192_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6439$2196_Y + connect \builder_csrbank13_txfull_w \main_uart_txfull_status + connect \main_uart_txfull_we \builder_csrbank13_txfull_we + connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status + connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we + connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage + connect \builder_csrbank13_txempty_w \main_uart_txempty_status + connect \main_uart_txempty_we \builder_csrbank13_txempty_we + connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status + connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we + connect \builder_csrbank14_sel $eq$ls180.v:6449$2197_Y + connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6451$2200_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6452$2204_Y + connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6454$2207_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6455$2211_Y + connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6457$2214_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6458$2218_Y + connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6460$2221_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6461$2225_Y + connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] + connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] + connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] + connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] + connect \builder_csr_interconnect_adr \builder_libresocsim_adr + connect \builder_csr_interconnect_we \builder_libresocsim_we + connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w + connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r + connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_csr_interconnect_dat_r $or$ls180.v:6515$2239_Y + connect \sdrio_clk \sys_clk_1 + connect \sdrio_clk_1 \sys_clk_1 + connect \sdrio_clk_2 \sys_clk_1 + connect \sdrio_clk_3 \sys_clk_1 + connect \sdrio_clk_4 \sys_clk_1 + connect \sdrio_clk_5 \sys_clk_1 + connect \sdrio_clk_6 \sys_clk_1 + connect \sdrio_clk_7 \sys_clk_1 + connect \sdrio_clk_8 \sys_clk_1 + connect \sdrio_clk_9 \sys_clk_1 + connect \sdrio_clk_10 \sys_clk_1 + connect \sdrio_clk_11 \sys_clk_1 + connect \sdrio_clk_12 \sys_clk_1 + connect \sdrio_clk_13 \sys_clk_1 + connect \sdrio_clk_14 \sys_clk_1 + connect \sdrio_clk_15 \sys_clk_1 + connect \sdrio_clk_16 \sys_clk_1 + connect \sdrio_clk_17 \sys_clk_1 + connect \sdrio_clk_18 \sys_clk_1 + connect \sdrio_clk_19 \sys_clk_1 + connect \sdrio_clk_20 \sys_clk_1 + connect \sdrio_clk_21 \sys_clk_1 + connect \sdrio_clk_22 \sys_clk_1 + connect \sdrio_clk_23 \sys_clk_1 + connect \sdrio_clk_24 \sys_clk_1 + connect \sdrio_clk_25 \sys_clk_1 + connect \sdrio_clk_26 \sys_clk_1 + connect \sdrio_clk_27 \sys_clk_1 + connect \sdrio_clk_28 \sys_clk_1 + connect \sdrio_clk_29 \sys_clk_1 + connect \sdrio_clk_30 \sys_clk_1 + connect \sdrio_clk_31 \sys_clk_1 + connect \sdrio_clk_32 \sys_clk_1 + connect \sdrio_clk_33 \sys_clk_1 + connect \sdrio_clk_34 \sys_clk_1 + connect \sdrio_clk_35 \sys_clk_1 + connect \sdrio_clk_36 \sys_clk_1 + connect \sdrio_clk_37 \sys_clk_1 + connect \sdrio_clk_38 \sys_clk_1 + connect \sdrio_clk_39 \sys_clk_1 + connect \sdrio_clk_40 \sys_clk_1 + connect \sdrio_clk_41 \sys_clk_1 + connect \sdrio_clk_42 \sys_clk_1 + connect \sdrio_clk_43 \sys_clk_1 + connect \sdrio_clk_44 \sys_clk_1 + connect \sdrio_clk_45 \sys_clk_1 + connect \sdrio_clk_46 \sys_clk_1 + connect \sdrio_clk_47 \sys_clk_1 + connect \sdrio_clk_48 \sys_clk_1 + connect \sdrio_clk_49 \sys_clk_1 + connect \sdrio_clk_50 \sys_clk_1 + connect \sdrio_clk_51 \sys_clk_1 + connect \sdrio_clk_52 \sys_clk_1 + connect \sdrio_clk_53 \sys_clk_1 + connect \sdrio_clk_54 \sys_clk_1 + connect \sdrio_clk_55 \sys_clk_1 + connect \main_uart_phy_rx \builder_multiregimpl0_regs1 + connect \main_pwm0_enable \main_pwm0_enable_storage + connect \main_pwm0_width \main_pwm0_width_storage + connect \main_pwm0_period \main_pwm0_period_storage + connect \main_pwm1_enable \main_pwm1_enable_storage + connect \main_pwm1_width \main_pwm1_width_storage + connect \main_pwm1_period \main_pwm1_period_storage + connect \sdrio_clk_56 \sys_clk_1 + connect \sdrio_clk_57 \sys_clk_1 + connect \sdrio_clk_58 \sys_clk_1 + connect \sdrio_clk_59 \sys_clk_1 + connect \sdrio_clk_60 \sys_clk_1 + connect \sdrio_clk_61 \sys_clk_1 + connect \sdrio_clk_62 \sys_clk_1 + connect \sdrio_clk_63 \sys_clk_1 + connect \sdrio_clk_64 \sys_clk_1 + connect \sdrio_clk_65 \sys_clk_1 + connect \sdrio_clk_66 \sys_clk_1 + connect \sdrio_clk_67 \sys_clk_1 + connect \sdrio_clk_68 \sys_clk_1 + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10055$2693_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10073$2700_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10087$2707_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10101$2714_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10115$2721_DATA + connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 + connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 + connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 + connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 + connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10163$2742_DATA + connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10177$2749_DATA +end +attribute \src "libresoc.v:45741.1-45785.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.pll" +attribute \generator "nMigen" +module \pll + attribute \src "libresoc.v:45742.7-45742.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:45774.3-45783.6" + wire $0\pll_18_o[0:0] + attribute \src "libresoc.v:45764.3-45773.6" + wire $0\pll_lck_o[0:0] + attribute \src "libresoc.v:45774.3-45783.6" + wire $1\pll_18_o[0:0] + attribute \src "libresoc.v:45764.3-45773.6" + wire $1\pll_lck_o[0:0] + attribute \src "libresoc.v:45761.17-45761.105" + wire $eq$libresoc.v:45761$1558_Y + attribute \src "libresoc.v:45762.17-45762.105" + wire $eq$libresoc.v:45762$1559_Y + attribute \src "libresoc.v:45763.17-45763.98" + wire $not$libresoc.v:45763$1560_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire input 1 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire output 5 \clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 3 \clk_sel_i + attribute \src "libresoc.v:45742.7-45742.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire output 2 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 4 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:45761$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:45761$1558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:45762$1559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:45762$1559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + cell $not $not$libresoc.v:45763$1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk_24_i + connect \Y $not$libresoc.v:45763$1560_Y + end + attribute \src "libresoc.v:45742.7-45742.20" + process $proc$libresoc.v:45742$1563 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:45764.3-45773.6" + process $proc$libresoc.v:45764$1561 + assign { } { } + assign { } { } + assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] + attribute \src "libresoc.v:45765.5-45765.29" + switch \initial + attribute \src "libresoc.v:45765.9-45765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_lck_o[0:0] \clk_24_i + case + assign $1\pll_lck_o[0:0] 1'0 + end + sync always + update \pll_lck_o $0\pll_lck_o[0:0] + end + attribute \src "libresoc.v:45774.3-45783.6" + process $proc$libresoc.v:45774$1562 + assign { } { } + assign { } { } + assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] + attribute \src "libresoc.v:45775.5-45775.29" + switch \initial + attribute \src "libresoc.v:45775.9-45775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_18_o[0:0] \$5 + case + assign $1\pll_18_o[0:0] 1'0 + end + sync always + update \pll_18_o $0\pll_18_o[0:0] + end + connect \$1 $eq$libresoc.v:45761$1558_Y + connect \$3 $eq$libresoc.v:45762$1559_Y + connect \$5 $not$libresoc.v:45763$1560_Y + connect \clk_pll_o \clk_24_i +end +attribute \src "libresoc.v:45789.1-45873.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick + attribute \src "libresoc.v:45846.17-45846.91" + wire $not$libresoc.v:45846$1564_Y + attribute \src "libresoc.v:45848.18-45848.93" + wire $not$libresoc.v:45848$1566_Y + attribute \src "libresoc.v:45850.18-45850.93" + wire $not$libresoc.v:45850$1568_Y + attribute \src "libresoc.v:45851.17-45851.138" + wire width 8 $not$libresoc.v:45851$1569_Y + attribute \src "libresoc.v:45853.18-45853.93" + wire $not$libresoc.v:45853$1571_Y + attribute \src "libresoc.v:45855.18-45855.93" + wire $not$libresoc.v:45855$1573_Y + attribute \src "libresoc.v:45857.18-45857.93" + wire $not$libresoc.v:45857$1575_Y + attribute \src "libresoc.v:45860.17-45860.91" + wire $not$libresoc.v:45860$1578_Y + attribute \src "libresoc.v:45847.18-45847.116" + wire $reduce_or$libresoc.v:45847$1565_Y + attribute \src "libresoc.v:45849.18-45849.122" + wire $reduce_or$libresoc.v:45849$1567_Y + attribute \src "libresoc.v:45852.18-45852.128" + wire $reduce_or$libresoc.v:45852$1570_Y + attribute \src "libresoc.v:45854.18-45854.134" + wire $reduce_or$libresoc.v:45854$1572_Y + attribute \src "libresoc.v:45856.18-45856.140" + wire $reduce_or$libresoc.v:45856$1574_Y + attribute \src "libresoc.v:45858.18-45858.90" + wire $reduce_or$libresoc.v:45858$1576_Y + attribute \src "libresoc.v:45859.17-45859.103" + wire $reduce_or$libresoc.v:45859$1577_Y + attribute \src "libresoc.v:45861.17-45861.109" + wire $reduce_or$libresoc.v:45861$1579_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45846$1564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:45846$1564_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45848$1566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:45848$1566_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45850$1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:45850$1568_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:45851$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:45851$1569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45853$1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:45853$1571_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45855$1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:45855$1573_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45857$1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:45857$1575_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45860$1578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:45860$1578_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45847$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:45847$1565_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45849$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:45849$1567_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45852$1570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:45852$1570_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45854$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:45854$1572_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45856$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:45856$1574_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:45858$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:45858$1576_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45859$1577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:45859$1577_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45861$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:45861$1579_Y + end + connect \$7 $not$libresoc.v:45846$1564_Y + connect \$12 $reduce_or$libresoc.v:45847$1565_Y + connect \$11 $not$libresoc.v:45848$1566_Y + connect \$16 $reduce_or$libresoc.v:45849$1567_Y + connect \$15 $not$libresoc.v:45850$1568_Y + connect \$1 $not$libresoc.v:45851$1569_Y + connect \$20 $reduce_or$libresoc.v:45852$1570_Y + connect \$19 $not$libresoc.v:45853$1571_Y + connect \$24 $reduce_or$libresoc.v:45854$1572_Y + connect \$23 $not$libresoc.v:45855$1573_Y + connect \$28 $reduce_or$libresoc.v:45856$1574_Y + connect \$27 $not$libresoc.v:45857$1575_Y + connect \$31 $reduce_or$libresoc.v:45858$1576_Y + connect \$4 $reduce_or$libresoc.v:45859$1577_Y + connect \$3 $not$libresoc.v:45860$1578_Y + connect \$8 $reduce_or$libresoc.v:45861$1579_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:45877.1-45961.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$1 + attribute \src "libresoc.v:45934.17-45934.91" + wire $not$libresoc.v:45934$1580_Y + attribute \src "libresoc.v:45936.18-45936.93" + wire $not$libresoc.v:45936$1582_Y + attribute \src "libresoc.v:45938.18-45938.93" + wire $not$libresoc.v:45938$1584_Y + attribute \src "libresoc.v:45939.17-45939.138" + wire width 8 $not$libresoc.v:45939$1585_Y + attribute \src "libresoc.v:45941.18-45941.93" + wire $not$libresoc.v:45941$1587_Y + attribute \src "libresoc.v:45943.18-45943.93" + wire $not$libresoc.v:45943$1589_Y + attribute \src "libresoc.v:45945.18-45945.93" + wire $not$libresoc.v:45945$1591_Y + attribute \src "libresoc.v:45948.17-45948.91" + wire $not$libresoc.v:45948$1594_Y + attribute \src "libresoc.v:45935.18-45935.116" + wire $reduce_or$libresoc.v:45935$1581_Y + attribute \src "libresoc.v:45937.18-45937.122" + wire $reduce_or$libresoc.v:45937$1583_Y + attribute \src "libresoc.v:45940.18-45940.128" + wire $reduce_or$libresoc.v:45940$1586_Y + attribute \src "libresoc.v:45942.18-45942.134" + wire $reduce_or$libresoc.v:45942$1588_Y + attribute \src "libresoc.v:45944.18-45944.140" + wire $reduce_or$libresoc.v:45944$1590_Y + attribute \src "libresoc.v:45946.18-45946.90" + wire $reduce_or$libresoc.v:45946$1592_Y + attribute \src "libresoc.v:45947.17-45947.103" + wire $reduce_or$libresoc.v:45947$1593_Y + attribute \src "libresoc.v:45949.17-45949.109" + wire $reduce_or$libresoc.v:45949$1595_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45934$1580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:45934$1580_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45936$1582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:45936$1582_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45938$1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:45938$1584_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:45939$1585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:45939$1585_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45941$1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:45941$1587_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45943$1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:45943$1589_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45945$1591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:45945$1591_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45948$1594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:45948$1594_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45935$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:45935$1581_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45937$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:45937$1583_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45940$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:45940$1586_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45942$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:45942$1588_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45944$1590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:45944$1590_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:45946$1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:45946$1592_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45947$1593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:45947$1593_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45949$1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:45949$1595_Y + end + connect \$7 $not$libresoc.v:45934$1580_Y + connect \$12 $reduce_or$libresoc.v:45935$1581_Y + connect \$11 $not$libresoc.v:45936$1582_Y + connect \$16 $reduce_or$libresoc.v:45937$1583_Y + connect \$15 $not$libresoc.v:45938$1584_Y + connect \$1 $not$libresoc.v:45939$1585_Y + connect \$20 $reduce_or$libresoc.v:45940$1586_Y + connect \$19 $not$libresoc.v:45941$1587_Y + connect \$24 $reduce_or$libresoc.v:45942$1588_Y + connect \$23 $not$libresoc.v:45943$1589_Y + connect \$28 $reduce_or$libresoc.v:45944$1590_Y + connect \$27 $not$libresoc.v:45945$1591_Y + connect \$31 $reduce_or$libresoc.v:45946$1592_Y + connect \$4 $reduce_or$libresoc.v:45947$1593_Y + connect \$3 $not$libresoc.v:45948$1594_Y + connect \$8 $reduce_or$libresoc.v:45949$1595_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:45965.1-46780.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" +attribute \generator "nMigen" +module \sprmap + attribute \src "libresoc.v:46092.3-46122.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:46123.3-46153.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:45966.7-45966.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:46154.3-46466.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:46467.3-46779.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:46092.3-46122.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:46123.3-46153.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:46154.3-46466.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:46467.3-46779.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:45966.7-45966.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:45966.7-45966.20" + process $proc$libresoc.v:45966$1600 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:46092.3-46122.6" + process $proc$libresoc.v:46092$1596 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:46093.5-46093.29" + switch \initial + attribute \src "libresoc.v:46093.9-46093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:46123.3-46153.6" + process $proc$libresoc.v:46123$1597 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:46124.5-46124.29" + switch \initial + attribute \src "libresoc.v:46124.9-46124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:46154.3-46466.6" + process $proc$libresoc.v:46154$1598 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:46155.5-46155.29" + switch \initial + attribute \src "libresoc.v:46155.9-46155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:46467.3-46779.6" + process $proc$libresoc.v:46467$1599 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:46468.5-46468.29" + switch \initial + attribute \src "libresoc.v:46468.9-46468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:46784.1-47599.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" +attribute \generator "nMigen" +module \sprmap$2 + attribute \src "libresoc.v:46911.3-46941.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:46942.3-46972.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:46785.7-46785.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:46973.3-47285.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:47286.3-47598.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:46911.3-46941.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:46942.3-46972.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:46973.3-47285.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:47286.3-47598.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:46785.7-46785.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:46785.7-46785.20" + process $proc$libresoc.v:46785$1605 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:46911.3-46941.6" + process $proc$libresoc.v:46911$1601 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:46912.5-46912.29" + switch \initial + attribute \src "libresoc.v:46912.9-46912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:46942.3-46972.6" + process $proc$libresoc.v:46942$1602 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:46943.5-46943.29" + switch \initial + attribute \src "libresoc.v:46943.9-46943.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:46973.3-47285.6" + process $proc$libresoc.v:46973$1603 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:46974.5-46974.29" + switch \initial + attribute \src "libresoc.v:46974.9-46974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:47286.3-47598.6" + process $proc$libresoc.v:47286$1604 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:47287.5-47287.29" + switch \initial + attribute \src "libresoc.v:47287.9-47287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:47604.1-48728.10" +attribute \cells_not_processed 1 +attribute \top 1 +attribute \nmigen.hierarchy "test_issuer" +attribute \generator "nMigen" +module \test_issuer + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 7 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 6 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 8 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105" + wire output 5 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 368 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 370 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104" + wire input 4 \core_bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 344 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 input 338 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 2 input 348 \dbus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 3 input 347 \dbus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 342 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 340 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 339 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 346 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 input 341 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 343 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 345 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 19 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 21 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 23 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 37 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 41 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 42 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 43 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 47 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 48 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 49 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 53 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 54 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 55 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 59 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 60 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 61 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 65 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 66 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 67 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 71 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 72 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 25 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 29 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 30 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 31 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 35 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 36 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 73 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 77 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 78 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 79 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 83 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 84 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 85 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 89 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 90 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 91 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 95 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 96 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 97 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 101 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 102 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 103 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 107 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 108 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 109 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 113 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 114 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 115 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 119 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 120 \gpio_s7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 333 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 327 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 2 input 337 \ibus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 3 input 336 \ibus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 331 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 329 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 328 \ibus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 335 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 330 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 332 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 334 \ibus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 355 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 349 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 353 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 351 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 350 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 357 \icp_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 352 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 354 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 356 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 364 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 358 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 362 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 360 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 359 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 366 \ics_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 4 input 361 \ics_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 363 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 365 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 367 \int_level_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 17 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 10 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 14 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 12 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 11 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 18 \jtag_wb__err + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 13 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 15 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 16 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:106" + wire input 3 \memerr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 122 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 124 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 127 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 126 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 130 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 132 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 135 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 134 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 144 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 137 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 141 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 142 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 373 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 1 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102" + wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:467" + wire output 371 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire \pll_clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire \pll_clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 372 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire \pll_pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482" + wire \pllclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482" + wire \pllclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 146 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 148 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 369 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 156 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 149 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 153 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 154 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 157 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 161 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 162 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 163 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 170 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 171 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 172 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 176 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 177 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 178 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 231 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 267 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 269 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 271 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 233 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 235 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 237 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 239 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 241 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 243 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 245 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 247 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 249 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 251 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 253 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 261 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 257 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 255 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 265 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 181 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 274 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 275 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 276 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 184 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 185 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 186 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 292 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 293 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 294 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 298 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 299 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 300 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 304 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 305 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 306 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 310 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 311 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 312 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 316 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 317 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 318 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 320 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 322 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 323 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 324 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 325 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 326 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 190 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 191 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 192 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 196 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 197 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 198 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 202 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 203 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 204 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 208 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 209 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 210 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 214 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 215 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 216 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 220 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 221 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 222 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 226 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 227 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 228 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 280 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 281 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 282 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 286 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 287 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 288 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 259 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 263 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire \ti_coresync_clk + attribute \module_not_derived 1 + attribute \src "libresoc.v:48363.7-48369.4" + cell \pll \pll + connect \clk_24_i \pll_clk_24_i + connect \clk_pll_o \pll_clk_pll_o + connect \clk_sel_i \clk_sel_i + connect \pll_18_o \pll_pll_18_o + connect \pll_lck_o \pll_lck_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:48370.6-48722.4" + cell \ti \ti + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \busy_o \busy_o + connect \clk \clk + connect \core_bigendian_i \core_bigendian_i + connect \coresync_clk \ti_coresync_clk + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + connect \mtwi_sda__pad__o \mtwi_sda__pad__o + connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe + connect \pc_i \pc_i + connect \pc_i_ok \pc_i_ok + connect \pc_o \pc_o + connect \pwm_0__core__o \pwm_0__core__o + connect \pwm_0__pad__o \pwm_0__pad__o + connect \pwm_1__core__o \pwm_1__core__o + connect \pwm_1__pad__o \pwm_1__pad__o + connect \rst \rst + connect \sd0_clk__core__o \sd0_clk__core__o + connect \sd0_clk__pad__o \sd0_clk__pad__o + connect \sd0_cmd__core__i \sd0_cmd__core__i + connect \sd0_cmd__core__o \sd0_cmd__core__o + connect \sd0_cmd__core__oe \sd0_cmd__core__oe + connect \sd0_cmd__pad__i \sd0_cmd__pad__i + connect \sd0_cmd__pad__o \sd0_cmd__pad__o + connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe + connect \sd0_data0__core__i \sd0_data0__core__i + connect \sd0_data0__core__o \sd0_data0__core__o + connect \sd0_data0__core__oe \sd0_data0__core__oe + connect \sd0_data0__pad__i \sd0_data0__pad__i + connect \sd0_data0__pad__o \sd0_data0__pad__o + connect \sd0_data0__pad__oe \sd0_data0__pad__oe + connect \sd0_data1__core__i \sd0_data1__core__i + connect \sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__i \sdr_dm_1__core__i + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe + connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o + end + connect \ti_coresync_clk \pll_clk_pll_o + connect \pllclk_rst \rst + connect \pll_18_o \pll_pll_18_o + connect \pll_clk_24_i \clk + connect \pllclk_clk \pll_clk_pll_o +end +attribute \src "libresoc.v:48732.1-52510.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti" +attribute \generator "nMigen" +module \ti + attribute \src "libresoc.v:52242.3-52278.6" + wire $0\bigendian_i$next[0:0]$2136 + attribute \src "libresoc.v:50859.3-50860.39" + wire $0\bigendian_i[0:0] + attribute \src "libresoc.v:51940.3-51952.6" + wire width 4 $0\cia__ren[3:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $0\core_asmcode$next[7:0]$1854 + attribute \src "libresoc.v:50863.3-50864.41" + wire width 8 $0\core_asmcode[7:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 64 $0\core_core_cia$next[63:0]$1855 + attribute \src "libresoc.v:50939.3-50940.43" + wire width 64 $0\core_core_cia[63:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $0\core_core_cr_rd$next[7:0]$1856 + attribute \src "libresoc.v:50983.3-50984.47" + wire width 8 $0\core_core_cr_rd[7:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_cr_rd_ok$next[0:0]$1857 + attribute \src "libresoc.v:50985.3-50986.53" + wire $0\core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $0\core_core_cr_wr$next[7:0]$1858 + attribute \src "libresoc.v:50987.3-50988.47" + wire width 8 $0\core_core_cr_wr[7:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_cr_wr_ok$next[0:0]$1859 + attribute \src "libresoc.v:50989.3-50990.53" + wire $0\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_exc_$signal$50$next[0:0]$1860 + attribute \src "libresoc.v:50965.3-50966.67" + wire $0\core_core_exc_$signal$50[0:0]$1729 + attribute \src "libresoc.v:48905.7-48905.40" + wire $0\core_core_exc_$signal$50[0:0]$2175 + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_exc_$signal$51$next[0:0]$1861 + attribute \src "libresoc.v:50967.3-50968.67" + wire $0\core_core_exc_$signal$51[0:0]$1731 + attribute \src "libresoc.v:48909.7-48909.40" + wire $0\core_core_exc_$signal$51[0:0]$2177 + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_exc_$signal$52$next[0:0]$1862 + attribute \src "libresoc.v:50969.3-50970.67" + wire $0\core_core_exc_$signal$52[0:0]$1733 + attribute \src "libresoc.v:48913.7-48913.40" + wire $0\core_core_exc_$signal$52[0:0]$2179 + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_exc_$signal$53$next[0:0]$1863 + attribute \src "libresoc.v:50971.3-50972.67" + wire $0\core_core_exc_$signal$53[0:0]$1735 + attribute \src "libresoc.v:48917.7-48917.40" + wire $0\core_core_exc_$signal$53[0:0]$2181 + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_exc_$signal$54$next[0:0]$1864 + attribute \src "libresoc.v:50973.3-50974.67" + wire $0\core_core_exc_$signal$54[0:0]$1737 + attribute \src "libresoc.v:48921.7-48921.40" + wire $0\core_core_exc_$signal$54[0:0]$2183 + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_exc_$signal$55$next[0:0]$1865 + attribute \src "libresoc.v:50975.3-50976.67" + wire $0\core_core_exc_$signal$55[0:0]$1739 + attribute \src "libresoc.v:48925.7-48925.40" + wire $0\core_core_exc_$signal$55[0:0]$2185 + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_exc_$signal$56$next[0:0]$1866 + attribute \src "libresoc.v:50977.3-50978.67" + wire $0\core_core_exc_$signal$56[0:0]$1741 + attribute \src "libresoc.v:48929.7-48929.40" + wire $0\core_core_exc_$signal$56[0:0]$2187 + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_exc_$signal$next[0:0]$1867 + attribute \src "libresoc.v:50963.3-50964.61" + wire $0\core_core_exc_$signal[0:0]$1727 + attribute \src "libresoc.v:48903.7-48903.37" + wire $0\core_core_exc_$signal[0:0]$2173 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 12 $0\core_core_fn_unit$next[11:0]$1868 + attribute \src "libresoc.v:50945.3-50946.51" + wire width 12 $0\core_core_fn_unit[11:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 2 $0\core_core_input_carry$next[1:0]$1869 + attribute \src "libresoc.v:50959.3-50960.59" + wire width 2 $0\core_core_input_carry[1:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 32 $0\core_core_insn$next[31:0]$1870 + attribute \src "libresoc.v:50941.3-50942.45" + wire width 32 $0\core_core_insn[31:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 7 $0\core_core_insn_type$next[6:0]$1871 + attribute \src "libresoc.v:50943.3-50944.55" + wire width 7 $0\core_core_insn_type[6:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_is_32bit$next[0:0]$1872 + attribute \src "libresoc.v:50991.3-50992.53" + wire $0\core_core_is_32bit[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_lk$next[0:0]$1873 + attribute \src "libresoc.v:50947.3-50948.41" + wire $0\core_core_lk[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 64 $0\core_core_msr$next[63:0]$1874 + attribute \src "libresoc.v:50937.3-50938.43" + wire width 64 $0\core_core_msr[63:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_oe$next[0:0]$1875 + attribute \src "libresoc.v:50953.3-50954.41" + wire $0\core_core_oe[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_oe_ok$next[0:0]$1876 + attribute \src "libresoc.v:50955.3-50956.47" + wire $0\core_core_oe_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_rc$next[0:0]$1877 + attribute \src "libresoc.v:50949.3-50950.41" + wire $0\core_core_rc[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_core_rc_ok$next[0:0]$1878 + attribute \src "libresoc.v:50951.3-50952.47" + wire $0\core_core_rc_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 13 $0\core_core_trapaddr$next[12:0]$1879 + attribute \src "libresoc.v:50981.3-50982.53" + wire width 13 $0\core_core_trapaddr[12:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $0\core_core_traptype$next[7:0]$1880 + attribute \src "libresoc.v:50961.3-50962.53" + wire width 8 $0\core_core_traptype[7:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $0\core_cr_in1$next[2:0]$1881 + attribute \src "libresoc.v:50919.3-50920.39" + wire width 3 $0\core_cr_in1[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_cr_in1_ok$next[0:0]$1882 + attribute \src "libresoc.v:50921.3-50922.45" + wire $0\core_cr_in1_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $0\core_cr_in2$48$next[2:0]$1883 + attribute \src "libresoc.v:50927.3-50928.47" + wire width 3 $0\core_cr_in2$48[2:0]$1707 + attribute \src "libresoc.v:49090.13-49090.36" + wire width 3 $0\core_cr_in2$48[2:0]$2205 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $0\core_cr_in2$next[2:0]$1884 + attribute \src "libresoc.v:50923.3-50924.39" + wire width 3 $0\core_cr_in2[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_cr_in2_ok$49$next[0:0]$1885 + attribute \src "libresoc.v:50929.3-50930.53" + wire $0\core_cr_in2_ok$49[0:0]$1709 + attribute \src "libresoc.v:49098.7-49098.33" + wire $0\core_cr_in2_ok$49[0:0]$2208 + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_cr_in2_ok$next[0:0]$1886 + attribute \src "libresoc.v:50925.3-50926.45" + wire $0\core_cr_in2_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $0\core_cr_out$next[2:0]$1887 + attribute \src "libresoc.v:50931.3-50932.39" + wire width 3 $0\core_cr_out[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_cr_out_ok$next[0:0]$1888 + attribute \src "libresoc.v:50933.3-50934.45" + wire $0\core_cr_out_ok[0:0] + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $0\core_dec$next[63:0]$1775 + attribute \src "libresoc.v:50849.3-50850.33" + wire width 64 $0\core_dec[63:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $0\core_ea$next[4:0]$1889 + attribute \src "libresoc.v:50871.3-50872.31" + wire width 5 $0\core_ea[4:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_ea_ok$next[0:0]$1890 + attribute \src "libresoc.v:50873.3-50874.37" + wire $0\core_ea_ok[0:0] + attribute \src "libresoc.v:51551.3-51582.6" + wire $0\core_eint$next[0:0]$1776 + attribute \src "libresoc.v:51017.3-51018.35" + wire $0\core_eint[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $0\core_fast1$next[2:0]$1891 + attribute \src "libresoc.v:50901.3-50902.37" + wire width 3 $0\core_fast1[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_fast1_ok$next[0:0]$1892 + attribute \src "libresoc.v:50903.3-50904.43" + wire $0\core_fast1_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $0\core_fast2$next[2:0]$1893 + attribute \src "libresoc.v:50905.3-50906.37" + wire width 3 $0\core_fast2[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_fast2_ok$next[0:0]$1894 + attribute \src "libresoc.v:50907.3-50908.43" + wire $0\core_fast2_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $0\core_fasto1$next[2:0]$1895 + attribute \src "libresoc.v:50909.3-50910.39" + wire width 3 $0\core_fasto1[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_fasto1_ok$next[0:0]$1896 + attribute \src "libresoc.v:50911.3-50912.45" + wire $0\core_fasto1_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $0\core_fasto2$next[2:0]$1897 + attribute \src "libresoc.v:50915.3-50916.39" + wire width 3 $0\core_fasto2[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_fasto2_ok$next[0:0]$1898 + attribute \src "libresoc.v:50917.3-50918.45" + wire $0\core_fasto2_ok[0:0] + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $0\core_msr$next[63:0]$1777 + attribute \src "libresoc.v:51001.3-51002.33" + wire width 64 $0\core_msr[63:0] + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $0\core_pc$next[63:0]$1778 + attribute \src "libresoc.v:50979.3-50980.31" + wire width 64 $0\core_pc[63:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $0\core_reg1$next[4:0]$1899 + attribute \src "libresoc.v:50875.3-50876.35" + wire width 5 $0\core_reg1[4:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_reg1_ok$next[0:0]$1900 + attribute \src "libresoc.v:50877.3-50878.41" + wire $0\core_reg1_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $0\core_reg2$next[4:0]$1901 + attribute \src "libresoc.v:50879.3-50880.35" + wire width 5 $0\core_reg2[4:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_reg2_ok$next[0:0]$1902 + attribute \src "libresoc.v:50881.3-50882.41" + wire $0\core_reg2_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $0\core_reg3$next[4:0]$1903 + attribute \src "libresoc.v:50883.3-50884.35" + wire width 5 $0\core_reg3[4:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_reg3_ok$next[0:0]$1904 + attribute \src "libresoc.v:50885.3-50886.41" + wire $0\core_reg3_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $0\core_rego$next[4:0]$1905 + attribute \src "libresoc.v:50865.3-50866.35" + wire width 5 $0\core_rego[4:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_rego_ok$next[0:0]$1906 + attribute \src "libresoc.v:50867.3-50868.41" + wire $0\core_rego_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 10 $0\core_spr1$next[9:0]$1907 + attribute \src "libresoc.v:50893.3-50894.35" + wire width 10 $0\core_spr1[9:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_spr1_ok$next[0:0]$1908 + attribute \src "libresoc.v:50895.3-50896.41" + wire $0\core_spr1_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 10 $0\core_spro$next[9:0]$1909 + attribute \src "libresoc.v:50887.3-50888.35" + wire width 10 $0\core_spro[9:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_spro_ok$next[0:0]$1910 + attribute \src "libresoc.v:50889.3-50890.41" + wire $0\core_spro_ok[0:0] + attribute \src "libresoc.v:52442.3-52460.6" + wire $0\core_stopped_i[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $0\core_xer_in$next[2:0]$1911 + attribute \src "libresoc.v:50897.3-50898.39" + wire width 3 $0\core_xer_in[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $0\core_xer_out$next[0:0]$1912 + attribute \src "libresoc.v:50899.3-50900.41" + wire $0\core_xer_out[0:0] + attribute \src "libresoc.v:50997.3-50998.30" + wire $0\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:51697.3-51705.6" + wire $0\d_cr_delay$next[0:0]$1807 + attribute \src "libresoc.v:50913.3-50914.37" + wire $0\d_cr_delay[0:0] + attribute \src "libresoc.v:51658.3-51666.6" + wire $0\d_reg_delay$next[0:0]$1801 + attribute \src "libresoc.v:50935.3-50936.39" + wire $0\d_reg_delay[0:0] + attribute \src "libresoc.v:51736.3-51744.6" + wire $0\d_xer_delay$next[0:0]$1813 + attribute \src "libresoc.v:50891.3-50892.39" + wire $0\d_xer_delay[0:0] + attribute \src "libresoc.v:51974.3-51994.6" + wire width 64 $0\data_i[63:0] + attribute \src "libresoc.v:52461.3-52479.6" + wire $0\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:51716.3-51725.6" + wire $0\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:51706.3-51715.6" + wire width 64 $0\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:51677.3-51686.6" + wire $0\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:51667.3-51676.6" + wire width 64 $0\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:51755.3-51764.6" + wire $0\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:51745.3-51754.6" + wire width 64 $0\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:51493.3-51501.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1763 + attribute \src "libresoc.v:51015.3-51016.45" + wire width 4 $0\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:52011.3-52019.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$1846 + attribute \src "libresoc.v:51009.3-51010.39" + wire width 64 $0\dbg_dmi_din[63:0] + attribute \src "libresoc.v:51502.3-51510.6" + wire $0\dbg_dmi_req_i$next[0:0]$1766 + attribute \src "libresoc.v:51013.3-51014.43" + wire $0\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:51906.3-51914.6" + wire $0\dbg_dmi_we_i$next[0:0]$1835 + attribute \src "libresoc.v:51011.3-51012.41" + wire $0\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:51879.3-51894.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$1830 + attribute \src "libresoc.v:50847.3-50848.41" + wire width 64 $0\dec2_cur_dec[63:0] + attribute \src "libresoc.v:52186.3-52194.6" + wire $0\dec2_cur_eint$next[0:0]$2124 + attribute \src "libresoc.v:51003.3-51004.43" + wire $0\dec2_cur_eint[0:0] + attribute \src "libresoc.v:51511.3-51531.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$1769 + attribute \src "libresoc.v:50851.3-50852.41" + wire width 64 $0\dec2_cur_msr[63:0] + attribute \src "libresoc.v:52345.3-52365.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$2145 + attribute \src "libresoc.v:50857.3-50858.39" + wire width 64 $0\dec2_cur_pc[63:0] + attribute \src "libresoc.v:51532.3-51550.6" + wire width 32 $0\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:52195.3-52204.6" + wire width 2 $0\delay$next[1:0]$2127 + attribute \src "libresoc.v:50999.3-51000.27" + wire width 2 $0\delay[1:0] + attribute \src "libresoc.v:51638.3-51647.6" + wire width 5 $0\dmi__addr[4:0] + attribute \src "libresoc.v:51648.3-51657.6" + wire $0\dmi__ren[0:0] + attribute \src "libresoc.v:51795.3-51822.6" + wire width 2 $0\fsm_state$131$next[1:0]$1820 + attribute \src "libresoc.v:50869.3-50870.45" + wire width 2 $0\fsm_state$131[1:0]$1677 + attribute \src "libresoc.v:50009.13-50009.35" + wire width 2 $0\fsm_state$131[1:0]$2254 + attribute \src "libresoc.v:52396.3-52441.6" + wire width 2 $0\fsm_state$next[1:0]$2156 + attribute \src "libresoc.v:50853.3-50854.35" + wire width 2 $0\fsm_state[1:0] + attribute \src "libresoc.v:51687.3-51696.6" + wire width 8 $0\full_rd2__ren[7:0] + attribute \src "libresoc.v:51726.3-51735.6" + wire width 3 $0\full_rd__ren[2:0] + attribute \src "libresoc.v:51583.3-51606.6" + wire width 32 $0\ilatch$next[31:0]$1792 + attribute \src "libresoc.v:50957.3-50958.29" + wire width 32 $0\ilatch[31:0] + attribute \src "libresoc.v:52279.3-52294.6" + wire width 48 $0\imem_a_pc_i[47:0] + attribute \src "libresoc.v:52295.3-52319.6" + wire $0\imem_a_valid_i[0:0] + attribute \src "libresoc.v:52320.3-52344.6" + wire $0\imem_f_valid_i[0:0] + attribute \src "libresoc.v:48733.7-48733.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:51834.3-51848.6" + wire width 3 $0\issue__addr$135[2:0]$1825 + attribute \src "libresoc.v:51765.3-51779.6" + wire width 3 $0\issue__addr[2:0] + attribute \src "libresoc.v:51864.3-51878.6" + wire width 64 $0\issue__data_i[63:0] + attribute \src "libresoc.v:51780.3-51794.6" + wire $0\issue__ren[0:0] + attribute \src "libresoc.v:51849.3-51863.6" + wire $0\issue__wen[0:0] + attribute \src "libresoc.v:51627.3-51637.6" + wire $0\issue_i[0:0] + attribute \src "libresoc.v:51607.3-51626.6" + wire $0\ivalid_i[0:0] + attribute \src "libresoc.v:52168.3-52176.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$2118 + attribute \src "libresoc.v:51007.3-51008.49" + wire $0\jtag_dmi0__ack_o[0:0] + attribute \src "libresoc.v:52177.3-52185.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$2121 + attribute \src "libresoc.v:51005.3-51006.47" + wire width 64 $0\jtag_dmi0__dout[63:0] + attribute \src "libresoc.v:51995.3-52010.6" + wire width 4 $0\msr__ren[3:0] + attribute \src "libresoc.v:52366.3-52395.6" + wire $0\msr_read$next[0:0]$2150 + attribute \src "libresoc.v:50855.3-50856.33" + wire $0\msr_read[0:0] + attribute \src "libresoc.v:51823.3-51833.6" + wire width 64 $0\new_dec[63:0] + attribute \src "libresoc.v:51895.3-51905.6" + wire width 64 $0\new_tb[63:0] + attribute \src "libresoc.v:51924.3-51939.6" + wire width 64 $0\pc[63:0] + attribute \src "libresoc.v:52020.3-52044.6" + wire $0\pc_changed$next[0:0]$1849 + attribute \src "libresoc.v:50993.3-50994.37" + wire $0\pc_changed[0:0] + attribute \src "libresoc.v:51915.3-51923.6" + wire $0\pc_ok_delay$next[0:0]$1838 + attribute \src "libresoc.v:50995.3-50996.39" + wire $0\pc_ok_delay[0:0] + attribute \src "libresoc.v:52205.3-52241.6" + wire width 32 $0\raw_insn_i$next[31:0]$2130 + attribute \src "libresoc.v:50861.3-50862.37" + wire width 32 $0\raw_insn_i[31:0] + attribute \src "libresoc.v:51953.3-51973.6" + wire width 4 $0\wen[3:0] + attribute \src "libresoc.v:52242.3-52278.6" + wire $1\bigendian_i$next[0:0]$2137 + attribute \src "libresoc.v:48865.7-48865.25" + wire $1\bigendian_i[0:0] + attribute \src "libresoc.v:51940.3-51952.6" + wire width 4 $1\cia__ren[3:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $1\core_asmcode$next[7:0]$1913 + attribute \src "libresoc.v:48877.13-48877.33" + wire width 8 $1\core_asmcode[7:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 64 $1\core_core_cia$next[63:0]$1914 + attribute \src "libresoc.v:48883.14-48883.50" + wire width 64 $1\core_core_cia[63:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $1\core_core_cr_rd$next[7:0]$1915 + attribute \src "libresoc.v:48887.13-48887.36" + wire width 8 $1\core_core_cr_rd[7:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_cr_rd_ok$next[0:0]$1916 + attribute \src "libresoc.v:48891.7-48891.32" + wire $1\core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $1\core_core_cr_wr$next[7:0]$1917 + attribute \src "libresoc.v:48895.13-48895.36" + wire width 8 $1\core_core_cr_wr[7:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_cr_wr_ok$next[0:0]$1918 + attribute \src "libresoc.v:48899.7-48899.32" + wire $1\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_exc_$signal$50$next[0:0]$1919 + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_exc_$signal$51$next[0:0]$1920 + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_exc_$signal$52$next[0:0]$1921 + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_exc_$signal$53$next[0:0]$1922 + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_exc_$signal$54$next[0:0]$1923 + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_exc_$signal$55$next[0:0]$1924 + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_exc_$signal$56$next[0:0]$1925 + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_exc_$signal$next[0:0]$1926 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 12 $1\core_core_fn_unit$next[11:0]$1927 + attribute \src "libresoc.v:48948.14-48948.41" + wire width 12 $1\core_core_fn_unit[11:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 2 $1\core_core_input_carry$next[1:0]$1928 + attribute \src "libresoc.v:48956.13-48956.41" + wire width 2 $1\core_core_input_carry[1:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 32 $1\core_core_insn$next[31:0]$1929 + attribute \src "libresoc.v:48960.14-48960.36" + wire width 32 $1\core_core_insn[31:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 7 $1\core_core_insn_type$next[6:0]$1930 + attribute \src "libresoc.v:49038.13-49038.40" + wire width 7 $1\core_core_insn_type[6:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_is_32bit$next[0:0]$1931 + attribute \src "libresoc.v:49042.7-49042.32" + wire $1\core_core_is_32bit[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_lk$next[0:0]$1932 + attribute \src "libresoc.v:49046.7-49046.26" + wire $1\core_core_lk[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 64 $1\core_core_msr$next[63:0]$1933 + attribute \src "libresoc.v:49050.14-49050.50" + wire width 64 $1\core_core_msr[63:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_oe$next[0:0]$1934 + attribute \src "libresoc.v:49054.7-49054.26" + wire $1\core_core_oe[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_oe_ok$next[0:0]$1935 + attribute \src "libresoc.v:49058.7-49058.29" + wire $1\core_core_oe_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_rc$next[0:0]$1936 + attribute \src "libresoc.v:49062.7-49062.26" + wire $1\core_core_rc[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_core_rc_ok$next[0:0]$1937 + attribute \src "libresoc.v:49066.7-49066.29" + wire $1\core_core_rc_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 13 $1\core_core_trapaddr$next[12:0]$1938 + attribute \src "libresoc.v:49070.14-49070.43" + wire width 13 $1\core_core_trapaddr[12:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $1\core_core_traptype$next[7:0]$1939 + attribute \src "libresoc.v:49074.13-49074.39" + wire width 8 $1\core_core_traptype[7:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $1\core_cr_in1$next[2:0]$1940 + attribute \src "libresoc.v:49080.13-49080.31" + wire width 3 $1\core_cr_in1[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_cr_in1_ok$next[0:0]$1941 + attribute \src "libresoc.v:49084.7-49084.28" + wire $1\core_cr_in1_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $1\core_cr_in2$48$next[2:0]$1942 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $1\core_cr_in2$next[2:0]$1943 + attribute \src "libresoc.v:49088.13-49088.31" + wire width 3 $1\core_cr_in2[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_cr_in2_ok$49$next[0:0]$1944 + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_cr_in2_ok$next[0:0]$1945 + attribute \src "libresoc.v:49096.7-49096.28" + wire $1\core_cr_in2_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $1\core_cr_out$next[2:0]$1946 + attribute \src "libresoc.v:49104.13-49104.31" + wire width 3 $1\core_cr_out[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_cr_out_ok$next[0:0]$1947 + attribute \src "libresoc.v:49108.7-49108.28" + wire $1\core_cr_out_ok[0:0] + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $1\core_dec$next[63:0]$1779 + attribute \src "libresoc.v:49112.14-49112.45" + wire width 64 $1\core_dec[63:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $1\core_ea$next[4:0]$1948 + attribute \src "libresoc.v:49116.13-49116.28" + wire width 5 $1\core_ea[4:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_ea_ok$next[0:0]$1949 + attribute \src "libresoc.v:49120.7-49120.24" + wire $1\core_ea_ok[0:0] + attribute \src "libresoc.v:51551.3-51582.6" + wire $1\core_eint$next[0:0]$1780 + attribute \src "libresoc.v:49124.7-49124.23" + wire $1\core_eint[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $1\core_fast1$next[2:0]$1950 + attribute \src "libresoc.v:49128.13-49128.30" + wire width 3 $1\core_fast1[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_fast1_ok$next[0:0]$1951 + attribute \src "libresoc.v:49132.7-49132.27" + wire $1\core_fast1_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $1\core_fast2$next[2:0]$1952 + attribute \src "libresoc.v:49136.13-49136.30" + wire width 3 $1\core_fast2[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_fast2_ok$next[0:0]$1953 + attribute \src "libresoc.v:49140.7-49140.27" + wire $1\core_fast2_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $1\core_fasto1$next[2:0]$1954 + attribute \src "libresoc.v:49144.13-49144.31" + wire width 3 $1\core_fasto1[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_fasto1_ok$next[0:0]$1955 + attribute \src "libresoc.v:49148.7-49148.28" + wire $1\core_fasto1_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $1\core_fasto2$next[2:0]$1956 + attribute \src "libresoc.v:49152.13-49152.31" + wire width 3 $1\core_fasto2[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_fasto2_ok$next[0:0]$1957 + attribute \src "libresoc.v:49156.7-49156.28" + wire $1\core_fasto2_ok[0:0] + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $1\core_msr$next[63:0]$1781 + attribute \src "libresoc.v:49160.14-49160.45" + wire width 64 $1\core_msr[63:0] + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $1\core_pc$next[63:0]$1782 + attribute \src "libresoc.v:49164.14-49164.44" + wire width 64 $1\core_pc[63:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $1\core_reg1$next[4:0]$1958 + attribute \src "libresoc.v:49168.13-49168.30" + wire width 5 $1\core_reg1[4:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_reg1_ok$next[0:0]$1959 + attribute \src "libresoc.v:49172.7-49172.26" + wire $1\core_reg1_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $1\core_reg2$next[4:0]$1960 + attribute \src "libresoc.v:49176.13-49176.30" + wire width 5 $1\core_reg2[4:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_reg2_ok$next[0:0]$1961 + attribute \src "libresoc.v:49180.7-49180.26" + wire $1\core_reg2_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $1\core_reg3$next[4:0]$1962 + attribute \src "libresoc.v:49184.13-49184.30" + wire width 5 $1\core_reg3[4:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_reg3_ok$next[0:0]$1963 + attribute \src "libresoc.v:49188.7-49188.26" + wire $1\core_reg3_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $1\core_rego$next[4:0]$1964 + attribute \src "libresoc.v:49192.13-49192.30" + wire width 5 $1\core_rego[4:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_rego_ok$next[0:0]$1965 + attribute \src "libresoc.v:49196.7-49196.26" + wire $1\core_rego_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 10 $1\core_spr1$next[9:0]$1966 + attribute \src "libresoc.v:49311.13-49311.32" + wire width 10 $1\core_spr1[9:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_spr1_ok$next[0:0]$1967 + attribute \src "libresoc.v:49315.7-49315.26" + wire $1\core_spr1_ok[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 10 $1\core_spro$next[9:0]$1968 + attribute \src "libresoc.v:49430.13-49430.32" + wire width 10 $1\core_spro[9:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_spro_ok$next[0:0]$1969 + attribute \src "libresoc.v:49434.7-49434.26" + wire $1\core_spro_ok[0:0] + attribute \src "libresoc.v:52442.3-52460.6" + wire $1\core_stopped_i[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $1\core_xer_in$next[2:0]$1970 + attribute \src "libresoc.v:49442.13-49442.31" + wire width 3 $1\core_xer_in[2:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire $1\core_xer_out$next[0:0]$1971 + attribute \src "libresoc.v:49446.7-49446.26" + wire $1\core_xer_out[0:0] + attribute \src "libresoc.v:49462.7-49462.30" + wire $1\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:51697.3-51705.6" + wire $1\d_cr_delay$next[0:0]$1808 + attribute \src "libresoc.v:49468.7-49468.24" + wire $1\d_cr_delay[0:0] + attribute \src "libresoc.v:51658.3-51666.6" + wire $1\d_reg_delay$next[0:0]$1802 + attribute \src "libresoc.v:49472.7-49472.25" + wire $1\d_reg_delay[0:0] + attribute \src "libresoc.v:51736.3-51744.6" + wire $1\d_xer_delay$next[0:0]$1814 + attribute \src "libresoc.v:49476.7-49476.25" + wire $1\d_xer_delay[0:0] + attribute \src "libresoc.v:51974.3-51994.6" + wire width 64 $1\data_i[63:0] + attribute \src "libresoc.v:52461.3-52479.6" + wire $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:51716.3-51725.6" + wire $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:51706.3-51715.6" + wire width 64 $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:51677.3-51686.6" + wire $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:51667.3-51676.6" + wire width 64 $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:51755.3-51764.6" + wire $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:51745.3-51754.6" + wire width 64 $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:51493.3-51501.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1764 + attribute \src "libresoc.v:49514.13-49514.34" + wire width 4 $1\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:52011.3-52019.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$1847 + attribute \src "libresoc.v:49518.14-49518.48" + wire width 64 $1\dbg_dmi_din[63:0] + attribute \src "libresoc.v:51502.3-51510.6" + wire $1\dbg_dmi_req_i$next[0:0]$1767 + attribute \src "libresoc.v:49524.7-49524.27" + wire $1\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:51906.3-51914.6" + wire $1\dbg_dmi_we_i$next[0:0]$1836 + attribute \src "libresoc.v:49528.7-49528.26" + wire $1\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:51879.3-51894.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$1831 + attribute \src "libresoc.v:49564.14-49564.49" + wire width 64 $1\dec2_cur_dec[63:0] + attribute \src "libresoc.v:52186.3-52194.6" + wire $1\dec2_cur_eint$next[0:0]$2125 + attribute \src "libresoc.v:49568.7-49568.27" + wire $1\dec2_cur_eint[0:0] + attribute \src "libresoc.v:51511.3-51531.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$1770 + attribute \src "libresoc.v:49572.14-49572.49" + wire width 64 $1\dec2_cur_msr[63:0] + attribute \src "libresoc.v:52345.3-52365.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$2146 + attribute \src "libresoc.v:49576.14-49576.48" + wire width 64 $1\dec2_cur_pc[63:0] + attribute \src "libresoc.v:51532.3-51550.6" + wire width 32 $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:52195.3-52204.6" + wire width 2 $1\delay$next[1:0]$2128 + attribute \src "libresoc.v:49985.13-49985.25" + wire width 2 $1\delay[1:0] + attribute \src "libresoc.v:51638.3-51647.6" + wire width 5 $1\dmi__addr[4:0] + attribute \src "libresoc.v:51648.3-51657.6" + wire $1\dmi__ren[0:0] + attribute \src "libresoc.v:51795.3-51822.6" + wire width 2 $1\fsm_state$131$next[1:0]$1821 + attribute \src "libresoc.v:52396.3-52441.6" + wire width 2 $1\fsm_state$next[1:0]$2157 + attribute \src "libresoc.v:50007.13-50007.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "libresoc.v:51687.3-51696.6" + wire width 8 $1\full_rd2__ren[7:0] + attribute \src "libresoc.v:51726.3-51735.6" + wire width 3 $1\full_rd__ren[2:0] + attribute \src "libresoc.v:51583.3-51606.6" + wire width 32 $1\ilatch$next[31:0]$1793 + attribute \src "libresoc.v:50259.14-50259.28" + wire width 32 $1\ilatch[31:0] + attribute \src "libresoc.v:52279.3-52294.6" + wire width 48 $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:52295.3-52319.6" + wire $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:52320.3-52344.6" + wire $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:51834.3-51848.6" + wire width 3 $1\issue__addr$135[2:0]$1826 + attribute \src "libresoc.v:51765.3-51779.6" + wire width 3 $1\issue__addr[2:0] + attribute \src "libresoc.v:51864.3-51878.6" + wire width 64 $1\issue__data_i[63:0] + attribute \src "libresoc.v:51780.3-51794.6" + wire $1\issue__ren[0:0] + attribute \src "libresoc.v:51849.3-51863.6" + wire $1\issue__wen[0:0] + attribute \src "libresoc.v:51627.3-51637.6" + wire $1\issue_i[0:0] + attribute \src "libresoc.v:51607.3-51626.6" + wire $1\ivalid_i[0:0] + attribute \src "libresoc.v:52168.3-52176.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$2119 + attribute \src "libresoc.v:50293.7-50293.30" + wire $1\jtag_dmi0__ack_o[0:0] + attribute \src "libresoc.v:52177.3-52185.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$2122 + attribute \src "libresoc.v:50301.14-50301.52" + wire width 64 $1\jtag_dmi0__dout[63:0] + attribute \src "libresoc.v:51995.3-52010.6" + wire width 4 $1\msr__ren[3:0] + attribute \src "libresoc.v:52366.3-52395.6" + wire $1\msr_read$next[0:0]$2151 + attribute \src "libresoc.v:50361.7-50361.22" + wire $1\msr_read[0:0] + attribute \src "libresoc.v:51823.3-51833.6" + wire width 64 $1\new_dec[63:0] + attribute \src "libresoc.v:51895.3-51905.6" + wire width 64 $1\new_tb[63:0] + attribute \src "libresoc.v:51924.3-51939.6" + wire width 64 $1\pc[63:0] + attribute \src "libresoc.v:52020.3-52044.6" + wire $1\pc_changed$next[0:0]$1850 + attribute \src "libresoc.v:50389.7-50389.24" + wire $1\pc_changed[0:0] + attribute \src "libresoc.v:51915.3-51923.6" + wire $1\pc_ok_delay$next[0:0]$1839 + attribute \src "libresoc.v:50399.7-50399.25" + wire $1\pc_ok_delay[0:0] + attribute \src "libresoc.v:52205.3-52241.6" + wire width 32 $1\raw_insn_i$next[31:0]$2131 + attribute \src "libresoc.v:50413.14-50413.32" + wire width 32 $1\raw_insn_i[31:0] + attribute \src "libresoc.v:51953.3-51973.6" + wire width 4 $1\wen[3:0] + attribute \src "libresoc.v:52242.3-52278.6" + wire $2\bigendian_i$next[0:0]$2138 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $2\core_asmcode$next[7:0]$1972 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 64 $2\core_core_cia$next[63:0]$1973 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $2\core_core_cr_rd$next[7:0]$1974 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_cr_rd_ok$next[0:0]$1975 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $2\core_core_cr_wr$next[7:0]$1976 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_cr_wr_ok$next[0:0]$1977 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_exc_$signal$50$next[0:0]$1978 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_exc_$signal$51$next[0:0]$1979 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_exc_$signal$52$next[0:0]$1980 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_exc_$signal$53$next[0:0]$1981 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_exc_$signal$54$next[0:0]$1982 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_exc_$signal$55$next[0:0]$1983 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_exc_$signal$56$next[0:0]$1984 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_exc_$signal$next[0:0]$1985 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 12 $2\core_core_fn_unit$next[11:0]$1986 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 2 $2\core_core_input_carry$next[1:0]$1987 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 32 $2\core_core_insn$next[31:0]$1988 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 7 $2\core_core_insn_type$next[6:0]$1989 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_is_32bit$next[0:0]$1990 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_lk$next[0:0]$1991 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 64 $2\core_core_msr$next[63:0]$1992 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_oe$next[0:0]$1993 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_oe_ok$next[0:0]$1994 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_rc$next[0:0]$1995 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_core_rc_ok$next[0:0]$1996 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 13 $2\core_core_trapaddr$next[12:0]$1997 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $2\core_core_traptype$next[7:0]$1998 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $2\core_cr_in1$next[2:0]$1999 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_cr_in1_ok$next[0:0]$2000 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $2\core_cr_in2$48$next[2:0]$2001 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $2\core_cr_in2$next[2:0]$2002 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_cr_in2_ok$49$next[0:0]$2003 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_cr_in2_ok$next[0:0]$2004 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $2\core_cr_out$next[2:0]$2005 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_cr_out_ok$next[0:0]$2006 + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $2\core_dec$next[63:0]$1783 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $2\core_ea$next[4:0]$2007 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_ea_ok$next[0:0]$2008 + attribute \src "libresoc.v:51551.3-51582.6" + wire $2\core_eint$next[0:0]$1784 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $2\core_fast1$next[2:0]$2009 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_fast1_ok$next[0:0]$2010 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $2\core_fast2$next[2:0]$2011 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_fast2_ok$next[0:0]$2012 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $2\core_fasto1$next[2:0]$2013 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_fasto1_ok$next[0:0]$2014 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $2\core_fasto2$next[2:0]$2015 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_fasto2_ok$next[0:0]$2016 + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $2\core_msr$next[63:0]$1785 + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $2\core_pc$next[63:0]$1786 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $2\core_reg1$next[4:0]$2017 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_reg1_ok$next[0:0]$2018 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $2\core_reg2$next[4:0]$2019 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_reg2_ok$next[0:0]$2020 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $2\core_reg3$next[4:0]$2021 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_reg3_ok$next[0:0]$2022 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $2\core_rego$next[4:0]$2023 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_rego_ok$next[0:0]$2024 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 10 $2\core_spr1$next[9:0]$2025 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_spr1_ok$next[0:0]$2026 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 10 $2\core_spro$next[9:0]$2027 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_spro_ok$next[0:0]$2028 + attribute \src "libresoc.v:52442.3-52460.6" + wire $2\core_stopped_i[0:0] + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $2\core_xer_in$next[2:0]$2029 + attribute \src "libresoc.v:52045.3-52167.6" + wire $2\core_xer_out$next[0:0]$2030 + attribute \src "libresoc.v:51974.3-51994.6" + wire width 64 $2\data_i[63:0] + attribute \src "libresoc.v:52461.3-52479.6" + wire $2\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:51879.3-51894.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$1832 + attribute \src "libresoc.v:51511.3-51531.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$1771 + attribute \src "libresoc.v:52345.3-52365.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$2147 + attribute \src "libresoc.v:51532.3-51550.6" + wire width 32 $2\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:51795.3-51822.6" + wire width 2 $2\fsm_state$131$next[1:0]$1822 + attribute \src "libresoc.v:52396.3-52441.6" + wire width 2 $2\fsm_state$next[1:0]$2158 + attribute \src "libresoc.v:51583.3-51606.6" + wire width 32 $2\ilatch$next[31:0]$1794 + attribute \src "libresoc.v:52279.3-52294.6" + wire width 48 $2\imem_a_pc_i[47:0] + attribute \src "libresoc.v:52295.3-52319.6" + wire $2\imem_a_valid_i[0:0] + attribute \src "libresoc.v:52320.3-52344.6" + wire $2\imem_f_valid_i[0:0] + attribute \src "libresoc.v:51607.3-51626.6" + wire $2\ivalid_i[0:0] + attribute \src "libresoc.v:51995.3-52010.6" + wire width 4 $2\msr__ren[3:0] + attribute \src "libresoc.v:52366.3-52395.6" + wire $2\msr_read$next[0:0]$2152 + attribute \src "libresoc.v:51924.3-51939.6" + wire width 64 $2\pc[63:0] + attribute \src "libresoc.v:52020.3-52044.6" + wire $2\pc_changed$next[0:0]$1851 + attribute \src "libresoc.v:52205.3-52241.6" + wire width 32 $2\raw_insn_i$next[31:0]$2132 + attribute \src "libresoc.v:51953.3-51973.6" + wire width 4 $2\wen[3:0] + attribute \src "libresoc.v:52242.3-52278.6" + wire $3\bigendian_i$next[0:0]$2139 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $3\core_asmcode$next[7:0]$2031 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 64 $3\core_core_cia$next[63:0]$2032 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $3\core_core_cr_rd$next[7:0]$2033 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_cr_rd_ok$next[0:0]$2034 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $3\core_core_cr_wr$next[7:0]$2035 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_cr_wr_ok$next[0:0]$2036 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_exc_$signal$50$next[0:0]$2037 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_exc_$signal$51$next[0:0]$2038 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_exc_$signal$52$next[0:0]$2039 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_exc_$signal$53$next[0:0]$2040 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_exc_$signal$54$next[0:0]$2041 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_exc_$signal$55$next[0:0]$2042 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_exc_$signal$56$next[0:0]$2043 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_exc_$signal$next[0:0]$2044 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 12 $3\core_core_fn_unit$next[11:0]$2045 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 2 $3\core_core_input_carry$next[1:0]$2046 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 32 $3\core_core_insn$next[31:0]$2047 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 7 $3\core_core_insn_type$next[6:0]$2048 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_is_32bit$next[0:0]$2049 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_lk$next[0:0]$2050 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 64 $3\core_core_msr$next[63:0]$2051 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_oe$next[0:0]$2052 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_oe_ok$next[0:0]$2053 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_rc$next[0:0]$2054 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_core_rc_ok$next[0:0]$2055 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 13 $3\core_core_trapaddr$next[12:0]$2056 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 8 $3\core_core_traptype$next[7:0]$2057 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $3\core_cr_in1$next[2:0]$2058 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_cr_in1_ok$next[0:0]$2059 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $3\core_cr_in2$48$next[2:0]$2060 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $3\core_cr_in2$next[2:0]$2061 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_cr_in2_ok$49$next[0:0]$2062 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_cr_in2_ok$next[0:0]$2063 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $3\core_cr_out$next[2:0]$2064 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_cr_out_ok$next[0:0]$2065 + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $3\core_dec$next[63:0]$1787 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $3\core_ea$next[4:0]$2066 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_ea_ok$next[0:0]$2067 + attribute \src "libresoc.v:51551.3-51582.6" + wire $3\core_eint$next[0:0]$1788 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $3\core_fast1$next[2:0]$2068 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_fast1_ok$next[0:0]$2069 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $3\core_fast2$next[2:0]$2070 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_fast2_ok$next[0:0]$2071 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $3\core_fasto1$next[2:0]$2072 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_fasto1_ok$next[0:0]$2073 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $3\core_fasto2$next[2:0]$2074 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_fasto2_ok$next[0:0]$2075 + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $3\core_msr$next[63:0]$1789 + attribute \src "libresoc.v:51551.3-51582.6" + wire width 64 $3\core_pc$next[63:0]$1790 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $3\core_reg1$next[4:0]$2076 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_reg1_ok$next[0:0]$2077 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $3\core_reg2$next[4:0]$2078 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_reg2_ok$next[0:0]$2079 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $3\core_reg3$next[4:0]$2080 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_reg3_ok$next[0:0]$2081 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 5 $3\core_rego$next[4:0]$2082 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_rego_ok$next[0:0]$2083 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 10 $3\core_spr1$next[9:0]$2084 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_spr1_ok$next[0:0]$2085 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 10 $3\core_spro$next[9:0]$2086 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_spro_ok$next[0:0]$2087 + attribute \src "libresoc.v:52045.3-52167.6" + wire width 3 $3\core_xer_in$next[2:0]$2088 + attribute \src "libresoc.v:52045.3-52167.6" + wire $3\core_xer_out$next[0:0]$2089 + attribute \src "libresoc.v:51974.3-51994.6" + wire width 64 $3\data_i[63:0] + attribute \src "libresoc.v:51511.3-51531.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$1772 + attribute \src "libresoc.v:52345.3-52365.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$2148 + attribute \src "libresoc.v:52396.3-52441.6" + wire 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attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 \dec2_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire \dec2_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire \dec2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \dec2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 \dec2_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec2_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec2_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec2_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec2_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec2_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec2_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 \dec2_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \dec2_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 \dec2_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + wire \dec2_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + wire width 2 \delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + wire width 2 \delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 170 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 15 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 171 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 16 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 172 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 17 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + wire width 2 \fsm_state$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + wire width 2 \fsm_state$131$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + wire width 2 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \full_rd2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 \full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 19 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 18 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 176 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 23 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 21 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 177 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 178 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \gpio_s7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 9 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 14 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 8 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 13 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 10 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 12 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 11 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 335 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 341 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 336 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 337 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 338 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 342 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 339 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 340 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 348 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 343 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 345 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 347 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 349 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 346 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 350 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" + wire width 32 \ilatch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" + wire width 32 \ilatch$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 \imem_a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire \imem_a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire \imem_f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 \imem_f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire \imem_f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \imem_wb_icache_en + attribute \src "libresoc.v:48733.7-48733.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 344 \int_level_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \issue__addr$135 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + wire \issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + wire \ivalid_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \jtag_dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 331 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 325 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 327 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 332 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 330 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 326 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 328 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 329 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \msr__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" + wire \msr_read + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" + wire \msr_read$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391" + wire width 64 \new_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408" + wire width 64 \new_tb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + wire width 64 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:204" + wire width 64 \pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \pc_changed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \pc_changed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 7 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 6 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102" + wire width 64 output 5 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + wire \pc_ok_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + wire \pc_ok_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire \por_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + wire width 32 \raw_insn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + wire width 32 \raw_insn_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 318 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 163 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 320 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 167 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 168 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 322 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 323 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + wire \ti_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \xics_icp_core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_icp_ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_icp_ics_i_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_ics_icp_o_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_ics_icp_o_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409" + cell $add $add$libresoc.v:50808$1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \issue__data_o + connect \B 1'1 + connect \Y $add$libresoc.v:50808$1626_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201" + cell $add $add$libresoc.v:50815$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B 3'100 + connect \Y $add$libresoc.v:50815$1633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50790$1606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$95 + connect \B \$97 + connect \Y $and$libresoc.v:50790$1606_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50794$1610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$103 + connect \B \$105 + connect \Y $and$libresoc.v:50794$1610_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50798$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$109 + connect \B \$111 + connect \Y $and$libresoc.v:50798$1614_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:50814$1632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o + connect \B \$21 + connect \Y $and$libresoc.v:50814$1632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50823$1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \B \$40 + connect \Y $and$libresoc.v:50823$1641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + cell $and $and$libresoc.v:50824$1642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \state_nia_wen + connect \B 1'1 + connect \Y $and$libresoc.v:50824$1642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50831$1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$63 + connect \B \$65 + connect \Y $and$libresoc.v:50831$1649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50834$1652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$69 + connect \B \$71 + connect \Y $and$libresoc.v:50834$1652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50837$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$75 + connect \B \$77 + connect \Y $and$libresoc.v:50837$1655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50840$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$81 + connect \B \$83 + connect \Y $and$libresoc.v:50840$1658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50843$1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$87 + connect \B \$89 + connect \Y $and$libresoc.v:50843$1661_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:50805$1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \full_rd2__data_o + connect \Y $extend$libresoc.v:50805$1621_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:50806$1623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \full_rd__data_o + connect \Y $extend$libresoc.v:50806$1623_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:50800$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:50800$1616_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:50802$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:50802$1618_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" + cell $ne $ne$libresoc.v:50795$1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \delay + connect \B 1'0 + connect \Y $ne$libresoc.v:50795$1611_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + cell $ne $ne$libresoc.v:50804$1620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \core_core_insn_type + connect \B 7'0000001 + connect \Y $ne$libresoc.v:50804$1620_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + cell $ne $ne$libresoc.v:50812$1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \delay + connect \B \$17 + connect \Y $ne$libresoc.v:50812$1630_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50791$1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50791$1607_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50792$1608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50792$1608_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50793$1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50793$1609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50796$1612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50796$1612_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50797$1613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50797$1613_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + cell $not $not$libresoc.v:50799$1615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:50799$1615_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:50813$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o_dly + connect \Y $not$libresoc.v:50813$1631_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" + cell $not $not$libresoc.v:50816$1634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_i_ok + connect \Y $not$libresoc.v:50816$1634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50817$1635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50817$1635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + cell $not $not$libresoc.v:50818$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$libresoc.v:50818$1636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50819$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50819$1637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + cell $not $not$libresoc.v:50820$1638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$libresoc.v:50820$1638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50821$1639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50821$1639_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50822$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50822$1640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50826$1644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50826$1644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50827$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50827$1645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50828$1646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50828$1646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50829$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50829$1647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50830$1648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50830$1648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50832$1650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50832$1650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50833$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50833$1651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50835$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50835$1653_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50836$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50836$1654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50838$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50838$1656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50839$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50839$1657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50841$1659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50841$1659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50842$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50842$1660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + cell $not $not$libresoc.v:50844$1662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:50844$1662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50845$1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50845$1663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50846$1664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50846$1664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + cell $or $or$libresoc.v:50810$1628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \dbg_core_rst_o + connect \Y $or$libresoc.v:50810$1628_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + cell $or $or$libresoc.v:50811$1629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \rst + connect \Y $or$libresoc.v:50811$1629_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:50805$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:50805$1621_Y + connect \Y $pos$libresoc.v:50805$1622_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:50806$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:50806$1623_Y + connect \Y $pos$libresoc.v:50806$1624_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:50825$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$45 + connect \Y $reduce_or$libresoc.v:50825$1643_Y + end + attribute \src "libresoc.v:50801.19-50801.42" + cell $shr $shr$libresoc.v:50801$1617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$118 + connect \Y $shr$libresoc.v:50801$1617_Y + end + attribute \src "libresoc.v:50803.19-50803.42" + cell $shr $shr$libresoc.v:50803$1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$122 + connect \Y $shr$libresoc.v:50803$1619_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393" + cell $sub $sub$libresoc.v:50807$1625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \issue__data_o + connect \B 1'1 + connect \Y $sub$libresoc.v:50807$1625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + cell $sub $sub$libresoc.v:50809$1627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \delay + connect \B 1'1 + connect \Y $sub$libresoc.v:50809$1627_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51019.8-51022.4" + cell \core \core + connect \coresync_clk \coresync_clk + connect \coresync_rst \core_coresync_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51023.7-51048.4" + cell \dbg \dbg + connect \clk \clk + connect \core_dbg_msr \dbg_core_dbg_msr + connect \core_dbg_pc \dbg_core_dbg_pc + connect \core_rst_o \dbg_core_rst_o + connect \core_stop_o \dbg_core_stop_o + connect \core_stopped_i \dbg_core_stopped_i + connect \d_cr_ack \dbg_d_cr_ack + connect \d_cr_data \dbg_d_cr_data + connect \d_cr_req \dbg_d_cr_req + connect \d_gpr_ack \dbg_d_gpr_ack + connect \d_gpr_addr \dbg_d_gpr_addr + connect \d_gpr_data \dbg_d_gpr_data + connect \d_gpr_req \dbg_d_gpr_req + connect \d_xer_ack \dbg_d_xer_ack + connect \d_xer_data \dbg_d_xer_data + connect \d_xer_req \dbg_d_xer_req + connect \dmi_ack_o \dbg_dmi_ack_o + connect \dmi_addr_i \dbg_dmi_addr_i + connect \dmi_din \dbg_dmi_din + connect \dmi_dout \dbg_dmi_dout + connect \dmi_req_i \dbg_dmi_req_i + connect \dmi_we_i \dbg_dmi_we_i + connect \rst \rst + connect \terminate_i \dbg_terminate_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51049.8-51115.4" + cell \dec2 \dec2 + connect \asmcode \dec2_asmcode + connect \bigendian \dec2_bigendian + connect \cia \dec2_cia + connect \cr_in1 \dec2_cr_in1 + connect \cr_in1_ok \dec2_cr_in1_ok + connect \cr_in2 \dec2_cr_in2 + connect \cr_in2$1 \dec2_cr_in2$1 + connect \cr_in2_ok \dec2_cr_in2_ok + connect \cr_in2_ok$2 \dec2_cr_in2_ok$2 + connect \cr_out \dec2_cr_out + connect \cr_out_ok \dec2_cr_out_ok + connect \cr_rd \dec2_cr_rd + connect \cr_rd_ok \dec2_cr_rd_ok + connect \cr_wr \dec2_cr_wr + connect \cr_wr_ok \dec2_cr_wr_ok + connect \cur_dec \dec2_cur_dec + connect \cur_eint \dec2_cur_eint + connect \cur_msr \dec2_cur_msr + connect \cur_pc \dec2_cur_pc + connect \ea \dec2_ea + connect \ea_ok \dec2_ea_ok + connect \exc_$signal \dec2_exc_$signal + connect \exc_$signal$3 \dec2_exc_$signal$3 + connect \exc_$signal$4 \dec2_exc_$signal$4 + connect \exc_$signal$5 \dec2_exc_$signal$5 + connect \exc_$signal$6 \dec2_exc_$signal$6 + connect \exc_$signal$7 \dec2_exc_$signal$7 + connect \exc_$signal$8 \dec2_exc_$signal$8 + connect \exc_$signal$9 \dec2_exc_$signal$9 + connect \fast1 \dec2_fast1 + connect \fast1_ok \dec2_fast1_ok + connect \fast2 \dec2_fast2 + connect \fast2_ok \dec2_fast2_ok + connect \fasto1 \dec2_fasto1 + connect \fasto1_ok \dec2_fasto1_ok + connect \fasto2 \dec2_fasto2 + connect \fasto2_ok \dec2_fasto2_ok + connect \fn_unit \dec2_fn_unit + connect \input_carry \dec2_input_carry + connect \insn \dec2_insn + connect \insn_type \dec2_insn_type + connect \is_32bit \dec2_is_32bit + connect \lk \dec2_lk + connect \msr \dec2_msr + connect \oe \dec2_oe + connect \oe_ok \dec2_oe_ok + connect \raw_opcode_in \dec2_raw_opcode_in + connect \rc \dec2_rc + connect \rc_ok \dec2_rc_ok + connect \reg1 \dec2_reg1 + connect \reg1_ok \dec2_reg1_ok + connect \reg2 \dec2_reg2 + connect \reg2_ok \dec2_reg2_ok + connect \reg3 \dec2_reg3 + connect \reg3_ok \dec2_reg3_ok + connect \rego \dec2_rego + connect \rego_ok \dec2_rego_ok + connect \spr1 \dec2_spr1 + connect \spr1_ok \dec2_spr1_ok + connect \spro \dec2_spro + connect \spro_ok \dec2_spro_ok + connect \trapaddr \dec2_trapaddr + connect \traptype \dec2_traptype + connect \xer_in \dec2_xer_in + connect \xer_out \dec2_xer_out + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51116.8-51132.4" + cell \imem \imem + connect \a_pc_i \imem_a_pc_i + connect \a_valid_i \imem_a_valid_i + connect \clk \clk + connect \f_busy_o \imem_f_busy_o + connect \f_instr_o \imem_f_instr_o + connect \f_valid_i \imem_f_valid_i + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \rst \rst + connect \wb_icache_en \imem_wb_icache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51133.8-51463.4" + cell \jtag \jtag + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \clk \clk + connect \dmi0__ack_o \jtag_dmi0__ack_o + connect \dmi0__addr_i \jtag_dmi0__addr_i + connect \dmi0__din \jtag_dmi0__din + connect \dmi0__dout \jtag_dmi0__dout + connect \dmi0__req_i \jtag_dmi0__req_i + connect \dmi0__we_i \jtag_dmi0__we_i + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + connect \mtwi_sda__pad__o \mtwi_sda__pad__o + connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe + connect \pwm_0__core__o \pwm_0__core__o + connect \pwm_0__pad__o \pwm_0__pad__o + connect \pwm_1__core__o \pwm_1__core__o + connect \pwm_1__pad__o \pwm_1__pad__o + connect \rst \rst + connect \sd0_clk__core__o \sd0_clk__core__o + connect \sd0_clk__pad__o \sd0_clk__pad__o + connect \sd0_cmd__core__i \sd0_cmd__core__i + connect \sd0_cmd__core__o \sd0_cmd__core__o + connect \sd0_cmd__core__oe \sd0_cmd__core__oe + connect \sd0_cmd__pad__i \sd0_cmd__pad__i + connect \sd0_cmd__pad__o \sd0_cmd__pad__o + connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe + connect \sd0_data0__core__i \sd0_data0__core__i + connect \sd0_data0__core__o \sd0_data0__core__o + connect \sd0_data0__core__oe \sd0_data0__core__oe + connect \sd0_data0__pad__i \sd0_data0__pad__i + connect \sd0_data0__pad__o \sd0_data0__pad__o + connect \sd0_data0__pad__oe \sd0_data0__pad__oe + connect \sd0_data1__core__i \sd0_data1__core__i + connect \sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__i \sdr_dm_1__core__i + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe + connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o + connect \wb_icache_en \imem_wb_icache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51464.12-51478.4" + cell \xics_icp \xics_icp + connect \clk \clk + connect \core_irq_o \xics_icp_core_irq_o + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_i_pri \xics_icp_ics_i_pri + connect \ics_i_src \xics_icp_ics_i_src + connect \rst \rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51479.12-51492.4" + cell \xics_ics \xics_ics + connect \clk \clk + connect \icp_o_pri \xics_ics_icp_o_pri + connect \icp_o_src \xics_ics_icp_o_src + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \rst \rst + end + attribute \src "libresoc.v:48733.7-48733.20" + process $proc$libresoc.v:48733$2164 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:48865.7-48865.25" + process $proc$libresoc.v:48865$2165 + assign { } { } + assign $1\bigendian_i[0:0] 1'0 + sync always + sync init + update \bigendian_i $1\bigendian_i[0:0] + end + attribute \src "libresoc.v:48877.13-48877.33" + process $proc$libresoc.v:48877$2166 + assign { } { } + assign $1\core_asmcode[7:0] 8'00000000 + sync always + sync init + update \core_asmcode $1\core_asmcode[7:0] + end + attribute \src "libresoc.v:48883.14-48883.50" + process $proc$libresoc.v:48883$2167 + assign { } { } + assign $1\core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_cia $1\core_core_cia[63:0] + end + attribute \src "libresoc.v:48887.13-48887.36" + process $proc$libresoc.v:48887$2168 + assign { } { } + assign $1\core_core_cr_rd[7:0] 8'00000000 + sync always + sync init + update \core_core_cr_rd $1\core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:48891.7-48891.32" + process $proc$libresoc.v:48891$2169 + assign { } { } + assign $1\core_core_cr_rd_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_rd_ok $1\core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:48895.13-48895.36" + process $proc$libresoc.v:48895$2170 + assign { } { } + assign $1\core_core_cr_wr[7:0] 8'00000000 + sync always + sync init + update \core_core_cr_wr $1\core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:48899.7-48899.32" + process $proc$libresoc.v:48899$2171 + assign { } { } + assign $1\core_core_cr_wr_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:48903.7-48903.37" + process $proc$libresoc.v:48903$2172 + assign { } { } + assign $0\core_core_exc_$signal[0:0]$2173 1'0 + sync always + sync init + update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$2173 + end + attribute \src "libresoc.v:48905.7-48905.40" + process $proc$libresoc.v:48905$2174 + assign { } { } + assign $0\core_core_exc_$signal$50[0:0]$2175 1'0 + sync always + sync init + update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$2175 + end + attribute \src "libresoc.v:48909.7-48909.40" + process $proc$libresoc.v:48909$2176 + assign { } { } + assign $0\core_core_exc_$signal$51[0:0]$2177 1'0 + sync always + sync init + update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$2177 + end + attribute \src "libresoc.v:48913.7-48913.40" + process $proc$libresoc.v:48913$2178 + assign { } { } + assign $0\core_core_exc_$signal$52[0:0]$2179 1'0 + sync always + sync init + update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$2179 + end + attribute \src "libresoc.v:48917.7-48917.40" + process $proc$libresoc.v:48917$2180 + assign { } { } + assign $0\core_core_exc_$signal$53[0:0]$2181 1'0 + sync always + sync init + update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$2181 + end + attribute \src "libresoc.v:48921.7-48921.40" + process $proc$libresoc.v:48921$2182 + assign { } { } + assign $0\core_core_exc_$signal$54[0:0]$2183 1'0 + sync always + sync init + update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$2183 + end + attribute \src "libresoc.v:48925.7-48925.40" + process $proc$libresoc.v:48925$2184 + assign { } { } + assign $0\core_core_exc_$signal$55[0:0]$2185 1'0 + sync always + sync init + update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$2185 + end + attribute \src "libresoc.v:48929.7-48929.40" + process $proc$libresoc.v:48929$2186 + assign { } { } + assign $0\core_core_exc_$signal$56[0:0]$2187 1'0 + sync always + sync init + update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$2187 + end + attribute \src "libresoc.v:48948.14-48948.41" + process $proc$libresoc.v:48948$2188 + assign { } { } + assign $1\core_core_fn_unit[11:0] 12'000000000000 + sync always + sync init + update \core_core_fn_unit $1\core_core_fn_unit[11:0] + end + attribute \src "libresoc.v:48956.13-48956.41" + process $proc$libresoc.v:48956$2189 + assign { } { } + assign $1\core_core_input_carry[1:0] 2'00 + sync always + sync init + update \core_core_input_carry $1\core_core_input_carry[1:0] + end + attribute \src "libresoc.v:48960.14-48960.36" + process $proc$libresoc.v:48960$2190 + assign { } { } + assign $1\core_core_insn[31:0] 0 + sync always + sync init + update \core_core_insn $1\core_core_insn[31:0] + end + attribute \src "libresoc.v:49038.13-49038.40" + process $proc$libresoc.v:49038$2191 + assign { } { } + assign $1\core_core_insn_type[6:0] 7'0000000 + sync always + sync init + update \core_core_insn_type $1\core_core_insn_type[6:0] + end + attribute \src "libresoc.v:49042.7-49042.32" + process $proc$libresoc.v:49042$2192 + assign { } { } + assign $1\core_core_is_32bit[0:0] 1'0 + sync always + sync init + update \core_core_is_32bit $1\core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:49046.7-49046.26" + process $proc$libresoc.v:49046$2193 + assign { } { } + assign $1\core_core_lk[0:0] 1'0 + sync always + sync init + update \core_core_lk $1\core_core_lk[0:0] + end + attribute \src "libresoc.v:49050.14-49050.50" + process $proc$libresoc.v:49050$2194 + assign { } { } + assign $1\core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_msr $1\core_core_msr[63:0] + end + attribute \src "libresoc.v:49054.7-49054.26" + process $proc$libresoc.v:49054$2195 + assign { } { } + assign $1\core_core_oe[0:0] 1'0 + sync always + sync init + update \core_core_oe $1\core_core_oe[0:0] + end + attribute \src "libresoc.v:49058.7-49058.29" + process $proc$libresoc.v:49058$2196 + assign { } { } + assign $1\core_core_oe_ok[0:0] 1'0 + sync always + sync init + update \core_core_oe_ok $1\core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:49062.7-49062.26" + process $proc$libresoc.v:49062$2197 + assign { } { } + assign $1\core_core_rc[0:0] 1'0 + sync always + sync init + update \core_core_rc $1\core_core_rc[0:0] + end + attribute \src "libresoc.v:49066.7-49066.29" + process $proc$libresoc.v:49066$2198 + assign { } { } + assign $1\core_core_rc_ok[0:0] 1'0 + sync always + sync init + update \core_core_rc_ok $1\core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:49070.14-49070.43" + process $proc$libresoc.v:49070$2199 + assign { } { } + assign $1\core_core_trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \core_core_trapaddr $1\core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:49074.13-49074.39" + process $proc$libresoc.v:49074$2200 + assign { } { } + assign $1\core_core_traptype[7:0] 8'00000000 + sync always + sync init + update \core_core_traptype $1\core_core_traptype[7:0] + end + attribute \src "libresoc.v:49080.13-49080.31" + process $proc$libresoc.v:49080$2201 + assign { } { } + assign $1\core_cr_in1[2:0] 3'000 + sync always + sync init + update \core_cr_in1 $1\core_cr_in1[2:0] + end + attribute \src "libresoc.v:49084.7-49084.28" + process $proc$libresoc.v:49084$2202 + assign { } { } + assign $1\core_cr_in1_ok[0:0] 1'0 + sync always + sync init + update \core_cr_in1_ok $1\core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:49088.13-49088.31" + process $proc$libresoc.v:49088$2203 + assign { } { } + assign $1\core_cr_in2[2:0] 3'000 + sync always + sync init + update \core_cr_in2 $1\core_cr_in2[2:0] + end + attribute \src "libresoc.v:49090.13-49090.36" + process $proc$libresoc.v:49090$2204 + assign { } { } + assign $0\core_cr_in2$48[2:0]$2205 3'000 + sync always + sync init + update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$2205 + end + attribute \src "libresoc.v:49096.7-49096.28" + process $proc$libresoc.v:49096$2206 + assign { } { } + assign $1\core_cr_in2_ok[0:0] 1'0 + sync always + sync init + update \core_cr_in2_ok $1\core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:49098.7-49098.33" + process $proc$libresoc.v:49098$2207 + assign { } { } + assign $0\core_cr_in2_ok$49[0:0]$2208 1'0 + sync always + sync init + update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$2208 + end + attribute \src "libresoc.v:49104.13-49104.31" + process $proc$libresoc.v:49104$2209 + assign { } { } + assign $1\core_cr_out[2:0] 3'000 + sync always + sync init + update \core_cr_out $1\core_cr_out[2:0] + end + attribute \src "libresoc.v:49108.7-49108.28" + process $proc$libresoc.v:49108$2210 + assign { } { } + assign $1\core_cr_out_ok[0:0] 1'0 + sync always + sync init + update \core_cr_out_ok $1\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:49112.14-49112.45" + process $proc$libresoc.v:49112$2211 + assign { } { } + assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_dec $1\core_dec[63:0] + end + attribute \src "libresoc.v:49116.13-49116.28" + process $proc$libresoc.v:49116$2212 + assign { } { } + assign $1\core_ea[4:0] 5'00000 + sync always + sync init + update \core_ea $1\core_ea[4:0] + end + attribute \src "libresoc.v:49120.7-49120.24" + process $proc$libresoc.v:49120$2213 + assign { } { } + assign $1\core_ea_ok[0:0] 1'0 + sync always + sync init + update \core_ea_ok $1\core_ea_ok[0:0] + end + attribute \src "libresoc.v:49124.7-49124.23" + process $proc$libresoc.v:49124$2214 + assign { } { } + assign $1\core_eint[0:0] 1'0 + sync always + sync init + update \core_eint $1\core_eint[0:0] + end + attribute \src "libresoc.v:49128.13-49128.30" + process $proc$libresoc.v:49128$2215 + assign { } { } + assign $1\core_fast1[2:0] 3'000 + sync always + sync init + update \core_fast1 $1\core_fast1[2:0] + end + attribute \src "libresoc.v:49132.7-49132.27" + process $proc$libresoc.v:49132$2216 + assign { } { } + assign $1\core_fast1_ok[0:0] 1'0 + sync always + sync init + update \core_fast1_ok $1\core_fast1_ok[0:0] + end + attribute \src "libresoc.v:49136.13-49136.30" + process $proc$libresoc.v:49136$2217 + assign { } { } + assign $1\core_fast2[2:0] 3'000 + sync always + sync init + update \core_fast2 $1\core_fast2[2:0] + end + attribute \src "libresoc.v:49140.7-49140.27" + process $proc$libresoc.v:49140$2218 + assign { } { } + assign $1\core_fast2_ok[0:0] 1'0 + sync always + sync init + update \core_fast2_ok $1\core_fast2_ok[0:0] + end + attribute \src "libresoc.v:49144.13-49144.31" + process $proc$libresoc.v:49144$2219 + assign { } { } + assign $1\core_fasto1[2:0] 3'000 + sync always + sync init + update \core_fasto1 $1\core_fasto1[2:0] + end + attribute \src "libresoc.v:49148.7-49148.28" + process $proc$libresoc.v:49148$2220 + assign { } { } + assign $1\core_fasto1_ok[0:0] 1'0 + sync always + sync init + update \core_fasto1_ok $1\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:49152.13-49152.31" + process $proc$libresoc.v:49152$2221 + assign { } { } + assign $1\core_fasto2[2:0] 3'000 + sync always + sync init + update \core_fasto2 $1\core_fasto2[2:0] + end + attribute \src "libresoc.v:49156.7-49156.28" + process $proc$libresoc.v:49156$2222 + assign { } { } + assign $1\core_fasto2_ok[0:0] 1'0 + sync always + sync init + update \core_fasto2_ok $1\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:49160.14-49160.45" + process $proc$libresoc.v:49160$2223 + assign { } { } + assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_msr $1\core_msr[63:0] + end + attribute \src "libresoc.v:49164.14-49164.44" + process $proc$libresoc.v:49164$2224 + assign { } { } + assign $1\core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_pc $1\core_pc[63:0] + end + attribute \src "libresoc.v:49168.13-49168.30" + process $proc$libresoc.v:49168$2225 + assign { } { } + assign $1\core_reg1[4:0] 5'00000 + sync always + sync init + update \core_reg1 $1\core_reg1[4:0] + end + attribute \src "libresoc.v:49172.7-49172.26" + process $proc$libresoc.v:49172$2226 + assign { } { } + assign $1\core_reg1_ok[0:0] 1'0 + sync always + sync init + update \core_reg1_ok $1\core_reg1_ok[0:0] + end + attribute \src "libresoc.v:49176.13-49176.30" + process $proc$libresoc.v:49176$2227 + assign { } { } + assign $1\core_reg2[4:0] 5'00000 + sync always + sync init + update \core_reg2 $1\core_reg2[4:0] + end + attribute \src "libresoc.v:49180.7-49180.26" + process $proc$libresoc.v:49180$2228 + assign { } { } + assign $1\core_reg2_ok[0:0] 1'0 + sync always + sync init + update \core_reg2_ok $1\core_reg2_ok[0:0] + end + attribute \src "libresoc.v:49184.13-49184.30" + process $proc$libresoc.v:49184$2229 + assign { } { } + assign $1\core_reg3[4:0] 5'00000 + sync always + sync init + update \core_reg3 $1\core_reg3[4:0] + end + attribute \src "libresoc.v:49188.7-49188.26" + process $proc$libresoc.v:49188$2230 + assign { } { } + assign $1\core_reg3_ok[0:0] 1'0 + sync always + sync init + update \core_reg3_ok $1\core_reg3_ok[0:0] + end + attribute \src "libresoc.v:49192.13-49192.30" + process $proc$libresoc.v:49192$2231 + assign { } { } + assign $1\core_rego[4:0] 5'00000 + sync always + sync init + update \core_rego $1\core_rego[4:0] + end + attribute \src "libresoc.v:49196.7-49196.26" + process $proc$libresoc.v:49196$2232 + assign { } { } + assign $1\core_rego_ok[0:0] 1'0 + sync always + sync init + update \core_rego_ok $1\core_rego_ok[0:0] + end + attribute \src "libresoc.v:49311.13-49311.32" + process $proc$libresoc.v:49311$2233 + assign { } { } + assign $1\core_spr1[9:0] 10'0000000000 + sync always + sync init + update \core_spr1 $1\core_spr1[9:0] + end + attribute \src "libresoc.v:49315.7-49315.26" + process $proc$libresoc.v:49315$2234 + assign { } { } + assign $1\core_spr1_ok[0:0] 1'0 + sync always + sync init + update \core_spr1_ok $1\core_spr1_ok[0:0] + end + attribute \src "libresoc.v:49430.13-49430.32" + process $proc$libresoc.v:49430$2235 + assign { } { } + assign $1\core_spro[9:0] 10'0000000000 + sync always + sync init + update \core_spro $1\core_spro[9:0] + end + attribute \src "libresoc.v:49434.7-49434.26" + process $proc$libresoc.v:49434$2236 + assign { } { } + assign $1\core_spro_ok[0:0] 1'0 + sync always + sync init + update \core_spro_ok $1\core_spro_ok[0:0] + end + attribute \src "libresoc.v:49442.13-49442.31" + process $proc$libresoc.v:49442$2237 + assign { } { } + assign $1\core_xer_in[2:0] 3'000 + sync always + sync init + update \core_xer_in $1\core_xer_in[2:0] + end + attribute \src "libresoc.v:49446.7-49446.26" + process $proc$libresoc.v:49446$2238 + assign { } { } + assign $1\core_xer_out[0:0] 1'0 + sync always + sync init + update \core_xer_out $1\core_xer_out[0:0] + end + attribute \src "libresoc.v:49462.7-49462.30" + process $proc$libresoc.v:49462$2239 + assign { } { } + assign $1\cu_st__rel_o_dly[0:0] 1'0 + sync always + sync init + update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:49468.7-49468.24" + process $proc$libresoc.v:49468$2240 + assign { } { } + assign $1\d_cr_delay[0:0] 1'0 + sync always + sync init + update \d_cr_delay $1\d_cr_delay[0:0] + end + attribute \src "libresoc.v:49472.7-49472.25" + process $proc$libresoc.v:49472$2241 + assign { } { } + assign $1\d_reg_delay[0:0] 1'0 + sync always + sync init + update \d_reg_delay $1\d_reg_delay[0:0] + end + attribute \src "libresoc.v:49476.7-49476.25" + process $proc$libresoc.v:49476$2242 + assign { } { } + assign $1\d_xer_delay[0:0] 1'0 + sync always + sync init + update \d_xer_delay $1\d_xer_delay[0:0] + end + attribute \src "libresoc.v:49514.13-49514.34" + process $proc$libresoc.v:49514$2243 + assign { } { } + assign $1\dbg_dmi_addr_i[3:0] 4'0000 + sync always + sync init + update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:49518.14-49518.48" + process $proc$libresoc.v:49518$2244 + assign { } { } + assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbg_dmi_din $1\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:49524.7-49524.27" + process $proc$libresoc.v:49524$2245 + assign { } { } + assign $1\dbg_dmi_req_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:49528.7-49528.26" + process $proc$libresoc.v:49528$2246 + assign { } { } + assign $1\dbg_dmi_we_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:49564.14-49564.49" + process $proc$libresoc.v:49564$2247 + assign { } { } + assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_dec $1\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:49568.7-49568.27" + process $proc$libresoc.v:49568$2248 + assign { } { } + assign $1\dec2_cur_eint[0:0] 1'0 + sync always + sync init + update \dec2_cur_eint $1\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:49572.14-49572.49" + process $proc$libresoc.v:49572$2249 + assign { } { } + assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_msr $1\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:49576.14-49576.48" + process $proc$libresoc.v:49576$2250 + assign { } { } + assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_pc $1\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:49985.13-49985.25" + process $proc$libresoc.v:49985$2251 + assign { } { } + assign $1\delay[1:0] 2'11 + sync always + sync init + update \delay $1\delay[1:0] + end + attribute \src "libresoc.v:50007.13-50007.29" + process $proc$libresoc.v:50007$2252 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "libresoc.v:50009.13-50009.35" + process $proc$libresoc.v:50009$2253 + assign { } { } + assign $0\fsm_state$131[1:0]$2254 2'00 + sync always + sync init + update \fsm_state$131 $0\fsm_state$131[1:0]$2254 + end + attribute \src "libresoc.v:50259.14-50259.28" + process $proc$libresoc.v:50259$2255 + assign { } { } + assign $1\ilatch[31:0] 0 + sync always + sync init + update \ilatch $1\ilatch[31:0] + end + attribute \src "libresoc.v:50293.7-50293.30" + process $proc$libresoc.v:50293$2256 + assign { } { } + assign $1\jtag_dmi0__ack_o[0:0] 1'0 + sync always + sync init + update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] + end + attribute \src "libresoc.v:50301.14-50301.52" + process $proc$libresoc.v:50301$2257 + assign { } { } + assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] + end + attribute \src "libresoc.v:50361.7-50361.22" + process $proc$libresoc.v:50361$2258 + assign { } { } + assign $1\msr_read[0:0] 1'1 + sync always + sync init + update \msr_read $1\msr_read[0:0] + end + attribute \src "libresoc.v:50389.7-50389.24" + process $proc$libresoc.v:50389$2259 + assign { } { } + assign $1\pc_changed[0:0] 1'0 + sync always + sync init + update \pc_changed $1\pc_changed[0:0] + end + attribute \src "libresoc.v:50399.7-50399.25" + process $proc$libresoc.v:50399$2260 + assign { } { } + assign $1\pc_ok_delay[0:0] 1'0 + sync always + sync init + update \pc_ok_delay $1\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:50413.14-50413.32" + process $proc$libresoc.v:50413$2261 + assign { } { } + assign $1\raw_insn_i[31:0] 0 + sync always + sync init + update \raw_insn_i $1\raw_insn_i[31:0] + end + attribute \src "libresoc.v:50847.3-50848.41" + process $proc$libresoc.v:50847$1665 + assign { } { } + assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next + sync posedge \clk + update \dec2_cur_dec $0\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:50849.3-50850.33" + process $proc$libresoc.v:50849$1666 + assign { } { } + assign $0\core_dec[63:0] \core_dec$next + sync posedge \clk + update \core_dec $0\core_dec[63:0] + end + attribute \src "libresoc.v:50851.3-50852.41" + process $proc$libresoc.v:50851$1667 + assign { } { } + assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next + sync posedge \clk + update \dec2_cur_msr $0\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:50853.3-50854.35" + process $proc$libresoc.v:50853$1668 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:50855.3-50856.33" + process $proc$libresoc.v:50855$1669 + assign { } { } + assign $0\msr_read[0:0] \msr_read$next + sync posedge \clk + update \msr_read $0\msr_read[0:0] + end + attribute \src "libresoc.v:50857.3-50858.39" + process $proc$libresoc.v:50857$1670 + assign { } { } + assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next + sync posedge \clk + update \dec2_cur_pc $0\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:50859.3-50860.39" + process $proc$libresoc.v:50859$1671 + assign { } { } + assign $0\bigendian_i[0:0] \bigendian_i$next + sync posedge \clk + update \bigendian_i $0\bigendian_i[0:0] + end + attribute \src "libresoc.v:50861.3-50862.37" + process $proc$libresoc.v:50861$1672 + assign { } { } + assign $0\raw_insn_i[31:0] \raw_insn_i$next + sync posedge \clk + update \raw_insn_i $0\raw_insn_i[31:0] + end + attribute \src "libresoc.v:50863.3-50864.41" + process $proc$libresoc.v:50863$1673 + assign { } { } + assign $0\core_asmcode[7:0] \core_asmcode$next + sync posedge \clk + update \core_asmcode $0\core_asmcode[7:0] + end + attribute \src "libresoc.v:50865.3-50866.35" + process $proc$libresoc.v:50865$1674 + assign { } { } + assign $0\core_rego[4:0] \core_rego$next + sync posedge \clk + update \core_rego $0\core_rego[4:0] + end + attribute \src "libresoc.v:50867.3-50868.41" + process $proc$libresoc.v:50867$1675 + assign { } { } + assign $0\core_rego_ok[0:0] \core_rego_ok$next + sync posedge \clk + update \core_rego_ok $0\core_rego_ok[0:0] + end + attribute \src "libresoc.v:50869.3-50870.45" + process $proc$libresoc.v:50869$1676 + assign { } { } + assign $0\fsm_state$131[1:0]$1677 \fsm_state$131$next + sync posedge \clk + update \fsm_state$131 $0\fsm_state$131[1:0]$1677 + end + attribute \src "libresoc.v:50871.3-50872.31" + process $proc$libresoc.v:50871$1678 + assign { } { } + assign $0\core_ea[4:0] \core_ea$next + sync posedge \clk + update \core_ea $0\core_ea[4:0] + end + attribute \src "libresoc.v:50873.3-50874.37" + process $proc$libresoc.v:50873$1679 + assign { } { } + assign $0\core_ea_ok[0:0] \core_ea_ok$next + sync posedge \clk + update \core_ea_ok $0\core_ea_ok[0:0] + end + attribute \src "libresoc.v:50875.3-50876.35" + process $proc$libresoc.v:50875$1680 + assign { } { } + assign $0\core_reg1[4:0] \core_reg1$next + sync posedge \clk + update \core_reg1 $0\core_reg1[4:0] + end + attribute \src "libresoc.v:50877.3-50878.41" + process $proc$libresoc.v:50877$1681 + assign { } { } + assign $0\core_reg1_ok[0:0] \core_reg1_ok$next + sync posedge \clk + update \core_reg1_ok $0\core_reg1_ok[0:0] + end + attribute \src "libresoc.v:50879.3-50880.35" + process $proc$libresoc.v:50879$1682 + assign { } { } + assign $0\core_reg2[4:0] \core_reg2$next + sync posedge \clk + update \core_reg2 $0\core_reg2[4:0] + end + attribute \src "libresoc.v:50881.3-50882.41" + process $proc$libresoc.v:50881$1683 + assign { } { } + assign $0\core_reg2_ok[0:0] \core_reg2_ok$next + sync posedge \clk + update \core_reg2_ok $0\core_reg2_ok[0:0] + end + attribute \src "libresoc.v:50883.3-50884.35" + process $proc$libresoc.v:50883$1684 + assign { } { } + assign $0\core_reg3[4:0] \core_reg3$next + sync posedge \clk + update \core_reg3 $0\core_reg3[4:0] + end + attribute \src "libresoc.v:50885.3-50886.41" + process $proc$libresoc.v:50885$1685 + assign { } { } + assign $0\core_reg3_ok[0:0] \core_reg3_ok$next + sync posedge \clk + update \core_reg3_ok $0\core_reg3_ok[0:0] + end + attribute \src "libresoc.v:50887.3-50888.35" + process $proc$libresoc.v:50887$1686 + assign { } { } + assign $0\core_spro[9:0] \core_spro$next + sync posedge \clk + update \core_spro $0\core_spro[9:0] + end + attribute \src "libresoc.v:50889.3-50890.41" + process $proc$libresoc.v:50889$1687 + assign { } { } + assign $0\core_spro_ok[0:0] \core_spro_ok$next + sync posedge \clk + update \core_spro_ok $0\core_spro_ok[0:0] + end + attribute \src "libresoc.v:50891.3-50892.39" + process $proc$libresoc.v:50891$1688 + assign { } { } + assign $0\d_xer_delay[0:0] \d_xer_delay$next + sync posedge \clk + update \d_xer_delay $0\d_xer_delay[0:0] + end + attribute \src "libresoc.v:50893.3-50894.35" + process $proc$libresoc.v:50893$1689 + assign { } { } + assign $0\core_spr1[9:0] \core_spr1$next + sync posedge \clk + update \core_spr1 $0\core_spr1[9:0] + end + attribute \src "libresoc.v:50895.3-50896.41" + process $proc$libresoc.v:50895$1690 + assign { } { } + assign $0\core_spr1_ok[0:0] \core_spr1_ok$next + sync posedge \clk + update \core_spr1_ok $0\core_spr1_ok[0:0] + end + attribute \src "libresoc.v:50897.3-50898.39" + process $proc$libresoc.v:50897$1691 + assign { } { } + assign $0\core_xer_in[2:0] \core_xer_in$next + sync posedge \clk + update \core_xer_in $0\core_xer_in[2:0] + end + attribute \src "libresoc.v:50899.3-50900.41" + process $proc$libresoc.v:50899$1692 + assign { } { } + assign $0\core_xer_out[0:0] \core_xer_out$next + sync posedge \clk + update \core_xer_out $0\core_xer_out[0:0] + end + attribute \src "libresoc.v:50901.3-50902.37" + process $proc$libresoc.v:50901$1693 + assign { } { } + assign $0\core_fast1[2:0] \core_fast1$next + sync posedge \clk + update \core_fast1 $0\core_fast1[2:0] + end + attribute \src "libresoc.v:50903.3-50904.43" + process $proc$libresoc.v:50903$1694 + assign { } { } + assign $0\core_fast1_ok[0:0] \core_fast1_ok$next + sync posedge \clk + update \core_fast1_ok $0\core_fast1_ok[0:0] + end + attribute \src "libresoc.v:50905.3-50906.37" + process $proc$libresoc.v:50905$1695 + assign { } { } + assign $0\core_fast2[2:0] \core_fast2$next + sync posedge \clk + update \core_fast2 $0\core_fast2[2:0] + end + attribute \src "libresoc.v:50907.3-50908.43" + process $proc$libresoc.v:50907$1696 + assign { } { } + assign $0\core_fast2_ok[0:0] \core_fast2_ok$next + sync posedge \clk + update \core_fast2_ok $0\core_fast2_ok[0:0] + end + attribute \src "libresoc.v:50909.3-50910.39" + process $proc$libresoc.v:50909$1697 + assign { } { } + assign $0\core_fasto1[2:0] \core_fasto1$next + sync posedge \clk + update \core_fasto1 $0\core_fasto1[2:0] + end + attribute \src "libresoc.v:50911.3-50912.45" + process $proc$libresoc.v:50911$1698 + assign { } { } + assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next + sync posedge \clk + update \core_fasto1_ok $0\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:50913.3-50914.37" + process $proc$libresoc.v:50913$1699 + assign { } { } + assign $0\d_cr_delay[0:0] \d_cr_delay$next + sync posedge \clk + update \d_cr_delay $0\d_cr_delay[0:0] + end + attribute \src "libresoc.v:50915.3-50916.39" + process $proc$libresoc.v:50915$1700 + assign { } { } + assign $0\core_fasto2[2:0] \core_fasto2$next + sync posedge \clk + update \core_fasto2 $0\core_fasto2[2:0] + end + attribute \src "libresoc.v:50917.3-50918.45" + process $proc$libresoc.v:50917$1701 + assign { } { } + assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next + sync posedge \clk + update \core_fasto2_ok $0\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:50919.3-50920.39" + process $proc$libresoc.v:50919$1702 + assign { } { } + assign $0\core_cr_in1[2:0] \core_cr_in1$next + sync posedge \clk + update \core_cr_in1 $0\core_cr_in1[2:0] + end + attribute \src "libresoc.v:50921.3-50922.45" + process $proc$libresoc.v:50921$1703 + assign { } { } + assign $0\core_cr_in1_ok[0:0] \core_cr_in1_ok$next + sync posedge \clk + update \core_cr_in1_ok $0\core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:50923.3-50924.39" + process $proc$libresoc.v:50923$1704 + assign { } { } + assign $0\core_cr_in2[2:0] \core_cr_in2$next + sync posedge \clk + update \core_cr_in2 $0\core_cr_in2[2:0] + end + attribute \src "libresoc.v:50925.3-50926.45" + process $proc$libresoc.v:50925$1705 + assign { } { } + assign $0\core_cr_in2_ok[0:0] \core_cr_in2_ok$next + sync posedge \clk + update \core_cr_in2_ok $0\core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:50927.3-50928.47" + process $proc$libresoc.v:50927$1706 + assign { } { } + assign $0\core_cr_in2$48[2:0]$1707 \core_cr_in2$48$next + sync posedge \clk + update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$1707 + end + attribute \src "libresoc.v:50929.3-50930.53" + process $proc$libresoc.v:50929$1708 + assign { } { } + assign $0\core_cr_in2_ok$49[0:0]$1709 \core_cr_in2_ok$49$next + sync posedge \clk + update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$1709 + end + attribute \src "libresoc.v:50931.3-50932.39" + process $proc$libresoc.v:50931$1710 + assign { } { } + assign $0\core_cr_out[2:0] \core_cr_out$next + sync posedge \clk + update \core_cr_out $0\core_cr_out[2:0] + end + attribute \src "libresoc.v:50933.3-50934.45" + process $proc$libresoc.v:50933$1711 + assign { } { } + assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next + sync posedge \clk + update \core_cr_out_ok $0\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:50935.3-50936.39" + process $proc$libresoc.v:50935$1712 + assign { } { } + assign $0\d_reg_delay[0:0] \d_reg_delay$next + sync posedge \clk + update \d_reg_delay $0\d_reg_delay[0:0] + end + attribute \src "libresoc.v:50937.3-50938.43" + process $proc$libresoc.v:50937$1713 + assign { } { } + assign $0\core_core_msr[63:0] \core_core_msr$next + sync posedge \clk + update \core_core_msr $0\core_core_msr[63:0] + end + attribute \src "libresoc.v:50939.3-50940.43" + process $proc$libresoc.v:50939$1714 + assign { } { } + assign $0\core_core_cia[63:0] \core_core_cia$next + sync posedge \clk + update \core_core_cia $0\core_core_cia[63:0] + end + attribute \src "libresoc.v:50941.3-50942.45" + process $proc$libresoc.v:50941$1715 + assign { } { } + assign $0\core_core_insn[31:0] \core_core_insn$next + sync posedge \clk + update \core_core_insn $0\core_core_insn[31:0] + end + attribute \src "libresoc.v:50943.3-50944.55" + process $proc$libresoc.v:50943$1716 + assign { } { } + assign $0\core_core_insn_type[6:0] \core_core_insn_type$next + sync posedge \clk + update \core_core_insn_type $0\core_core_insn_type[6:0] + end + attribute \src "libresoc.v:50945.3-50946.51" + process $proc$libresoc.v:50945$1717 + assign { } { } + assign $0\core_core_fn_unit[11:0] \core_core_fn_unit$next + sync posedge \clk + update \core_core_fn_unit $0\core_core_fn_unit[11:0] + end + attribute \src "libresoc.v:50947.3-50948.41" + process $proc$libresoc.v:50947$1718 + assign { } { } + assign $0\core_core_lk[0:0] \core_core_lk$next + sync posedge \clk + update \core_core_lk $0\core_core_lk[0:0] + end + attribute \src "libresoc.v:50949.3-50950.41" + process $proc$libresoc.v:50949$1719 + assign { } { } + assign $0\core_core_rc[0:0] \core_core_rc$next + sync posedge \clk + update \core_core_rc $0\core_core_rc[0:0] + end + attribute \src "libresoc.v:50951.3-50952.47" + process $proc$libresoc.v:50951$1720 + assign { } { } + assign $0\core_core_rc_ok[0:0] \core_core_rc_ok$next + sync posedge \clk + update \core_core_rc_ok $0\core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:50953.3-50954.41" + process $proc$libresoc.v:50953$1721 + assign { } { } + assign $0\core_core_oe[0:0] \core_core_oe$next + sync posedge \clk + update \core_core_oe $0\core_core_oe[0:0] + end + attribute \src "libresoc.v:50955.3-50956.47" + process $proc$libresoc.v:50955$1722 + assign { } { } + assign $0\core_core_oe_ok[0:0] \core_core_oe_ok$next + sync posedge \clk + update \core_core_oe_ok $0\core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:50957.3-50958.29" + process $proc$libresoc.v:50957$1723 + assign { } { } + assign $0\ilatch[31:0] \ilatch$next + sync posedge \clk + update \ilatch $0\ilatch[31:0] + end + attribute \src "libresoc.v:50959.3-50960.59" + process $proc$libresoc.v:50959$1724 + assign { } { } + assign $0\core_core_input_carry[1:0] \core_core_input_carry$next + sync posedge \clk + update \core_core_input_carry $0\core_core_input_carry[1:0] + end + attribute \src "libresoc.v:50961.3-50962.53" + process $proc$libresoc.v:50961$1725 + assign { } { } + assign $0\core_core_traptype[7:0] \core_core_traptype$next + sync posedge \clk + update \core_core_traptype $0\core_core_traptype[7:0] + end + attribute \src "libresoc.v:50963.3-50964.61" + process $proc$libresoc.v:50963$1726 + assign { } { } + assign $0\core_core_exc_$signal[0:0]$1727 \core_core_exc_$signal$next + sync posedge \clk + update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$1727 + end + attribute \src "libresoc.v:50965.3-50966.67" + process $proc$libresoc.v:50965$1728 + assign { } { } + assign $0\core_core_exc_$signal$50[0:0]$1729 \core_core_exc_$signal$50$next + sync posedge \clk + update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$1729 + end + attribute \src "libresoc.v:50967.3-50968.67" + process $proc$libresoc.v:50967$1730 + assign { } { } + assign $0\core_core_exc_$signal$51[0:0]$1731 \core_core_exc_$signal$51$next + sync posedge \clk + update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$1731 + end + attribute \src "libresoc.v:50969.3-50970.67" + process $proc$libresoc.v:50969$1732 + assign { } { } + assign $0\core_core_exc_$signal$52[0:0]$1733 \core_core_exc_$signal$52$next + sync posedge \clk + update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$1733 + end + attribute \src "libresoc.v:50971.3-50972.67" + process $proc$libresoc.v:50971$1734 + assign { } { } + assign $0\core_core_exc_$signal$53[0:0]$1735 \core_core_exc_$signal$53$next + sync posedge \clk + update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$1735 + end + attribute \src "libresoc.v:50973.3-50974.67" + process $proc$libresoc.v:50973$1736 + assign { } { } + assign $0\core_core_exc_$signal$54[0:0]$1737 \core_core_exc_$signal$54$next + sync posedge \clk + update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$1737 + end + attribute \src "libresoc.v:50975.3-50976.67" + process $proc$libresoc.v:50975$1738 + assign { } { } + assign $0\core_core_exc_$signal$55[0:0]$1739 \core_core_exc_$signal$55$next + sync posedge \clk + update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$1739 + end + attribute \src "libresoc.v:50977.3-50978.67" + process $proc$libresoc.v:50977$1740 + assign { } { } + assign $0\core_core_exc_$signal$56[0:0]$1741 \core_core_exc_$signal$56$next + sync posedge \clk + update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$1741 + end + attribute \src "libresoc.v:50979.3-50980.31" + process $proc$libresoc.v:50979$1742 + assign { } { } + assign $0\core_pc[63:0] \core_pc$next + sync posedge \clk + update \core_pc $0\core_pc[63:0] + end + attribute \src "libresoc.v:50981.3-50982.53" + process $proc$libresoc.v:50981$1743 + assign { } { } + assign $0\core_core_trapaddr[12:0] \core_core_trapaddr$next + sync posedge \clk + update \core_core_trapaddr $0\core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:50983.3-50984.47" + process $proc$libresoc.v:50983$1744 + assign { } { } + assign $0\core_core_cr_rd[7:0] \core_core_cr_rd$next + sync posedge \clk + update \core_core_cr_rd $0\core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:50985.3-50986.53" + process $proc$libresoc.v:50985$1745 + assign { } { } + assign $0\core_core_cr_rd_ok[0:0] \core_core_cr_rd_ok$next + sync posedge \clk + update \core_core_cr_rd_ok $0\core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:50987.3-50988.47" + process $proc$libresoc.v:50987$1746 + assign { } { } + assign $0\core_core_cr_wr[7:0] \core_core_cr_wr$next + sync posedge \clk + update \core_core_cr_wr $0\core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:50989.3-50990.53" + process $proc$libresoc.v:50989$1747 + assign { } { } + assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next + sync posedge \clk + update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:50991.3-50992.53" + process $proc$libresoc.v:50991$1748 + assign { } { } + assign $0\core_core_is_32bit[0:0] \core_core_is_32bit$next + sync posedge \clk + update \core_core_is_32bit $0\core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:50993.3-50994.37" + process $proc$libresoc.v:50993$1749 + assign { } { } + assign $0\pc_changed[0:0] \pc_changed$next + sync posedge \clk + update \pc_changed $0\pc_changed[0:0] + end + attribute \src "libresoc.v:50995.3-50996.39" + process $proc$libresoc.v:50995$1750 + assign { } { } + assign $0\pc_ok_delay[0:0] \pc_ok_delay$next + sync posedge \clk + update \pc_ok_delay $0\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:50997.3-50998.30" + process $proc$libresoc.v:50997$1751 + assign { } { } + assign $0\cu_st__rel_o_dly[0:0] 1'0 + sync posedge \clk + update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:50999.3-51000.27" + process $proc$libresoc.v:50999$1752 + assign { } { } + assign $0\delay[1:0] \delay$next + sync posedge \por_clk + update \delay $0\delay[1:0] + end + attribute \src "libresoc.v:51001.3-51002.33" + process $proc$libresoc.v:51001$1753 + assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "libresoc.v:51003.3-51004.43" + process $proc$libresoc.v:51003$1754 + assign { } { } + assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next + sync posedge \clk + update \dec2_cur_eint $0\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:51005.3-51006.47" + process $proc$libresoc.v:51005$1755 + assign { } { } + assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next + sync posedge \clk + update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] + end + attribute \src "libresoc.v:51007.3-51008.49" + process $proc$libresoc.v:51007$1756 + assign { } { } + assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next + sync posedge \clk + update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] + end + attribute \src "libresoc.v:51009.3-51010.39" + process $proc$libresoc.v:51009$1757 + assign { } { } + assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next + sync posedge \clk + update \dbg_dmi_din $0\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:51011.3-51012.41" + process $proc$libresoc.v:51011$1758 + assign { } { } + assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next + sync posedge \clk + update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:51013.3-51014.43" + process $proc$libresoc.v:51013$1759 + assign { } { } + assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next + sync posedge \clk + update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:51015.3-51016.45" + process $proc$libresoc.v:51015$1760 + assign { } { } + assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next + sync posedge \clk + update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:51017.3-51018.35" + process $proc$libresoc.v:51017$1761 + assign { } { } + assign $0\core_eint[0:0] \core_eint$next + sync posedge \clk + update \core_eint $0\core_eint[0:0] + end + attribute \src "libresoc.v:51493.3-51501.6" + process $proc$libresoc.v:51493$1762 + assign { } { } + assign { } { } + assign $0\dbg_dmi_addr_i$next[3:0]$1763 $1\dbg_dmi_addr_i$next[3:0]$1764 + attribute \src "libresoc.v:51494.5-51494.29" + switch \initial + attribute \src "libresoc.v:51494.9-51494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_addr_i$next[3:0]$1764 4'0000 + case + assign $1\dbg_dmi_addr_i$next[3:0]$1764 \jtag_dmi0__addr_i + end + sync always + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1763 + end + attribute \src "libresoc.v:51502.3-51510.6" + process $proc$libresoc.v:51502$1765 + assign { } { } + assign { } { } + assign $0\dbg_dmi_req_i$next[0:0]$1766 $1\dbg_dmi_req_i$next[0:0]$1767 + attribute \src "libresoc.v:51503.5-51503.29" + switch \initial + attribute \src "libresoc.v:51503.9-51503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_req_i$next[0:0]$1767 1'0 + case + assign $1\dbg_dmi_req_i$next[0:0]$1767 \jtag_dmi0__req_i + end + sync always + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1766 + end + attribute \src "libresoc.v:51511.3-51531.6" + process $proc$libresoc.v:51511$1768 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_msr$next[63:0]$1769 $3\dec2_cur_msr$next[63:0]$1772 + attribute \src "libresoc.v:51512.5-51512.29" + switch \initial + attribute \src "libresoc.v:51512.9-51512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_msr$next[63:0]$1770 $2\dec2_cur_msr$next[63:0]$1771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$1771 \msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$1771 \dec2_cur_msr + end + case + assign $1\dec2_cur_msr$next[63:0]$1770 \dec2_cur_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_msr$next[63:0]$1772 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_msr$next[63:0]$1772 $1\dec2_cur_msr$next[63:0]$1770 + end + sync always + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1769 + end + attribute \src "libresoc.v:51532.3-51550.6" + process $proc$libresoc.v:51532$1773 + assign { } { } + assign { } { } + assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:51533.5-51533.29" + switch \initial + attribute \src "libresoc.v:51533.9-51533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dec2_raw_opcode_in[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dec2_raw_opcode_in[31:0] \$117 + end + case + assign $1\dec2_raw_opcode_in[31:0] 0 + end + sync always + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + end + attribute \src "libresoc.v:51551.3-51582.6" + process $proc$libresoc.v:51551$1774 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_dec$next[63:0]$1775 $3\core_dec$next[63:0]$1787 + assign $0\core_eint$next[0:0]$1776 $3\core_eint$next[0:0]$1788 + assign $0\core_msr$next[63:0]$1777 $3\core_msr$next[63:0]$1789 + assign $0\core_pc$next[63:0]$1778 $3\core_pc$next[63:0]$1790 + attribute \src "libresoc.v:51552.5-51552.29" + switch \initial + attribute \src "libresoc.v:51552.9-51552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_dec$next[63:0]$1779 $2\core_dec$next[63:0]$1783 + assign $1\core_eint$next[0:0]$1780 $2\core_eint$next[0:0]$1784 + assign $1\core_msr$next[63:0]$1781 $2\core_msr$next[63:0]$1785 + assign $1\core_pc$next[63:0]$1782 $2\core_pc$next[63:0]$1786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_dec$next[63:0]$1783 \core_dec + assign $2\core_eint$next[0:0]$1784 \core_eint + assign $2\core_msr$next[63:0]$1785 \core_msr + assign $2\core_pc$next[63:0]$1786 \core_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_dec$next[63:0]$1783 $2\core_eint$next[0:0]$1784 $2\core_msr$next[63:0]$1785 $2\core_pc$next[63:0]$1786 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + end + case + assign $1\core_dec$next[63:0]$1779 \core_dec + assign $1\core_eint$next[0:0]$1780 \core_eint + assign $1\core_msr$next[63:0]$1781 \core_msr + assign $1\core_pc$next[63:0]$1782 \core_pc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\core_pc$next[63:0]$1790 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$1789 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$1788 1'0 + assign $3\core_dec$next[63:0]$1787 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_dec$next[63:0]$1787 $1\core_dec$next[63:0]$1779 + assign $3\core_eint$next[0:0]$1788 $1\core_eint$next[0:0]$1780 + assign $3\core_msr$next[63:0]$1789 $1\core_msr$next[63:0]$1781 + assign $3\core_pc$next[63:0]$1790 $1\core_pc$next[63:0]$1782 + end + sync always + update \core_dec$next $0\core_dec$next[63:0]$1775 + update \core_eint$next $0\core_eint$next[0:0]$1776 + update \core_msr$next $0\core_msr$next[63:0]$1777 + update \core_pc$next $0\core_pc$next[63:0]$1778 + end + attribute \src "libresoc.v:51583.3-51606.6" + process $proc$libresoc.v:51583$1791 + assign { } { } + assign { } { } + assign { } { } + assign $0\ilatch$next[31:0]$1792 $3\ilatch$next[31:0]$1795 + attribute \src "libresoc.v:51584.5-51584.29" + switch \initial + attribute \src "libresoc.v:51584.9-51584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\ilatch$next[31:0]$1793 $2\ilatch$next[31:0]$1794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\ilatch$next[31:0]$1794 \ilatch + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ilatch$next[31:0]$1794 \$121 + end + case + assign $1\ilatch$next[31:0]$1793 \ilatch + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ilatch$next[31:0]$1795 0 + case + assign $3\ilatch$next[31:0]$1795 $1\ilatch$next[31:0]$1793 + end + sync always + update \ilatch$next $0\ilatch$next[31:0]$1792 + end + attribute \src "libresoc.v:51607.3-51626.6" + process $proc$libresoc.v:51607$1796 + assign { } { } + assign { } { } + assign $0\ivalid_i[0:0] $1\ivalid_i[0:0] + attribute \src "libresoc.v:51608.5-51608.29" + switch \initial + attribute \src "libresoc.v:51608.9-51608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\ivalid_i[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\ivalid_i[0:0] $2\ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ivalid_i[0:0] 1'1 + case + assign $2\ivalid_i[0:0] 1'0 + end + case + assign $1\ivalid_i[0:0] 1'0 + end + sync always + update \ivalid_i $0\ivalid_i[0:0] + end + attribute \src "libresoc.v:51627.3-51637.6" + process $proc$libresoc.v:51627$1797 + assign { } { } + assign { } { } + assign $0\issue_i[0:0] $1\issue_i[0:0] + attribute \src "libresoc.v:51628.5-51628.29" + switch \initial + attribute \src "libresoc.v:51628.9-51628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\issue_i[0:0] 1'1 + case + assign $1\issue_i[0:0] 1'0 + end + sync always + update \issue_i $0\issue_i[0:0] + end + attribute \src "libresoc.v:51638.3-51647.6" + process $proc$libresoc.v:51638$1798 + assign { } { } + assign { } { } + assign $0\dmi__addr[4:0] $1\dmi__addr[4:0] + attribute \src "libresoc.v:51639.5-51639.29" + switch \initial + attribute \src "libresoc.v:51639.9-51639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi__addr[4:0] \dbg_d_gpr_addr [4:0] + case + assign $1\dmi__addr[4:0] 5'00000 + end + sync always + update \dmi__addr $0\dmi__addr[4:0] + end + attribute \src "libresoc.v:51648.3-51657.6" + process $proc$libresoc.v:51648$1799 + assign { } { } + assign { } { } + assign $0\dmi__ren[0:0] $1\dmi__ren[0:0] + attribute \src "libresoc.v:51649.5-51649.29" + switch \initial + attribute \src "libresoc.v:51649.9-51649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi__ren[0:0] 1'1 + case + assign $1\dmi__ren[0:0] 1'0 + end + sync always + update \dmi__ren $0\dmi__ren[0:0] + end + attribute \src "libresoc.v:51658.3-51666.6" + process $proc$libresoc.v:51658$1800 + assign { } { } + assign { } { } + assign $0\d_reg_delay$next[0:0]$1801 $1\d_reg_delay$next[0:0]$1802 + attribute \src "libresoc.v:51659.5-51659.29" + switch \initial + attribute \src "libresoc.v:51659.9-51659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_reg_delay$next[0:0]$1802 1'0 + case + assign $1\d_reg_delay$next[0:0]$1802 \dbg_d_gpr_req + end + sync always + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1801 + end + attribute \src "libresoc.v:51667.3-51676.6" + process $proc$libresoc.v:51667$1803 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:51668.5-51668.29" + switch \initial + attribute \src "libresoc.v:51668.9-51668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_data[63:0] \dmi__data_o + case + assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] + end + attribute \src "libresoc.v:51677.3-51686.6" + process $proc$libresoc.v:51677$1804 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:51678.5-51678.29" + switch \initial + attribute \src "libresoc.v:51678.9-51678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_ack[0:0] 1'1 + case + assign $1\dbg_d_gpr_ack[0:0] 1'0 + end + sync always + update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] + end + attribute \src "libresoc.v:51687.3-51696.6" + process $proc$libresoc.v:51687$1805 + assign { } { } + assign { } { } + assign $0\full_rd2__ren[7:0] $1\full_rd2__ren[7:0] + attribute \src "libresoc.v:51688.5-51688.29" + switch \initial + attribute \src "libresoc.v:51688.9-51688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" + switch \dbg_d_cr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\full_rd2__ren[7:0] 8'11111111 + case + assign $1\full_rd2__ren[7:0] 8'00000000 + end + sync always + update \full_rd2__ren $0\full_rd2__ren[7:0] + end + attribute \src "libresoc.v:51697.3-51705.6" + process $proc$libresoc.v:51697$1806 + assign { } { } + assign { } { } + assign $0\d_cr_delay$next[0:0]$1807 $1\d_cr_delay$next[0:0]$1808 + attribute \src "libresoc.v:51698.5-51698.29" + switch \initial + attribute \src "libresoc.v:51698.9-51698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_cr_delay$next[0:0]$1808 1'0 + case + assign $1\d_cr_delay$next[0:0]$1808 \dbg_d_cr_req + end + sync always + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1807 + end + attribute \src "libresoc.v:51706.3-51715.6" + process $proc$libresoc.v:51706$1809 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:51707.5-51707.29" + switch \initial + attribute \src "libresoc.v:51707.9-51707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_data[63:0] \$127 + case + assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] + end + attribute \src "libresoc.v:51716.3-51725.6" + process $proc$libresoc.v:51716$1810 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:51717.5-51717.29" + switch \initial + attribute \src "libresoc.v:51717.9-51717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_ack[0:0] 1'1 + case + assign $1\dbg_d_cr_ack[0:0] 1'0 + end + sync always + update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] + end + attribute \src "libresoc.v:51726.3-51735.6" + process $proc$libresoc.v:51726$1811 + assign { } { } + assign { } { } + assign $0\full_rd__ren[2:0] $1\full_rd__ren[2:0] + attribute \src "libresoc.v:51727.5-51727.29" + switch \initial + attribute \src "libresoc.v:51727.9-51727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + switch \dbg_d_xer_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\full_rd__ren[2:0] 3'111 + case + assign $1\full_rd__ren[2:0] 3'000 + end + sync always + update \full_rd__ren $0\full_rd__ren[2:0] + end + attribute \src "libresoc.v:51736.3-51744.6" + process $proc$libresoc.v:51736$1812 + assign { } { } + assign { } { } + assign $0\d_xer_delay$next[0:0]$1813 $1\d_xer_delay$next[0:0]$1814 + attribute \src "libresoc.v:51737.5-51737.29" + switch \initial + attribute \src "libresoc.v:51737.9-51737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_xer_delay$next[0:0]$1814 1'0 + case + assign $1\d_xer_delay$next[0:0]$1814 \dbg_d_xer_req + end + sync always + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1813 + end + attribute \src "libresoc.v:51745.3-51754.6" + process $proc$libresoc.v:51745$1815 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:51746.5-51746.29" + switch \initial + attribute \src "libresoc.v:51746.9-51746.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_data[63:0] \$129 + case + assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] + end + attribute \src "libresoc.v:51755.3-51764.6" + process $proc$libresoc.v:51755$1816 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:51756.5-51756.29" + switch \initial + attribute \src "libresoc.v:51756.9-51756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_ack[0:0] 1'1 + case + assign $1\dbg_d_xer_ack[0:0] 1'0 + end + sync always + update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] + end + attribute \src "libresoc.v:51765.3-51779.6" + process $proc$libresoc.v:51765$1817 + assign { } { } + assign { } { } + assign $0\issue__addr[2:0] $1\issue__addr[2:0] + attribute \src "libresoc.v:51766.5-51766.29" + switch \initial + attribute \src "libresoc.v:51766.9-51766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\issue__addr[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\issue__addr[2:0] 3'111 + case + assign $1\issue__addr[2:0] 3'000 + end + sync always + update \issue__addr $0\issue__addr[2:0] + end + attribute \src "libresoc.v:51780.3-51794.6" + process $proc$libresoc.v:51780$1818 + assign { } { } + assign { } { } + assign $0\issue__ren[0:0] $1\issue__ren[0:0] + attribute \src "libresoc.v:51781.5-51781.29" + switch \initial + attribute \src "libresoc.v:51781.9-51781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\issue__ren[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\issue__ren[0:0] 1'1 + case + assign $1\issue__ren[0:0] 1'0 + end + sync always + update \issue__ren $0\issue__ren[0:0] + end + attribute \src "libresoc.v:51795.3-51822.6" + process $proc$libresoc.v:51795$1819 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$131$next[1:0]$1820 $2\fsm_state$131$next[1:0]$1822 + attribute \src "libresoc.v:51796.5-51796.29" + switch \initial + attribute \src "libresoc.v:51796.9-51796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$131$next[1:0]$1821 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$131$next[1:0]$1821 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$131$next[1:0]$1821 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$131$next[1:0]$1821 2'00 + case + assign $1\fsm_state$131$next[1:0]$1821 \fsm_state$131 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$131$next[1:0]$1822 2'00 + case + assign $2\fsm_state$131$next[1:0]$1822 $1\fsm_state$131$next[1:0]$1821 + end + sync always + update \fsm_state$131$next $0\fsm_state$131$next[1:0]$1820 + end + attribute \src "libresoc.v:51823.3-51833.6" + process $proc$libresoc.v:51823$1823 + assign { } { } + assign { } { } + assign $0\new_dec[63:0] $1\new_dec[63:0] + attribute \src "libresoc.v:51824.5-51824.29" + switch \initial + attribute \src "libresoc.v:51824.9-51824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\new_dec[63:0] \$132 [63:0] + case + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_dec $0\new_dec[63:0] + end + attribute \src "libresoc.v:51834.3-51848.6" + process $proc$libresoc.v:51834$1824 + assign { } { } + assign { } { } + assign $0\issue__addr$135[2:0]$1825 $1\issue__addr$135[2:0]$1826 + attribute \src "libresoc.v:51835.5-51835.29" + switch \initial + attribute \src "libresoc.v:51835.9-51835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\issue__addr$135[2:0]$1826 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\issue__addr$135[2:0]$1826 3'111 + case + assign $1\issue__addr$135[2:0]$1826 3'000 + end + sync always + update \issue__addr$135 $0\issue__addr$135[2:0]$1825 + end + attribute \src "libresoc.v:51849.3-51863.6" + process $proc$libresoc.v:51849$1827 + assign { } { } + assign { } { } + assign $0\issue__wen[0:0] $1\issue__wen[0:0] + attribute \src "libresoc.v:51850.5-51850.29" + switch \initial + attribute \src "libresoc.v:51850.9-51850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\issue__wen[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\issue__wen[0:0] 1'1 + case + assign $1\issue__wen[0:0] 1'0 + end + sync always + update \issue__wen $0\issue__wen[0:0] + end + attribute \src "libresoc.v:51864.3-51878.6" + process $proc$libresoc.v:51864$1828 + assign { } { } + assign { } { } + assign $0\issue__data_i[63:0] $1\issue__data_i[63:0] + attribute \src "libresoc.v:51865.5-51865.29" + switch \initial + attribute \src "libresoc.v:51865.9-51865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\issue__data_i[63:0] \new_dec + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\issue__data_i[63:0] \new_tb + case + assign $1\issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \issue__data_i $0\issue__data_i[63:0] + end + attribute \src "libresoc.v:51879.3-51894.6" + process $proc$libresoc.v:51879$1829 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_dec$next[63:0]$1830 $2\dec2_cur_dec$next[63:0]$1832 + attribute \src "libresoc.v:51880.5-51880.29" + switch \initial + attribute \src "libresoc.v:51880.9-51880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_dec$next[63:0]$1831 \new_dec + case + assign $1\dec2_cur_dec$next[63:0]$1831 \dec2_cur_dec + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_dec$next[63:0]$1832 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\dec2_cur_dec$next[63:0]$1832 $1\dec2_cur_dec$next[63:0]$1831 + end + sync always + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1830 + end + attribute \src "libresoc.v:51895.3-51905.6" + process $proc$libresoc.v:51895$1833 + assign { } { } + assign { } { } + assign $0\new_tb[63:0] $1\new_tb[63:0] + attribute \src "libresoc.v:51896.5-51896.29" + switch \initial + attribute \src "libresoc.v:51896.9-51896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\new_tb[63:0] \$136 [63:0] + case + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_tb $0\new_tb[63:0] + end + attribute \src "libresoc.v:51906.3-51914.6" + process $proc$libresoc.v:51906$1834 + assign { } { } + assign { } { } + assign $0\dbg_dmi_we_i$next[0:0]$1835 $1\dbg_dmi_we_i$next[0:0]$1836 + attribute \src "libresoc.v:51907.5-51907.29" + switch \initial + attribute \src "libresoc.v:51907.9-51907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_we_i$next[0:0]$1836 1'0 + case + assign $1\dbg_dmi_we_i$next[0:0]$1836 \jtag_dmi0__we_i + end + sync always + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1835 + end + attribute \src "libresoc.v:51915.3-51923.6" + process $proc$libresoc.v:51915$1837 + assign { } { } + assign { } { } + assign $0\pc_ok_delay$next[0:0]$1838 $1\pc_ok_delay$next[0:0]$1839 + attribute \src "libresoc.v:51916.5-51916.29" + switch \initial + attribute \src "libresoc.v:51916.9-51916.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc_ok_delay$next[0:0]$1839 1'0 + case + assign $1\pc_ok_delay$next[0:0]$1839 \$28 + end + sync always + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1838 + end + attribute \src "libresoc.v:51924.3-51939.6" + process $proc$libresoc.v:51924$1840 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc[63:0] $2\pc[63:0] + attribute \src "libresoc.v:51925.5-51925.29" + switch \initial + attribute \src "libresoc.v:51925.9-51925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc[63:0] \pc_i + case + assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \pc_ok_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc[63:0] \cia__data_o + case + assign $2\pc[63:0] $1\pc[63:0] + end + sync always + update \pc $0\pc[63:0] + end + attribute \src "libresoc.v:51940.3-51952.6" + process $proc$libresoc.v:51940$1841 + assign { } { } + assign { } { } + assign $0\cia__ren[3:0] $1\cia__ren[3:0] + attribute \src "libresoc.v:51941.5-51941.29" + switch \initial + attribute \src "libresoc.v:51941.9-51941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\cia__ren[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cia__ren[3:0] 4'0001 + end + sync always + update \cia__ren $0\cia__ren[3:0] + end + attribute \src "libresoc.v:51953.3-51973.6" + process $proc$libresoc.v:51953$1842 + assign { } { } + assign { } { } + assign $0\wen[3:0] $1\wen[3:0] + attribute \src "libresoc.v:51954.5-51954.29" + switch \initial + attribute \src "libresoc.v:51954.9-51954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\wen[3:0] $2\wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$30 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wen[3:0] $3\wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \$32 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wen[3:0] 4'0001 + case + assign $3\wen[3:0] 4'0000 + end + case + assign $2\wen[3:0] 4'0000 + end + case + assign $1\wen[3:0] 4'0000 + end + sync always + update \wen $0\wen[3:0] + end + attribute \src "libresoc.v:51974.3-51994.6" + process $proc$libresoc.v:51974$1843 + assign { } { } + assign { } { } + assign $0\data_i[63:0] $1\data_i[63:0] + attribute \src "libresoc.v:51975.5-51975.29" + switch \initial + attribute \src "libresoc.v:51975.9-51975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\data_i[63:0] $2\data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\data_i[63:0] $3\data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \$36 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_i[63:0] \nia + case + assign $3\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $2\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \data_i $0\data_i[63:0] + end + attribute \src "libresoc.v:51995.3-52010.6" + process $proc$libresoc.v:51995$1844 + assign { } { } + assign { } { } + assign $0\msr__ren[3:0] $1\msr__ren[3:0] + attribute \src "libresoc.v:51996.5-51996.29" + switch \initial + attribute \src "libresoc.v:51996.9-51996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr__ren[3:0] $2\msr__ren[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr__ren[3:0] 4'0010 + case + assign $2\msr__ren[3:0] 4'0000 + end + case + assign $1\msr__ren[3:0] 4'0000 + end + sync always + update \msr__ren $0\msr__ren[3:0] + end + attribute \src "libresoc.v:52011.3-52019.6" + process $proc$libresoc.v:52011$1845 + assign { } { } + assign { } { } + assign $0\dbg_dmi_din$next[63:0]$1846 $1\dbg_dmi_din$next[63:0]$1847 + attribute \src "libresoc.v:52012.5-52012.29" + switch \initial + attribute \src "libresoc.v:52012.9-52012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_din$next[63:0]$1847 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\dbg_dmi_din$next[63:0]$1847 \jtag_dmi0__din + end + sync always + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1846 + end + attribute \src "libresoc.v:52020.3-52044.6" + process $proc$libresoc.v:52020$1848 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc_changed$next[0:0]$1849 $3\pc_changed$next[0:0]$1852 + attribute \src "libresoc.v:52021.5-52021.29" + switch \initial + attribute \src "libresoc.v:52021.9-52021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\pc_changed$next[0:0]$1850 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\pc_changed$next[0:0]$1850 $2\pc_changed$next[0:0]$1851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc_changed$next[0:0]$1851 1'1 + case + assign $2\pc_changed$next[0:0]$1851 \pc_changed + end + case + assign $1\pc_changed$next[0:0]$1850 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\pc_changed$next[0:0]$1852 1'0 + case + assign $3\pc_changed$next[0:0]$1852 $1\pc_changed$next[0:0]$1850 + end + sync always + update \pc_changed$next $0\pc_changed$next[0:0]$1849 + end + attribute \src "libresoc.v:52045.3-52167.6" + process $proc$libresoc.v:52045$1853 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_asmcode$next[7:0]$1854 $1\core_asmcode$next[7:0]$1913 + assign $0\core_core_cia$next[63:0]$1855 $1\core_core_cia$next[63:0]$1914 + assign $0\core_core_cr_rd$next[7:0]$1856 $1\core_core_cr_rd$next[7:0]$1915 + assign { } { } + assign $0\core_core_cr_wr$next[7:0]$1858 $1\core_core_cr_wr$next[7:0]$1917 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_fn_unit$next[11:0]$1868 $1\core_core_fn_unit$next[11:0]$1927 + assign $0\core_core_input_carry$next[1:0]$1869 $1\core_core_input_carry$next[1:0]$1928 + assign $0\core_core_insn$next[31:0]$1870 $1\core_core_insn$next[31:0]$1929 + assign $0\core_core_insn_type$next[6:0]$1871 $1\core_core_insn_type$next[6:0]$1930 + assign $0\core_core_is_32bit$next[0:0]$1872 $1\core_core_is_32bit$next[0:0]$1931 + assign $0\core_core_lk$next[0:0]$1873 $1\core_core_lk$next[0:0]$1932 + assign $0\core_core_msr$next[63:0]$1874 $1\core_core_msr$next[63:0]$1933 + assign $0\core_core_oe$next[0:0]$1875 $1\core_core_oe$next[0:0]$1934 + assign { } { } + assign $0\core_core_rc$next[0:0]$1877 $1\core_core_rc$next[0:0]$1936 + assign { } { } + assign $0\core_core_trapaddr$next[12:0]$1879 $1\core_core_trapaddr$next[12:0]$1938 + assign $0\core_core_traptype$next[7:0]$1880 $1\core_core_traptype$next[7:0]$1939 + assign $0\core_cr_in1$next[2:0]$1881 $1\core_cr_in1$next[2:0]$1940 + assign { } { } + assign $0\core_cr_in2$48$next[2:0]$1883 $1\core_cr_in2$48$next[2:0]$1942 + assign $0\core_cr_in2$next[2:0]$1884 $1\core_cr_in2$next[2:0]$1943 + assign { } { } + assign { } { } + assign $0\core_cr_out$next[2:0]$1887 $1\core_cr_out$next[2:0]$1946 + assign { } { } + assign $0\core_ea$next[4:0]$1889 $1\core_ea$next[4:0]$1948 + assign { } { } + assign $0\core_fast1$next[2:0]$1891 $1\core_fast1$next[2:0]$1950 + assign { } { } + assign $0\core_fast2$next[2:0]$1893 $1\core_fast2$next[2:0]$1952 + assign { } { } + assign $0\core_fasto1$next[2:0]$1895 $1\core_fasto1$next[2:0]$1954 + assign { } { } + assign $0\core_fasto2$next[2:0]$1897 $1\core_fasto2$next[2:0]$1956 + assign { } { } + assign $0\core_reg1$next[4:0]$1899 $1\core_reg1$next[4:0]$1958 + assign { } { } + assign $0\core_reg2$next[4:0]$1901 $1\core_reg2$next[4:0]$1960 + assign { } { } + assign $0\core_reg3$next[4:0]$1903 $1\core_reg3$next[4:0]$1962 + assign { } { } + assign $0\core_rego$next[4:0]$1905 $1\core_rego$next[4:0]$1964 + assign { } { } + assign $0\core_spr1$next[9:0]$1907 $1\core_spr1$next[9:0]$1966 + assign { } { } + assign $0\core_spro$next[9:0]$1909 $1\core_spro$next[9:0]$1968 + assign { } { } + assign $0\core_xer_in$next[2:0]$1911 $1\core_xer_in$next[2:0]$1970 + assign $0\core_xer_out$next[0:0]$1912 $1\core_xer_out$next[0:0]$1971 + assign $0\core_core_cr_rd_ok$next[0:0]$1857 $4\core_core_cr_rd_ok$next[0:0]$2090 + assign $0\core_core_cr_wr_ok$next[0:0]$1859 $4\core_core_cr_wr_ok$next[0:0]$2091 + assign $0\core_core_exc_$signal$50$next[0:0]$1860 $4\core_core_exc_$signal$50$next[0:0]$2092 + assign $0\core_core_exc_$signal$51$next[0:0]$1861 $4\core_core_exc_$signal$51$next[0:0]$2093 + assign $0\core_core_exc_$signal$52$next[0:0]$1862 $4\core_core_exc_$signal$52$next[0:0]$2094 + assign $0\core_core_exc_$signal$53$next[0:0]$1863 $4\core_core_exc_$signal$53$next[0:0]$2095 + assign $0\core_core_exc_$signal$54$next[0:0]$1864 $4\core_core_exc_$signal$54$next[0:0]$2096 + assign $0\core_core_exc_$signal$55$next[0:0]$1865 $4\core_core_exc_$signal$55$next[0:0]$2097 + assign $0\core_core_exc_$signal$56$next[0:0]$1866 $4\core_core_exc_$signal$56$next[0:0]$2098 + assign $0\core_core_exc_$signal$next[0:0]$1867 $4\core_core_exc_$signal$next[0:0]$2099 + assign $0\core_core_oe_ok$next[0:0]$1876 $4\core_core_oe_ok$next[0:0]$2100 + assign $0\core_core_rc_ok$next[0:0]$1878 $4\core_core_rc_ok$next[0:0]$2101 + assign $0\core_cr_in1_ok$next[0:0]$1882 $4\core_cr_in1_ok$next[0:0]$2102 + assign $0\core_cr_in2_ok$49$next[0:0]$1885 $4\core_cr_in2_ok$49$next[0:0]$2103 + assign $0\core_cr_in2_ok$next[0:0]$1886 $4\core_cr_in2_ok$next[0:0]$2104 + assign $0\core_cr_out_ok$next[0:0]$1888 $4\core_cr_out_ok$next[0:0]$2105 + assign $0\core_ea_ok$next[0:0]$1890 $4\core_ea_ok$next[0:0]$2106 + assign $0\core_fast1_ok$next[0:0]$1892 $4\core_fast1_ok$next[0:0]$2107 + assign $0\core_fast2_ok$next[0:0]$1894 $4\core_fast2_ok$next[0:0]$2108 + assign $0\core_fasto1_ok$next[0:0]$1896 $4\core_fasto1_ok$next[0:0]$2109 + assign $0\core_fasto2_ok$next[0:0]$1898 $4\core_fasto2_ok$next[0:0]$2110 + assign $0\core_reg1_ok$next[0:0]$1900 $4\core_reg1_ok$next[0:0]$2111 + assign $0\core_reg2_ok$next[0:0]$1902 $4\core_reg2_ok$next[0:0]$2112 + assign $0\core_reg3_ok$next[0:0]$1904 $4\core_reg3_ok$next[0:0]$2113 + assign $0\core_rego_ok$next[0:0]$1906 $4\core_rego_ok$next[0:0]$2114 + assign $0\core_spr1_ok$next[0:0]$1908 $4\core_spr1_ok$next[0:0]$2115 + assign $0\core_spro_ok$next[0:0]$1910 $4\core_spro_ok$next[0:0]$2116 + attribute \src "libresoc.v:52046.5-52046.29" + switch \initial + attribute \src "libresoc.v:52046.9-52046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\core_core_is_32bit$next[0:0]$1931 $1\core_core_cr_wr_ok$next[0:0]$1918 $1\core_core_cr_wr$next[7:0]$1917 $1\core_core_cr_rd_ok$next[0:0]$1916 $1\core_core_cr_rd$next[7:0]$1915 $1\core_core_trapaddr$next[12:0]$1938 $1\core_core_exc_$signal$56$next[0:0]$1925 $1\core_core_exc_$signal$55$next[0:0]$1924 $1\core_core_exc_$signal$54$next[0:0]$1923 $1\core_core_exc_$signal$53$next[0:0]$1922 $1\core_core_exc_$signal$52$next[0:0]$1921 $1\core_core_exc_$signal$51$next[0:0]$1920 $1\core_core_exc_$signal$50$next[0:0]$1919 $1\core_core_exc_$signal$next[0:0]$1926 $1\core_core_traptype$next[7:0]$1939 $1\core_core_input_carry$next[1:0]$1928 $1\core_core_oe_ok$next[0:0]$1935 $1\core_core_oe$next[0:0]$1934 $1\core_core_rc_ok$next[0:0]$1937 $1\core_core_rc$next[0:0]$1936 $1\core_core_lk$next[0:0]$1932 $1\core_core_fn_unit$next[11:0]$1927 $1\core_core_insn_type$next[6:0]$1930 $1\core_core_insn$next[31:0]$1929 $1\core_core_cia$next[63:0]$1914 $1\core_core_msr$next[63:0]$1933 $1\core_cr_out_ok$next[0:0]$1947 $1\core_cr_out$next[2:0]$1946 $1\core_cr_in2_ok$49$next[0:0]$1944 $1\core_cr_in2$48$next[2:0]$1942 $1\core_cr_in2_ok$next[0:0]$1945 $1\core_cr_in2$next[2:0]$1943 $1\core_cr_in1_ok$next[0:0]$1941 $1\core_cr_in1$next[2:0]$1940 $1\core_fasto2_ok$next[0:0]$1957 $1\core_fasto2$next[2:0]$1956 $1\core_fasto1_ok$next[0:0]$1955 $1\core_fasto1$next[2:0]$1954 $1\core_fast2_ok$next[0:0]$1953 $1\core_fast2$next[2:0]$1952 $1\core_fast1_ok$next[0:0]$1951 $1\core_fast1$next[2:0]$1950 $1\core_xer_out$next[0:0]$1971 $1\core_xer_in$next[2:0]$1970 $1\core_spr1_ok$next[0:0]$1967 $1\core_spr1$next[9:0]$1966 $1\core_spro_ok$next[0:0]$1969 $1\core_spro$next[9:0]$1968 $1\core_reg3_ok$next[0:0]$1963 $1\core_reg3$next[4:0]$1962 $1\core_reg2_ok$next[0:0]$1961 $1\core_reg2$next[4:0]$1960 $1\core_reg1_ok$next[0:0]$1959 $1\core_reg1$next[4:0]$1958 $1\core_ea_ok$next[0:0]$1949 $1\core_ea$next[4:0]$1948 $1\core_rego_ok$next[0:0]$1965 $1\core_rego$next[4:0]$1964 $1\core_asmcode$next[7:0]$1913 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$1913 $2\core_asmcode$next[7:0]$1972 + assign $1\core_core_cia$next[63:0]$1914 $2\core_core_cia$next[63:0]$1973 + assign $1\core_core_cr_rd$next[7:0]$1915 $2\core_core_cr_rd$next[7:0]$1974 + assign $1\core_core_cr_rd_ok$next[0:0]$1916 $2\core_core_cr_rd_ok$next[0:0]$1975 + assign $1\core_core_cr_wr$next[7:0]$1917 $2\core_core_cr_wr$next[7:0]$1976 + assign $1\core_core_cr_wr_ok$next[0:0]$1918 $2\core_core_cr_wr_ok$next[0:0]$1977 + assign $1\core_core_exc_$signal$50$next[0:0]$1919 $2\core_core_exc_$signal$50$next[0:0]$1978 + assign $1\core_core_exc_$signal$51$next[0:0]$1920 $2\core_core_exc_$signal$51$next[0:0]$1979 + assign $1\core_core_exc_$signal$52$next[0:0]$1921 $2\core_core_exc_$signal$52$next[0:0]$1980 + assign $1\core_core_exc_$signal$53$next[0:0]$1922 $2\core_core_exc_$signal$53$next[0:0]$1981 + assign $1\core_core_exc_$signal$54$next[0:0]$1923 $2\core_core_exc_$signal$54$next[0:0]$1982 + assign $1\core_core_exc_$signal$55$next[0:0]$1924 $2\core_core_exc_$signal$55$next[0:0]$1983 + assign $1\core_core_exc_$signal$56$next[0:0]$1925 $2\core_core_exc_$signal$56$next[0:0]$1984 + assign $1\core_core_exc_$signal$next[0:0]$1926 $2\core_core_exc_$signal$next[0:0]$1985 + assign $1\core_core_fn_unit$next[11:0]$1927 $2\core_core_fn_unit$next[11:0]$1986 + assign $1\core_core_input_carry$next[1:0]$1928 $2\core_core_input_carry$next[1:0]$1987 + assign $1\core_core_insn$next[31:0]$1929 $2\core_core_insn$next[31:0]$1988 + assign $1\core_core_insn_type$next[6:0]$1930 $2\core_core_insn_type$next[6:0]$1989 + assign $1\core_core_is_32bit$next[0:0]$1931 $2\core_core_is_32bit$next[0:0]$1990 + assign $1\core_core_lk$next[0:0]$1932 $2\core_core_lk$next[0:0]$1991 + assign $1\core_core_msr$next[63:0]$1933 $2\core_core_msr$next[63:0]$1992 + assign $1\core_core_oe$next[0:0]$1934 $2\core_core_oe$next[0:0]$1993 + assign $1\core_core_oe_ok$next[0:0]$1935 $2\core_core_oe_ok$next[0:0]$1994 + assign $1\core_core_rc$next[0:0]$1936 $2\core_core_rc$next[0:0]$1995 + assign $1\core_core_rc_ok$next[0:0]$1937 $2\core_core_rc_ok$next[0:0]$1996 + assign $1\core_core_trapaddr$next[12:0]$1938 $2\core_core_trapaddr$next[12:0]$1997 + assign $1\core_core_traptype$next[7:0]$1939 $2\core_core_traptype$next[7:0]$1998 + assign $1\core_cr_in1$next[2:0]$1940 $2\core_cr_in1$next[2:0]$1999 + assign $1\core_cr_in1_ok$next[0:0]$1941 $2\core_cr_in1_ok$next[0:0]$2000 + assign $1\core_cr_in2$48$next[2:0]$1942 $2\core_cr_in2$48$next[2:0]$2001 + assign $1\core_cr_in2$next[2:0]$1943 $2\core_cr_in2$next[2:0]$2002 + assign $1\core_cr_in2_ok$49$next[0:0]$1944 $2\core_cr_in2_ok$49$next[0:0]$2003 + assign $1\core_cr_in2_ok$next[0:0]$1945 $2\core_cr_in2_ok$next[0:0]$2004 + assign $1\core_cr_out$next[2:0]$1946 $2\core_cr_out$next[2:0]$2005 + assign $1\core_cr_out_ok$next[0:0]$1947 $2\core_cr_out_ok$next[0:0]$2006 + assign $1\core_ea$next[4:0]$1948 $2\core_ea$next[4:0]$2007 + assign $1\core_ea_ok$next[0:0]$1949 $2\core_ea_ok$next[0:0]$2008 + assign $1\core_fast1$next[2:0]$1950 $2\core_fast1$next[2:0]$2009 + assign $1\core_fast1_ok$next[0:0]$1951 $2\core_fast1_ok$next[0:0]$2010 + assign $1\core_fast2$next[2:0]$1952 $2\core_fast2$next[2:0]$2011 + assign $1\core_fast2_ok$next[0:0]$1953 $2\core_fast2_ok$next[0:0]$2012 + assign $1\core_fasto1$next[2:0]$1954 $2\core_fasto1$next[2:0]$2013 + assign $1\core_fasto1_ok$next[0:0]$1955 $2\core_fasto1_ok$next[0:0]$2014 + assign $1\core_fasto2$next[2:0]$1956 $2\core_fasto2$next[2:0]$2015 + assign $1\core_fasto2_ok$next[0:0]$1957 $2\core_fasto2_ok$next[0:0]$2016 + assign $1\core_reg1$next[4:0]$1958 $2\core_reg1$next[4:0]$2017 + assign $1\core_reg1_ok$next[0:0]$1959 $2\core_reg1_ok$next[0:0]$2018 + assign $1\core_reg2$next[4:0]$1960 $2\core_reg2$next[4:0]$2019 + assign $1\core_reg2_ok$next[0:0]$1961 $2\core_reg2_ok$next[0:0]$2020 + assign $1\core_reg3$next[4:0]$1962 $2\core_reg3$next[4:0]$2021 + assign $1\core_reg3_ok$next[0:0]$1963 $2\core_reg3_ok$next[0:0]$2022 + assign $1\core_rego$next[4:0]$1964 $2\core_rego$next[4:0]$2023 + assign $1\core_rego_ok$next[0:0]$1965 $2\core_rego_ok$next[0:0]$2024 + assign $1\core_spr1$next[9:0]$1966 $2\core_spr1$next[9:0]$2025 + assign $1\core_spr1_ok$next[0:0]$1967 $2\core_spr1_ok$next[0:0]$2026 + assign $1\core_spro$next[9:0]$1968 $2\core_spro$next[9:0]$2027 + assign $1\core_spro_ok$next[0:0]$1969 $2\core_spro_ok$next[0:0]$2028 + assign $1\core_xer_in$next[2:0]$1970 $2\core_xer_in$next[2:0]$2029 + assign $1\core_xer_out$next[0:0]$1971 $2\core_xer_out$next[0:0]$2030 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_asmcode$next[7:0]$1972 \core_asmcode + assign $2\core_core_cia$next[63:0]$1973 \core_core_cia + assign $2\core_core_cr_rd$next[7:0]$1974 \core_core_cr_rd + assign $2\core_core_cr_rd_ok$next[0:0]$1975 \core_core_cr_rd_ok + assign $2\core_core_cr_wr$next[7:0]$1976 \core_core_cr_wr + assign $2\core_core_cr_wr_ok$next[0:0]$1977 \core_core_cr_wr_ok + assign $2\core_core_exc_$signal$50$next[0:0]$1978 \core_core_exc_$signal$50 + assign $2\core_core_exc_$signal$51$next[0:0]$1979 \core_core_exc_$signal$51 + assign $2\core_core_exc_$signal$52$next[0:0]$1980 \core_core_exc_$signal$52 + assign $2\core_core_exc_$signal$53$next[0:0]$1981 \core_core_exc_$signal$53 + assign $2\core_core_exc_$signal$54$next[0:0]$1982 \core_core_exc_$signal$54 + assign $2\core_core_exc_$signal$55$next[0:0]$1983 \core_core_exc_$signal$55 + assign $2\core_core_exc_$signal$56$next[0:0]$1984 \core_core_exc_$signal$56 + assign $2\core_core_exc_$signal$next[0:0]$1985 \core_core_exc_$signal + assign $2\core_core_fn_unit$next[11:0]$1986 \core_core_fn_unit + assign $2\core_core_input_carry$next[1:0]$1987 \core_core_input_carry + assign $2\core_core_insn$next[31:0]$1988 \core_core_insn + assign $2\core_core_insn_type$next[6:0]$1989 \core_core_insn_type + assign $2\core_core_is_32bit$next[0:0]$1990 \core_core_is_32bit + assign $2\core_core_lk$next[0:0]$1991 \core_core_lk + assign $2\core_core_msr$next[63:0]$1992 \core_core_msr + assign $2\core_core_oe$next[0:0]$1993 \core_core_oe + assign $2\core_core_oe_ok$next[0:0]$1994 \core_core_oe_ok + assign $2\core_core_rc$next[0:0]$1995 \core_core_rc + assign $2\core_core_rc_ok$next[0:0]$1996 \core_core_rc_ok + assign $2\core_core_trapaddr$next[12:0]$1997 \core_core_trapaddr + assign $2\core_core_traptype$next[7:0]$1998 \core_core_traptype + assign $2\core_cr_in1$next[2:0]$1999 \core_cr_in1 + assign $2\core_cr_in1_ok$next[0:0]$2000 \core_cr_in1_ok + assign $2\core_cr_in2$48$next[2:0]$2001 \core_cr_in2$48 + assign $2\core_cr_in2$next[2:0]$2002 \core_cr_in2 + assign $2\core_cr_in2_ok$49$next[0:0]$2003 \core_cr_in2_ok$49 + assign $2\core_cr_in2_ok$next[0:0]$2004 \core_cr_in2_ok + assign $2\core_cr_out$next[2:0]$2005 \core_cr_out + assign $2\core_cr_out_ok$next[0:0]$2006 \core_cr_out_ok + assign $2\core_ea$next[4:0]$2007 \core_ea + assign $2\core_ea_ok$next[0:0]$2008 \core_ea_ok + assign $2\core_fast1$next[2:0]$2009 \core_fast1 + assign $2\core_fast1_ok$next[0:0]$2010 \core_fast1_ok + assign $2\core_fast2$next[2:0]$2011 \core_fast2 + assign $2\core_fast2_ok$next[0:0]$2012 \core_fast2_ok + assign $2\core_fasto1$next[2:0]$2013 \core_fasto1 + assign $2\core_fasto1_ok$next[0:0]$2014 \core_fasto1_ok + assign $2\core_fasto2$next[2:0]$2015 \core_fasto2 + assign $2\core_fasto2_ok$next[0:0]$2016 \core_fasto2_ok + assign $2\core_reg1$next[4:0]$2017 \core_reg1 + assign $2\core_reg1_ok$next[0:0]$2018 \core_reg1_ok + assign $2\core_reg2$next[4:0]$2019 \core_reg2 + assign $2\core_reg2_ok$next[0:0]$2020 \core_reg2_ok + assign $2\core_reg3$next[4:0]$2021 \core_reg3 + assign $2\core_reg3_ok$next[0:0]$2022 \core_reg3_ok + assign $2\core_rego$next[4:0]$2023 \core_rego + assign $2\core_rego_ok$next[0:0]$2024 \core_rego_ok + assign $2\core_spr1$next[9:0]$2025 \core_spr1 + assign $2\core_spr1_ok$next[0:0]$2026 \core_spr1_ok + assign $2\core_spro$next[9:0]$2027 \core_spro + assign $2\core_spro_ok$next[0:0]$2028 \core_spro_ok + assign $2\core_xer_in$next[2:0]$2029 \core_xer_in + assign $2\core_xer_out$next[0:0]$2030 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_is_32bit$next[0:0]$1990 $2\core_core_cr_wr_ok$next[0:0]$1977 $2\core_core_cr_wr$next[7:0]$1976 $2\core_core_cr_rd_ok$next[0:0]$1975 $2\core_core_cr_rd$next[7:0]$1974 $2\core_core_trapaddr$next[12:0]$1997 $2\core_core_exc_$signal$56$next[0:0]$1984 $2\core_core_exc_$signal$55$next[0:0]$1983 $2\core_core_exc_$signal$54$next[0:0]$1982 $2\core_core_exc_$signal$53$next[0:0]$1981 $2\core_core_exc_$signal$52$next[0:0]$1980 $2\core_core_exc_$signal$51$next[0:0]$1979 $2\core_core_exc_$signal$50$next[0:0]$1978 $2\core_core_exc_$signal$next[0:0]$1985 $2\core_core_traptype$next[7:0]$1998 $2\core_core_input_carry$next[1:0]$1987 $2\core_core_oe_ok$next[0:0]$1994 $2\core_core_oe$next[0:0]$1993 $2\core_core_rc_ok$next[0:0]$1996 $2\core_core_rc$next[0:0]$1995 $2\core_core_lk$next[0:0]$1991 $2\core_core_fn_unit$next[11:0]$1986 $2\core_core_insn_type$next[6:0]$1989 $2\core_core_insn$next[31:0]$1988 $2\core_core_cia$next[63:0]$1973 $2\core_core_msr$next[63:0]$1992 $2\core_cr_out_ok$next[0:0]$2006 $2\core_cr_out$next[2:0]$2005 $2\core_cr_in2_ok$49$next[0:0]$2003 $2\core_cr_in2$48$next[2:0]$2001 $2\core_cr_in2_ok$next[0:0]$2004 $2\core_cr_in2$next[2:0]$2002 $2\core_cr_in1_ok$next[0:0]$2000 $2\core_cr_in1$next[2:0]$1999 $2\core_fasto2_ok$next[0:0]$2016 $2\core_fasto2$next[2:0]$2015 $2\core_fasto1_ok$next[0:0]$2014 $2\core_fasto1$next[2:0]$2013 $2\core_fast2_ok$next[0:0]$2012 $2\core_fast2$next[2:0]$2011 $2\core_fast1_ok$next[0:0]$2010 $2\core_fast1$next[2:0]$2009 $2\core_xer_out$next[0:0]$2030 $2\core_xer_in$next[2:0]$2029 $2\core_spr1_ok$next[0:0]$2026 $2\core_spr1$next[9:0]$2025 $2\core_spro_ok$next[0:0]$2028 $2\core_spro$next[9:0]$2027 $2\core_reg3_ok$next[0:0]$2022 $2\core_reg3$next[4:0]$2021 $2\core_reg2_ok$next[0:0]$2020 $2\core_reg2$next[4:0]$2019 $2\core_reg1_ok$next[0:0]$2018 $2\core_reg1$next[4:0]$2017 $2\core_ea_ok$next[0:0]$2008 $2\core_ea$next[4:0]$2007 $2\core_rego_ok$next[0:0]$2024 $2\core_rego$next[4:0]$2023 $2\core_asmcode$next[7:0]$1972 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$9 \dec2_exc_$signal$8 \dec2_exc_$signal$7 \dec2_exc_$signal$6 \dec2_exc_$signal$5 \dec2_exc_$signal$4 \dec2_exc_$signal$3 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$2 \dec2_cr_in2$1 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$1913 $3\core_asmcode$next[7:0]$2031 + assign $1\core_core_cia$next[63:0]$1914 $3\core_core_cia$next[63:0]$2032 + assign $1\core_core_cr_rd$next[7:0]$1915 $3\core_core_cr_rd$next[7:0]$2033 + assign $1\core_core_cr_rd_ok$next[0:0]$1916 $3\core_core_cr_rd_ok$next[0:0]$2034 + assign $1\core_core_cr_wr$next[7:0]$1917 $3\core_core_cr_wr$next[7:0]$2035 + assign $1\core_core_cr_wr_ok$next[0:0]$1918 $3\core_core_cr_wr_ok$next[0:0]$2036 + assign $1\core_core_exc_$signal$50$next[0:0]$1919 $3\core_core_exc_$signal$50$next[0:0]$2037 + assign $1\core_core_exc_$signal$51$next[0:0]$1920 $3\core_core_exc_$signal$51$next[0:0]$2038 + assign $1\core_core_exc_$signal$52$next[0:0]$1921 $3\core_core_exc_$signal$52$next[0:0]$2039 + assign $1\core_core_exc_$signal$53$next[0:0]$1922 $3\core_core_exc_$signal$53$next[0:0]$2040 + assign $1\core_core_exc_$signal$54$next[0:0]$1923 $3\core_core_exc_$signal$54$next[0:0]$2041 + assign $1\core_core_exc_$signal$55$next[0:0]$1924 $3\core_core_exc_$signal$55$next[0:0]$2042 + assign $1\core_core_exc_$signal$56$next[0:0]$1925 $3\core_core_exc_$signal$56$next[0:0]$2043 + assign $1\core_core_exc_$signal$next[0:0]$1926 $3\core_core_exc_$signal$next[0:0]$2044 + assign $1\core_core_fn_unit$next[11:0]$1927 $3\core_core_fn_unit$next[11:0]$2045 + assign $1\core_core_input_carry$next[1:0]$1928 $3\core_core_input_carry$next[1:0]$2046 + assign $1\core_core_insn$next[31:0]$1929 $3\core_core_insn$next[31:0]$2047 + assign $1\core_core_insn_type$next[6:0]$1930 $3\core_core_insn_type$next[6:0]$2048 + assign $1\core_core_is_32bit$next[0:0]$1931 $3\core_core_is_32bit$next[0:0]$2049 + assign $1\core_core_lk$next[0:0]$1932 $3\core_core_lk$next[0:0]$2050 + assign $1\core_core_msr$next[63:0]$1933 $3\core_core_msr$next[63:0]$2051 + assign $1\core_core_oe$next[0:0]$1934 $3\core_core_oe$next[0:0]$2052 + assign $1\core_core_oe_ok$next[0:0]$1935 $3\core_core_oe_ok$next[0:0]$2053 + assign $1\core_core_rc$next[0:0]$1936 $3\core_core_rc$next[0:0]$2054 + assign $1\core_core_rc_ok$next[0:0]$1937 $3\core_core_rc_ok$next[0:0]$2055 + assign $1\core_core_trapaddr$next[12:0]$1938 $3\core_core_trapaddr$next[12:0]$2056 + assign $1\core_core_traptype$next[7:0]$1939 $3\core_core_traptype$next[7:0]$2057 + assign $1\core_cr_in1$next[2:0]$1940 $3\core_cr_in1$next[2:0]$2058 + assign $1\core_cr_in1_ok$next[0:0]$1941 $3\core_cr_in1_ok$next[0:0]$2059 + assign $1\core_cr_in2$48$next[2:0]$1942 $3\core_cr_in2$48$next[2:0]$2060 + assign $1\core_cr_in2$next[2:0]$1943 $3\core_cr_in2$next[2:0]$2061 + assign $1\core_cr_in2_ok$49$next[0:0]$1944 $3\core_cr_in2_ok$49$next[0:0]$2062 + assign $1\core_cr_in2_ok$next[0:0]$1945 $3\core_cr_in2_ok$next[0:0]$2063 + assign $1\core_cr_out$next[2:0]$1946 $3\core_cr_out$next[2:0]$2064 + assign $1\core_cr_out_ok$next[0:0]$1947 $3\core_cr_out_ok$next[0:0]$2065 + assign $1\core_ea$next[4:0]$1948 $3\core_ea$next[4:0]$2066 + assign $1\core_ea_ok$next[0:0]$1949 $3\core_ea_ok$next[0:0]$2067 + assign $1\core_fast1$next[2:0]$1950 $3\core_fast1$next[2:0]$2068 + assign $1\core_fast1_ok$next[0:0]$1951 $3\core_fast1_ok$next[0:0]$2069 + assign $1\core_fast2$next[2:0]$1952 $3\core_fast2$next[2:0]$2070 + assign $1\core_fast2_ok$next[0:0]$1953 $3\core_fast2_ok$next[0:0]$2071 + assign $1\core_fasto1$next[2:0]$1954 $3\core_fasto1$next[2:0]$2072 + assign $1\core_fasto1_ok$next[0:0]$1955 $3\core_fasto1_ok$next[0:0]$2073 + assign $1\core_fasto2$next[2:0]$1956 $3\core_fasto2$next[2:0]$2074 + assign $1\core_fasto2_ok$next[0:0]$1957 $3\core_fasto2_ok$next[0:0]$2075 + assign $1\core_reg1$next[4:0]$1958 $3\core_reg1$next[4:0]$2076 + assign $1\core_reg1_ok$next[0:0]$1959 $3\core_reg1_ok$next[0:0]$2077 + assign $1\core_reg2$next[4:0]$1960 $3\core_reg2$next[4:0]$2078 + assign $1\core_reg2_ok$next[0:0]$1961 $3\core_reg2_ok$next[0:0]$2079 + assign $1\core_reg3$next[4:0]$1962 $3\core_reg3$next[4:0]$2080 + assign $1\core_reg3_ok$next[0:0]$1963 $3\core_reg3_ok$next[0:0]$2081 + assign $1\core_rego$next[4:0]$1964 $3\core_rego$next[4:0]$2082 + assign $1\core_rego_ok$next[0:0]$1965 $3\core_rego_ok$next[0:0]$2083 + assign $1\core_spr1$next[9:0]$1966 $3\core_spr1$next[9:0]$2084 + assign $1\core_spr1_ok$next[0:0]$1967 $3\core_spr1_ok$next[0:0]$2085 + assign $1\core_spro$next[9:0]$1968 $3\core_spro$next[9:0]$2086 + assign $1\core_spro_ok$next[0:0]$1969 $3\core_spro_ok$next[0:0]$2087 + assign $1\core_xer_in$next[2:0]$1970 $3\core_xer_in$next[2:0]$2088 + assign $1\core_xer_out$next[0:0]$1971 $3\core_xer_out$next[0:0]$2089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\core_core_is_32bit$next[0:0]$2049 $3\core_core_cr_wr_ok$next[0:0]$2036 $3\core_core_cr_wr$next[7:0]$2035 $3\core_core_cr_rd_ok$next[0:0]$2034 $3\core_core_cr_rd$next[7:0]$2033 $3\core_core_trapaddr$next[12:0]$2056 $3\core_core_exc_$signal$56$next[0:0]$2043 $3\core_core_exc_$signal$55$next[0:0]$2042 $3\core_core_exc_$signal$54$next[0:0]$2041 $3\core_core_exc_$signal$53$next[0:0]$2040 $3\core_core_exc_$signal$52$next[0:0]$2039 $3\core_core_exc_$signal$51$next[0:0]$2038 $3\core_core_exc_$signal$50$next[0:0]$2037 $3\core_core_exc_$signal$next[0:0]$2044 $3\core_core_traptype$next[7:0]$2057 $3\core_core_input_carry$next[1:0]$2046 $3\core_core_oe_ok$next[0:0]$2053 $3\core_core_oe$next[0:0]$2052 $3\core_core_rc_ok$next[0:0]$2055 $3\core_core_rc$next[0:0]$2054 $3\core_core_lk$next[0:0]$2050 $3\core_core_fn_unit$next[11:0]$2045 $3\core_core_insn_type$next[6:0]$2048 $3\core_core_insn$next[31:0]$2047 $3\core_core_cia$next[63:0]$2032 $3\core_core_msr$next[63:0]$2051 $3\core_cr_out_ok$next[0:0]$2065 $3\core_cr_out$next[2:0]$2064 $3\core_cr_in2_ok$49$next[0:0]$2062 $3\core_cr_in2$48$next[2:0]$2060 $3\core_cr_in2_ok$next[0:0]$2063 $3\core_cr_in2$next[2:0]$2061 $3\core_cr_in1_ok$next[0:0]$2059 $3\core_cr_in1$next[2:0]$2058 $3\core_fasto2_ok$next[0:0]$2075 $3\core_fasto2$next[2:0]$2074 $3\core_fasto1_ok$next[0:0]$2073 $3\core_fasto1$next[2:0]$2072 $3\core_fast2_ok$next[0:0]$2071 $3\core_fast2$next[2:0]$2070 $3\core_fast1_ok$next[0:0]$2069 $3\core_fast1$next[2:0]$2068 $3\core_xer_out$next[0:0]$2089 $3\core_xer_in$next[2:0]$2088 $3\core_spr1_ok$next[0:0]$2085 $3\core_spr1$next[9:0]$2084 $3\core_spro_ok$next[0:0]$2087 $3\core_spro$next[9:0]$2086 $3\core_reg3_ok$next[0:0]$2081 $3\core_reg3$next[4:0]$2080 $3\core_reg2_ok$next[0:0]$2079 $3\core_reg2$next[4:0]$2078 $3\core_reg1_ok$next[0:0]$2077 $3\core_reg1$next[4:0]$2076 $3\core_ea_ok$next[0:0]$2067 $3\core_ea$next[4:0]$2066 $3\core_rego_ok$next[0:0]$2083 $3\core_rego$next[4:0]$2082 $3\core_asmcode$next[7:0]$2031 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_asmcode$next[7:0]$2031 \core_asmcode + assign $3\core_core_cia$next[63:0]$2032 \core_core_cia + assign $3\core_core_cr_rd$next[7:0]$2033 \core_core_cr_rd + assign $3\core_core_cr_rd_ok$next[0:0]$2034 \core_core_cr_rd_ok + assign $3\core_core_cr_wr$next[7:0]$2035 \core_core_cr_wr + assign $3\core_core_cr_wr_ok$next[0:0]$2036 \core_core_cr_wr_ok + assign $3\core_core_exc_$signal$50$next[0:0]$2037 \core_core_exc_$signal$50 + assign $3\core_core_exc_$signal$51$next[0:0]$2038 \core_core_exc_$signal$51 + assign $3\core_core_exc_$signal$52$next[0:0]$2039 \core_core_exc_$signal$52 + assign $3\core_core_exc_$signal$53$next[0:0]$2040 \core_core_exc_$signal$53 + assign $3\core_core_exc_$signal$54$next[0:0]$2041 \core_core_exc_$signal$54 + assign $3\core_core_exc_$signal$55$next[0:0]$2042 \core_core_exc_$signal$55 + assign $3\core_core_exc_$signal$56$next[0:0]$2043 \core_core_exc_$signal$56 + assign $3\core_core_exc_$signal$next[0:0]$2044 \core_core_exc_$signal + assign $3\core_core_fn_unit$next[11:0]$2045 \core_core_fn_unit + assign $3\core_core_input_carry$next[1:0]$2046 \core_core_input_carry + assign $3\core_core_insn$next[31:0]$2047 \core_core_insn + assign $3\core_core_insn_type$next[6:0]$2048 \core_core_insn_type + assign $3\core_core_is_32bit$next[0:0]$2049 \core_core_is_32bit + assign $3\core_core_lk$next[0:0]$2050 \core_core_lk + assign $3\core_core_msr$next[63:0]$2051 \core_core_msr + assign $3\core_core_oe$next[0:0]$2052 \core_core_oe + assign $3\core_core_oe_ok$next[0:0]$2053 \core_core_oe_ok + assign $3\core_core_rc$next[0:0]$2054 \core_core_rc + assign $3\core_core_rc_ok$next[0:0]$2055 \core_core_rc_ok + assign $3\core_core_trapaddr$next[12:0]$2056 \core_core_trapaddr + assign $3\core_core_traptype$next[7:0]$2057 \core_core_traptype + assign $3\core_cr_in1$next[2:0]$2058 \core_cr_in1 + assign $3\core_cr_in1_ok$next[0:0]$2059 \core_cr_in1_ok + assign $3\core_cr_in2$48$next[2:0]$2060 \core_cr_in2$48 + assign $3\core_cr_in2$next[2:0]$2061 \core_cr_in2 + assign $3\core_cr_in2_ok$49$next[0:0]$2062 \core_cr_in2_ok$49 + assign $3\core_cr_in2_ok$next[0:0]$2063 \core_cr_in2_ok + assign $3\core_cr_out$next[2:0]$2064 \core_cr_out + assign $3\core_cr_out_ok$next[0:0]$2065 \core_cr_out_ok + assign $3\core_ea$next[4:0]$2066 \core_ea + assign $3\core_ea_ok$next[0:0]$2067 \core_ea_ok + assign $3\core_fast1$next[2:0]$2068 \core_fast1 + assign $3\core_fast1_ok$next[0:0]$2069 \core_fast1_ok + assign $3\core_fast2$next[2:0]$2070 \core_fast2 + assign $3\core_fast2_ok$next[0:0]$2071 \core_fast2_ok + assign $3\core_fasto1$next[2:0]$2072 \core_fasto1 + assign $3\core_fasto1_ok$next[0:0]$2073 \core_fasto1_ok + assign $3\core_fasto2$next[2:0]$2074 \core_fasto2 + assign $3\core_fasto2_ok$next[0:0]$2075 \core_fasto2_ok + assign $3\core_reg1$next[4:0]$2076 \core_reg1 + assign $3\core_reg1_ok$next[0:0]$2077 \core_reg1_ok + assign $3\core_reg2$next[4:0]$2078 \core_reg2 + assign $3\core_reg2_ok$next[0:0]$2079 \core_reg2_ok + assign $3\core_reg3$next[4:0]$2080 \core_reg3 + assign $3\core_reg3_ok$next[0:0]$2081 \core_reg3_ok + assign $3\core_rego$next[4:0]$2082 \core_rego + assign $3\core_rego_ok$next[0:0]$2083 \core_rego_ok + assign $3\core_spr1$next[9:0]$2084 \core_spr1 + assign $3\core_spr1_ok$next[0:0]$2085 \core_spr1_ok + assign $3\core_spro$next[9:0]$2086 \core_spro + assign $3\core_spro_ok$next[0:0]$2087 \core_spro_ok + assign $3\core_xer_in$next[2:0]$2088 \core_xer_in + assign $3\core_xer_out$next[0:0]$2089 \core_xer_out + end + case + assign $1\core_asmcode$next[7:0]$1913 \core_asmcode + assign $1\core_core_cia$next[63:0]$1914 \core_core_cia + assign $1\core_core_cr_rd$next[7:0]$1915 \core_core_cr_rd + assign $1\core_core_cr_rd_ok$next[0:0]$1916 \core_core_cr_rd_ok + assign $1\core_core_cr_wr$next[7:0]$1917 \core_core_cr_wr + assign $1\core_core_cr_wr_ok$next[0:0]$1918 \core_core_cr_wr_ok + assign $1\core_core_exc_$signal$50$next[0:0]$1919 \core_core_exc_$signal$50 + assign $1\core_core_exc_$signal$51$next[0:0]$1920 \core_core_exc_$signal$51 + assign $1\core_core_exc_$signal$52$next[0:0]$1921 \core_core_exc_$signal$52 + assign $1\core_core_exc_$signal$53$next[0:0]$1922 \core_core_exc_$signal$53 + assign $1\core_core_exc_$signal$54$next[0:0]$1923 \core_core_exc_$signal$54 + assign $1\core_core_exc_$signal$55$next[0:0]$1924 \core_core_exc_$signal$55 + assign $1\core_core_exc_$signal$56$next[0:0]$1925 \core_core_exc_$signal$56 + assign $1\core_core_exc_$signal$next[0:0]$1926 \core_core_exc_$signal + assign $1\core_core_fn_unit$next[11:0]$1927 \core_core_fn_unit + assign $1\core_core_input_carry$next[1:0]$1928 \core_core_input_carry + assign $1\core_core_insn$next[31:0]$1929 \core_core_insn + assign $1\core_core_insn_type$next[6:0]$1930 \core_core_insn_type + assign $1\core_core_is_32bit$next[0:0]$1931 \core_core_is_32bit + assign $1\core_core_lk$next[0:0]$1932 \core_core_lk + assign $1\core_core_msr$next[63:0]$1933 \core_core_msr + assign $1\core_core_oe$next[0:0]$1934 \core_core_oe + assign $1\core_core_oe_ok$next[0:0]$1935 \core_core_oe_ok + assign $1\core_core_rc$next[0:0]$1936 \core_core_rc + assign $1\core_core_rc_ok$next[0:0]$1937 \core_core_rc_ok + assign $1\core_core_trapaddr$next[12:0]$1938 \core_core_trapaddr + assign $1\core_core_traptype$next[7:0]$1939 \core_core_traptype + assign $1\core_cr_in1$next[2:0]$1940 \core_cr_in1 + assign $1\core_cr_in1_ok$next[0:0]$1941 \core_cr_in1_ok + assign $1\core_cr_in2$48$next[2:0]$1942 \core_cr_in2$48 + assign $1\core_cr_in2$next[2:0]$1943 \core_cr_in2 + assign $1\core_cr_in2_ok$49$next[0:0]$1944 \core_cr_in2_ok$49 + assign $1\core_cr_in2_ok$next[0:0]$1945 \core_cr_in2_ok + assign $1\core_cr_out$next[2:0]$1946 \core_cr_out + assign $1\core_cr_out_ok$next[0:0]$1947 \core_cr_out_ok + assign $1\core_ea$next[4:0]$1948 \core_ea + assign $1\core_ea_ok$next[0:0]$1949 \core_ea_ok + assign $1\core_fast1$next[2:0]$1950 \core_fast1 + assign $1\core_fast1_ok$next[0:0]$1951 \core_fast1_ok + assign $1\core_fast2$next[2:0]$1952 \core_fast2 + assign $1\core_fast2_ok$next[0:0]$1953 \core_fast2_ok + assign $1\core_fasto1$next[2:0]$1954 \core_fasto1 + assign $1\core_fasto1_ok$next[0:0]$1955 \core_fasto1_ok + assign $1\core_fasto2$next[2:0]$1956 \core_fasto2 + assign $1\core_fasto2_ok$next[0:0]$1957 \core_fasto2_ok + assign $1\core_reg1$next[4:0]$1958 \core_reg1 + assign $1\core_reg1_ok$next[0:0]$1959 \core_reg1_ok + assign $1\core_reg2$next[4:0]$1960 \core_reg2 + assign $1\core_reg2_ok$next[0:0]$1961 \core_reg2_ok + assign $1\core_reg3$next[4:0]$1962 \core_reg3 + assign $1\core_reg3_ok$next[0:0]$1963 \core_reg3_ok + assign $1\core_rego$next[4:0]$1964 \core_rego + assign $1\core_rego_ok$next[0:0]$1965 \core_rego_ok + assign $1\core_spr1$next[9:0]$1966 \core_spr1 + assign $1\core_spr1_ok$next[0:0]$1967 \core_spr1_ok + assign $1\core_spro$next[9:0]$1968 \core_spro + assign $1\core_spro_ok$next[0:0]$1969 \core_spro_ok + assign $1\core_xer_in$next[2:0]$1970 \core_xer_in + assign $1\core_xer_out$next[0:0]$1971 \core_xer_out + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\core_rego_ok$next[0:0]$2114 1'0 + assign $4\core_ea_ok$next[0:0]$2106 1'0 + assign $4\core_reg1_ok$next[0:0]$2111 1'0 + assign $4\core_reg2_ok$next[0:0]$2112 1'0 + assign $4\core_reg3_ok$next[0:0]$2113 1'0 + assign $4\core_spro_ok$next[0:0]$2116 1'0 + assign $4\core_spr1_ok$next[0:0]$2115 1'0 + assign $4\core_fast1_ok$next[0:0]$2107 1'0 + assign $4\core_fast2_ok$next[0:0]$2108 1'0 + assign $4\core_fasto1_ok$next[0:0]$2109 1'0 + assign $4\core_fasto2_ok$next[0:0]$2110 1'0 + assign $4\core_cr_in1_ok$next[0:0]$2102 1'0 + assign $4\core_cr_in2_ok$next[0:0]$2104 1'0 + assign $4\core_cr_in2_ok$49$next[0:0]$2103 1'0 + assign $4\core_cr_out_ok$next[0:0]$2105 1'0 + assign $4\core_core_rc_ok$next[0:0]$2101 1'0 + assign $4\core_core_oe_ok$next[0:0]$2100 1'0 + assign $4\core_core_exc_$signal$next[0:0]$2099 1'0 + assign $4\core_core_exc_$signal$50$next[0:0]$2092 1'0 + assign $4\core_core_exc_$signal$51$next[0:0]$2093 1'0 + assign $4\core_core_exc_$signal$52$next[0:0]$2094 1'0 + assign $4\core_core_exc_$signal$53$next[0:0]$2095 1'0 + assign $4\core_core_exc_$signal$54$next[0:0]$2096 1'0 + assign $4\core_core_exc_$signal$55$next[0:0]$2097 1'0 + assign $4\core_core_exc_$signal$56$next[0:0]$2098 1'0 + assign $4\core_core_cr_rd_ok$next[0:0]$2090 1'0 + assign $4\core_core_cr_wr_ok$next[0:0]$2091 1'0 + case + assign $4\core_core_cr_rd_ok$next[0:0]$2090 $1\core_core_cr_rd_ok$next[0:0]$1916 + assign $4\core_core_cr_wr_ok$next[0:0]$2091 $1\core_core_cr_wr_ok$next[0:0]$1918 + assign $4\core_core_exc_$signal$50$next[0:0]$2092 $1\core_core_exc_$signal$50$next[0:0]$1919 + assign $4\core_core_exc_$signal$51$next[0:0]$2093 $1\core_core_exc_$signal$51$next[0:0]$1920 + assign $4\core_core_exc_$signal$52$next[0:0]$2094 $1\core_core_exc_$signal$52$next[0:0]$1921 + assign $4\core_core_exc_$signal$53$next[0:0]$2095 $1\core_core_exc_$signal$53$next[0:0]$1922 + assign $4\core_core_exc_$signal$54$next[0:0]$2096 $1\core_core_exc_$signal$54$next[0:0]$1923 + assign $4\core_core_exc_$signal$55$next[0:0]$2097 $1\core_core_exc_$signal$55$next[0:0]$1924 + assign $4\core_core_exc_$signal$56$next[0:0]$2098 $1\core_core_exc_$signal$56$next[0:0]$1925 + assign $4\core_core_exc_$signal$next[0:0]$2099 $1\core_core_exc_$signal$next[0:0]$1926 + assign $4\core_core_oe_ok$next[0:0]$2100 $1\core_core_oe_ok$next[0:0]$1935 + assign $4\core_core_rc_ok$next[0:0]$2101 $1\core_core_rc_ok$next[0:0]$1937 + assign $4\core_cr_in1_ok$next[0:0]$2102 $1\core_cr_in1_ok$next[0:0]$1941 + assign $4\core_cr_in2_ok$49$next[0:0]$2103 $1\core_cr_in2_ok$49$next[0:0]$1944 + assign $4\core_cr_in2_ok$next[0:0]$2104 $1\core_cr_in2_ok$next[0:0]$1945 + assign $4\core_cr_out_ok$next[0:0]$2105 $1\core_cr_out_ok$next[0:0]$1947 + assign $4\core_ea_ok$next[0:0]$2106 $1\core_ea_ok$next[0:0]$1949 + assign $4\core_fast1_ok$next[0:0]$2107 $1\core_fast1_ok$next[0:0]$1951 + assign $4\core_fast2_ok$next[0:0]$2108 $1\core_fast2_ok$next[0:0]$1953 + assign $4\core_fasto1_ok$next[0:0]$2109 $1\core_fasto1_ok$next[0:0]$1955 + assign $4\core_fasto2_ok$next[0:0]$2110 $1\core_fasto2_ok$next[0:0]$1957 + assign $4\core_reg1_ok$next[0:0]$2111 $1\core_reg1_ok$next[0:0]$1959 + assign $4\core_reg2_ok$next[0:0]$2112 $1\core_reg2_ok$next[0:0]$1961 + assign $4\core_reg3_ok$next[0:0]$2113 $1\core_reg3_ok$next[0:0]$1963 + assign $4\core_rego_ok$next[0:0]$2114 $1\core_rego_ok$next[0:0]$1965 + assign $4\core_spr1_ok$next[0:0]$2115 $1\core_spr1_ok$next[0:0]$1967 + assign $4\core_spro_ok$next[0:0]$2116 $1\core_spro_ok$next[0:0]$1969 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$1854 + update \core_core_cia$next $0\core_core_cia$next[63:0]$1855 + update \core_core_cr_rd$next $0\core_core_cr_rd$next[7:0]$1856 + update \core_core_cr_rd_ok$next $0\core_core_cr_rd_ok$next[0:0]$1857 + update \core_core_cr_wr$next $0\core_core_cr_wr$next[7:0]$1858 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$1859 + update \core_core_exc_$signal$50$next $0\core_core_exc_$signal$50$next[0:0]$1860 + update \core_core_exc_$signal$51$next $0\core_core_exc_$signal$51$next[0:0]$1861 + update \core_core_exc_$signal$52$next $0\core_core_exc_$signal$52$next[0:0]$1862 + update \core_core_exc_$signal$53$next $0\core_core_exc_$signal$53$next[0:0]$1863 + update \core_core_exc_$signal$54$next $0\core_core_exc_$signal$54$next[0:0]$1864 + update \core_core_exc_$signal$55$next $0\core_core_exc_$signal$55$next[0:0]$1865 + update \core_core_exc_$signal$56$next $0\core_core_exc_$signal$56$next[0:0]$1866 + update \core_core_exc_$signal$next $0\core_core_exc_$signal$next[0:0]$1867 + update \core_core_fn_unit$next $0\core_core_fn_unit$next[11:0]$1868 + update \core_core_input_carry$next $0\core_core_input_carry$next[1:0]$1869 + update \core_core_insn$next $0\core_core_insn$next[31:0]$1870 + update \core_core_insn_type$next $0\core_core_insn_type$next[6:0]$1871 + update \core_core_is_32bit$next $0\core_core_is_32bit$next[0:0]$1872 + update \core_core_lk$next $0\core_core_lk$next[0:0]$1873 + update \core_core_msr$next $0\core_core_msr$next[63:0]$1874 + update \core_core_oe$next $0\core_core_oe$next[0:0]$1875 + update \core_core_oe_ok$next $0\core_core_oe_ok$next[0:0]$1876 + update \core_core_rc$next $0\core_core_rc$next[0:0]$1877 + update \core_core_rc_ok$next $0\core_core_rc_ok$next[0:0]$1878 + update \core_core_trapaddr$next $0\core_core_trapaddr$next[12:0]$1879 + update \core_core_traptype$next $0\core_core_traptype$next[7:0]$1880 + update \core_cr_in1$next $0\core_cr_in1$next[2:0]$1881 + update \core_cr_in1_ok$next $0\core_cr_in1_ok$next[0:0]$1882 + update \core_cr_in2$48$next $0\core_cr_in2$48$next[2:0]$1883 + update \core_cr_in2$next $0\core_cr_in2$next[2:0]$1884 + update \core_cr_in2_ok$49$next $0\core_cr_in2_ok$49$next[0:0]$1885 + update \core_cr_in2_ok$next $0\core_cr_in2_ok$next[0:0]$1886 + update \core_cr_out$next $0\core_cr_out$next[2:0]$1887 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$1888 + update \core_ea$next $0\core_ea$next[4:0]$1889 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$1890 + update \core_fast1$next $0\core_fast1$next[2:0]$1891 + update \core_fast1_ok$next $0\core_fast1_ok$next[0:0]$1892 + update \core_fast2$next $0\core_fast2$next[2:0]$1893 + update \core_fast2_ok$next $0\core_fast2_ok$next[0:0]$1894 + update \core_fasto1$next $0\core_fasto1$next[2:0]$1895 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$1896 + update \core_fasto2$next $0\core_fasto2$next[2:0]$1897 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$1898 + update \core_reg1$next $0\core_reg1$next[4:0]$1899 + update \core_reg1_ok$next $0\core_reg1_ok$next[0:0]$1900 + update \core_reg2$next $0\core_reg2$next[4:0]$1901 + update \core_reg2_ok$next $0\core_reg2_ok$next[0:0]$1902 + update \core_reg3$next $0\core_reg3$next[4:0]$1903 + update \core_reg3_ok$next $0\core_reg3_ok$next[0:0]$1904 + update \core_rego$next $0\core_rego$next[4:0]$1905 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$1906 + update \core_spr1$next $0\core_spr1$next[9:0]$1907 + update \core_spr1_ok$next $0\core_spr1_ok$next[0:0]$1908 + update \core_spro$next $0\core_spro$next[9:0]$1909 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$1910 + update \core_xer_in$next $0\core_xer_in$next[2:0]$1911 + update \core_xer_out$next $0\core_xer_out$next[0:0]$1912 + end + attribute \src "libresoc.v:52168.3-52176.6" + process $proc$libresoc.v:52168$2117 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__ack_o$next[0:0]$2118 $1\jtag_dmi0__ack_o$next[0:0]$2119 + attribute \src "libresoc.v:52169.5-52169.29" + switch \initial + attribute \src "libresoc.v:52169.9-52169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__ack_o$next[0:0]$2119 1'0 + case + assign $1\jtag_dmi0__ack_o$next[0:0]$2119 \dbg_dmi_ack_o + end + sync always + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$2118 + end + attribute \src "libresoc.v:52177.3-52185.6" + process $proc$libresoc.v:52177$2120 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__dout$next[63:0]$2121 $1\jtag_dmi0__dout$next[63:0]$2122 + attribute \src "libresoc.v:52178.5-52178.29" + switch \initial + attribute \src "libresoc.v:52178.9-52178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__dout$next[63:0]$2122 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\jtag_dmi0__dout$next[63:0]$2122 \dbg_dmi_dout + end + sync always + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$2121 + end + attribute \src "libresoc.v:52186.3-52194.6" + process $proc$libresoc.v:52186$2123 + assign { } { } + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$2124 $1\dec2_cur_eint$next[0:0]$2125 + attribute \src "libresoc.v:52187.5-52187.29" + switch \initial + attribute \src "libresoc.v:52187.9-52187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dec2_cur_eint$next[0:0]$2125 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$2125 \xics_icp_core_irq_o + end + sync always + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$2124 + end + attribute \src "libresoc.v:52195.3-52204.6" + process $proc$libresoc.v:52195$2126 + assign { } { } + assign { } { } + assign $0\delay$next[1:0]$2127 $1\delay$next[1:0]$2128 + attribute \src "libresoc.v:52196.5-52196.29" + switch \initial + attribute \src "libresoc.v:52196.9-52196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" + switch \$10 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$2128 \$12 [1:0] + case + assign $1\delay$next[1:0]$2128 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$2127 + end + attribute \src "libresoc.v:52205.3-52241.6" + process $proc$libresoc.v:52205$2129 + assign { } { } + assign { } { } + assign { } { } + assign $0\raw_insn_i$next[31:0]$2130 $4\raw_insn_i$next[31:0]$2134 + attribute \src "libresoc.v:52206.5-52206.29" + switch \initial + attribute \src "libresoc.v:52206.9-52206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\raw_insn_i$next[31:0]$2131 0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\raw_insn_i$next[31:0]$2131 $2\raw_insn_i$next[31:0]$2132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\raw_insn_i$next[31:0]$2132 \raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\raw_insn_i$next[31:0]$2132 \dec2_raw_opcode_in + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\raw_insn_i$next[31:0]$2131 $3\raw_insn_i$next[31:0]$2133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\raw_insn_i$next[31:0]$2133 0 + case + assign $3\raw_insn_i$next[31:0]$2133 \raw_insn_i + end + case + assign $1\raw_insn_i$next[31:0]$2131 \raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\raw_insn_i$next[31:0]$2134 0 + case + assign $4\raw_insn_i$next[31:0]$2134 $1\raw_insn_i$next[31:0]$2131 + end + sync always + update \raw_insn_i$next $0\raw_insn_i$next[31:0]$2130 + end + attribute \src "libresoc.v:52242.3-52278.6" + process $proc$libresoc.v:52242$2135 + assign { } { } + assign { } { } + assign { } { } + assign $0\bigendian_i$next[0:0]$2136 $4\bigendian_i$next[0:0]$2140 + attribute \src "libresoc.v:52243.5-52243.29" + switch \initial + attribute \src "libresoc.v:52243.9-52243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\bigendian_i$next[0:0]$2137 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\bigendian_i$next[0:0]$2137 $2\bigendian_i$next[0:0]$2138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\bigendian_i$next[0:0]$2138 \bigendian_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\bigendian_i$next[0:0]$2138 \core_bigendian_i + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\bigendian_i$next[0:0]$2137 $3\bigendian_i$next[0:0]$2139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\bigendian_i$next[0:0]$2139 1'0 + case + assign $3\bigendian_i$next[0:0]$2139 \bigendian_i + end + case + assign $1\bigendian_i$next[0:0]$2137 \bigendian_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\bigendian_i$next[0:0]$2140 1'0 + case + assign $4\bigendian_i$next[0:0]$2140 $1\bigendian_i$next[0:0]$2137 + end + sync always + update \bigendian_i$next $0\bigendian_i$next[0:0]$2136 + end + attribute \src "libresoc.v:52279.3-52294.6" + process $proc$libresoc.v:52279$2141 + assign { } { } + assign { } { } + assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:52280.5-52280.29" + switch \initial + attribute \src "libresoc.v:52280.9-52280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_pc_i[47:0] \pc [47:0] + case + assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + sync always + update \imem_a_pc_i $0\imem_a_pc_i[47:0] + end + attribute \src "libresoc.v:52295.3-52319.6" + process $proc$libresoc.v:52295$2142 + assign { } { } + assign { } { } + assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:52296.5-52296.29" + switch \initial + attribute \src "libresoc.v:52296.9-52296.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_valid_i[0:0] 1'1 + case + assign $2\imem_a_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_a_valid_i[0:0] 1'1 + case + assign $3\imem_a_valid_i[0:0] 1'0 + end + case + assign $1\imem_a_valid_i[0:0] 1'0 + end + sync always + update \imem_a_valid_i $0\imem_a_valid_i[0:0] + end + attribute \src "libresoc.v:52320.3-52344.6" + process $proc$libresoc.v:52320$2143 + assign { } { } + assign { } { } + assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:52321.5-52321.29" + switch \initial + attribute \src "libresoc.v:52321.9-52321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_f_valid_i[0:0] 1'1 + case + assign $2\imem_f_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_f_valid_i[0:0] 1'1 + case + assign $3\imem_f_valid_i[0:0] 1'0 + end + case + assign $1\imem_f_valid_i[0:0] 1'0 + end + sync always + update \imem_f_valid_i $0\imem_f_valid_i[0:0] + end + attribute \src "libresoc.v:52345.3-52365.6" + process $proc$libresoc.v:52345$2144 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_pc$next[63:0]$2145 $3\dec2_cur_pc$next[63:0]$2148 + attribute \src "libresoc.v:52346.5-52346.29" + switch \initial + attribute \src "libresoc.v:52346.9-52346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec2_cur_pc$next[63:0]$2146 $2\dec2_cur_pc$next[63:0]$2147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_pc$next[63:0]$2147 \pc + case + assign $2\dec2_cur_pc$next[63:0]$2147 \dec2_cur_pc + end + case + assign $1\dec2_cur_pc$next[63:0]$2146 \dec2_cur_pc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_pc$next[63:0]$2148 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_pc$next[63:0]$2148 $1\dec2_cur_pc$next[63:0]$2146 + end + sync always + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$2145 + end + attribute \src "libresoc.v:52366.3-52395.6" + process $proc$libresoc.v:52366$2149 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr_read$next[0:0]$2150 $4\msr_read$next[0:0]$2154 + attribute \src "libresoc.v:52367.5-52367.29" + switch \initial + attribute \src "libresoc.v:52367.9-52367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr_read$next[0:0]$2151 $2\msr_read$next[0:0]$2152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_read$next[0:0]$2152 1'0 + case + assign $2\msr_read$next[0:0]$2152 \msr_read + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\msr_read$next[0:0]$2151 $3\msr_read$next[0:0]$2153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr_read$next[0:0]$2153 1'1 + case + assign $3\msr_read$next[0:0]$2153 \msr_read + end + case + assign $1\msr_read$next[0:0]$2151 \msr_read + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr_read$next[0:0]$2154 1'1 + case + assign $4\msr_read$next[0:0]$2154 $1\msr_read$next[0:0]$2151 + end + sync always + update \msr_read$next $0\msr_read$next[0:0]$2150 + end + attribute \src "libresoc.v:52396.3-52441.6" + process $proc$libresoc.v:52396$2155 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$2156 $5\fsm_state$next[1:0]$2161 + attribute \src "libresoc.v:52397.5-52397.29" + switch \initial + attribute \src "libresoc.v:52397.9-52397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$2157 $2\fsm_state$next[1:0]$2158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$2158 2'01 + case + assign $2\fsm_state$next[1:0]$2158 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$2157 $3\fsm_state$next[1:0]$2159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\fsm_state$next[1:0]$2159 \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\fsm_state$next[1:0]$2159 2'10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$2157 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$next[1:0]$2157 $4\fsm_state$next[1:0]$2160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$2160 2'00 + case + assign $4\fsm_state$next[1:0]$2160 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$2157 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[1:0]$2161 2'00 + case + assign $5\fsm_state$next[1:0]$2161 $1\fsm_state$next[1:0]$2157 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$2156 + end + attribute \src "libresoc.v:52442.3-52460.6" + process $proc$libresoc.v:52442$2162 + assign { } { } + assign { } { } + assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] + attribute \src "libresoc.v:52443.5-52443.29" + switch \initial + attribute \src "libresoc.v:52443.9-52443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$107 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_stopped_i[0:0] 1'1 + end + case + assign $1\core_stopped_i[0:0] 1'0 + end + sync always + update \core_stopped_i $0\core_stopped_i[0:0] + end + attribute \src "libresoc.v:52461.3-52479.6" + process $proc$libresoc.v:52461$2163 + assign { } { } + assign { } { } + assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:52462.5-52462.29" + switch \initial + attribute \src "libresoc.v:52462.9-52462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbg_core_stopped_i[0:0] 1'1 + end + case + assign $1\dbg_core_stopped_i[0:0] 1'0 + end + sync always + update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] + end + connect \$99 $and$libresoc.v:50790$1606_Y + connect \$101 $not$libresoc.v:50791$1607_Y + connect \$103 $not$libresoc.v:50792$1608_Y + connect \$105 $not$libresoc.v:50793$1609_Y + connect \$107 $and$libresoc.v:50794$1610_Y + connect \$10 $ne$libresoc.v:50795$1611_Y + connect \$109 $not$libresoc.v:50796$1612_Y + connect \$111 $not$libresoc.v:50797$1613_Y + connect \$113 $and$libresoc.v:50798$1614_Y + connect \$115 $not$libresoc.v:50799$1615_Y + connect \$118 $mul$libresoc.v:50800$1616_Y + connect \$117 $shr$libresoc.v:50801$1617_Y [31:0] + connect \$122 $mul$libresoc.v:50802$1618_Y + connect \$121 $shr$libresoc.v:50803$1619_Y [31:0] + connect \$125 $ne$libresoc.v:50804$1620_Y + connect \$127 $pos$libresoc.v:50805$1622_Y + connect \$129 $pos$libresoc.v:50806$1624_Y + connect \$133 $sub$libresoc.v:50807$1625_Y + connect \$137 $add$libresoc.v:50808$1626_Y + connect \$13 $sub$libresoc.v:50809$1627_Y + connect \$15 $or$libresoc.v:50810$1628_Y + connect \$17 $or$libresoc.v:50811$1629_Y + connect \$19 $ne$libresoc.v:50812$1630_Y + connect \$21 $not$libresoc.v:50813$1631_Y + connect \$23 $and$libresoc.v:50814$1632_Y + connect \$26 $add$libresoc.v:50815$1633_Y + connect \$28 $not$libresoc.v:50816$1634_Y + connect \$30 $not$libresoc.v:50817$1635_Y + connect \$32 $not$libresoc.v:50818$1636_Y + connect \$34 $not$libresoc.v:50819$1637_Y + connect \$36 $not$libresoc.v:50820$1638_Y + connect \$38 $not$libresoc.v:50821$1639_Y + connect \$40 $not$libresoc.v:50822$1640_Y + connect \$42 $and$libresoc.v:50823$1641_Y + connect \$45 $and$libresoc.v:50824$1642_Y + connect \$44 $reduce_or$libresoc.v:50825$1643_Y + connect \$57 $not$libresoc.v:50826$1644_Y + connect \$59 $not$libresoc.v:50827$1645_Y + connect \$61 $not$libresoc.v:50828$1646_Y + connect \$63 $not$libresoc.v:50829$1647_Y + connect \$65 $not$libresoc.v:50830$1648_Y + connect \$67 $and$libresoc.v:50831$1649_Y + connect \$69 $not$libresoc.v:50832$1650_Y + connect \$71 $not$libresoc.v:50833$1651_Y + connect \$73 $and$libresoc.v:50834$1652_Y + connect \$75 $not$libresoc.v:50835$1653_Y + connect \$77 $not$libresoc.v:50836$1654_Y + connect \$79 $and$libresoc.v:50837$1655_Y + connect \$81 $not$libresoc.v:50838$1656_Y + connect \$83 $not$libresoc.v:50839$1657_Y + connect \$85 $and$libresoc.v:50840$1658_Y + connect \$87 $not$libresoc.v:50841$1659_Y + connect \$89 $not$libresoc.v:50842$1660_Y + connect \$91 $and$libresoc.v:50843$1661_Y + connect \$93 $not$libresoc.v:50844$1662_Y + connect \$95 $not$libresoc.v:50845$1663_Y + connect \$97 $not$libresoc.v:50846$1664_Y + connect \$12 \$13 + connect \$25 \$26 + connect \$132 \$133 + connect \$136 \$137 + connect \corebusy_o 1'0 + connect \cu_st__rel_o 1'0 + connect \cu_ad__rel_o 1'0 + connect \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \core_terminate_o 1'0 + connect \state_nia_wen 4'0000 + connect \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \full_rd2__data_o 0 + connect \full_rd__data_o 6'000000 + connect \issue__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \dbg_core_dbg_msr \dec2_cur_msr + connect \dbg_core_dbg_pc \pc + connect \dbg_terminate_i 1'0 + connect \nia \$26 [63:0] + connect \pc_o \dec2_cur_pc + connect \cu_st__go_i \cu_st__rel_o_rise + connect \cu_ad__go_i 1'0 + connect \cu_st__rel_o_rise \$23 + connect \cu_st__rel_o_dly$next 1'0 + connect \dec2_bigendian \core_bigendian_i + connect \busy_o 1'0 + connect \core_coresync_rst \ti_rst + connect \ti_rst \$19 + connect \por_clk \clk + connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } +end +attribute \src "libresoc.v:52514.1-52828.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" +attribute \generator "nMigen" +module \xics_icp + attribute \src "libresoc.v:52692.3-52720.6" + wire width 32 $0\be_out[31:0] + attribute \src "libresoc.v:52743.3-52751.6" + wire $0\core_irq_o$next[0:0]$2297 + attribute \src "libresoc.v:52634.3-52635.37" + wire $0\core_irq_o[0:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire width 8 $0\cppr$10[7:0]$2301 + attribute \src "libresoc.v:52648.3-52663.6" + wire width 8 $0\cppr$next[7:0]$2280 + attribute \src "libresoc.v:52638.3-52639.25" + wire width 8 $0\cppr[7:0] + attribute \src "libresoc.v:52752.3-52761.6" + wire width 32 $0\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:52515.7-52515.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire $0\irq$12[0:0]$2302 + attribute \src "libresoc.v:52648.3-52663.6" + wire $0\irq$next[0:0]$2281 + attribute \src "libresoc.v:52642.3-52643.23" + wire $0\irq[0:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire width 8 $0\mfrr$11[7:0]$2303 + attribute \src "libresoc.v:52648.3-52663.6" + wire width 8 $0\mfrr$next[7:0]$2282 + attribute \src "libresoc.v:52640.3-52641.25" + wire width 8 $0\mfrr[7:0] + attribute \src "libresoc.v:52731.3-52742.6" + wire width 8 $0\min_pri[7:0] + attribute \src "libresoc.v:52721.3-52730.6" + wire width 8 $0\pending_priority[7:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire $0\wb_ack$14[0:0]$2304 + attribute \src "libresoc.v:52648.3-52663.6" + wire $0\wb_ack$next[0:0]$2283 + attribute \src "libresoc.v:52646.3-52647.29" + wire $0\wb_ack[0:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire width 32 $0\wb_rd_data$13[31:0]$2305 + attribute \src "libresoc.v:52648.3-52663.6" + wire width 32 $0\wb_rd_data$next[31:0]$2284 + attribute \src "libresoc.v:52644.3-52645.37" + wire width 32 $0\wb_rd_data[31:0] + attribute \src "libresoc.v:52664.3-52691.6" + wire $0\xirr_accept_rd[0:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire width 24 $0\xisr$9[23:0]$2306 + attribute \src "libresoc.v:52648.3-52663.6" + wire width 24 $0\xisr$next[23:0]$2285 + attribute \src "libresoc.v:52636.3-52637.25" + wire width 24 $0\xisr[23:0] + attribute \src "libresoc.v:52692.3-52720.6" + wire width 32 $1\be_out[31:0] + attribute \src "libresoc.v:52743.3-52751.6" + wire $1\core_irq_o$next[0:0]$2298 + attribute \src "libresoc.v:52544.7-52544.24" + wire $1\core_irq_o[0:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire width 8 $1\cppr$10[7:0]$2307 + attribute \src "libresoc.v:52648.3-52663.6" + wire width 8 $1\cppr$next[7:0]$2286 + attribute \src "libresoc.v:52548.13-52548.25" + wire width 8 $1\cppr[7:0] + attribute \src "libresoc.v:52752.3-52761.6" + wire width 32 $1\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire $1\irq$12[0:0]$2317 + attribute \src "libresoc.v:52648.3-52663.6" + wire $1\irq$next[0:0]$2287 + attribute \src "libresoc.v:52577.7-52577.17" + wire $1\irq[0:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire width 8 $1\mfrr$11[7:0]$2308 + attribute \src "libresoc.v:52648.3-52663.6" + wire width 8 $1\mfrr$next[7:0]$2288 + attribute \src "libresoc.v:52585.13-52585.25" + wire width 8 $1\mfrr[7:0] + attribute \src "libresoc.v:52731.3-52742.6" + wire width 8 $1\min_pri[7:0] + attribute \src "libresoc.v:52721.3-52730.6" + wire width 8 $1\pending_priority[7:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire $1\wb_ack$14[0:0]$2309 + attribute \src "libresoc.v:52648.3-52663.6" + wire $1\wb_ack$next[0:0]$2289 + attribute \src "libresoc.v:52599.7-52599.20" + wire $1\wb_ack[0:0] + attribute \src "libresoc.v:52648.3-52663.6" + wire width 32 $1\wb_rd_data$next[31:0]$2290 + attribute \src "libresoc.v:52607.14-52607.32" + wire width 32 $1\wb_rd_data[31:0] + attribute \src "libresoc.v:52664.3-52691.6" + wire $1\xirr_accept_rd[0:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire width 24 $1\xisr$9[23:0]$2314 + attribute \src "libresoc.v:52648.3-52663.6" + wire width 24 $1\xisr$next[23:0]$2291 + attribute \src "libresoc.v:52617.14-52617.31" + wire width 24 $1\xisr[23:0] + attribute \src "libresoc.v:52692.3-52720.6" + wire width 32 $2\be_out[31:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire width 8 $2\cppr$10[7:0]$2310 + attribute \src "libresoc.v:52762.3-52824.6" + wire width 8 $2\mfrr$11[7:0]$2311 + attribute \src "libresoc.v:52664.3-52691.6" + wire $2\xirr_accept_rd[0:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire width 24 $2\xisr$9[23:0]$2315 + attribute \src "libresoc.v:52692.3-52720.6" + wire width 32 $3\be_out[31:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire width 8 $3\cppr$10[7:0]$2312 + attribute \src "libresoc.v:52762.3-52824.6" + wire width 8 $3\mfrr$11[7:0]$2313 + attribute \src "libresoc.v:52664.3-52691.6" + wire $3\xirr_accept_rd[0:0] + attribute \src "libresoc.v:52762.3-52824.6" + wire width 8 $4\cppr$10[7:0]$2316 + attribute \src "libresoc.v:52664.3-52691.6" + wire $4\xirr_accept_rd[0:0] + attribute \src "libresoc.v:52624.18-52624.116" + wire $and$libresoc.v:52624$2262_Y + attribute \src "libresoc.v:52628.18-52628.116" + wire $and$libresoc.v:52628$2266_Y + attribute \src "libresoc.v:52630.18-52630.116" + wire $and$libresoc.v:52630$2268_Y + attribute \src "libresoc.v:52633.17-52633.109" + wire $and$libresoc.v:52633$2271_Y + attribute \src "libresoc.v:52629.18-52629.110" + wire $eq$libresoc.v:52629$2267_Y + attribute \src "libresoc.v:52626.18-52626.114" + wire $lt$libresoc.v:52626$2264_Y + attribute \src "libresoc.v:52627.18-52627.109" + wire $lt$libresoc.v:52627$2265_Y + attribute \src "libresoc.v:52632.18-52632.114" + wire $lt$libresoc.v:52632$2270_Y + attribute \src "libresoc.v:52625.18-52625.109" + wire $ne$libresoc.v:52625$2263_Y + attribute \src "libresoc.v:52631.18-52631.109" + wire $ne$libresoc.v:52631$2269_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:103" + wire width 32 \be_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" + wire width 32 \be_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 13 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire output 4 \core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \core_irq_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 5 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 11 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 6 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 7 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 8 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 12 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 9 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 10 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 input 3 \ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 input 2 \ics_i_src + attribute \src "libresoc.v:52515.7-52515.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:107" + wire width 8 \min_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" + wire width 8 \pending_priority + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:101" + wire \xirr_accept_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:52624$2262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:52624$2262_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:52628$2266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:52628$2266_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:52630$2268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:52630$2268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + cell $and $and$libresoc.v:52633$2271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wb_ack + connect \B \icp_wb__cyc + connect \Y $and$libresoc.v:52633$2271_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + cell $eq $eq$libresoc.v:52629$2267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \icp_wb__sel + connect \B 4'1111 + connect \Y $eq$libresoc.v:52629$2267_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$libresoc.v:52626$2264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$libresoc.v:52626$2264_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + cell $lt $lt$libresoc.v:52627$2265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \min_pri + connect \B \cppr$10 + connect \Y $lt$libresoc.v:52627$2265_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$libresoc.v:52632$2270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$libresoc.v:52632$2270_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$libresoc.v:52625$2263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$libresoc.v:52625$2263_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$libresoc.v:52631$2269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$libresoc.v:52631$2269_Y + end + attribute \src "libresoc.v:52515.7-52515.20" + process $proc$libresoc.v:52515$2318 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:52544.7-52544.24" + process $proc$libresoc.v:52544$2319 + assign { } { } + assign $1\core_irq_o[0:0] 1'0 + sync always + sync init + update \core_irq_o $1\core_irq_o[0:0] + end + attribute \src "libresoc.v:52548.13-52548.25" + process $proc$libresoc.v:52548$2320 + assign { } { } + assign $1\cppr[7:0] 8'00000000 + sync always + sync init + update \cppr $1\cppr[7:0] + end + attribute \src "libresoc.v:52577.7-52577.17" + process $proc$libresoc.v:52577$2321 + assign { } { } + assign $1\irq[0:0] 1'0 + sync always + sync init + update \irq $1\irq[0:0] + end + attribute \src "libresoc.v:52585.13-52585.25" + process $proc$libresoc.v:52585$2322 + assign { } { } + assign $1\mfrr[7:0] 8'11111111 + sync always + sync init + update \mfrr $1\mfrr[7:0] + end + attribute \src "libresoc.v:52599.7-52599.20" + process $proc$libresoc.v:52599$2323 + assign { } { } + assign $1\wb_ack[0:0] 1'0 + sync always + sync init + update \wb_ack $1\wb_ack[0:0] + end + attribute \src "libresoc.v:52607.14-52607.32" + process $proc$libresoc.v:52607$2324 + assign { } { } + assign $1\wb_rd_data[31:0] 0 + sync always + sync init + update \wb_rd_data $1\wb_rd_data[31:0] + end + attribute \src "libresoc.v:52617.14-52617.31" + process $proc$libresoc.v:52617$2325 + assign { } { } + assign $1\xisr[23:0] 24'000000000000000000000000 + sync always + sync init + update \xisr $1\xisr[23:0] + end + attribute \src "libresoc.v:52634.3-52635.37" + process $proc$libresoc.v:52634$2272 + assign { } { } + assign $0\core_irq_o[0:0] \core_irq_o$next + sync posedge \clk + update \core_irq_o $0\core_irq_o[0:0] + end + attribute \src "libresoc.v:52636.3-52637.25" + process $proc$libresoc.v:52636$2273 + assign { } { } + assign $0\xisr[23:0] \xisr$next + sync posedge \clk + update \xisr $0\xisr[23:0] + end + attribute \src "libresoc.v:52638.3-52639.25" + process $proc$libresoc.v:52638$2274 + assign { } { } + assign $0\cppr[7:0] \cppr$next + sync posedge \clk + update \cppr $0\cppr[7:0] + end + attribute \src "libresoc.v:52640.3-52641.25" + process $proc$libresoc.v:52640$2275 + assign { } { } + assign $0\mfrr[7:0] \mfrr$next + sync posedge \clk + update \mfrr $0\mfrr[7:0] + end + attribute \src "libresoc.v:52642.3-52643.23" + process $proc$libresoc.v:52642$2276 + assign { } { } + assign $0\irq[0:0] \irq$next + sync posedge \clk + update \irq $0\irq[0:0] + end + attribute \src "libresoc.v:52644.3-52645.37" + process $proc$libresoc.v:52644$2277 + assign { } { } + assign $0\wb_rd_data[31:0] \wb_rd_data$next + sync posedge \clk + update \wb_rd_data $0\wb_rd_data[31:0] + end + attribute \src "libresoc.v:52646.3-52647.29" + process $proc$libresoc.v:52646$2278 + assign { } { } + assign $0\wb_ack[0:0] \wb_ack$next + sync posedge \clk + update \wb_ack $0\wb_ack[0:0] + end + attribute \src "libresoc.v:52648.3-52663.6" + process $proc$libresoc.v:52648$2279 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cppr$next[7:0]$2280 $1\cppr$next[7:0]$2286 + assign $0\irq$next[0:0]$2281 $1\irq$next[0:0]$2287 + assign $0\mfrr$next[7:0]$2282 $1\mfrr$next[7:0]$2288 + assign $0\wb_ack$next[0:0]$2283 $1\wb_ack$next[0:0]$2289 + assign $0\wb_rd_data$next[31:0]$2284 $1\wb_rd_data$next[31:0]$2290 + assign $0\xisr$next[23:0]$2285 $1\xisr$next[23:0]$2291 + attribute \src "libresoc.v:52649.5-52649.29" + switch \initial + attribute \src "libresoc.v:52649.9-52649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xisr$next[23:0]$2291 24'000000000000000000000000 + assign $1\cppr$next[7:0]$2286 8'00000000 + assign $1\mfrr$next[7:0]$2288 8'11111111 + assign $1\irq$next[0:0]$2287 1'0 + assign $1\wb_rd_data$next[31:0]$2290 0 + assign $1\wb_ack$next[0:0]$2289 1'0 + case + assign $1\cppr$next[7:0]$2286 \cppr$2 + assign $1\irq$next[0:0]$2287 \irq$4 + assign $1\mfrr$next[7:0]$2288 \mfrr$3 + assign $1\wb_ack$next[0:0]$2289 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$2290 \wb_rd_data$5 + assign $1\xisr$next[23:0]$2291 \xisr$1 + end + sync always + update \cppr$next $0\cppr$next[7:0]$2280 + update \irq$next $0\irq$next[0:0]$2281 + update \mfrr$next $0\mfrr$next[7:0]$2282 + update \wb_ack$next $0\wb_ack$next[0:0]$2283 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2284 + update \xisr$next $0\xisr$next[23:0]$2285 + end + attribute \src "libresoc.v:52664.3-52691.6" + process $proc$libresoc.v:52664$2292 + assign { } { } + assign { } { } + assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] + attribute \src "libresoc.v:52665.5-52665.29" + switch \initial + attribute \src "libresoc.v:52665.9-52665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xirr_accept_rd[0:0] $2\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\xirr_accept_rd[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\xirr_accept_rd[0:0] $3\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\xirr_accept_rd[0:0] 1'1 + case + assign $4\xirr_accept_rd[0:0] 1'0 + end + case + assign $3\xirr_accept_rd[0:0] 1'0 + end + end + case + assign $1\xirr_accept_rd[0:0] 1'0 + end + sync always + update \xirr_accept_rd $0\xirr_accept_rd[0:0] + end + attribute \src "libresoc.v:52692.3-52720.6" + process $proc$libresoc.v:52692$2293 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "libresoc.v:52693.5-52693.29" + switch \initial + attribute \src "libresoc.v:52693.9-52693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\be_out[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\be_out[31:0] $3\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign $3\be_out[31:0] [23:0] 24'000000000000000000000000 + assign $3\be_out[31:0] [31:24] \mfrr + case + assign $3\be_out[31:0] 0 + end + end + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "libresoc.v:52721.3-52730.6" + process $proc$libresoc.v:52721$2294 + assign { } { } + assign { } { } + assign $0\pending_priority[7:0] $1\pending_priority[7:0] + attribute \src "libresoc.v:52722.5-52722.29" + switch \initial + attribute \src "libresoc.v:52722.9-52722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pending_priority[7:0] \ics_i_pri + case + assign $1\pending_priority[7:0] 8'11111111 + end + sync always + update \pending_priority $0\pending_priority[7:0] + end + attribute \src "libresoc.v:52731.3-52742.6" + process $proc$libresoc.v:52731$2295 + assign { } { } + assign $0\min_pri[7:0] $1\min_pri[7:0] + attribute \src "libresoc.v:52732.5-52732.29" + switch \initial + attribute \src "libresoc.v:52732.9-52732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\min_pri[7:0] \mfrr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\min_pri[7:0] \pending_priority + end + sync always + update \min_pri $0\min_pri[7:0] + end + attribute \src "libresoc.v:52743.3-52751.6" + process $proc$libresoc.v:52743$2296 + assign { } { } + assign { } { } + assign $0\core_irq_o$next[0:0]$2297 $1\core_irq_o$next[0:0]$2298 + attribute \src "libresoc.v:52744.5-52744.29" + switch \initial + attribute \src "libresoc.v:52744.9-52744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_irq_o$next[0:0]$2298 1'0 + case + assign $1\core_irq_o$next[0:0]$2298 \irq + end + sync always + update \core_irq_o$next $0\core_irq_o$next[0:0]$2297 + end + attribute \src "libresoc.v:52752.3-52761.6" + process $proc$libresoc.v:52752$2299 + assign { } { } + assign { } { } + assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:52753.5-52753.29" + switch \initial + attribute \src "libresoc.v:52753.9-52753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" + switch \icp_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\icp_wb__dat_r[31:0] \wb_rd_data + case + assign $1\icp_wb__dat_r[31:0] 0 + end + sync always + update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] + end + attribute \src "libresoc.v:52762.3-52824.6" + process $proc$libresoc.v:52762$2300 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mfrr$11[7:0]$2303 $1\mfrr$11[7:0]$2308 + assign $0\wb_ack$14[0:0]$2304 $1\wb_ack$14[0:0]$2309 + assign { } { } + assign { } { } + assign { } { } + assign $0\xisr$9[23:0]$2306 $2\xisr$9[23:0]$2315 + assign $0\cppr$10[7:0]$2301 $4\cppr$10[7:0]$2316 + assign $0\wb_rd_data$13[31:0]$2305 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$2302 $1\irq$12[0:0]$2317 + attribute \src "libresoc.v:52763.5-52763.29" + switch \initial + attribute \src "libresoc.v:52763.9-52763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1\wb_ack$14[0:0]$2309 1'1 + assign $1\cppr$10[7:0]$2307 $2\cppr$10[7:0]$2310 + assign $1\mfrr$11[7:0]$2308 $2\mfrr$11[7:0]$2311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\cppr$10[7:0]$2310 $3\cppr$10[7:0]$2312 + assign $2\mfrr$11[7:0]$2311 $3\mfrr$11[7:0]$2313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\mfrr$11[7:0]$2313 \mfrr + assign $3\cppr$10[7:0]$2312 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\mfrr$11[7:0]$2313 \mfrr + assign $3\cppr$10[7:0]$2312 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign $3\cppr$10[7:0]$2312 \cppr + assign { } { } + assign $3\mfrr$11[7:0]$2313 \be_in [31:24] + case + assign $3\cppr$10[7:0]$2312 \cppr + assign $3\mfrr$11[7:0]$2313 \mfrr + end + case + assign $2\cppr$10[7:0]$2310 \cppr + assign $2\mfrr$11[7:0]$2311 \mfrr + end + case + assign $1\cppr$10[7:0]$2307 \cppr + assign $1\mfrr$11[7:0]$2308 \mfrr + assign $1\wb_ack$14[0:0]$2309 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xisr$9[23:0]$2314 { 20'00000000000000000001 \ics_i_src } + case + assign $1\xisr$9[23:0]$2314 24'000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xisr$9[23:0]$2315 24'000000000000000000000010 + case + assign $2\xisr$9[23:0]$2315 $1\xisr$9[23:0]$2314 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" + switch \xirr_accept_rd + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cppr$10[7:0]$2316 \min_pri + case + assign $4\cppr$10[7:0]$2316 $1\cppr$10[7:0]$2307 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + switch { \irq \$21 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\irq$12[0:0]$2317 1'1 + case + assign $1\irq$12[0:0]$2317 1'0 + end + sync always + update \cppr$10 $0\cppr$10[7:0]$2301 + update \irq$12 $0\irq$12[0:0]$2302 + update \mfrr$11 $0\mfrr$11[7:0]$2303 + update \wb_ack$14 $0\wb_ack$14[0:0]$2304 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2305 + update \xisr$9 $0\xisr$9[23:0]$2306 + end + connect \$15 $and$libresoc.v:52624$2262_Y + connect \$17 $ne$libresoc.v:52625$2263_Y + connect \$19 $lt$libresoc.v:52626$2264_Y + connect \$21 $lt$libresoc.v:52627$2265_Y + connect \$23 $and$libresoc.v:52628$2266_Y + connect \$25 $eq$libresoc.v:52629$2267_Y + connect \$27 $and$libresoc.v:52630$2268_Y + connect \$29 $ne$libresoc.v:52631$2269_Y + connect \$31 $lt$libresoc.v:52632$2270_Y + connect \$7 $and$libresoc.v:52633$2271_Y + connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } + connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } + connect \icp_wb__ack \$7 +end +attribute \src "libresoc.v:52832.1-53881.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" +attribute \generator "nMigen" +module \xics_ics + attribute \src "libresoc.v:53762.3-53811.6" + wire width 32 $0\be_out[31:0] + attribute \src "libresoc.v:53473.3-53482.6" + wire width 4 $0\cur_idx0[3:0] + attribute \src "libresoc.v:53682.3-53691.6" + wire width 4 $0\cur_idx10[3:0] + attribute \src "libresoc.v:53702.3-53711.6" + wire width 4 $0\cur_idx11[3:0] + attribute \src "libresoc.v:53722.3-53731.6" + wire width 4 $0\cur_idx12[3:0] + attribute \src "libresoc.v:53742.3-53751.6" + wire width 4 $0\cur_idx13[3:0] + attribute \src "libresoc.v:53812.3-53821.6" + wire width 4 $0\cur_idx14[3:0] + attribute \src "libresoc.v:53832.3-53841.6" + wire width 4 $0\cur_idx15[3:0] + attribute \src "libresoc.v:53493.3-53502.6" + wire width 4 $0\cur_idx1[3:0] + attribute \src "libresoc.v:53513.3-53522.6" + wire width 4 $0\cur_idx2[3:0] + attribute \src "libresoc.v:53533.3-53542.6" + wire width 4 $0\cur_idx3[3:0] + attribute \src "libresoc.v:53562.3-53571.6" + wire width 4 $0\cur_idx4[3:0] + attribute \src "libresoc.v:53582.3-53591.6" + wire width 4 $0\cur_idx5[3:0] + attribute \src "libresoc.v:53602.3-53611.6" + wire width 4 $0\cur_idx6[3:0] + attribute \src "libresoc.v:53622.3-53631.6" + wire width 4 $0\cur_idx7[3:0] + attribute \src "libresoc.v:53642.3-53651.6" + wire width 4 $0\cur_idx8[3:0] + attribute \src "libresoc.v:53662.3-53671.6" + wire width 4 $0\cur_idx9[3:0] + attribute \src "libresoc.v:53463.3-53472.6" + wire width 8 $0\cur_pri0[7:0] + attribute \src "libresoc.v:53672.3-53681.6" + wire width 8 $0\cur_pri10[7:0] + attribute \src "libresoc.v:53692.3-53701.6" + wire width 8 $0\cur_pri11[7:0] + attribute \src "libresoc.v:53712.3-53721.6" + wire width 8 $0\cur_pri12[7:0] + attribute \src "libresoc.v:53732.3-53741.6" + wire width 8 $0\cur_pri13[7:0] + attribute \src "libresoc.v:53752.3-53761.6" + wire width 8 $0\cur_pri14[7:0] + attribute \src "libresoc.v:53822.3-53831.6" + wire width 8 $0\cur_pri15[7:0] + attribute \src "libresoc.v:53483.3-53492.6" + wire width 8 $0\cur_pri1[7:0] + attribute \src "libresoc.v:53503.3-53512.6" + wire width 8 $0\cur_pri2[7:0] + attribute \src "libresoc.v:53523.3-53532.6" + wire width 8 $0\cur_pri3[7:0] + attribute \src "libresoc.v:53543.3-53552.6" + wire width 8 $0\cur_pri4[7:0] + attribute \src "libresoc.v:53572.3-53581.6" + wire width 8 $0\cur_pri5[7:0] + attribute \src "libresoc.v:53592.3-53601.6" + wire width 8 $0\cur_pri6[7:0] + attribute \src "libresoc.v:53612.3-53621.6" + wire width 8 $0\cur_pri7[7:0] + attribute \src "libresoc.v:53632.3-53641.6" + wire width 8 $0\cur_pri8[7:0] + attribute \src "libresoc.v:53652.3-53661.6" + wire width 8 $0\cur_pri9[7:0] + attribute \src "libresoc.v:53842.3-53851.6" + wire $0\ibit[0:0] + attribute \src "libresoc.v:53353.3-53354.25" + wire width 8 $0\icp_o_pri[7:0] + attribute \src "libresoc.v:53351.3-53352.28" + wire width 4 $0\icp_o_src[3:0] + attribute \src "libresoc.v:53861.3-53869.6" + wire $0\ics_wb__ack$next[0:0]$2572 + attribute \src "libresoc.v:53345.3-53346.39" + wire $0\ics_wb__ack[0:0] + attribute \src "libresoc.v:53852.3-53860.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$2569 + attribute \src "libresoc.v:53347.3-53348.43" + wire width 32 $0\ics_wb__dat_r[31:0] + attribute \src "libresoc.v:52833.7-52833.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:53553.3-53561.6" + wire width 16 $0\int_level_l$next[15:0]$2541 + attribute \src "libresoc.v:53349.3-53350.39" + wire width 16 $0\int_level_l[15:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive0_pri$next[7:0]$2451 + attribute \src "libresoc.v:53355.3-53356.35" + wire width 8 $0\xive0_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive10_pri$next[7:0]$2452 + attribute \src "libresoc.v:53375.3-53376.37" + wire width 8 $0\xive10_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive11_pri$next[7:0]$2453 + attribute \src "libresoc.v:53335.3-53336.37" + wire width 8 $0\xive11_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive12_pri$next[7:0]$2454 + attribute \src "libresoc.v:53337.3-53338.37" + wire width 8 $0\xive12_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive13_pri$next[7:0]$2455 + attribute \src "libresoc.v:53339.3-53340.37" + wire width 8 $0\xive13_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive14_pri$next[7:0]$2456 + attribute \src "libresoc.v:53341.3-53342.37" + wire width 8 $0\xive14_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive15_pri$next[7:0]$2457 + attribute \src "libresoc.v:53343.3-53344.37" + wire width 8 $0\xive15_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive1_pri$next[7:0]$2458 + attribute \src "libresoc.v:53357.3-53358.35" + wire width 8 $0\xive1_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive2_pri$next[7:0]$2459 + attribute \src "libresoc.v:53359.3-53360.35" + wire width 8 $0\xive2_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive3_pri$next[7:0]$2460 + attribute \src "libresoc.v:53361.3-53362.35" + wire width 8 $0\xive3_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive4_pri$next[7:0]$2461 + attribute \src "libresoc.v:53363.3-53364.35" + wire width 8 $0\xive4_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive5_pri$next[7:0]$2462 + attribute \src "libresoc.v:53365.3-53366.35" + wire width 8 $0\xive5_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive6_pri$next[7:0]$2463 + attribute \src "libresoc.v:53367.3-53368.35" + wire width 8 $0\xive6_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive7_pri$next[7:0]$2464 + attribute \src "libresoc.v:53369.3-53370.35" + wire width 8 $0\xive7_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive8_pri$next[7:0]$2465 + attribute \src "libresoc.v:53371.3-53372.35" + wire width 8 $0\xive8_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $0\xive9_pri$next[7:0]$2466 + attribute \src "libresoc.v:53373.3-53374.35" + wire width 8 $0\xive9_pri[7:0] + attribute \src "libresoc.v:53762.3-53811.6" + wire width 32 $1\be_out[31:0] + attribute \src "libresoc.v:53473.3-53482.6" + wire width 4 $1\cur_idx0[3:0] + attribute \src "libresoc.v:53682.3-53691.6" + wire width 4 $1\cur_idx10[3:0] + attribute \src "libresoc.v:53702.3-53711.6" + wire width 4 $1\cur_idx11[3:0] + attribute \src "libresoc.v:53722.3-53731.6" + wire width 4 $1\cur_idx12[3:0] + attribute \src "libresoc.v:53742.3-53751.6" + wire width 4 $1\cur_idx13[3:0] + attribute \src "libresoc.v:53812.3-53821.6" + wire width 4 $1\cur_idx14[3:0] + attribute \src "libresoc.v:53832.3-53841.6" + wire width 4 $1\cur_idx15[3:0] + attribute \src "libresoc.v:53493.3-53502.6" + wire width 4 $1\cur_idx1[3:0] + attribute \src "libresoc.v:53513.3-53522.6" + wire width 4 $1\cur_idx2[3:0] + attribute \src "libresoc.v:53533.3-53542.6" + wire width 4 $1\cur_idx3[3:0] + attribute \src "libresoc.v:53562.3-53571.6" + wire width 4 $1\cur_idx4[3:0] + attribute \src "libresoc.v:53582.3-53591.6" + wire width 4 $1\cur_idx5[3:0] + attribute \src "libresoc.v:53602.3-53611.6" + wire width 4 $1\cur_idx6[3:0] + attribute \src "libresoc.v:53622.3-53631.6" + wire width 4 $1\cur_idx7[3:0] + attribute \src "libresoc.v:53642.3-53651.6" + wire width 4 $1\cur_idx8[3:0] + attribute \src "libresoc.v:53662.3-53671.6" + wire width 4 $1\cur_idx9[3:0] + attribute \src "libresoc.v:53463.3-53472.6" + wire width 8 $1\cur_pri0[7:0] + attribute \src "libresoc.v:53672.3-53681.6" + wire width 8 $1\cur_pri10[7:0] + attribute \src "libresoc.v:53692.3-53701.6" + wire width 8 $1\cur_pri11[7:0] + attribute \src "libresoc.v:53712.3-53721.6" + wire width 8 $1\cur_pri12[7:0] + attribute \src "libresoc.v:53732.3-53741.6" + wire width 8 $1\cur_pri13[7:0] + attribute \src "libresoc.v:53752.3-53761.6" + wire width 8 $1\cur_pri14[7:0] + attribute \src "libresoc.v:53822.3-53831.6" + wire width 8 $1\cur_pri15[7:0] + attribute \src "libresoc.v:53483.3-53492.6" + wire width 8 $1\cur_pri1[7:0] + attribute \src "libresoc.v:53503.3-53512.6" + wire width 8 $1\cur_pri2[7:0] + attribute \src "libresoc.v:53523.3-53532.6" + wire width 8 $1\cur_pri3[7:0] + attribute \src "libresoc.v:53543.3-53552.6" + wire width 8 $1\cur_pri4[7:0] + attribute \src "libresoc.v:53572.3-53581.6" + wire width 8 $1\cur_pri5[7:0] + attribute \src "libresoc.v:53592.3-53601.6" + wire width 8 $1\cur_pri6[7:0] + attribute \src "libresoc.v:53612.3-53621.6" + wire width 8 $1\cur_pri7[7:0] + attribute \src "libresoc.v:53632.3-53641.6" + wire width 8 $1\cur_pri8[7:0] + attribute \src "libresoc.v:53652.3-53661.6" + wire width 8 $1\cur_pri9[7:0] + attribute \src "libresoc.v:53842.3-53851.6" + wire $1\ibit[0:0] + attribute \src "libresoc.v:53114.13-53114.30" + wire width 8 $1\icp_o_pri[7:0] + attribute \src "libresoc.v:53119.13-53119.29" + wire width 4 $1\icp_o_src[3:0] + attribute \src "libresoc.v:53861.3-53869.6" + wire $1\ics_wb__ack$next[0:0]$2573 + attribute \src "libresoc.v:53128.7-53128.25" + wire $1\ics_wb__ack[0:0] + attribute \src "libresoc.v:53852.3-53860.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$2570 + attribute \src "libresoc.v:53137.14-53137.35" + wire width 32 $1\ics_wb__dat_r[31:0] + attribute \src "libresoc.v:53553.3-53561.6" + wire width 16 $1\int_level_l$next[15:0]$2542 + attribute \src "libresoc.v:53149.14-53149.36" + wire width 16 $1\int_level_l[15:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive0_pri$next[7:0]$2467 + attribute \src "libresoc.v:53169.13-53169.30" + wire width 8 $1\xive0_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive10_pri$next[7:0]$2468 + attribute \src "libresoc.v:53173.13-53173.31" + wire width 8 $1\xive10_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive11_pri$next[7:0]$2469 + attribute \src "libresoc.v:53177.13-53177.31" + wire width 8 $1\xive11_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive12_pri$next[7:0]$2470 + attribute \src "libresoc.v:53181.13-53181.31" + wire width 8 $1\xive12_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive13_pri$next[7:0]$2471 + attribute \src "libresoc.v:53185.13-53185.31" + wire width 8 $1\xive13_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive14_pri$next[7:0]$2472 + attribute \src "libresoc.v:53189.13-53189.31" + wire width 8 $1\xive14_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive15_pri$next[7:0]$2473 + attribute \src "libresoc.v:53193.13-53193.31" + wire width 8 $1\xive15_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive1_pri$next[7:0]$2474 + attribute \src "libresoc.v:53197.13-53197.30" + wire width 8 $1\xive1_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive2_pri$next[7:0]$2475 + attribute \src "libresoc.v:53201.13-53201.30" + wire width 8 $1\xive2_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive3_pri$next[7:0]$2476 + attribute \src "libresoc.v:53205.13-53205.30" + wire width 8 $1\xive3_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive4_pri$next[7:0]$2477 + attribute \src "libresoc.v:53209.13-53209.30" + wire width 8 $1\xive4_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive5_pri$next[7:0]$2478 + attribute \src "libresoc.v:53213.13-53213.30" + wire width 8 $1\xive5_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive6_pri$next[7:0]$2479 + attribute \src "libresoc.v:53217.13-53217.30" + wire width 8 $1\xive6_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive7_pri$next[7:0]$2480 + attribute \src "libresoc.v:53221.13-53221.30" + wire width 8 $1\xive7_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive8_pri$next[7:0]$2481 + attribute \src "libresoc.v:53225.13-53225.30" + wire width 8 $1\xive8_pri[7:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $1\xive9_pri$next[7:0]$2482 + attribute \src "libresoc.v:53229.13-53229.30" + wire width 8 $1\xive9_pri[7:0] + attribute \src "libresoc.v:53762.3-53811.6" + wire width 32 $2\be_out[31:0] + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive0_pri$next[7:0]$2483 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive10_pri$next[7:0]$2484 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive11_pri$next[7:0]$2485 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive12_pri$next[7:0]$2486 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive13_pri$next[7:0]$2487 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive14_pri$next[7:0]$2488 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive15_pri$next[7:0]$2489 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive1_pri$next[7:0]$2490 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive2_pri$next[7:0]$2491 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive3_pri$next[7:0]$2492 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive4_pri$next[7:0]$2493 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive5_pri$next[7:0]$2494 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive6_pri$next[7:0]$2495 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive7_pri$next[7:0]$2496 + attribute \src "libresoc.v:53377.3-53462.6" + wire width 8 $2\xive8_pri$next[7:0]$2497 + attribute \src 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$lt$libresoc.v:53241$2335_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53243$2337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive5_pri + connect \B \cur_pri4 + connect \Y $lt$libresoc.v:53243$2337_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53245$2339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive6_pri + connect \B \cur_pri5 + connect \Y $lt$libresoc.v:53245$2339_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53247$2341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive6_pri + connect \B \cur_pri5 + connect \Y $lt$libresoc.v:53247$2341_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53250$2344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive7_pri + connect \B \cur_pri6 + connect \Y $lt$libresoc.v:53250$2344_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53252$2346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive7_pri + connect \B \cur_pri6 + connect \Y $lt$libresoc.v:53252$2346_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53255$2349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive8_pri + connect \B \cur_pri7 + connect \Y $lt$libresoc.v:53255$2349_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53257$2351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive8_pri + connect \B \cur_pri7 + connect \Y $lt$libresoc.v:53257$2351_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53259$2353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive9_pri + connect \B \cur_pri8 + connect \Y $lt$libresoc.v:53259$2353_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53261$2355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive9_pri + connect \B \cur_pri8 + connect \Y $lt$libresoc.v:53261$2355_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53263$2357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive10_pri + connect \B \cur_pri9 + connect \Y $lt$libresoc.v:53263$2357_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53265$2359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive10_pri + connect \B \cur_pri9 + connect \Y $lt$libresoc.v:53265$2359_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53267$2361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive11_pri + connect \B \cur_pri10 + connect \Y $lt$libresoc.v:53267$2361_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53269$2363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive11_pri + connect \B \cur_pri10 + connect \Y $lt$libresoc.v:53269$2363_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53272$2366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive12_pri + connect \B \cur_pri11 + connect \Y $lt$libresoc.v:53272$2366_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53274$2368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive12_pri + connect \B \cur_pri11 + connect \Y $lt$libresoc.v:53274$2368_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53277$2371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive13_pri + connect \B \cur_pri12 + connect \Y $lt$libresoc.v:53277$2371_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53279$2373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive13_pri + connect \B \cur_pri12 + connect \Y $lt$libresoc.v:53279$2373_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53281$2375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B \cur_pri13 + connect \Y $lt$libresoc.v:53281$2375_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53283$2377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B \cur_pri13 + connect \Y $lt$libresoc.v:53283$2377_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53285$2379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B \cur_pri14 + connect \Y $lt$libresoc.v:53285$2379_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53288$2382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B \cur_pri14 + connect \Y $lt$libresoc.v:53288$2382_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53322$2416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$libresoc.v:53322$2416_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53324$2418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$libresoc.v:53324$2418_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53326$2420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$libresoc.v:53326$2420_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53328$2422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$libresoc.v:53328$2422_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53331$2425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$libresoc.v:53331$2425_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:53333$2427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$libresoc.v:53333$2427_Y + end + attribute \src "libresoc.v:53320.18-53320.40" + cell $shr $shr$libresoc.v:53320$2414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \int_level_l + connect \B \reg_idx + connect \Y $shr$libresoc.v:53320$2414_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53232$2326 + parameter \WIDTH 8 + connect \A \xive0_pri + connect \B 8'11111111 + connect \S \$8 + connect \Y $ternary$libresoc.v:53232$2326_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53254$2348 + parameter \WIDTH 8 + connect \A \xive1_pri + connect \B 8'11111111 + connect \S \$12 + connect \Y $ternary$libresoc.v:53254$2348_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53276$2370 + parameter \WIDTH 8 + connect \A \xive2_pri + connect \B 8'11111111 + connect \S \$16 + connect \Y $ternary$libresoc.v:53276$2370_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53291$2385 + parameter \WIDTH 8 + connect \A \cur_pri15 + connect \B 8'11111111 + connect \S \$204 + connect \Y $ternary$libresoc.v:53291$2385_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53293$2387 + parameter \WIDTH 8 + connect \A \xive3_pri + connect \B 8'11111111 + connect \S \$20 + connect \Y $ternary$libresoc.v:53293$2387_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53295$2389 + parameter \WIDTH 8 + connect \A \xive4_pri + connect \B 8'11111111 + connect \S \$24 + connect \Y $ternary$libresoc.v:53295$2389_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53297$2391 + parameter \WIDTH 8 + connect \A \xive5_pri + connect \B 8'11111111 + connect \S \$28 + connect \Y $ternary$libresoc.v:53297$2391_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53299$2393 + parameter \WIDTH 8 + connect \A \xive6_pri + connect \B 8'11111111 + connect \S \$32 + connect \Y $ternary$libresoc.v:53299$2393_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53301$2395 + parameter \WIDTH 8 + connect \A \xive7_pri + connect \B 8'11111111 + connect \S \$36 + connect \Y $ternary$libresoc.v:53301$2395_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53304$2398 + parameter \WIDTH 8 + connect \A \xive8_pri + connect \B 8'11111111 + connect \S \$40 + connect \Y $ternary$libresoc.v:53304$2398_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53306$2400 + parameter \WIDTH 8 + connect \A \xive9_pri + connect \B 8'11111111 + connect \S \$44 + connect \Y $ternary$libresoc.v:53306$2400_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53308$2402 + parameter \WIDTH 8 + connect \A \xive10_pri + connect \B 8'11111111 + connect \S \$48 + connect \Y $ternary$libresoc.v:53308$2402_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53310$2404 + parameter \WIDTH 8 + connect \A \xive11_pri + connect \B 8'11111111 + connect \S \$52 + connect \Y $ternary$libresoc.v:53310$2404_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53312$2406 + parameter \WIDTH 8 + connect \A \xive12_pri + connect \B 8'11111111 + connect \S \$56 + connect \Y $ternary$libresoc.v:53312$2406_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53315$2409 + parameter \WIDTH 8 + connect \A \xive13_pri + connect \B 8'11111111 + connect \S \$60 + connect \Y $ternary$libresoc.v:53315$2409_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53317$2411 + parameter \WIDTH 8 + connect \A \xive14_pri + connect \B 8'11111111 + connect \S \$64 + connect \Y $ternary$libresoc.v:53317$2411_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:53319$2413 + parameter \WIDTH 8 + connect \A \xive15_pri + connect \B 8'11111111 + connect \S \$68 + connect \Y $ternary$libresoc.v:53319$2413_Y + end + attribute \src "libresoc.v:52833.7-52833.20" + process $proc$libresoc.v:52833$2574 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:53114.13-53114.30" + process $proc$libresoc.v:53114$2575 + assign { } { } + assign $1\icp_o_pri[7:0] 8'00000000 + sync always + sync init + update \icp_o_pri $1\icp_o_pri[7:0] + end + attribute \src "libresoc.v:53119.13-53119.29" + process $proc$libresoc.v:53119$2576 + assign { } { } + assign $1\icp_o_src[3:0] 4'0000 + sync always + sync init + update \icp_o_src $1\icp_o_src[3:0] + end + attribute \src "libresoc.v:53128.7-53128.25" + process $proc$libresoc.v:53128$2577 + assign { } { } + assign $1\ics_wb__ack[0:0] 1'0 + sync always + sync init + update \ics_wb__ack $1\ics_wb__ack[0:0] + end + attribute \src "libresoc.v:53137.14-53137.35" + process $proc$libresoc.v:53137$2578 + assign { } { } + assign $1\ics_wb__dat_r[31:0] 0 + sync always + sync init + update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] + end + attribute \src "libresoc.v:53149.14-53149.36" + process $proc$libresoc.v:53149$2579 + assign { } { } + assign $1\int_level_l[15:0] 16'0000000000000000 + sync always + sync init + update \int_level_l $1\int_level_l[15:0] + end + attribute \src "libresoc.v:53169.13-53169.30" + process $proc$libresoc.v:53169$2580 + assign { } { } + assign $1\xive0_pri[7:0] 8'11111111 + sync always + sync init + update \xive0_pri $1\xive0_pri[7:0] + end + attribute \src "libresoc.v:53173.13-53173.31" + process $proc$libresoc.v:53173$2581 + assign { } { } + assign $1\xive10_pri[7:0] 8'11111111 + sync always + sync init + update \xive10_pri $1\xive10_pri[7:0] + end + attribute \src "libresoc.v:53177.13-53177.31" + process $proc$libresoc.v:53177$2582 + assign { } { } + assign $1\xive11_pri[7:0] 8'11111111 + sync always + sync init + update \xive11_pri $1\xive11_pri[7:0] + end + attribute \src "libresoc.v:53181.13-53181.31" + process $proc$libresoc.v:53181$2583 + assign { } { } + assign $1\xive12_pri[7:0] 8'11111111 + sync always + sync init + update \xive12_pri $1\xive12_pri[7:0] + end + attribute \src "libresoc.v:53185.13-53185.31" + process $proc$libresoc.v:53185$2584 + assign { } { } + assign $1\xive13_pri[7:0] 8'11111111 + sync always + sync init + update \xive13_pri $1\xive13_pri[7:0] + end + attribute \src "libresoc.v:53189.13-53189.31" + process $proc$libresoc.v:53189$2585 + assign { } { } + assign $1\xive14_pri[7:0] 8'11111111 + sync always + sync init + update \xive14_pri $1\xive14_pri[7:0] + end + attribute \src "libresoc.v:53193.13-53193.31" + process $proc$libresoc.v:53193$2586 + assign { } { } + assign $1\xive15_pri[7:0] 8'11111111 + sync always + sync init + update \xive15_pri $1\xive15_pri[7:0] + end + attribute \src "libresoc.v:53197.13-53197.30" + process $proc$libresoc.v:53197$2587 + assign { } { } + assign $1\xive1_pri[7:0] 8'11111111 + sync always + sync init + update \xive1_pri $1\xive1_pri[7:0] + end + attribute \src "libresoc.v:53201.13-53201.30" + process $proc$libresoc.v:53201$2588 + assign { } { } + assign $1\xive2_pri[7:0] 8'11111111 + sync always + sync init + update \xive2_pri $1\xive2_pri[7:0] + end + attribute \src "libresoc.v:53205.13-53205.30" + process $proc$libresoc.v:53205$2589 + assign { } { } + assign $1\xive3_pri[7:0] 8'11111111 + sync always + sync init + update \xive3_pri $1\xive3_pri[7:0] + end + attribute \src "libresoc.v:53209.13-53209.30" + process $proc$libresoc.v:53209$2590 + assign { } { } + assign $1\xive4_pri[7:0] 8'11111111 + sync always + sync init + update \xive4_pri $1\xive4_pri[7:0] + end + attribute \src "libresoc.v:53213.13-53213.30" + process $proc$libresoc.v:53213$2591 + assign { } { } + assign $1\xive5_pri[7:0] 8'11111111 + sync always + sync init + update \xive5_pri $1\xive5_pri[7:0] + end + attribute \src "libresoc.v:53217.13-53217.30" + process $proc$libresoc.v:53217$2592 + assign { } { } + assign $1\xive6_pri[7:0] 8'11111111 + sync always + sync init + update \xive6_pri $1\xive6_pri[7:0] + end + attribute \src "libresoc.v:53221.13-53221.30" + process $proc$libresoc.v:53221$2593 + assign { } { } + assign $1\xive7_pri[7:0] 8'11111111 + sync always + sync init + update \xive7_pri $1\xive7_pri[7:0] + end + attribute \src "libresoc.v:53225.13-53225.30" + process $proc$libresoc.v:53225$2594 + assign { } { } + assign $1\xive8_pri[7:0] 8'11111111 + sync always + sync init + update \xive8_pri $1\xive8_pri[7:0] + end + attribute \src "libresoc.v:53229.13-53229.30" + process $proc$libresoc.v:53229$2595 + assign { } { } + assign $1\xive9_pri[7:0] 8'11111111 + sync always + sync init + update \xive9_pri $1\xive9_pri[7:0] + end + attribute \src "libresoc.v:53335.3-53336.37" + process $proc$libresoc.v:53335$2429 + assign { } { } + assign $0\xive11_pri[7:0] \xive11_pri$next + sync posedge \clk + update \xive11_pri $0\xive11_pri[7:0] + end + attribute \src "libresoc.v:53337.3-53338.37" + process $proc$libresoc.v:53337$2430 + assign { } { } + assign $0\xive12_pri[7:0] \xive12_pri$next + sync posedge \clk + update \xive12_pri $0\xive12_pri[7:0] + end + attribute \src "libresoc.v:53339.3-53340.37" + process $proc$libresoc.v:53339$2431 + assign { } { } + assign $0\xive13_pri[7:0] \xive13_pri$next + sync posedge \clk + update \xive13_pri $0\xive13_pri[7:0] + end + attribute \src "libresoc.v:53341.3-53342.37" + process $proc$libresoc.v:53341$2432 + assign { } { } + assign $0\xive14_pri[7:0] \xive14_pri$next + sync posedge \clk + update \xive14_pri $0\xive14_pri[7:0] + end + attribute \src "libresoc.v:53343.3-53344.37" + process $proc$libresoc.v:53343$2433 + assign { } { } + assign $0\xive15_pri[7:0] \xive15_pri$next + sync posedge \clk + update \xive15_pri $0\xive15_pri[7:0] + end + attribute \src "libresoc.v:53345.3-53346.39" + process $proc$libresoc.v:53345$2434 + assign { } { } + assign $0\ics_wb__ack[0:0] \ics_wb__ack$next + sync posedge \clk + update \ics_wb__ack $0\ics_wb__ack[0:0] + end + attribute \src "libresoc.v:53347.3-53348.43" + process $proc$libresoc.v:53347$2435 + assign { } { } + assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next + sync posedge \clk + update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] + end + attribute \src "libresoc.v:53349.3-53350.39" + process $proc$libresoc.v:53349$2436 + assign { } { } + assign $0\int_level_l[15:0] \int_level_l$next + sync posedge \clk + update \int_level_l $0\int_level_l[15:0] + end + attribute \src "libresoc.v:53351.3-53352.28" + process $proc$libresoc.v:53351$2437 + assign { } { } + assign $0\icp_o_src[3:0] \cur_idx15 + sync posedge \clk + update \icp_o_src $0\icp_o_src[3:0] + end + attribute \src "libresoc.v:53353.3-53354.25" + process $proc$libresoc.v:53353$2438 + assign { } { } + assign $0\icp_o_pri[7:0] \$203 + sync posedge \clk + update \icp_o_pri $0\icp_o_pri[7:0] + end + attribute \src "libresoc.v:53355.3-53356.35" + process $proc$libresoc.v:53355$2439 + assign { } { } + assign $0\xive0_pri[7:0] \xive0_pri$next + sync posedge \clk + update \xive0_pri $0\xive0_pri[7:0] + end + attribute \src "libresoc.v:53357.3-53358.35" + process $proc$libresoc.v:53357$2440 + assign { } { } + assign $0\xive1_pri[7:0] \xive1_pri$next + sync posedge \clk + update \xive1_pri $0\xive1_pri[7:0] + end + attribute \src "libresoc.v:53359.3-53360.35" + process $proc$libresoc.v:53359$2441 + assign { } { } + assign $0\xive2_pri[7:0] \xive2_pri$next + sync posedge \clk + update \xive2_pri $0\xive2_pri[7:0] + end + attribute \src "libresoc.v:53361.3-53362.35" + process $proc$libresoc.v:53361$2442 + assign { } { } + assign $0\xive3_pri[7:0] \xive3_pri$next + sync posedge \clk + update \xive3_pri $0\xive3_pri[7:0] + end + attribute \src "libresoc.v:53363.3-53364.35" + process $proc$libresoc.v:53363$2443 + assign { } { } + assign $0\xive4_pri[7:0] \xive4_pri$next + sync posedge \clk + update \xive4_pri $0\xive4_pri[7:0] + end + attribute \src "libresoc.v:53365.3-53366.35" + process $proc$libresoc.v:53365$2444 + assign { } { } + assign $0\xive5_pri[7:0] \xive5_pri$next + sync posedge \clk + update \xive5_pri $0\xive5_pri[7:0] + end + attribute \src "libresoc.v:53367.3-53368.35" + process $proc$libresoc.v:53367$2445 + assign { } { } + assign $0\xive6_pri[7:0] \xive6_pri$next + sync posedge \clk + update \xive6_pri $0\xive6_pri[7:0] + end + attribute \src "libresoc.v:53369.3-53370.35" + process $proc$libresoc.v:53369$2446 + assign { } { } + assign $0\xive7_pri[7:0] \xive7_pri$next + sync posedge \clk + update \xive7_pri $0\xive7_pri[7:0] + end + attribute \src "libresoc.v:53371.3-53372.35" + process $proc$libresoc.v:53371$2447 + assign { } { } + assign $0\xive8_pri[7:0] \xive8_pri$next + sync posedge \clk + update \xive8_pri $0\xive8_pri[7:0] + end + attribute \src "libresoc.v:53373.3-53374.35" + process $proc$libresoc.v:53373$2448 + assign { } { } + assign $0\xive9_pri[7:0] \xive9_pri$next + sync posedge \clk + update \xive9_pri $0\xive9_pri[7:0] + end + attribute \src "libresoc.v:53375.3-53376.37" + process $proc$libresoc.v:53375$2449 + assign { } { } + assign $0\xive10_pri[7:0] \xive10_pri$next + sync posedge \clk + update \xive10_pri $0\xive10_pri[7:0] + end + attribute \src "libresoc.v:53377.3-53462.6" + process $proc$libresoc.v:53377$2450 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xive0_pri$next[7:0]$2451 $4\xive0_pri$next[7:0]$2515 + assign $0\xive10_pri$next[7:0]$2452 $4\xive10_pri$next[7:0]$2516 + assign $0\xive11_pri$next[7:0]$2453 $4\xive11_pri$next[7:0]$2517 + assign $0\xive12_pri$next[7:0]$2454 $4\xive12_pri$next[7:0]$2518 + assign $0\xive13_pri$next[7:0]$2455 $4\xive13_pri$next[7:0]$2519 + assign $0\xive14_pri$next[7:0]$2456 $4\xive14_pri$next[7:0]$2520 + assign $0\xive15_pri$next[7:0]$2457 $4\xive15_pri$next[7:0]$2521 + assign $0\xive1_pri$next[7:0]$2458 $4\xive1_pri$next[7:0]$2522 + assign $0\xive2_pri$next[7:0]$2459 $4\xive2_pri$next[7:0]$2523 + assign $0\xive3_pri$next[7:0]$2460 $4\xive3_pri$next[7:0]$2524 + assign $0\xive4_pri$next[7:0]$2461 $4\xive4_pri$next[7:0]$2525 + assign $0\xive5_pri$next[7:0]$2462 $4\xive5_pri$next[7:0]$2526 + assign $0\xive6_pri$next[7:0]$2463 $4\xive6_pri$next[7:0]$2527 + assign $0\xive7_pri$next[7:0]$2464 $4\xive7_pri$next[7:0]$2528 + assign $0\xive8_pri$next[7:0]$2465 $4\xive8_pri$next[7:0]$2529 + assign $0\xive9_pri$next[7:0]$2466 $4\xive9_pri$next[7:0]$2530 + attribute \src "libresoc.v:53378.5-53378.29" + switch \initial + attribute \src "libresoc.v:53378.9-53378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xive0_pri$next[7:0]$2467 $2\xive0_pri$next[7:0]$2483 + assign $1\xive10_pri$next[7:0]$2468 $2\xive10_pri$next[7:0]$2484 + assign $1\xive11_pri$next[7:0]$2469 $2\xive11_pri$next[7:0]$2485 + assign $1\xive12_pri$next[7:0]$2470 $2\xive12_pri$next[7:0]$2486 + assign $1\xive13_pri$next[7:0]$2471 $2\xive13_pri$next[7:0]$2487 + assign $1\xive14_pri$next[7:0]$2472 $2\xive14_pri$next[7:0]$2488 + assign $1\xive15_pri$next[7:0]$2473 $2\xive15_pri$next[7:0]$2489 + assign $1\xive1_pri$next[7:0]$2474 $2\xive1_pri$next[7:0]$2490 + assign $1\xive2_pri$next[7:0]$2475 $2\xive2_pri$next[7:0]$2491 + assign $1\xive3_pri$next[7:0]$2476 $2\xive3_pri$next[7:0]$2492 + assign $1\xive4_pri$next[7:0]$2477 $2\xive4_pri$next[7:0]$2493 + assign $1\xive5_pri$next[7:0]$2478 $2\xive5_pri$next[7:0]$2494 + assign $1\xive6_pri$next[7:0]$2479 $2\xive6_pri$next[7:0]$2495 + assign $1\xive7_pri$next[7:0]$2480 $2\xive7_pri$next[7:0]$2496 + assign $1\xive8_pri$next[7:0]$2481 $2\xive8_pri$next[7:0]$2497 + assign $1\xive9_pri$next[7:0]$2482 $2\xive9_pri$next[7:0]$2498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" + switch \reg_is_xive + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\xive0_pri$next[7:0]$2483 $3\xive0_pri$next[7:0]$2499 + assign $2\xive10_pri$next[7:0]$2484 $3\xive10_pri$next[7:0]$2500 + assign $2\xive11_pri$next[7:0]$2485 $3\xive11_pri$next[7:0]$2501 + assign $2\xive12_pri$next[7:0]$2486 $3\xive12_pri$next[7:0]$2502 + assign $2\xive13_pri$next[7:0]$2487 $3\xive13_pri$next[7:0]$2503 + assign $2\xive14_pri$next[7:0]$2488 $3\xive14_pri$next[7:0]$2504 + assign $2\xive15_pri$next[7:0]$2489 $3\xive15_pri$next[7:0]$2505 + assign $2\xive1_pri$next[7:0]$2490 $3\xive1_pri$next[7:0]$2506 + assign $2\xive2_pri$next[7:0]$2491 $3\xive2_pri$next[7:0]$2507 + assign $2\xive3_pri$next[7:0]$2492 $3\xive3_pri$next[7:0]$2508 + assign $2\xive4_pri$next[7:0]$2493 $3\xive4_pri$next[7:0]$2509 + assign $2\xive5_pri$next[7:0]$2494 $3\xive5_pri$next[7:0]$2510 + assign $2\xive6_pri$next[7:0]$2495 $3\xive6_pri$next[7:0]$2511 + assign $2\xive7_pri$next[7:0]$2496 $3\xive7_pri$next[7:0]$2512 + assign $2\xive8_pri$next[7:0]$2497 $3\xive8_pri$next[7:0]$2513 + assign $2\xive9_pri$next[7:0]$2498 $3\xive9_pri$next[7:0]$2514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" + switch \reg_idx + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive0_pri$next[7:0]$2499 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign { } { } + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive1_pri$next[7:0]$2506 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign { } { } + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive2_pri$next[7:0]$2507 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign { } { } + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive3_pri$next[7:0]$2508 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign { } { } + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive4_pri$next[7:0]$2509 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign { } { } + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive5_pri$next[7:0]$2510 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign { } { } + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive6_pri$next[7:0]$2511 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign { } { } + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive7_pri$next[7:0]$2512 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive8_pri$next[7:0]$2513 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$2514 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign { } { } + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive10_pri$next[7:0]$2500 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign { } { } + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive11_pri$next[7:0]$2501 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1100 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign { } { } + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive12_pri$next[7:0]$2502 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign { } { } + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive13_pri$next[7:0]$2503 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1110 + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign { } { } + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive14_pri$next[7:0]$2504 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'---- + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign { } { } + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + assign $3\xive15_pri$next[7:0]$2505 \be_in [7:0] + case + assign $3\xive0_pri$next[7:0]$2499 \xive0_pri + assign $3\xive10_pri$next[7:0]$2500 \xive10_pri + assign $3\xive11_pri$next[7:0]$2501 \xive11_pri + assign $3\xive12_pri$next[7:0]$2502 \xive12_pri + assign $3\xive13_pri$next[7:0]$2503 \xive13_pri + assign $3\xive14_pri$next[7:0]$2504 \xive14_pri + assign $3\xive15_pri$next[7:0]$2505 \xive15_pri + assign $3\xive1_pri$next[7:0]$2506 \xive1_pri + assign $3\xive2_pri$next[7:0]$2507 \xive2_pri + assign $3\xive3_pri$next[7:0]$2508 \xive3_pri + assign $3\xive4_pri$next[7:0]$2509 \xive4_pri + assign $3\xive5_pri$next[7:0]$2510 \xive5_pri + assign $3\xive6_pri$next[7:0]$2511 \xive6_pri + assign $3\xive7_pri$next[7:0]$2512 \xive7_pri + assign $3\xive8_pri$next[7:0]$2513 \xive8_pri + assign $3\xive9_pri$next[7:0]$2514 \xive9_pri + end + case + assign $2\xive0_pri$next[7:0]$2483 \xive0_pri + assign $2\xive10_pri$next[7:0]$2484 \xive10_pri + assign $2\xive11_pri$next[7:0]$2485 \xive11_pri + assign $2\xive12_pri$next[7:0]$2486 \xive12_pri + assign $2\xive13_pri$next[7:0]$2487 \xive13_pri + assign $2\xive14_pri$next[7:0]$2488 \xive14_pri + assign $2\xive15_pri$next[7:0]$2489 \xive15_pri + assign $2\xive1_pri$next[7:0]$2490 \xive1_pri + assign $2\xive2_pri$next[7:0]$2491 \xive2_pri + assign $2\xive3_pri$next[7:0]$2492 \xive3_pri + assign $2\xive4_pri$next[7:0]$2493 \xive4_pri + assign $2\xive5_pri$next[7:0]$2494 \xive5_pri + assign $2\xive6_pri$next[7:0]$2495 \xive6_pri + assign $2\xive7_pri$next[7:0]$2496 \xive7_pri + assign $2\xive8_pri$next[7:0]$2497 \xive8_pri + assign $2\xive9_pri$next[7:0]$2498 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$2467 \xive0_pri + assign $1\xive10_pri$next[7:0]$2468 \xive10_pri + assign $1\xive11_pri$next[7:0]$2469 \xive11_pri + assign $1\xive12_pri$next[7:0]$2470 \xive12_pri + assign $1\xive13_pri$next[7:0]$2471 \xive13_pri + assign $1\xive14_pri$next[7:0]$2472 \xive14_pri + assign $1\xive15_pri$next[7:0]$2473 \xive15_pri + assign $1\xive1_pri$next[7:0]$2474 \xive1_pri + assign $1\xive2_pri$next[7:0]$2475 \xive2_pri + assign $1\xive3_pri$next[7:0]$2476 \xive3_pri + assign $1\xive4_pri$next[7:0]$2477 \xive4_pri + assign $1\xive5_pri$next[7:0]$2478 \xive5_pri + assign $1\xive6_pri$next[7:0]$2479 \xive6_pri + assign $1\xive7_pri$next[7:0]$2480 \xive7_pri + assign $1\xive8_pri$next[7:0]$2481 \xive8_pri + assign $1\xive9_pri$next[7:0]$2482 \xive9_pri + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\xive0_pri$next[7:0]$2515 8'11111111 + assign $4\xive1_pri$next[7:0]$2522 8'11111111 + assign $4\xive2_pri$next[7:0]$2523 8'11111111 + assign $4\xive3_pri$next[7:0]$2524 8'11111111 + assign $4\xive4_pri$next[7:0]$2525 8'11111111 + assign $4\xive5_pri$next[7:0]$2526 8'11111111 + assign $4\xive6_pri$next[7:0]$2527 8'11111111 + assign $4\xive7_pri$next[7:0]$2528 8'11111111 + assign $4\xive8_pri$next[7:0]$2529 8'11111111 + assign $4\xive9_pri$next[7:0]$2530 8'11111111 + assign $4\xive10_pri$next[7:0]$2516 8'11111111 + assign $4\xive11_pri$next[7:0]$2517 8'11111111 + assign $4\xive12_pri$next[7:0]$2518 8'11111111 + assign $4\xive13_pri$next[7:0]$2519 8'11111111 + assign $4\xive14_pri$next[7:0]$2520 8'11111111 + assign $4\xive15_pri$next[7:0]$2521 8'11111111 + case + assign $4\xive0_pri$next[7:0]$2515 $1\xive0_pri$next[7:0]$2467 + assign $4\xive10_pri$next[7:0]$2516 $1\xive10_pri$next[7:0]$2468 + assign $4\xive11_pri$next[7:0]$2517 $1\xive11_pri$next[7:0]$2469 + assign $4\xive12_pri$next[7:0]$2518 $1\xive12_pri$next[7:0]$2470 + assign $4\xive13_pri$next[7:0]$2519 $1\xive13_pri$next[7:0]$2471 + assign $4\xive14_pri$next[7:0]$2520 $1\xive14_pri$next[7:0]$2472 + assign $4\xive15_pri$next[7:0]$2521 $1\xive15_pri$next[7:0]$2473 + assign $4\xive1_pri$next[7:0]$2522 $1\xive1_pri$next[7:0]$2474 + assign $4\xive2_pri$next[7:0]$2523 $1\xive2_pri$next[7:0]$2475 + assign $4\xive3_pri$next[7:0]$2524 $1\xive3_pri$next[7:0]$2476 + assign $4\xive4_pri$next[7:0]$2525 $1\xive4_pri$next[7:0]$2477 + assign $4\xive5_pri$next[7:0]$2526 $1\xive5_pri$next[7:0]$2478 + assign $4\xive6_pri$next[7:0]$2527 $1\xive6_pri$next[7:0]$2479 + assign $4\xive7_pri$next[7:0]$2528 $1\xive7_pri$next[7:0]$2480 + assign $4\xive8_pri$next[7:0]$2529 $1\xive8_pri$next[7:0]$2481 + assign $4\xive9_pri$next[7:0]$2530 $1\xive9_pri$next[7:0]$2482 + end + sync always + update \xive0_pri$next $0\xive0_pri$next[7:0]$2451 + update \xive10_pri$next $0\xive10_pri$next[7:0]$2452 + update \xive11_pri$next $0\xive11_pri$next[7:0]$2453 + update \xive12_pri$next $0\xive12_pri$next[7:0]$2454 + update \xive13_pri$next $0\xive13_pri$next[7:0]$2455 + update \xive14_pri$next $0\xive14_pri$next[7:0]$2456 + update \xive15_pri$next $0\xive15_pri$next[7:0]$2457 + update \xive1_pri$next $0\xive1_pri$next[7:0]$2458 + update \xive2_pri$next $0\xive2_pri$next[7:0]$2459 + update \xive3_pri$next $0\xive3_pri$next[7:0]$2460 + update \xive4_pri$next $0\xive4_pri$next[7:0]$2461 + update \xive5_pri$next $0\xive5_pri$next[7:0]$2462 + update \xive6_pri$next $0\xive6_pri$next[7:0]$2463 + update \xive7_pri$next $0\xive7_pri$next[7:0]$2464 + update \xive8_pri$next $0\xive8_pri$next[7:0]$2465 + update \xive9_pri$next $0\xive9_pri$next[7:0]$2466 + end + attribute \src "libresoc.v:53463.3-53472.6" + process $proc$libresoc.v:53463$2531 + assign { } { } + assign { } { } + assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] + attribute \src "libresoc.v:53464.5-53464.29" + switch \initial + attribute \src "libresoc.v:53464.9-53464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri0[7:0] \xive0_pri + case + assign $1\cur_pri0[7:0] \max_pri + end + sync always + update \cur_pri0 $0\cur_pri0[7:0] + end + attribute \src "libresoc.v:53473.3-53482.6" + process $proc$libresoc.v:53473$2532 + assign { } { } + assign { } { } + assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] + attribute \src "libresoc.v:53474.5-53474.29" + switch \initial + attribute \src "libresoc.v:53474.9-53474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx0[3:0] 4'0000 + case + assign $1\cur_idx0[3:0] \max_idx + end + sync always + update \cur_idx0 $0\cur_idx0[3:0] + end + attribute \src "libresoc.v:53483.3-53492.6" + process $proc$libresoc.v:53483$2533 + assign { } { } + assign { } { } + assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] + attribute \src "libresoc.v:53484.5-53484.29" + switch \initial + attribute \src "libresoc.v:53484.9-53484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri1[7:0] \xive1_pri + case + assign $1\cur_pri1[7:0] \cur_pri0 + end + sync always + update \cur_pri1 $0\cur_pri1[7:0] + end + attribute \src "libresoc.v:53493.3-53502.6" + process $proc$libresoc.v:53493$2534 + assign { } { } + assign { } { } + assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] + attribute \src "libresoc.v:53494.5-53494.29" + switch \initial + attribute \src "libresoc.v:53494.9-53494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx1[3:0] 4'0001 + case + assign $1\cur_idx1[3:0] \cur_idx0 + end + sync always + update \cur_idx1 $0\cur_idx1[3:0] + end + attribute \src "libresoc.v:53503.3-53512.6" + process $proc$libresoc.v:53503$2535 + assign { } { } + assign { } { } + assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] + attribute \src "libresoc.v:53504.5-53504.29" + switch \initial + attribute \src "libresoc.v:53504.9-53504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri2[7:0] \xive2_pri + case + assign $1\cur_pri2[7:0] \cur_pri1 + end + sync always + update \cur_pri2 $0\cur_pri2[7:0] + end + attribute \src "libresoc.v:53513.3-53522.6" + process $proc$libresoc.v:53513$2536 + assign { } { } + assign { } { } + assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] + attribute \src "libresoc.v:53514.5-53514.29" + switch \initial + attribute \src "libresoc.v:53514.9-53514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx2[3:0] 4'0010 + case + assign $1\cur_idx2[3:0] \cur_idx1 + end + sync always + update \cur_idx2 $0\cur_idx2[3:0] + end + attribute \src "libresoc.v:53523.3-53532.6" + process $proc$libresoc.v:53523$2537 + assign { } { } + assign { } { } + assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] + attribute \src "libresoc.v:53524.5-53524.29" + switch \initial + attribute \src "libresoc.v:53524.9-53524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri3[7:0] \xive3_pri + case + assign $1\cur_pri3[7:0] \cur_pri2 + end + sync always + update \cur_pri3 $0\cur_pri3[7:0] + end + attribute \src "libresoc.v:53533.3-53542.6" + process $proc$libresoc.v:53533$2538 + assign { } { } + assign { } { } + assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] + attribute \src "libresoc.v:53534.5-53534.29" + switch \initial + attribute \src "libresoc.v:53534.9-53534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx3[3:0] 4'0011 + case + assign $1\cur_idx3[3:0] \cur_idx2 + end + sync always + update \cur_idx3 $0\cur_idx3[3:0] + end + attribute \src "libresoc.v:53543.3-53552.6" + process $proc$libresoc.v:53543$2539 + assign { } { } + assign { } { } + assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] + attribute \src "libresoc.v:53544.5-53544.29" + switch \initial + attribute \src "libresoc.v:53544.9-53544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri4[7:0] \xive4_pri + case + assign $1\cur_pri4[7:0] \cur_pri3 + end + sync always + update \cur_pri4 $0\cur_pri4[7:0] + end + attribute \src "libresoc.v:53553.3-53561.6" + process $proc$libresoc.v:53553$2540 + assign { } { } + assign { } { } + assign $0\int_level_l$next[15:0]$2541 $1\int_level_l$next[15:0]$2542 + attribute \src "libresoc.v:53554.5-53554.29" + switch \initial + attribute \src "libresoc.v:53554.9-53554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\int_level_l$next[15:0]$2542 16'0000000000000000 + case + assign $1\int_level_l$next[15:0]$2542 \int_level_i + end + sync always + update \int_level_l$next $0\int_level_l$next[15:0]$2541 + end + attribute \src "libresoc.v:53562.3-53571.6" + process $proc$libresoc.v:53562$2543 + assign { } { } + assign { } { } + assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] + attribute \src "libresoc.v:53563.5-53563.29" + switch \initial + attribute \src "libresoc.v:53563.9-53563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx4[3:0] 4'0100 + case + assign $1\cur_idx4[3:0] \cur_idx3 + end + sync always + update \cur_idx4 $0\cur_idx4[3:0] + end + attribute \src "libresoc.v:53572.3-53581.6" + process $proc$libresoc.v:53572$2544 + assign { } { } + assign { } { } + assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] + attribute \src "libresoc.v:53573.5-53573.29" + switch \initial + attribute \src "libresoc.v:53573.9-53573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri5[7:0] \xive5_pri + case + assign $1\cur_pri5[7:0] \cur_pri4 + end + sync always + update \cur_pri5 $0\cur_pri5[7:0] + end + attribute \src "libresoc.v:53582.3-53591.6" + process $proc$libresoc.v:53582$2545 + assign { } { } + assign { } { } + assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] + attribute \src "libresoc.v:53583.5-53583.29" + switch \initial + attribute \src "libresoc.v:53583.9-53583.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx5[3:0] 4'0101 + case + assign $1\cur_idx5[3:0] \cur_idx4 + end + sync always + update \cur_idx5 $0\cur_idx5[3:0] + end + attribute \src "libresoc.v:53592.3-53601.6" + process $proc$libresoc.v:53592$2546 + assign { } { } + assign { } { } + assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] + attribute \src "libresoc.v:53593.5-53593.29" + switch \initial + attribute \src "libresoc.v:53593.9-53593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri6[7:0] \xive6_pri + case + assign $1\cur_pri6[7:0] \cur_pri5 + end + sync always + update \cur_pri6 $0\cur_pri6[7:0] + end + attribute \src "libresoc.v:53602.3-53611.6" + process $proc$libresoc.v:53602$2547 + assign { } { } + assign { } { } + assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] + attribute \src "libresoc.v:53603.5-53603.29" + switch \initial + attribute \src "libresoc.v:53603.9-53603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx6[3:0] 4'0110 + case + assign $1\cur_idx6[3:0] \cur_idx5 + end + sync always + update \cur_idx6 $0\cur_idx6[3:0] + end + attribute \src "libresoc.v:53612.3-53621.6" + process $proc$libresoc.v:53612$2548 + assign { } { } + assign { } { } + assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] + attribute \src "libresoc.v:53613.5-53613.29" + switch \initial + attribute \src "libresoc.v:53613.9-53613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri7[7:0] \xive7_pri + case + assign $1\cur_pri7[7:0] \cur_pri6 + end + sync always + update \cur_pri7 $0\cur_pri7[7:0] + end + attribute \src "libresoc.v:53622.3-53631.6" + process $proc$libresoc.v:53622$2549 + assign { } { } + assign { } { } + assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] + attribute \src "libresoc.v:53623.5-53623.29" + switch \initial + attribute \src "libresoc.v:53623.9-53623.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$137 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx7[3:0] 4'0111 + case + assign $1\cur_idx7[3:0] \cur_idx6 + end + sync always + update \cur_idx7 $0\cur_idx7[3:0] + end + attribute \src "libresoc.v:53632.3-53641.6" + process $proc$libresoc.v:53632$2550 + assign { } { } + assign { } { } + assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] + attribute \src "libresoc.v:53633.5-53633.29" + switch \initial + attribute \src "libresoc.v:53633.9-53633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$141 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri8[7:0] \xive8_pri + case + assign $1\cur_pri8[7:0] \cur_pri7 + end + sync always + update \cur_pri8 $0\cur_pri8[7:0] + end + attribute \src "libresoc.v:53642.3-53651.6" + process $proc$libresoc.v:53642$2551 + assign { } { } + assign { } { } + assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] + attribute \src "libresoc.v:53643.5-53643.29" + switch \initial + attribute \src "libresoc.v:53643.9-53643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$145 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx8[3:0] 4'1000 + case + assign $1\cur_idx8[3:0] \cur_idx7 + end + sync always + update \cur_idx8 $0\cur_idx8[3:0] + end + attribute \src "libresoc.v:53652.3-53661.6" + process $proc$libresoc.v:53652$2552 + assign { } { } + assign { } { } + assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] + attribute \src "libresoc.v:53653.5-53653.29" + switch \initial + attribute \src "libresoc.v:53653.9-53653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$149 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri9[7:0] \xive9_pri + case + assign $1\cur_pri9[7:0] \cur_pri8 + end + sync always + update \cur_pri9 $0\cur_pri9[7:0] + end + attribute \src "libresoc.v:53662.3-53671.6" + process $proc$libresoc.v:53662$2553 + assign { } { } + assign { } { } + assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] + attribute \src "libresoc.v:53663.5-53663.29" + switch \initial + attribute \src "libresoc.v:53663.9-53663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$153 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx9[3:0] 4'1001 + case + assign $1\cur_idx9[3:0] \cur_idx8 + end + sync always + update \cur_idx9 $0\cur_idx9[3:0] + end + attribute \src "libresoc.v:53672.3-53681.6" + process $proc$libresoc.v:53672$2554 + assign { } { } + assign { } { } + assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] + attribute \src "libresoc.v:53673.5-53673.29" + switch \initial + attribute \src "libresoc.v:53673.9-53673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$157 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri10[7:0] \xive10_pri + case + assign $1\cur_pri10[7:0] \cur_pri9 + end + sync always + update \cur_pri10 $0\cur_pri10[7:0] + end + attribute \src "libresoc.v:53682.3-53691.6" + process $proc$libresoc.v:53682$2555 + assign { } { } + assign { } { } + assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] + attribute \src "libresoc.v:53683.5-53683.29" + switch \initial + attribute \src "libresoc.v:53683.9-53683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$161 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx10[3:0] 4'1010 + case + assign $1\cur_idx10[3:0] \cur_idx9 + end + sync always + update \cur_idx10 $0\cur_idx10[3:0] + end + attribute \src "libresoc.v:53692.3-53701.6" + process $proc$libresoc.v:53692$2556 + assign { } { } + assign { } { } + assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] + attribute \src "libresoc.v:53693.5-53693.29" + switch \initial + attribute \src "libresoc.v:53693.9-53693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$165 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri11[7:0] \xive11_pri + case + assign $1\cur_pri11[7:0] \cur_pri10 + end + sync always + update \cur_pri11 $0\cur_pri11[7:0] + end + attribute \src "libresoc.v:53702.3-53711.6" + process $proc$libresoc.v:53702$2557 + assign { } { } + assign { } { } + assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] + attribute \src "libresoc.v:53703.5-53703.29" + switch \initial + attribute \src "libresoc.v:53703.9-53703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$169 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx11[3:0] 4'1011 + case + assign $1\cur_idx11[3:0] \cur_idx10 + end + sync always + update \cur_idx11 $0\cur_idx11[3:0] + end + attribute \src "libresoc.v:53712.3-53721.6" + process $proc$libresoc.v:53712$2558 + assign { } { } + assign { } { } + assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] + attribute \src "libresoc.v:53713.5-53713.29" + switch \initial + attribute \src "libresoc.v:53713.9-53713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$173 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri12[7:0] \xive12_pri + case + assign $1\cur_pri12[7:0] \cur_pri11 + end + sync always + update \cur_pri12 $0\cur_pri12[7:0] + end + attribute \src "libresoc.v:53722.3-53731.6" + process $proc$libresoc.v:53722$2559 + assign { } { } + assign { } { } + assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] + attribute \src "libresoc.v:53723.5-53723.29" + switch \initial + attribute \src "libresoc.v:53723.9-53723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx12[3:0] 4'1100 + case + assign $1\cur_idx12[3:0] \cur_idx11 + end + sync always + update \cur_idx12 $0\cur_idx12[3:0] + end + attribute \src "libresoc.v:53732.3-53741.6" + process $proc$libresoc.v:53732$2560 + assign { } { } + assign { } { } + assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] + attribute \src "libresoc.v:53733.5-53733.29" + switch \initial + attribute \src "libresoc.v:53733.9-53733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$181 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri13[7:0] \xive13_pri + case + assign $1\cur_pri13[7:0] \cur_pri12 + end + sync always + update \cur_pri13 $0\cur_pri13[7:0] + end + attribute \src "libresoc.v:53742.3-53751.6" + process $proc$libresoc.v:53742$2561 + assign { } { } + assign { } { } + assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] + attribute \src "libresoc.v:53743.5-53743.29" + switch \initial + attribute \src "libresoc.v:53743.9-53743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$185 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx13[3:0] 4'1101 + case + assign $1\cur_idx13[3:0] \cur_idx12 + end + sync always + update \cur_idx13 $0\cur_idx13[3:0] + end + attribute \src "libresoc.v:53752.3-53761.6" + process $proc$libresoc.v:53752$2562 + assign { } { } + assign { } { } + assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] + attribute \src "libresoc.v:53753.5-53753.29" + switch \initial + attribute \src "libresoc.v:53753.9-53753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$189 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri14[7:0] \xive14_pri + case + assign $1\cur_pri14[7:0] \cur_pri13 + end + sync always + update \cur_pri14 $0\cur_pri14[7:0] + end + attribute \src "libresoc.v:53762.3-53811.6" + process $proc$libresoc.v:53762$2563 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "libresoc.v:53763.5-53763.29" + switch \initial + attribute \src "libresoc.v:53763.9-53763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + switch \reg_idx + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$15 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$19 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$23 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$27 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$31 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$35 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$43 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$47 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$51 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$55 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$59 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$63 } + attribute \src "libresoc.v:0.0-0.0" + case 4'---- + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$67 } + case + assign $2\be_out[31:0] 0 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\be_out[31:0] 134217744 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\be_out[31:0] { \icp_r_src 20'00000000000000000000 \icp_r_pri } + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "libresoc.v:53812.3-53821.6" + process $proc$libresoc.v:53812$2564 + assign { } { } + assign { } { } + assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] + attribute \src "libresoc.v:53813.5-53813.29" + switch \initial + attribute \src "libresoc.v:53813.9-53813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$193 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx14[3:0] 4'1110 + case + assign $1\cur_idx14[3:0] \cur_idx13 + end + sync always + update \cur_idx14 $0\cur_idx14[3:0] + end + attribute \src "libresoc.v:53822.3-53831.6" + process $proc$libresoc.v:53822$2565 + assign { } { } + assign { } { } + assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] + attribute \src "libresoc.v:53823.5-53823.29" + switch \initial + attribute \src "libresoc.v:53823.9-53823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$197 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri15[7:0] \xive15_pri + case + assign $1\cur_pri15[7:0] \cur_pri14 + end + sync always + update \cur_pri15 $0\cur_pri15[7:0] + end + attribute \src "libresoc.v:53832.3-53841.6" + process $proc$libresoc.v:53832$2566 + assign { } { } + assign { } { } + assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] + attribute \src "libresoc.v:53833.5-53833.29" + switch \initial + attribute \src "libresoc.v:53833.9-53833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$201 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx15[3:0] 4'1111 + case + assign $1\cur_idx15[3:0] \cur_idx14 + end + sync always + update \cur_idx15 $0\cur_idx15[3:0] + end + attribute \src "libresoc.v:53842.3-53851.6" + process $proc$libresoc.v:53842$2567 + assign { } { } + assign { } { } + assign $0\ibit[0:0] $1\ibit[0:0] + attribute \src "libresoc.v:53843.5-53843.29" + switch \initial + attribute \src "libresoc.v:53843.9-53843.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ibit[0:0] \$71 + case + assign $1\ibit[0:0] 1'0 + end + sync always + update \ibit $0\ibit[0:0] + end + attribute \src "libresoc.v:53852.3-53860.6" + process $proc$libresoc.v:53852$2568 + assign { } { } + assign { } { } + assign $0\ics_wb__dat_r$next[31:0]$2569 $1\ics_wb__dat_r$next[31:0]$2570 + attribute \src "libresoc.v:53853.5-53853.29" + switch \initial + attribute \src "libresoc.v:53853.9-53853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__dat_r$next[31:0]$2570 0 + case + assign $1\ics_wb__dat_r$next[31:0]$2570 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + end + sync always + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2569 + end + attribute \src "libresoc.v:53861.3-53869.6" + process $proc$libresoc.v:53861$2571 + assign { } { } + assign { } { } + assign $0\ics_wb__ack$next[0:0]$2572 $1\ics_wb__ack$next[0:0]$2573 + attribute \src "libresoc.v:53862.5-53862.29" + switch \initial + attribute \src "libresoc.v:53862.9-53862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__ack$next[0:0]$2573 1'0 + case + assign $1\ics_wb__ack$next[0:0]$2573 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2572 + end + connect \$7 $ternary$libresoc.v:53232$2326_Y + connect \$99 $lt$libresoc.v:53233$2327_Y + connect \$101 $and$libresoc.v:53234$2328_Y + connect \$103 $lt$libresoc.v:53235$2329_Y + connect \$105 $and$libresoc.v:53236$2330_Y + connect \$107 $lt$libresoc.v:53237$2331_Y + connect \$109 $and$libresoc.v:53238$2332_Y + connect \$111 $lt$libresoc.v:53239$2333_Y + connect \$113 $and$libresoc.v:53240$2334_Y + connect \$115 $lt$libresoc.v:53241$2335_Y + connect \$117 $and$libresoc.v:53242$2336_Y + connect \$119 $lt$libresoc.v:53243$2337_Y + connect \$121 $and$libresoc.v:53244$2338_Y + connect \$123 $lt$libresoc.v:53245$2339_Y + connect \$125 $and$libresoc.v:53246$2340_Y + connect \$127 $lt$libresoc.v:53247$2341_Y + connect \$12 $eq$libresoc.v:53248$2342_Y + connect \$129 $and$libresoc.v:53249$2343_Y + connect \$131 $lt$libresoc.v:53250$2344_Y + connect \$133 $and$libresoc.v:53251$2345_Y + connect \$135 $lt$libresoc.v:53252$2346_Y + connect \$137 $and$libresoc.v:53253$2347_Y + connect \$11 $ternary$libresoc.v:53254$2348_Y + connect \$139 $lt$libresoc.v:53255$2349_Y + connect \$141 $and$libresoc.v:53256$2350_Y + connect \$143 $lt$libresoc.v:53257$2351_Y + connect \$145 $and$libresoc.v:53258$2352_Y + connect \$147 $lt$libresoc.v:53259$2353_Y + connect \$149 $and$libresoc.v:53260$2354_Y + connect \$151 $lt$libresoc.v:53261$2355_Y + connect \$153 $and$libresoc.v:53262$2356_Y + connect \$155 $lt$libresoc.v:53263$2357_Y + connect \$157 $and$libresoc.v:53264$2358_Y + connect \$159 $lt$libresoc.v:53265$2359_Y + connect \$161 $and$libresoc.v:53266$2360_Y + connect \$163 $lt$libresoc.v:53267$2361_Y + connect \$165 $and$libresoc.v:53268$2362_Y + connect \$167 $lt$libresoc.v:53269$2363_Y + connect \$16 $eq$libresoc.v:53270$2364_Y + connect \$169 $and$libresoc.v:53271$2365_Y + connect \$171 $lt$libresoc.v:53272$2366_Y + connect \$173 $and$libresoc.v:53273$2367_Y + connect \$175 $lt$libresoc.v:53274$2368_Y + connect \$177 $and$libresoc.v:53275$2369_Y + connect \$15 $ternary$libresoc.v:53276$2370_Y + connect \$179 $lt$libresoc.v:53277$2371_Y + connect \$181 $and$libresoc.v:53278$2372_Y + connect \$183 $lt$libresoc.v:53279$2373_Y + connect \$185 $and$libresoc.v:53280$2374_Y + connect \$187 $lt$libresoc.v:53281$2375_Y + connect \$189 $and$libresoc.v:53282$2376_Y + connect \$191 $lt$libresoc.v:53283$2377_Y + connect \$193 $and$libresoc.v:53284$2378_Y + connect \$195 $lt$libresoc.v:53285$2379_Y + connect \$197 $and$libresoc.v:53286$2380_Y + connect \$1 $eq$libresoc.v:53287$2381_Y + connect \$199 $lt$libresoc.v:53288$2382_Y + connect \$201 $and$libresoc.v:53289$2383_Y + connect \$204 $eq$libresoc.v:53290$2384_Y + connect \$203 $ternary$libresoc.v:53291$2385_Y + connect \$20 $eq$libresoc.v:53292$2386_Y + connect \$19 $ternary$libresoc.v:53293$2387_Y + connect \$24 $eq$libresoc.v:53294$2388_Y + connect \$23 $ternary$libresoc.v:53295$2389_Y + connect \$28 $eq$libresoc.v:53296$2390_Y + connect \$27 $ternary$libresoc.v:53297$2391_Y + connect \$32 $eq$libresoc.v:53298$2392_Y + connect \$31 $ternary$libresoc.v:53299$2393_Y + connect \$36 $eq$libresoc.v:53300$2394_Y + connect \$35 $ternary$libresoc.v:53301$2395_Y + connect \$3 $eq$libresoc.v:53302$2396_Y + connect \$40 $eq$libresoc.v:53303$2397_Y + connect \$39 $ternary$libresoc.v:53304$2398_Y + connect \$44 $eq$libresoc.v:53305$2399_Y + connect \$43 $ternary$libresoc.v:53306$2400_Y + connect \$48 $eq$libresoc.v:53307$2401_Y + connect \$47 $ternary$libresoc.v:53308$2402_Y + connect \$52 $eq$libresoc.v:53309$2403_Y + connect \$51 $ternary$libresoc.v:53310$2404_Y + connect \$56 $eq$libresoc.v:53311$2405_Y + connect \$55 $ternary$libresoc.v:53312$2406_Y + connect \$5 $and$libresoc.v:53313$2407_Y + connect \$60 $eq$libresoc.v:53314$2408_Y + connect \$59 $ternary$libresoc.v:53315$2409_Y + connect \$64 $eq$libresoc.v:53316$2410_Y + connect \$63 $ternary$libresoc.v:53317$2411_Y + connect \$68 $eq$libresoc.v:53318$2412_Y + connect \$67 $ternary$libresoc.v:53319$2413_Y + connect \$71 $shr$libresoc.v:53320$2414_Y [0] + connect \$73 $and$libresoc.v:53321$2415_Y + connect \$75 $lt$libresoc.v:53322$2416_Y + connect \$77 $and$libresoc.v:53323$2417_Y + connect \$79 $lt$libresoc.v:53324$2418_Y + connect \$81 $and$libresoc.v:53325$2419_Y + connect \$83 $lt$libresoc.v:53326$2420_Y + connect \$85 $and$libresoc.v:53327$2421_Y + connect \$87 $lt$libresoc.v:53328$2422_Y + connect \$8 $eq$libresoc.v:53329$2423_Y + connect \$89 $and$libresoc.v:53330$2424_Y + connect \$91 $lt$libresoc.v:53331$2425_Y + connect \$93 $and$libresoc.v:53332$2426_Y + connect \$95 $lt$libresoc.v:53333$2427_Y + connect \$97 $and$libresoc.v:53334$2428_Y + connect \icp_r_pri \$203 + connect \icp_r_src \cur_idx15 + connect \max_idx 4'0000 + connect \max_pri 8'11111111 + connect { \icp_o_pri$next \icp_o_src$next } { \icp_r_pri \icp_r_src } + connect \be_in { \ics_wb__dat_w [7:0] \ics_wb__dat_w [15:8] \ics_wb__dat_w [23:16] \ics_wb__dat_w [31:24] } + connect \wb_valid \$5 + connect \reg_idx \ics_wb__adr [3:0] + connect \reg_is_debug \$3 + connect \reg_is_config \$1 + connect \reg_is_xive \ics_wb__adr [9] +end