From: Gabriel L. Somlo <gsomlo@gmail.com>
Date: Thu, 23 May 2019 12:53:26 +0000 (-0400)
Subject: tools/litex_sim: restore functionality of '--with-sdram' option
X-Git-Tag: 24jan2021_ls180~1206^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e90caa86833cbde064c868506cc565e6e26d9887;p=litex.git

tools/litex_sim: restore functionality of '--with-sdram' option

After LiteDRAM commit #50e1d478, an additional positional argument
('databits') is required by the PhySettings() constructor.

The value used here (32) will generate a 64MByte simulated SDRAM.
---

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 126da466..033a0e45 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -116,6 +116,7 @@ class SimSoC(SoCSDRAM):
             sdram_module =  MT48LC16M16(100e6, "1:1") # use 100MHz timings
             phy_settings = PhySettings(
                 memtype="SDR",
+                databits=32,
                 dfi_databits=16,
                 nphases=1,
                 rdphase=0,