From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 16 Jan 2015 18:25:35 +0000 (+0100)
Subject: phy: remove GTXE2_COMMON (no longer need since it was a Vivado bug that is now fixed)
X-Git-Tag: 24jan2021_ls180~2572^2~56
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e90d97e9c2dfe901d6625cbc9d897fa80d6e0182;p=litex.git

phy: remove GTXE2_COMMON (no longer need since it was a Vivado bug that is now fixed)
---

diff --git a/lib/sata/phy/k7/crg.py b/lib/sata/phy/k7/crg.py
index 3d008a67..7e57e608 100644
--- a/lib/sata/phy/k7/crg.py
+++ b/lib/sata/phy/k7/crg.py
@@ -1,7 +1,6 @@
 from math import ceil
 
 from lib.sata.common import *
-from lib.sata.phy.k7.trx import GTXE2_COMMON
 
 class K7SATAPHYCRG(Module):
 	def __init__(self, pads, gtx, clk_freq, speed):
@@ -23,16 +22,6 @@ class K7SATAPHYCRG(Module):
 		)
 		self.comb += gtx.gtrefclk0.eq(refclk)
 
-	# QPLL
-		# not used but need to be there... see AR43339...
-		gtx_common = GTXE2_COMMON()
-		self.comb += [
-			gtx_common.refclk0.eq(refclk),
-			gtx.qpllclk.eq(gtx_common.qpllclk),
-			gtx.qpllrefclk.eq(gtx_common.qpllrefclk),
-		]
-		self.submodules += gtx_common
-
 	# TX clocking
 		# (SATA3) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 300MHz (16-bits)
 		# (SATA2) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 150MHz (16-bits)
diff --git a/lib/sata/phy/k7/trx.py b/lib/sata/phy/k7/trx.py
index e524c72a..eba35f13 100644
--- a/lib/sata/phy/k7/trx.py
+++ b/lib/sata/phy/k7/trx.py
@@ -852,105 +852,3 @@ class K7SATAPHYTRX(Module):
 
 					**gtxe2_channel_parameters
 			)
-
-
-class GTXE2_COMMON(Module):
-	def __init__(self, fbdiv=16):
-		self.refclk0 = Signal()
-
-		self.qpllclk = Signal()
-		self.qpllrefclk = Signal()
-
-		# fbdiv config
-		fbdiv_in_config = {
-			16 :	0b0000100000,
-			20 :	0b0000110000,
-			32 :	0b0001100000,
-			40 :	0b0010000000,
-			64 :	0b0011100000,
-			66 :	0b0101000000,
-			80 :	0b0100100000,
-			100 :	0b0101110000
-		}
-		fbdiv_in = fbdiv_in_config[fbdiv]
-
-		fbdiv_ratio_config = {
-			16 :	0b1,
-			20 :	0b1,
-			32 :	0b1,
-			40 :	0b1,
-			64 :	0b1,
-			66 :	0b0,
-			80 :	0b1,
-			100 :	0b1
-		}
-		fbdiv_ratio = fbdiv_ratio_config[fbdiv]
-
-		self.specials += \
-			Instance("GTXE2_COMMON",
-				# Simulation attributes
-					p_SIM_RESET_SPEEDUP="TRUE",
-					p_SIM_QPLLREFCLK_SEL=0b001,
-					p_SIM_VERSION="4.0",
-
-				# Common block attributes
-					p_BIAS_CFG=0x0000040000001000,
-					p_COMMON_CFG=0,
-					p_QPLL_CFG=0x06801c1,
-					p_QPLL_CLKOUT_CFG=0,
-					p_QPLL_COARSE_FREQ_OVRD=0b010000,
-					p_QPLL_COARSE_FREQ_OVRD_EN=0,
-					p_QPLL_CP=0b0000011111,
-					p_QPLL_CP_MONITOR_EN=0,
-					p_QPLL_DMONITOR_SEL=0,
-					p_QPLL_FBDIV=fbdiv_in,
-					p_QPLL_FBDIV_MONITOR_EN=0,
-					p_QPLL_FBDIV_RATIO=fbdiv_ratio,
-					p_QPLL_INIT_CFG=0x000006,
-					p_QPLL_LOCK_CFG=0x21e9,
-					p_QPLL_LPF=0b1111,
-					p_QPLL_REFCLK_DIV=1,
-
-				# Common block - Dynamic Reconfiguration Port (DRP)
-					i_DRPADDR=0,
-					i_DRPCLK=0,
-					i_DRPDI=0,
-					#o_DRPDO=,
-					i_DRPEN=0,
-					#o_DRPRDY=,
-					i_DRPWE=0,
-
-				# Common block  - Ref Clock Ports
-					i_GTGREFCLK=0,
-					i_GTNORTHREFCLK0=0,
-					i_GTNORTHREFCLK1=0,
-					i_GTREFCLK0=self.refclk0,
-					i_GTREFCLK1=0,
-					i_GTSOUTHREFCLK0=0,
-					i_GTSOUTHREFCLK1=0,
-
-				# Common block - QPLL Ports
-					#o_QPLLDMONITOR=,
-					#o_QPLLFBCLKLOST=,
-					#o_QPLLLOCK=,
-					i_QPLLLOCKDETCLK=0,
-					i_QPLLLOCKEN=1,
-					o_QPLLOUTCLK=self.qpllclk,
-					o_QPLLOUTREFCLK=self.qpllrefclk,
-					i_QPLLOUTRESET=0,
-					i_QPLLPD=0,
-					#o_QPLLREFCLKLOST=,
-					i_QPLLREFCLKSEL=0b001,
-					i_QPLLRESET=0,
-					i_QPLLRSVD1=0,
-					i_QPLLRSVD2=ones(5),
-					#o_REFCLKOUTMONITOR=,
-
-				# Common block Ports
-					i_BGBYPASSB=1,
-					i_BGMONITORENB=1,
-					i_BGPDB=1,
-					i_BGRCALOVRD=0,
-					i_PMARSVD=0,
-					i_RCALENB=1
-			)