From: clairexen <claire@symbioticeda.com>
Date: Tue, 20 Oct 2020 15:11:36 +0000 (+0200)
Subject: Merge pull request #2405 from byuccl/fix_xilinx_cells
X-Git-Tag: working-ls180~238
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e919d0c1255cda47fa5835ad468266621cab0ecf;p=yosys.git

Merge pull request #2405 from byuccl/fix_xilinx_cells

xilinx/cells_sim.v: Move signal declaration to before first use
---

e919d0c1255cda47fa5835ad468266621cab0ecf